Professional Documents
Culture Documents
Release
Doulos
Contents
Table of Contents:
1.1 Introduction . . . . . . . . .
1.2 Quick Start . . . . . . . . . .
1.3 Settings & Buttons . . . . . .
1.4 Yosys Circuit Diagrams . . .
1.5 Tutorials and Code Examples
1.6 FAQ . . . . . . . . . . . . . .
1.7 Privacy Policy . . . . . . . .
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ii
EDA Playground on YouTube - Tutorials for Verilog, SystemVerilog, UVM, and VHDL, interview questions, news
and features, etc.
Contents
Contents
CHAPTER 1
Table of Contents:
1.1 Introduction
EDA Playground on YouTube - Tutorials for Verilog, SystemVerilog, UVM, and VHDL, interview questions, news
and features, etc.
1.1.1 Overview
EDA Playground gives engineers immediate hands-on exposure to simulating SystemVerilog, Verilog, VHDL,
C++/SystemC, and other HDLs. All you need is a web browser. The goal is to accelerate learning of design/testbench
development with easier code sharing, and with simpler access to EDA tools and libraries. EDA Playground is specifically designed for small prototypes and examples.
With a simple click, run your code and see console output in real time. Pick another simulator version and run
it again.
View waves for your simulation using EPWave browser-based wave viewer.
Save your code snippets. Share your code and simulation results with a web link. Perfect for web forum
discussions or emails. Great for asking questions or sharing your knowledge.
Quickly try something out
Try out a SystemVerilog feature before using it on your project.
Try out a library that youre thinking of using.
Modify another engineers shared code and re-run it.
Eliminate environment differences. Since the code always executes in the same environment, everyone will see
the same result on a subsequent re-run.
Browse and use a large repository of working code examples and templates.
1.1. Introduction
1.1.8 Credits
EDA Playground was created by Doulos.
2. In either the Design or Testbench window pane, type in the following code:
module test;
initial
$display("Hello World!");
endmodule
(Note: The code in the right Design pane is compiled first, followed by code in the left Testbench pane.)
3. Click
Yes, running a sim is as simple as that!
4. In the bottom pane, you should see real-time results as your code is being compiled and then run. A run typically
takes 1-5 seconds, depending on network traffic and simulator. Near the bottom of result output, you should see:
Hello World!
5. Now, lets save our good work. Type in a descriptive name in the Details area on the left.
and click
6. The browser page will reload and the browser address bar will change. This is a persistent link to your saved
code. You can send the link by email, post it on a web page, post it on Stack Overflow forums, etc. Here is what
the link looks like for one users Hello World! playground: http://www.edaplayground.com/s/3/12
7. Now, lets try modifying existing code. Load the following example: RAM
8. On the left editor pane, before the end of initial block, add the following:
write_enable = 1;
data_write = 8h2C;
toggle_clk_write;
toggle_clk_read;
$display("data[%0h]: %0h",
address_read, data_read);
The above code will write new data and read it out again. ( address_read and address_write should be the same).
9. Run the sim. In the results you should see this new message:
data[1b]: 2c
10. Optional. Click Copy to save a personal version of the modified RAM code, including the simulation results.
Select a simulator and check the Open EPWave after run checkbox. (Not all simulators may have this run
option.)
Click Run. After the run completes, the resulting waves will load in a new EPWave window. (Pop-ups must be
enabled.)
Loading Waves for VHDL Simulations
Check the Open EPWave after run checkbox.
Specify the Top entity to simulate.
Click Run. After the run completes, the resulting waves will load in a new EPWave window. (Pop-ups must be
enabled.)
The waves for all signals in the specified Top entity and any of its components will be dumped.
In EPWave window, click Get Signals to select the signals to view.
To add a file, click the + sign in the testbench or design pane. Then create a new file or upload an existing file. The
filename may not contain special characters.
Simulating code with multiple files
For SystemVerilog, use include statements such as the following to include the added source files in the compile:
include "adpcm_seq_item.svh"
For VHDL, all files with the .vhd and .vhdl extensions are automatically included in the compile.
For Python, use import statements:
from design import *
To rename a file, double click the tab name. (The initial testbench and design files cannot be renamed.)
Testbench + Design
The testbench (left editor pane) and design (right editor pane) may be written using one of these languages:
Verilog/SystemVerilog for both
VHDL for both
e for testbench, and SystemVerilog/Verilog for design
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When language is Verilog/SystemVerilog, a UVM or OVM library can be used for both the design and testbench. The
following libraries are available:
UVM 1.2
UVM 1.1d
OVM 2.1.2
Other Libraries (SystemVerilog/Verilog)
When language is Verilog/SystemVerilog, other Verilog libraries can be used for both the design and testbench. These
libraries may be used along with UVM/OVM. Multiple libraries may be selected at the same time. Ctrl+Click to select
multiple libraries. Available libraries:
OVL 2.8.1
SVUnit 2.11
ClueLib 0.2.0
svlib 0.3
Libraries (VHDL)
When language is VHDL, the following VHDL libraries can be used for both design and testbench.
OVL 2.8.1
OSVVM 2014.01
Top entity (VHDL)
When language is VHDL, the top entity of the design must be specified before running a simulation.
Specman
When testbench language is e, one of the following Specman versions must be used.
Specman 2014.10
Libraries (C++)
When language is C++/SystemC, the following libraries can be used for both design and testbench.
SystemC 2.3.1
SystemC 2.3.0
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When testbench language is Python and design language is Verilog/SystemVerilog, the following verification environments are available:
cocotb 0.4
cocotb 0.3
cocotb 0.2
When testbench and design language is Python, the following methodologies are available:
MyHDL 0.8
Migen X
Migen Before running synthesis on a Migen design, the Top class corresponding to the top module must be specified.
The Top class is the class instantiation to use when converting the Migen design to Verilog. Some examples:
MyModule()
Divisor(4)
MyMemory(16, 2**12, init=list(range(20)))
Tools & Simulators
For running the code, several tools/simulators may be selected. Many simulators have additional options that may be
specified. Any options needed for languages and libraries will automatically be included.
Open EPWave after run
Checking this option will open EPWave wave viewer in a new window after the simulation run completes (pop-ups
must be enabled). It is available for all simulators that have a run step.
Checking this option will download the run directory as a ZIP file after the simulation run (pop-ups must be enabled).
The simulation run does not have to be successful for the download to occur. The ZIP file will include all the code
files as well as any generated files such as wave dumps, log files, etc.
YouTube video: How to download code and results from EDA Playground
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Riviera-PRO EDU
Additional command-line compile options and run options may be specified in the bottom textboxes.
The Run Time option can be used to specify the number of timesteps for the simulation to run. By default, the
simulation runs forever until it hits a breakpoint or $finish.
The Use run.do Tcl file option is for using a custom run.do DO file for specifying simulation commands.
Riviera-PRO Compile Options for SystemVerilog/Verilog For SystemVerilog and Verilog simulations, RivieraPRO compile options are prepopulated with -timescale 1ns/1ns -sv2k9 and run options are prepopulated with +access+r
Riviera-PRO Compile Options for VHDL
with -2008
Icarus Verilog
Additional command-line compile options and run options may be specified in the bottom textboxes.
Icarus Verilog 0.9.7 and Icarus Verilog 0.9.6 compile options are pre-populated with -Wall
Icarus Verilog 0.10.0 compile options are prepopulated with -Wall -g2012
An example of custom compile and run options is here: http://www.edaplayground.com/s/4/202
Note: When using Migen co-simulation, the compile/run options are not available.
GPL Cver
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VeriWell
This is a g++ Linux compiler for C++. It is used for C++ and SystemC runs.
Additional command-line compile options and run options may be specified in the bottom textboxes.
Csh
This is a standard Csh (C Shell) interpreter. Currently, no additional options are available for Csh.
Perl
This is a standard Perl compiler. Currently, no additional options are available for Perl.
Python
This is a standard Python compiler. It is only used for MyHDL when both testbench and design are written in Python.
Currently, no additional options are available for Python.
Yosys
Yosis is a synthesis tool for performing logical synthesis and creating a netlist. It supports using ABC to synthesize
for a sample cell library.
Yosys will only process code in the right Design pane. The code in the left Testbench pane will be ignored.
UVM/OVM/Methodology/Libraries selections are also ignored.
The following synthesis options are available:
use ABC with cell library - synthesize for a demo cell library using ABC
memory -nomap - skip memory_map step
fsm -nomap - skip fsm_map step
skip FSM step
Show diagram after run - open the generated circuit diagram after synthesis flow completes (pop-ups must be
enabled).
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When using Yosys with Migen, the Top class must be specified, which is used to convert Migen design to Verilog.
When using Yosys with MyHDL, the Testbench pane must contain code to convert MyHDL design to a Verilog file.
The Verilog file must have suffix .v, and can be named anything EXCEPT tb_* or a Verilog reserved keyword. Thus,
when running Yosys on MyHDL code, the Testbench code will be run first before synthesis.
VTR
Verilog-to-Routing is a complete physical design flow that includes elaboration, logical sysnthesis, FPGA technology
mapping, packing, placement, and routing. The recommended architecture file k6_frac_N10_mem32K_40nm.xml is
used for the flow. In addition, route channel width is set at a high 100 to ensure no routing issues with dense designs.
VTR will only process code in the right Design pane. The code in the left Testbench pane will be ignored.
UVM/OVM/Methodology/Libraries selections are also ignored. Currently, no additional options are available for
VTR.
Currently, VTR cannot be used with MyHDL or Migen.
Details
The options in this section are only used when saving the playground.
Name
A brief name/title of the playground. Visible by others when they open a saved playground.
Description
A longer description of the playground. Visible by others when they open a saved playground.
Public
Whether this playground should be publicly accessible after being saved. When checked, anyone will be able to view
this playground. When unchecked, only the creator will be able to view the playground.
Examples
Links to code examples created on EDA Playground. Some examples may have additional documentation provided in
the (docs) link.
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Note that Vim and Emacs modes are only loose approximations of the actual bindings.
Default Mode
The default mode comes with search/replace functionality. The keybindings are:
Ctrl-F / Cmd-F - Start searching
Ctrl-G / Cmd-G - Find next
Shift-Ctrl-G / Shift-Cmd-G - Find previous
Shift-Ctrl-F / Cmd-Option-F - Replace
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// For All
keyMap.basic = {
"Left": "goCharLeft", "Right": "goCharRight", "Up": "goLineUp", "Down": "goLineDown",
"End": "goLineEnd", "Home": "goLineStartSmart", "PageUp": "goPageUp", "PageDown": "goPageDown",
"Delete": "delCharAfter", "Backspace": "delCharBefore", "Tab": "defaultTab", "Shift-Tab": "indentAu
"Enter": "newlineAndIndent", "Insert": "toggleOverwrite"
};
// For PC
keyMap.pcDefault = {
"Ctrl-A": "selectAll", "Ctrl-D": "deleteLine", "Ctrl-Z": "undo", "Shift-Ctrl-Z": "redo", "Ctrl-Y":
"Ctrl-Home": "goDocStart", "Alt-Up": "goDocStart", "Ctrl-End": "goDocEnd", "Ctrl-Down": "goDocEnd",
"Ctrl-Left": "goGroupLeft", "Ctrl-Right": "goGroupRight", "Alt-Left": "goLineStart", "Alt-Right": "
"Ctrl-Backspace": "delGroupBefore", "Ctrl-Delete": "delGroupAfter", "Ctrl-F": "find",
"Ctrl-G": "findNext", "Shift-Ctrl-G": "findPrev",
"Ctrl-[": "indentLess", "Ctrl-]": "indentMore",
fallthrough: "basic"
};
// For MAC
keyMap.macDefault = {
"Cmd-A": "selectAll", "Cmd-D": "deleteLine", "Cmd-Z": "undo", "Shift-Cmd-Z": "redo", "Cmd-Y": "redo
"Cmd-Up": "goDocStart", "Cmd-End": "goDocEnd", "Cmd-Down": "goDocEnd", "Alt-Left": "goGroupLeft",
"Alt-Right": "goGroupRight", "Cmd-Left": "goLineStart", "Cmd-Right": "goLineEnd", "Alt-Backspace":
"Ctrl-Alt-Backspace": "delGroupAfter", "Alt-Delete": "delGroupAfter", "Cmd-F": "find",
"Cmd-G": "findNext", "Shift-Cmd-G": "findPrev",
"Cmd-[": "indentLess", "Cmd-]": "indentMore",
fallthrough: ["basic", "emacsy"]
};
keyMap.emacsy = {
"Ctrl-F": "goCharRight", "Ctrl-B": "goCharLeft", "Ctrl-P": "goLineUp", "Ctrl-N": "goLineDown",
"Alt-F": "goWordRight", "Alt-B": "goWordLeft", "Ctrl-A": "goLineStart", "Ctrl-E": "goLineEnd",
"Ctrl-V": "goPageDown", "Shift-Ctrl-V": "goPageUp", "Ctrl-D": "delCharAfter", "Ctrl-H": "delCharBef
"Alt-D": "delWordAfter", "Alt-Backspace": "delWordBefore", "Ctrl-K": "killLine", "Ctrl-T": "transpo
};
1.3.4 Buttons
Log In
The user must be logged in to save or run playground code. Playground code and results may be viewed without
logging in.
Run
Shortcut: Ctrl+Enter
Run the current code using the selected tool/simulator and options. The code runs on the EDA Playground server and
the results are printed in the bottom Results pane.
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Save
Shortcut: Ctrl+S
Save the current playground, including code, bottom 200 lines of results, and options. Once the playground is saved,
the page reloads. The location specified in the address bar is a static link to this playground this link can be shared
with others.
If the playground has been saved previously, clicking on Save updates the currently saved playground. The static link
does not change.
If you modified a code example but did not save, youll see an asterisk in the Save button.
Copy
This button shows up for everyone when viewing a saved playground. Clicking on it creates a new copy of the current
playground. The copy will be complitely separate from the original, and it will have its own link that can be shared
with others.
If you modified a code example but did not save, youll see an asterisk in the Copy button.
Share
This button only shows up for saved playgrounds. It displays a modal pop-up with a static link to the current playground. Also, it displays buttons for sharing on Twitter, Facebook, or LinkedIn.
Collaborate
Allows real-time collaborations where multiple users can edit code simultaneously.
Real-Time Collaboration Intro on YouTube.
About
Links to EDA Playground documentation (these pages).
Apps
Shows links to other apps available on EDA Playground, such as EPWave.
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The numbers tell you which bits on which side are connected. for example 3:0 - 7:4 means that the bits 3:0
from the left net are connected to bits 7:4 from the right net. Usually the box has a single connection on one
side and individual connections on the other side. When such boxes are connected to each other or to a cell port,
the connections have little diamonds on the ends instead of arrows. Thats because its not an actual connection
in the sense of the internal RTLIL netlist format.
For a detailed explanation, see Yosys Application Note 011: Interactive Design Investigation
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http://www.doulos.com/knowhow/verilog_designers_guide/
D Flip-Flop (DFF)
Code located at: Verilog D Flip-Flop
This example demonstrates the design and verification of a simple D flip-flop (Wikipedia link).
Design
Type
input
input
input
output
output
Description
the clock; rising edge of the clock captures the value
asynchronous reset; when reset is high, the DFF output q is 0
the main input
the d value captured at the last rising clock edge
inverted version of q
Testbench
The testbench is a simple directed test which toggles the DFF inputs and displays the outputs to the console.
The reg signals are used to drive inputs, and wire signals are used to observe outputs:
reg clk;
reg reset;
reg d;
wire q;
wire qb;
The initial block contains the actual test. First, reset is driven to 1 to reset the flop, while d is driven with an X:
clk = 0;
reset = 1;
d = 1bx;
From the console display, we see that the flop has been properly reset with q == 0
Reset flop.
d:x, q:0, qb:1
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d = 1;
reset = 0;
The output q remains at 0 because the design did not see a rising edge of clk and did not capture the d input:
Release reset.
d:1, q:0, qb:1
Note: Before calling the $display task, we always tell simulation to proceed for 1 time unit #1 to allow the output
signals to propagate.
Ripple Carry Counter
Code located at: Verilog Ripple Carry Counter
$display System Task
Code located at: Verilog $display System Task
define Text Macros
Code located at: Verilog define Text Macros
Port Declaration & Connection
Code located at: Verilog Module Ports for Ripple Carry Counter
Ripple Carry Full Adder
Code located at: Verilog Ripple Carry Full Adder
Blocking and Nonblocking Assignments
Code located at: Verilog Blocking and Nonblocking Assignments
always @ event wait
Code located at: Verilog always @ event wait
if-else conditional and case statements
Code located at: Verilog if-else and case statements
1.5. Tutorials and Code Examples
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Parameters
Code located at: Verilog Parameter
Generate Blocks
The StackOverflow question mentioned in this Verilog tutorial: http://stackoverflow.com/questions/18153405/parameterizednumber-of-cycle-delays-in-verilog
The generate example from the StackOverflow question: Delay with Verilog generate
The generate conditional example from this Verilog tutorial: Verilog generate conditional
Verilog Tutorials on YouTube
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interface svunitOnSwitch (
output logic on
);
initial on = hx;
function logic true();
// no implementation yet
endfunction
function logic false();
// no implementation yet
endfunction
function int return43();
// no implementation yet
endfunction
function void turn_on();
// no implementation yet
endfunction
function void turn_off();
// no implementation yet
endfunction
endinterface
The SVTESTs below are the acceptance unit tests that verify the functionality of the svunitOnSwitch. If you
run the tests on EDA Playground youll see all the tests fail because none of the svunitOnSwitch functionality is
implemented. Your job is to build a complete svunitOnSwitch, one requirement at a time, by:
examining the requirement defined in the unit test
(HINT: a unit test is marked by the SVTEST macro)
implementng the corresponding code in the svunitOnSwitch
(HINT: watch for the no implementation yet comment)
running the test suite to make sure your implementation satisfies the unit test
When youve gone through all the tests and your entire test suite passes, youre done!
svunitOnSwitch and learned the basics of SVUnit!
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*/
SVUNIT_TESTS_END
//===================================
// This is the UUT that were
// running the Unit Tests on
//===================================
svunitOnSwitch uut();
//===================================
// Build. Runs once
//===================================
function void build();
svunit_ut = new(name);
endfunction
//===================================
// Setup for running the Unit Tests
// Runs before every SVTEST.
//===================================
task setup();
svunit_ut.setup();
/* Place Setup Code Here */
endtask
//===================================
// Here we deconstruct anything we
// need after running the Unit Tests
// Runs after every SVTEST.
//===================================
task teardown();
svunit_ut.teardown();
/* Place Teardown Code Here */
endtask
endmodule
You can do a lot more than test a simple svunitOnSwith with SVUnit. When youre ready to test your own design
and testbench IP visit: http://www.AgileSoC.com/svunit
SVUnit Examples on YouTube
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1.6 FAQ
1.6.1 How do I start a blank playground design?
When working on code at http://www.edaplayground.com, you can start a blank design by clicking the EDA Playground logo in the top left. (Before doing that, please ensure that your existing code edits are saved.)
1.6.2 How do I modify one of the examples? How do I modify someone elses playground?
After making code edits, you can save your own version by clicking Copy.
1.6.4 Can I view the waves from my EDA Playground sim using EPWaves?
Yes, waves are supported for all languages, frameworks, and libraries. See Loading Waves from EDA Playground
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Contacting us
If you have any questions about this Privacy Policy, the practices of this Site, or your dealings with this Site, please
contact us at: http://www.doulos.com
This document was last updated on April 1, 2015
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