CMOS Transistor Theory

Introduction to VLSI Design, VLSI I, Fall 2011
4. CMOS Transistor Theory
mm
40
40
60
80
100
120

J. A. Abraham
60
Department
of Electrical and Computer Engineering

The University of Texas at Austin
80
EE 382M.7 VLSI I
Fall 2011
September 7, 2011
ECE Department, University of Texas at Austin
Lecture 4. CMOS Transistor Theory
J. A. Abraham, September 7, 2011
1 / 31
Electrical Properties
Necessary to understand basic electrical properties of the MOS
mm to design
transistor
40 useful circuits
60
80
100
Deal with non-ideal devices
120
Ensure that the circuits are robust

Create working layouts
40
Predict delays and power consumption

As circuit dimensions
scale down, electrical
effects become
more
60
important, even for
digital circuits
1.65 GHz square wave
from an 80
HDMI Interface
(Source: Dunnihoo, EE
Times Asia, 8/25/2005)
1 / 31
Department of Electrical and Computer Engineering, The University of Texas at Austin


The nMOS Transistor

mm
40
60
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40
Terminal Voltages
Modes of operation depend on Vg , Vd , Vs
60
Vgs = Vg Vs
Vgd = Vg Vd
Vd s = Vd Vs = Vgs Vgd
Source and drain are symmetric diffusion terminals

By convention, source is terminal at lower voltage, so Vds 0
80
nMOS body is grounded for simple designs; assume source is 0
Three regions of operation: Cutoff, Linear, Saturated

2 / 31
Modes in nMOS Structure

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60
80
3 / 31


nMOS Transistor Operation

Positive voltage on Gate produces electric field across substrate
attracts
to the Gate 60
and repels holes
mm electrons 40
80
100
120
With sufficient voltage, region under Gate changes from p- to
n-Type conducting path between the Source and Drain
Inversion layer is field-induced junction, unlike a PN junction
which
is metallurgical
40
Horizontal component of electric field associated with Vds > 0
is responsible for sweeping electrons from channel to drain
Threshold
Voltage
60
The gate voltage at which conduction takes place is the
Threshold Voltage, Vt
Current flow occurs when the drain to source voltage Vds > 0,
and
80 consists almost entirely of majority-carriers (electrons),
that flow through the channel
A depletion region insulates the channel from the substrate
4 / 31
Conducting nMOS Transistor

Conduction when Vgs > Vt and Vds > 0
No significant current through the substrate because of reverse

mm biased PN
40junction with
60 the channel80
100
120
As the voltage from drain to source is increased, the resistive
drop along the channel begins to change the shape of the
channel characteristic
At source end of the channel, the full gate voltage is effective
40
in inverting the channel
At drain end of the channel, only the difference between the
gate and the drain voltage is effective
If Vds > Vgs Vt , then Vgd < Vt , and the channel is pinched
down
(the inversion layer no longer reaches the drain)
60
In this case, conduction is brought about by the drift
mechanism of electrons under the influence of positive drain
voltage; as the negative electrons leave the channel, they are
accelerated towards the drain
80
Voltage
across the pinchdown channel tends to remain fixed
at (Vgs Vt ), and the channel current remains constant with
increasing Vds
5 / 31


nMOS Device Behavior

Vgs > Vt , Vds = 0
mm
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Nonsaturated Mode
Vds < Vgs Vt
40
Saturated Mode
(Vds > Vgs Vt )
60
80
6 / 31
The pMOS Transistor

mm
40
40
60
80
100
120
Moderately doped n- type

substrate (or well) in which
two heavily doped p+ regions,
the Source and Drain, are
diffused
Application of a negative gate voltage (w.r.t. source) draws

holes
60 into the region below the gate; channel changes from n
to p-type (source-drain conduction path)
Conduction due to holes; negative Vd sweeps holes from
source (through channel) to drain
80
7 / 31


Current in the Channel

In the Linear region, Ids depends on how much charge there is in
mm
40 fast the charge
60
80
100
120
the channel and how
is moving
Channel Charge
MOS structure looks like parallel plate capacitor while
operating
in inversion (Gate Oxide Channel)
40
Qchannel = CV
C = Cg = ox W L/tox = Cox W L (Cox = ox /tox )
V = Vgc Vt = (Vgs Vds /2) Vt
60
80
8 / 31
Carrier Velocity
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Charge is carried by electrons

Carrier velocity proportional to lateral E- field between
40
source
and drain
= E
is called mobility
E = Vds /L
60
Time for carrier to cross channel: t = L/
80
9 / 31


I-V Characteristics
nMOS Linear I-V
Current
from 60
charge in channel
and the
mm can be obtained
40
80
100time t
each carrier takes to cross
Qchannel
Ids =
t
W
40
= Cox
(Vgs Vt Vds /2) Vds
L
= (Vgs Vt Vds /2) Vds
120
nMOS Saturation I-V

60
If Vgd < Vt , channel pinches off near drain
when Vds > Vdsat = Vgs Vt
Now drain voltage no longer increases with current

80
Ids = (Vgs Vt Vdsat /2) Vdsat
= (Vgs Vt )2
2
10 / 31
nMOS I-V Summary

mm
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60
80
100
120
Shockley First Order transistor models

40
Ids
0
Vgs < Vt
Cutof f
(Vgs Vt Vds /2) Vds Vds < Vdsat
Linear
=
2
(V
V
)
V
>
V
Saturation
gs
t
ds
dsat
2
60
80
11 / 31


pMOS I-V
mm
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60
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100
120
All dopings and voltages are inverted for pMOS (compared with
nMOS)
40
Mobility p is determined by holes

Typically 2x-3x lower than that of electrons n
Thus pMOS must be wider to provide the same current

60
Simple assumption,
n
p
=2
80
12 / 31
Capacitance
Capacitance in CMOS circuits
Two conductors separated by an insulator have capacitance
mm
40
60
80
100
Gate to channel capacitor is very important
120
Creates channel charge necessary for operation
Source and drain have capacitance to body

40
Across reverse-biased diodes

Called diffusion capacitance because it is associated with
source/drain diffusion
Interconnection wires also have (distributed) capacitance

60
Gate Capacitance
Approximate channel as
connected to source
Cgs = ox W L/tox = Cox W L =

80
Cpermicron W
Typical Cpermicron 2fF/m
13 / 31


Device Capacitances
The mm
dynamic response (switching speed) of a CMOS circuit is
40
60
80
100
120
very dependent on parasitic capacitances associated with the circuit
Use a simple
approximation for quick
estimates
40 of
capacitances; use tools
for extraction of more
accurate values from
actual layouts
60
Consider the
capacitances seen during
the different regions of
operation
80
14 / 31
Device Capacitances, Contd

Off Region
mm
40
60
80
100
Vgs Vt ; when the MOS device is off, only Cgb (due to the
series combination of gate oxide and depletion layer
capacitance) is non-zero.
Cgb = Cox = A/tox , where A is the gate area, and
40
= 0 SiO2
120
0 is the permittivity of free space (8.854 104 F/m), and

SiO2 is the dielectric constant of SiO2 (about 3.9)
Linear60Region
Depletion region exists, forming dielectric of depletion
capacitance, Cdep in series with Cox
As the device turns on, Cgb reduces to 0
80
The gate capacitance is now a function of the gate voltage

15 / 31


Device Capacitances, Contd

Saturated Region
Region under40the gate is 60
heavily inverted,
mm
80 and drain
100region of 120
channel pinched off, with Cgd reducing to zero
Gate capacitance is now less than Cox
40
60
Source: Mlynik and Leblebici
EPFL web-based course
Approximation
of Gate Capacitance
80
For simplicity, we can assume the gate capacitance to be
constant, Cg = A/tox
16 / 31
Diffusion (Source/Drain) Capacitance

Capacitance at the drain (Cdb ) or
source (Csb ) of a device, or when
mm is used as40a wire
60
diffusion
80
100
120
Two components:
1
An Area component
A40Peripheral (sidewall)
component
The peripheral component comes

from the depth of the diffusion
60
Assume diffusion
capacitance is
approximately Cg for
contacted
diffusion
80
It is 1/2Cg for
uncontacted diffusion
Contacted
Uncontacted
17 / 31


10
Pass Transistors
Have assumed that source is grounded
40
Whatmm
happens if source
> 0? 60
Example, pass transistor passing
VDD
Vg = VDD
40
80
100
120
If Vs > VDD Vt , Vgs < Vt

Hence, transistor would turn
itself off
nMOS
60pass transistors pull no higher than VDD Vt
Called a degraded 1
Degraded value reached slowly in a transition (low Ids )
80pass transistors pull no lower than Vtp
pMOS
Degraded 0
18 / 31
Pass Transistor Circuits

40 voltages on
60the different
80 nodes? 100
Whatmm
would be the
120
40
60
80
19 / 31


11

mm
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80
What would be the voltages on the different nodes?
100
120
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80
20 / 31

mm
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60
80
What would be the voltages on the different nodes?
100
120
40
60
80
21 / 31


12
Example 1
Assumption: initial voltage on each node is 2.5 volts
mm transistor
40parameters60are, V = 5V
80 , V = 1V
100and
Relevant
tn
dd
|Vtp | = 0.7V
120
40
60
80
22 / 31
Example 1, Contd
Vdd =
5V , Vtn = 40
1V and |Vtp |60= 0.7V
mm
80
100
120
40
60
80
23 / 31


13
Example 2
Assume: initial voltage of 0.5V on all the internal nodes
Vdd =
1.0V , Vtn =
mm
400.2V and |V
60tp | = 0.2V 80
100
120
40
60
80
24 / 31
Example 2, Contd
Assume: initial voltage of 0.5V on all the internal nodes
Vdd =
1.0V , Vtn =
mm
400.2V and |V
60tp | = 0.2V 80
100
120
40
60
80
25 / 31


14
Effective Resistance
Resistance of a bar of uniform material
L
L
R
=
=
A
t
W
mm
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60
80
where = resistivity of the material
A = cross-section of the resistor
t, W = thickness, width of the material
100
120
The channel resistance

of a MOS transistor in the linear

L
40
,
region,
Rc = k W
where k =
1
Cox (Vgs Vt )
Resistance values depend on the technology

60
Obtain
the information from the technology files
Sheet resistance (/)
Lowest for metal, increases for poly, active, highest for Well
Contact (via) resistance becomes more important as

80
processes scale down
Channel (turned-on transistor) on the order of 1000 /
26 / 31
Example of Process Parameters and Simulation

Example: TSMC 0.18 process
mm
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100
120
http://www.mosis.com/cgi-bin/cgiwrap/umosis/swp/params/tsmc-018/
Look at one process

Example of SPICE simulation
40
60
80
27 / 31


15
Resistance on a Turned-On Transistor

Circuit delay depends on resistance and capacitance delay
mm on RC 40
60
80
100
120
depends
Need to deal with the resistance of conducting transistors and
interconnects
Shockley models have limited value for obtaining resistance
40
Not accurate enough for modern transistors

Too complicated for much hand analysis
Simplification: treat transistor as resistor

60
Replace Ids (Vds , Vgs ) with effective resistance R

Ids = VRds
R averaged across switching of digital gate
Too inaccurate to predict current at any given time, but good

enough to predict RC delay
80
More
accurate values of delay obtained from detailed design
using the tools
28 / 31
RC Delay Model
Use mm
equivalent circuits
for MOS
40
60 transistors80
Ideal switch + capacitance and ON resistance
100
120
Unit nMOS has resistance R, capacitance C

Unit pMOS has resistance 2R, capacitance C
40
Capacitance
proportional to width
Resistance inversely proportional to width

60
80
29 / 31


16
Inverter Delay Estimate

mm
40
60
80
Estimate the delay of a fanout-of-1 inverter
100
120
40
60
80
30 / 31
Inverter Delay Estimate

mm
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60
80
Estimate the delay of a fanout-of-1 inverter
100
120
40
60
80
d = 6RC
31 / 31


CMOS Transistor Theory

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Introduction to VLSI Design, VLSI I, Fall 2011

4. CMOS Transistor Theory

4. CMOS Transistor Theory

of Electrical and Computer Engineering

ECE Department, University of Texas at Austin

Lecture 4. CMOS Transistor Theory

J. A. Abraham, September 7, 2011

Ensure that the circuits are robust

Predict delays and power consumption

Lecture 4. CMOS Transistor Theory

J. A. Abraham, September 7, 2011

Department of Electrical and Computer Engineering, The University of Texas at Austin

Introduction to VLSI Design, VLSI I, Fall 2011

The nMOS Transistor

Source and drain are symmetric diffusion terminals

Three regions of operation: Cutoff, Linear, Saturated

Lecture 4. CMOS Transistor Theory

J. A. Abraham, September 7, 2011

Modes in nMOS Structure

ECE Department, University of Texas at Austin

Lecture 4. CMOS Transistor Theory

J. A. Abraham, September 7, 2011

Department of Electrical and Computer Engineering, The University of Texas at Austin

Introduction to VLSI Design, VLSI I, Fall 2011

nMOS Transistor Operation

Lecture 4. CMOS Transistor Theory

J. A. Abraham, September 7, 2011

Conducting nMOS Transistor

No significant current through the substrate because of reverse

Lecture 4. CMOS Transistor Theory

J. A. Abraham, September 7, 2011

Department of Electrical and Computer Engineering, The University of Texas at Austin

Introduction to VLSI Design, VLSI I, Fall 2011

nMOS Device Behavior

ECE Department, University of Texas at Austin

Lecture 4. CMOS Transistor Theory

J. A. Abraham, September 7, 2011

The pMOS Transistor

Moderately doped n- type

Application of a negative gate voltage (w.r.t. source) draws

ECE Department, University of Texas at Austin

Lecture 4. CMOS Transistor Theory

J. A. Abraham, September 7, 2011

Department of Electrical and Computer Engineering, The University of Texas at Austin

Introduction to VLSI Design, VLSI I, Fall 2011

Current in the Channel

ECE Department, University of Texas at Austin

Lecture 4. CMOS Transistor Theory

J. A. Abraham, September 7, 2011

Charge is carried by electrons

Time for carrier to cross channel: t = L/

ECE Department, University of Texas at Austin

Lecture 4. CMOS Transistor Theory

J. A. Abraham, September 7, 2011

Department of Electrical and Computer Engineering, The University of Texas at Austin

Introduction to VLSI Design, VLSI I, Fall 2011

nMOS Saturation I-V

Now drain voltage no longer increases with current

ECE Department, University of Texas at Austin

Ids = (Vgs Vt Vdsat /2) Vdsat

J. A. Abraham, September 7, 2011

nMOS I-V Summary

Shockley First Order transistor models

Cgs = ox W L/tox = Cox W L =

0 is the permittivity of free space (8.854 104 F/m), and