Tempus141 TSO Slides PDF

Tempus 14.
1 Training:
Timing Signoff Optimization (TSO)
June 2014
Content
1. Feature Overview
2. Use Model
3. Incremental Timing Closure
4. Hierarchical Timing Closure
5. Path-based Analysis Optimization
6. Master Clone Optimization
Copyright 2014 Cadence Design Systems, Inc. All Rights Reserved.
Content .. Contd.
7. Routing Congestion-aware Optimization
8. Selected Endpoints Optimization
Special Sections
Whats New in Tempus 14.1 TSO

EDI 14.1 Signoff Timing Closure using Tempus 14.1 TSO
1. Feature Overview
Tempus TSO Advanced Capabilities

Address the timing closure challenges introduced from the increased analysis
complexities and capacities!
Standard Features
Tempus
Built-in signoff delay and SI analysis
Distributed or concurrent MMMC
Physically aware optimization
Legalized / DRC clean placement directives
Hierarchical or flat ECO generation
Optimized MMMC timing graph for fast and

high capacity optimization
Graph or path based optimization
Common timing engine within

implementation
New Features in Tempus TSO 14.1
On-route buffering
Master / Clone support
Multi-threaded ECO db generation
20nm/16nm design rule compliant
Place and route
Physically
aware ECO
2-3
Iteration
Physical
view
(LEF/
DEF)
Tempus TSO
Distributed
MMMC
delay
calculation
and STA
Physicallyaware
optimization
Hold, DRV,
setup,
leakage
Timing closed
Timing Closure Flow

In a flat design flow, Tempus Timing Signoff
Optimization (TSO) is for final signoff timing closure
Timing
Met?
Post CTS
Setup/Hold Fixing
Timing
Met?
Physical
Verification
Routing
Post Route
Setup/Hold Fixing
SI
Setup/Hold Fixing
SIGNOFF
Pre CTS
Setup Fixing
Clock Tree
Synthesis
POST ROUTE FLOW
Timing, Mode
Setup
JTAG/Cell
Placement
POST CTS FLOW
Load
Floorplan
PRE CTS FLOW
DESIGN INITIALIZATION
Design Import
Scan
Defintion
Timing Analysis
Tempus TSO
ECO
Timing Analysis
Timing
Met?
GDSII
Hierarchical Timing Closure Flow
Timing
Setup
Partition
Definition
Partition Pin
Assignment
Design
Initialization
Pre-CTS
Flow
Post-CTS
Flow
Post-Route
Flow
SI
Setup/Hold Fixing
Timing
Met?
Opt Virtual /
Budgeting
Partitioning
Design
Initialization
Pre-CTS
Flow
Post-CTS
Flow
Post-Route
+ SI Flow
Model
Generation
Timing
Met?
ASSEMBLY & SIGNOFF
Clock / Latency
Specification
JTAG / Cell
Placement
BLOCK IMPLEMENTATION
DESIGN INITIALIZATION
Load
Floorplan
VIRTUAL PROTOTYPING
Design Import
TOP IMPLEMENTATION
In a hierarchical design flow,

Tempus TSO is for final full-chip
signoff timing closure
Assemble
Design
Signoff Extraction
Timing Analysis
Tempus TSO
ECO
on full flat DB
Signoff Extraction
Timing Analysis
GDSII
Why Tempus TSO?

Motivations overview
In signOff environment, designers always find some remaining
timing violations that must be cleaned up :
- Block level vs top level timing analysis do not match. Timing model difference.
- Timing budgeting is not precise or not always done (for Hold timing).
- Over fixing is killing, thus counting on SignOff stage to catch/fix real violations.
- Additional corners or modes added in SignOff stage.
- Implementation tools cannot optimize timing with full SignOff STA precision
Complementary solution to the timing closure at implementation stage.

Need for such feature to fix remaining violation in SignOff STA environment
Technology trend
The timing environment is getting more and more complex :
- Many clocks because of many functions.
- Complicated timing exception because of many functions.
- Large number of MMMC views ( > 100 views).
- Large Hierarchical and MSV designs ( > 100M gates) .
This is leading to runtime and memory explosion. There is a need for a more
efficient data management to allow increasing tool capacity.
8
Tempus TSO Features Highlights

Feature highlights
- Focus on timing convergence by being MMMC-aware, STA SignOff aware and SI-aware
- By default this feature is Physical-aware. No placement legalization needed
- Concurrent and distributed timing analysis. Highly scalable
- Smart Bottleneck analysis algorithm to target minimal netlist change
- The local density and routing congestion are considered when adding buffers
- Support for MSV and Hierarchical based designs (including different row height)
- Native support for replicated hierarchies (also named Master/Clone optimization)
- Need only one single ECO loop to close timing
- Very large capacity in netlist size (>200M gates) and number of active views timed (>100)
Input data
Technology data
Design data
Physical data
(Can load EDI DB)
Tempus TSO
Buffering, Vth Swapping and Sizing
Violations fixed :
Hold timing violations
Setup timing violations
Design Rule Violations
(max_cap/max_tran)
Leakage power reduction
Output data
Detailed reporting on all ECOs
being performed
Detailed diagnostic report on
remaining violations not fixed
Standard format ECO file
Final timing summary reports
Front-to-back Physical Aware Timing Closure
Logical only
SignOff ECO
Timing
Closure
Why would you accept to
lose accuracy/predictability
when reaching SignOff
stage ?
10
Physical
Aware
Synthesis
Routing
aware
Placement
&
Timing
Optimization
Physical &
Routing Aware
SignOff ECO
Timing
Closure
Predictable and
convergent flow !
RC-EDI-Tempus Front to Back

implementation flow
Routing
aware
Placement
&
Timing
Optimization
Traditional Front to Back implementation flow
Physical
Aware
Synthesis
Benefit of Tempus TSO Physical-awareness

The goal is to improve correlation between evaluated timing during
ECO and real timing after place&route loop by :
-
Performing legal location checks during buffer insertion and output coordinates in the
ECO file to be reused by the implementation tool.
Taking in account routing information when adding buffer.
Buffer
insertion
Legalization
Legalization
Non-Physical Mode
Buffer
insertion
Physical Mode
11
Difficult to predict the timing impact of placement refinement !
Buffer is already getting legal location from Tempus
No move would happen later on in place&route
Routing estimations are more precise
On Which Design Style Can It Be Used?

Hierarchical flow
Block implementation
Interface
CPU1
B
U
S
CPU2
Very large flat netlist
CPU
R
A
M
Fix the inter-partition timing

violations, after assembling
the design, on the full flat DB
Small amount but large
violations to be fixed
Challenge is on capacity,
TAT and TopLevel buffering
Network
Fix the real remaining

violations in SignOff STA tool
to avoid adding pessimism in
implementation tool
Timing violations to fix are
probably small and not too
many. Can recover leakage.
Flat implementation of very

large netlist where Hold fixing
only done with SignOff ECO
feature to avoid
capacity/runtime issue
Need precise fixing

without creating any Setup
violations and make usage of
physical-aware techniques
Above several 100k

violations to be fixed with
physical-aware techniques in
reasonable runtime and Mem
Integrated solution enables Signoff Timing Closure in different design

methodologies
12
Tempus TSO Architecture

Logical
Design
MMMC
Views
Physical
Design
Physically aware for

legalized placement
Tempus TSO
Distributed MMMC Timing/SI Analysis
view 1
view 2
view 3
Optimization across all

parameters to eliminate
new violations
view n
MMMC Optimization Engine

Hold
Leakage
P&R
System
DRV
Distributed processing
maximizes analysis
performance
Setup
ECO file
Single-pass MMMC Signoff ECOs

with simultaneous optimization across all MMMC views
13
2. Use Model
14
Tempus TSO ECO Flow

Tempus cockpit
Distributed SignOff Timing Analysis

Tempus TSO
ECO file
Convergent
timing closure
flow
(eco_edi.tcl)
EDI cockpit + QRC
ECO Route
SignOff RC Extraction
SPEF files
Verilog
Tempus cockpit

15
Timing reported
in Tempus after
optimization step
will be very close
to the one
measured at the
end of the full
P&R flow
The ECO File Result From Tempus TSO
16
The Tempus TSO Use Model

Use model overview :
Simple command to access all the timing/power optimization capabilities
Tool will automatically switch the Physical-aware when Physical data are loaded
Reusing the distributed processing management settings already
available (and used by D-MMMC)
set_multi_cpu_usage/set_distribute_host
To set the distributed MMMC environment
write_eco_opt_db
To save ECO Timing DB files, containing timing information per view
set_eco_opt_mode
To pilot ECO timing closure with any specific options
eco_opt_design [-hold] [-drv] [-leakage] [-setup] \

[-help] [-analysis_script <file>]
To run either DRV or Hold or Setup and Leakage optimization
17
Main Command For Tempus TSO

eco_opt_design [-hold] [-drv] [-leakage] [setup]
[-analysis_script <file>] [-help]
Description:
This command triggers the MMMC SignOff ECO.
depending on the set_eco_opt_mode settings, it will either auto generate the
ECO timing db or load existing one, then proceed to the timing fixing phase
and finally output an ECO file and detailed diagnostics.
The analysis_script option is mandatory (see next slide).
Output:
This command will generate the eco_edi.tcl file which should be used in
EDI to perform place&route. It also generates eco_tempus.tcl file which can
be sourced in Tempus to do timing analysis after ECOs
Example:
eco_opt_design -hold analysis_script sta.tcl

This will perform Hold fixing while not degrading Setup timing.
Notes:
It is important to correctly set up the timing environment and multiCPU settings
before running this command.
18
Main Command Mandatory Option (1/2)

eco_opt_design analysis_script <file>
Description:
This mandatory option allows to provide a file containing instructions to load
the SPEF files for every active RC corner.
This file may also contain information to enable SI analysis, when needed.
Example of file to be passed to analysis_script option:

read_spef -rc_corner rc_max max.spef.gz
read_spef -rc_corner rc_min1 min1.spef.gz
This will instruct the tool on how to load the SPEF files.
Notes:
When no SI analysis instruction are provided, the tool will perform
non-SI signOff timing analysis.
The file provided through -analysis_script option should be similar to the file one
would use for D-MMMC (and provided through -script option for
command distribute_views )
19
Main Command Mandatory Option (2/2)

eco_opt_design analysis_script <file>
Example of file to be passed to analysis_script option for SPEF

loading + SI analysis settings:
set_delay_cal_mode -SIAware true
This will instruct the tool on how to load the SPEF files and
what are the settings that should be used for SI analysis.
Notes:
To perform SI analysis/fixing, SPEF must contain the coupling capacitance data.
20
Fixing DRV Timing Violations

eco_opt_design -drv -analysis_script <file>
Description: When specifying the -drv option, eco_opt_design will fix the
max_cap and max_tran violations by ensuring minimal Setup timing impact. The fixing
is done through buffering by default, but also through resizing as an optional technique.
Fixing method: Buffering (default) and resizing.
Examples:
set_eco_opt_mode resize_inst true

eco_opt_design drv analysis_script spef.tcl
This will perform DRV fixing by using buffering and resizing techniques.
set_eco_opt_mode drv_margin -0.1
This will perform DRV fixing on all the max_cap/max_tran violations that are violating by more
than 10% of the target.
21
Fixing Hold Timing Violations

eco_opt_design -hold -analysis_script <file>
Description: When specifying the hold option, eco_opt_design will fix the Hold
timing violations by ensuring no Setup or DRV timing degradation.
The following Hold fixing capabilities are worth to mention :
Perform Vth swapping (sizing between cells of the same physical footprint)
Taking advantage of Hold Friendly and de-skewed sequential elements
Ability to resize existing buffers in to delay cells
Fixing method: Buffering (default), Vth swapping and resizing.

Examples:
set_eco_opt_mode swap_inst true

eco_opt_design hold analysis_script spef.tcl
This will perform Hold fixing by using Vth swapping and buffering techniques.
set_eco_opt_mode swap_inst true resize_inst true
This will perform Hold fixing by using Vth swapping, buffering and resizing techniques on
combinational cells.
22
Fixing Setup Timing Violations

eco_opt_design -setup -analysis_script <file>
Description: When specifying the -setup option, eco_opt_design will fix the
Setup timing violations by ensuring no impact on Hold timing and DRV. The fixing is
done through Vth swapping by default, but also through resizing and buffering as
optional technique.
Fixing method: Vth swapping (default), buffering and resizing.

Example:
set_eco_opt_mode resize_inst true add_inst true

eco_opt_design setup analysis_script spef.tcl
This will perform Setup fixing by using Vth swapping , buffering and resizing techniques.
Notes:
23
When resizing instances, tool will look for legal locations so that the ECO file generated would
not lead to any overlapping instances.
Reducing Leakage Power

eco_opt_design -leakage -analysis_script <file>
Description: When specifying the -leakage option, eco_opt_design will reduce
leakage power by ensuring no impact timing and DRV. The power reduction is done
through Vth swapping on combinational cells by default, but also on sequential
elements as an optional technique.
Examples:
eco_opt_design leakage analysis_script spef.tcl
This will perform Leakage power reduction by performing Vth swapping on combinational cells.
set_eco_opt_mode -optimize_sequential_cells true
eco_opt_design leakage analysis_script spef.tcl
This will perform Leakage power reduction by performing Vth swapping on all standard cells
Notes:
24
Instances marked as Fixed can be Vth swapped. To avoid that, one can apply dont_touch
attribute on those instances.
The command set_power_analysis_mode -view <view> allows to choose in which
corner must be used to collect the leakage power numbers (can be a non-active view).
Two supported use model flows

Fixing timing with embedded Distributed TA
In this mode the tool will load the design/libraries data, run Distributed TA to collect the
timing information per view, then optimize timing and finally re-time the design based
on the ECO change committed
This is the simplest use model since all is automated.
It requires that the number of CPUs available is superior or equal to the amount of
Setup + Hold unique active views.
Fixing on existing ECO timing DB
25
In this mode the tool will load the design/libraries data, then read the previously
generated ECO timing db, then optimize timing and report the final timing based on the
evaluated timing.
This allows the user to run fixing on many more views, since there is no limit in the
amount of active views.
This approach leads to a smaller memory footprint than above one.
Script Example of Embedded TA Mode TSO

Timing fixing with embedded Distributed TA using Physical-aware mode:
Read_view_definition $viewdef_file
read_lib lef $lef
read_verilog $netlist
set_top_module
read_def $def_file
set_distribute_host -local
set_multi_cpu_usage -localCpu 8
When both LEF and DEF files are

provided or initial data loaded with
read_design physical_data,
the tool will automatically
run in Physical-aware mode
set_eco_opt_mode buffer_cell_list BUFX1 BUFX2 BUFX4 BUFX6 BUFX8 DLYX1

DLYX2 DLYX4"
eco_opt_design hold analysis_script sta.tcl
Note :
The sta.tcl must contain read_spef command for every active rc_corner, and SI
analysis settings in case SI timing is requested for SignOff
26
Script Example of 2-pass flow

Session 2
Session 1
ECO timing DB generation using D-MMMC :
set_distribute_host local
Same script
can be used
distribute_read_design \
-design_script loadDesign.tcl -outdir .
distribute_views -views $setup_and_hold_views \
-script sta.tcl
Timing fixing using previously generated

ECO timing DB :
source loadDesign.tcl
set_analysis_view setup [list $setup_views] \
hold [list $hold_views]
set_distribute_host local
set_eco_opt_mode load_eco_opt_db mySignOffTGDir
Content example for sta.tcl :
Same script
can be used

set_eco_opt_mode save_eco_opt_db mySignOffTGDir
write_eco_opt_db
eco_opt_design hold analysis_script sta.tcl

OR
eco_opt_design drv analysis_script sta.tcl
OR
eco_opt_design leakage analysis_script sta.tcl
Note :
The eco_opt_design command will automatically skip the set_eco_opt_mode and
write_eco_opt_db commands from sta.tcl file since ECO timing DB information is already provided.
The loadDesign.tcl must contain Physical data to ensure fixing is done in Physical-Aware mode
27
3. Incremental Timing Closure
28
Incremental ECO Functionality

Example 1
Scenario: Customer wants to
fix Hold first at Top level and
then at Block level
Tempus
Example 2
fix DRV, then Hold and then
Setup in one session
Tempus
Example 3
fix Hold with specific buffers
and then fix Setup with Vth
Swapping only
Tempus
set_dont_touch PTN* true
DRV fixing ECO1
Buffer cell list with DLY*
Hold fixing ECO1
Hold fixing ECO2
Hold fixing ECO1
set_dont_touch PTN* false
Setup fixing ECO3
Allow only Vth swapping
Hold fixing ECO2
Setup fixing ECO2
Very flexible use model which allows any combination of DRV, Hold and Setup
optimization in one single Tempus session
29
Incremental ECO Functionality (2)

set_eco_opt_mode -allow_multiple_incremental true
Description: This option allows the user to run several eco_opt_design
commands in a row using the same initial ECO Timing DB. In the same session, the
user can fix Setup, Hold and DRV violations. An ECO file is generated per
eco_opt_design call.
Default: false
Example:
set_eco_opt_mode load_eco_opt_db ECOdb

set_eco_opt_mode allow_multiple_incremental true
set_eco_opt_mode -eco_file_prefix DRV_FIX
set_eco_opt_mode -eco_file_prefix HOLD_FIX
This will perform DRV fixing followed by Hold fixing, while giving a different prefix for the ECO files.
Notes:
30
The leakage option is not supported in incremental mode and no intermediate timing reports
can be done in betweens eco_opt_design commands.
The ECO files must then be later sourced in the same order as they were generated.
4. Hierarchical Timing Closure
31
Hierarchical Design Chip Finishing

Top Level and block level Verilog/DEF/SPEF are loaded in Tempus to perform full flat
timing analysis in MMMC
Tempus TSO can perform timing optimization in any of the following way:
Fix timing at Top Level only
Fix timing at Top Level and in any, or all, partitions
Interface
Top
Level
M
E
M
CPU
.v
.def
.spef
.v
.def
.spef
B
U
S
.v
.def
.spef
.v
.def
.spef
Top Level fixing only
.v
.def
.spef
Tempus
Interface
CPU1
Native support for

replicated
hierarchies
CPU2
B
U
S
M
E
M
Buffering is logical and physical hierarchy aware
Tempus TSO
Partition interface is unchanged

ECO
Top
Level
32
ECO
Interface
ECO
CPU
ECO
MEM
ECO
BUS
Can output an ECO file per partitions/topLevel
Generating a Per-Partition ECO File

set_eco_opt_mode -partition_list_file <file>
Description: The -partition_list_file option allows the user to select the
modules that should be treated as partitions. The file provided to this option must
contain a list of cells name of such modules. The eco_opt_design would then
generate an ECO file per top and partitions (with relative locations).
Default: empty
Examples:
set_eco_opt_mode partition_list_file partition.txt

This will perform Hold fixing and treat every cell listed in the partition.txt file as partition.
Notes:
33
It is mandatory that the modules that must be treated as partitions are of type FENCE.
To avoid doing any ECO in a given partition, one need to apply dont_touch on that module.
To perform top level only buffering, one need to apply dont_touch on every partitions.
Assembling a Design in Tempus

merge_hierarchical_def <top and block def files>
Description: This command allows the user to load DEF files for the modules that is
currently treated as a black box (represented by LEF/LIB). This command is needed for
Hierarchical designs in order to assemble the top level database with all the block level
databases. The tool will automatically create a FENCE for every partition loaded.
Default: empty
Examples:
merge_hierachical_def {top.def ptn1.def}
This will assemble the ptn1 block level database to the top level database already in memory.
34
Hierarchical Chip Finishing Example

Example for a design with two partitions (ptn1 and ptn2) :
read_lib $liberty
read_lib lef $cell_lef ptn1.lef ptn2.lef
read_verilog my_top.v ptn1.v ptn2.v
set_top_module my_top
merge_hierarchical_def {my_top.def ptn1.def ptn2.def
source viewDefinition_and_derating.tcl
set_eco_opt_mode load_eco_opt_db myECODB

Content example for partition.txt :

tdsp_core
test_control
Content example for spef.tcl :

read_spef -rc_corner rc_max my_top_max.spef ptn1_max.spef ptn2_max.spef
read_spef -rc_corner rc_min1 my_top_min1.spef ptn1_min1.spef ptn2_min1.spef
read_spef -rc_corner rc_min2 my_top_min2.spef ptn1_min2.spef ptn2_min2.spef
Notes :
1) Must provide pointer to ECO DB since D-MMMC cannot be used with merge_hierarchical_defs
based flow.
2) When loading one full flat DEF/Verilog, the partition LEFs must not be provided, but the full flat DEF has
to contain FENCEs definition for the modules that should be treated as partitions.
35
5. Path-based Analysis Optimization
36
Path-based Analysis Mode Support

Tempus TSO supports timing optimization in Path Based Analysis including SI mode
The different types of Path Based Analysis supported are :
aocv : Re-timing the timing critical paths using the AOCV derating factors
path_slew_propagation : Re-timing the timing critical paths using the actual slews for the path
aocv_path_slew_propagation : Combination of re-timing with aocv + path_slew_propagation
waveform_propagation : Re-timing with waveform effect taken into consideration during delayCal
Hold fixing in PBA (path_slew_propagation) vs GBA
Gain in added area
Gain in number of inserted buffers
Design 1
4.7%
4.3%
Design 2
0.4%
0.45%
Design 3
2.3%
2.8%
Design 4
5.7%
6.6%
Applying Path Based Analysis allows to remove some timing

pessimism and leads the tool to fix only the real timing violations
37
Path-based Analysis leakage power results
High Speed Core design, 32nm technology

Analysis Mode
Total Leakage
Graph Based Analysis
300mW
Path Based Analysis
264mW
Sequential
cells
Combinational
cells
25mW
191mW
18mW
164mW
12%
Improvement
Block Level
1.2M instances, 45nm technology, 95% of initial low VT cells
7 Hold views and 7 Setup views
Analysis Mode
Number of Cells
swapped
% of Low VT to HVT
conversion
Setup degradation
MSV or Placement
violations
GBA-SI
0.8M
75%
None
None
PBA-SI
1M
93%
None
None
38
18%
Improvement
Path-based Analysis Mode Support

PBA related options:
set_eco_opt_mode \
-retime <aocv | path_slew_propagation | aocv_path_slew_propagation >
# Default =
-check_type early | late
# Default =
-max_slack <slack in lib_unit>
# Default =
-max_paths <paths>
# Default =
-nworst <nworst>
# Default =
early
0
500000
50
Notes : Those options are only honored when set_eco_opt_mode retime is being activated.
Examples:
set_eco_opt_mode -retime path_slew_propagation -check_type late
write_eco_opt_db
This will generate ECO DB with Setup timing being done in PBA path_slew_propagation mode
set_eco_opt_mode -retime aocv
write_eco_opt_db
This will generate ECO DB with Hold timing being done in PBA aocv mode
39
6. Routing Congestion-aware
Optimization
40
Routing aware buffering for Hold fixing

set_eco_opt_mode routing_congestion_aware true
Description: The routing_congestion_aware option allows to force the
buffering to avoid inserting buffers in areas where routing congestion is already very
high. The goal is to not cause new routing DRC due to ECO buffering as well as
avoiding routing detour for new ECO nets.
Default: false
Examples:
set_eco_opt_mode routing_congestion_aware true

This will perform Hold fixing in routing congestion aware mode.
Notes:
41
This option may lead to worse Hold timing closure when design has routing congestion but it will
limit potential Setup timing degradation and routing DRC increase after full place&route loop.
This option applies only for Hold fixing since this is where buffer count inserted is usually high.
Routing-aware Buffering For Hold Fixing (2)

Customer example
Default mode
Initial DB
New routing DRC hotspot created
Setup timing degradation
Congestion map
SETUP : WNS = -0.8ns, TNS = -10ns

HOLD : WNS = -0.6ns, TNS = -2.3ns
Routing DRC = 324
Routing DRC markers
Congestion aware mode

No new routing DRC
Very limited Setup timing impact
SETUP : WNS = -0.8ns, TNS = -4ns

HOLD : WNS = -0.9ns, TNS = -96ns
Routing DRC = 40
42
SETUP : WNS = -0.8ns, TNS = -5.6ns

HOLD : WNS = -0.8ns, TNS = -26ns
Routing DRC = 25
7. Master Clone Optimization
43
Master/Clone timing optimization

Overview
Hierarchical implementation with Master/Clones
Common blocks/duplicated functionality built and verified once (master) and
instantiated multiple times (clones) in design
Keeping a non-uniquified netlist makes easier the scope and breadth of late logic
changes, reducing the critical path turn-around time and re-verification required to
achieve final signoff
Reduces work load and data storage
A cloned block is implemented such that it can operate in the worst-case corner
scenario in any of its instantiation but once assembled in its top level, the full flat
STA might reveal new timing violations.
Master/Clones timing optimization is needed because each clone can have:
Different physical environments ( like different IO loads )
Different timing environments (like change in clock slew/skew/OCV between blocks and
flat)
Different Signal Integrity environments
44
Why does Master/Clone support help ?

No Master/Clone support
Only top level is optimized
All CPU modules will be dont_touch
Cpu1 Cpu2
(cellA)
(cellA)
Top
Cpu3 Cpu4
(cellA)
(cellA)
Uniquified netlist
Cpu1 Cpu2
(cellA1) (cellA2)
Top
Cpu3 Cpu4
(cellA3) (cellA4)
With Master/Clone support

Cpu1 Cpu2
(cellA)
(cellA)
Top
Cpu3 Cpu4
(cellA)
45
(cellA)
Timing optimization with sub-optimal QOR

Top and CPUs are optimized
Each CPU will get a unique ECO file
ECOs from one CPU may degrade
timing when applied on the other CPUS
Which CPU ECO file for implementation ?
Top and CPUs are optimized
One ECO file for all CPUs
ECOs generated are valid for each
CPUs timing context
Optimal timing closure for full flat timing !
Master/Clone timing optimization

Definitions
- Tool is able to fix DRV/Hold/Setup/leakage with
buffering/resizing/VthSwapping.
- Only one unique DEF/Verilog for a Master/Clone, even after timing
optimization. There is only one ECO file per Master/Clone.
- Timing closure happens outside master/clone as much as possible.
- Timing closure can happen inside master/clone but also on boundary paths.
- Any netlist change done in a Clone is checked in every other Clone to ensure
no timing degradation and no placement violation in their respective physical
context .
- Performance and capacity are maintained :
QOR of eco_opt_design with clones should be as close as possible to what

would be obtained on the uniquified netlist or with customers manual flow which
consist in optimizing only one clones (others are dont_touch) and then replicate the
ECO in all clones identically.
TAT of eco_opt_design with clones should be similar to same design with

uniquified netlist.
46
No impact on memory usage
Basic example of Master/Clones implementation

Z1
Top
Block1 (cellA)
(CellA)
Block2 (cellA)
FF2
FF2
O1
FF1
FF1
In1
O1
In1
Z2
T1
I0
I1
Physical/timing context is different for every Clones boundary

Timing optimization must work on any kind of paths :
from FF1 to FF2 on all clones or inter-clones paths too (if any)
from Top/T1 to Block1/FF1 and from Top/T1 to Block2/FF1
from Block1/FF2 to Top/Z1 and from Block2/FF2 to Top/Z2
Paths crossing multiple clones like Block1/FF2 to Block2/FF1
Buffering can happen on any nets, even nets crossing clones boundary.
47
How to enable Master/Clone support ?

set_eco_opt_mode optimize_replicated_modules true
Description: By enabling the optimize_replicated_modules option, the tool will
be able to optimize timing in the replicated modules. Any netlist change will be checked
against each clones timing and physical context to ensure that no violations are created.
In this mode only one ECO file is generated per group of clones. It is mandatory to list the
cell name of the clones inside the file provided to partition_list_file option.
Default: false
Examples:
set_eco_opt_mode optimize_replicated_modules true

set_eco_opt_mode partition_list_file partitions.txt
This will perform Hold fixing and the replicated modules of the cell listed in the partition list file will be
treated as clones.
Notes:
48
The design must be assembled in EDI (through assembleDesign command) or in Tempus

(through the read_partition command).
Mechanism to load Master/Clone design

Two possible flows
EDI
restoreDesign
Tempus
assembleDesign
Load top level data

read_partition
Encounter DB
Tempus
read_design
ECO fixing
running in
Master/Clone
aware mode
set_eco_opt_mode
eco_opt_design
set_eco_opt_mode
eco_opt_design
Run first EDI to assemble the design,

block by block, and then run Tempus to
load the full DB to perform ECO fixing.
Run Tempus to assemble the

design, block by block, and then run
ECO fixing
The read_def command in Tempus should not be used to assemble a hierarchical design
49
Master/Clones flow use model

Example for a design with two clones (Block1 and Block2) :
read_lib $liberty
read_lib lef $all_lef
read_verilog my_top.v cellA.v
set_top_module my_top
Design example:
Or
Top
read_design top.enc \
physical_data
Block1 (cellA) Block2 (cellA)
merge_hierachical_def {my_top.def cellA.def}

source viewDefinition_and_derating.tcl
set_eco_opt_mode load_eco_opt_db myECODB
set_eco_opt_mode -optimize_replicated_modules true
Content of partition.txt :
cellA
Content example for spef.tcl :

read_spef -rc_corner rc_max my_top_max.spef cellA_max.spef
read_spef -rc_corner rc_min1 my_top_min1.spef cellA_min1.spef
read_spef -rc_corner rc_min2 my_top_min2.spef cellA_min2.spef
Notes :
1)
2)
3)
50
Must provide pointer to ECO DB since embedded D-MMMC ECO flow cannot be used with
merge_hierarchical based flow.
Mandatory to provide the partition LEF when loading the top level design. A basic LEF for a block can
be easily generated using lefOut in EDI
When replicated instances have different orientation, the design must be assembled in EDI or in
Tempus, because loading one full flat DEF/Verilog will not work.
Full ECO loop flow for Master/Clones

Tempus cockpit

MMMC SignOff ECO (with Master/Clones)
ECO file
Top_edi.tcl
ECO file
cellA_edi.tcl
Design example:
Top
Block1 (cellA) Block2 (cellA)
EDI + QRC
EDI + QRC
ECO Route
ECO Route
SignOff RC
Extraction
SignOff RC
Extraction
SPEF files
Verilog
SPEF files
Verilog
Tempus cockpit

51
Master/Clones implementation with rotation

Top
Block1 (cellA)
Block2 (cellA)
Block3 (cellA)
Block4 (cellA)
Clones can be mirrored on the X or Y direction : R0 , R180 , MX and MY

No support for R90 /R270 rotation (which is anyway not recommended by
foundries)
52
Master/Clones at multi-levels
Top
T/B1/A0 (cellC)
T/B1/A1 (cellC)
T/B1/A3 (cellC)
T/B1/A2 (cellC)
T/B1 (cellA)
T/B2 (cellB)
T/B2/A0 (cellC)
T/A0 (cellC)
Master/Clones can be inside any level of

hierarchy and part of different modules
(size/shape)
Timing optimization gives priority to netlist
change at higher hierarchy levels, to limit
impact on clones.
A net can drive multiple clones in multiple
hierarchies
Top
T/B1/A0 (cellC)
T/B1/A1 (cellC)
T/B1/A3 (cellC)
T/B1/A2 (cellC)
T/B2/A0 (cellC)
T/B2/A1 (cellC)
T/B2/A3 (cellC)
T/B2/A2 (cellC)
T/B1 (cellA)
T/B2 (cellA)
53
Multiple levels of Master/Clones can be

assembled
Timing optimization and placement
supports such scenario
Timing optimization gives priority to netlist
change at higher hierarchy levels, to limit
impact on clones.
Master/Clones with Channel-less floorplan

T/B1/A0 (cellC)
T/B1/C0 (cellD)
T/B1 (cellA)
T/B1/A1 (cellC)
T/B1/A2 (cellC)
T/B1/C1 (cellD)
T/B1/A3 (cellC)
T/B2/A0 (cellC)
T/B2/C0 (cellD)
T/B0 (cellB)
T/B2 (cellA)
T/B2/A1 (cellC)
T/B2/A2 (cellC)
T/B2/C1 (cellD)
T/B2/A3 (cellC)
T/B3/A0 (cellC)
T/B3/C0 (cellD)
T/B3 (cellA)
T/B3/A1 (cellC)
T/B3/A2 (cellC)
T/B3/C1(cellD)
T/B3/A3 (cellC)
No netlist change possible at Top. ECO allowed only in sub-blocks

Timing optimization gives priority to netlist change at higher hierarchy levels
By construction, ECO buffering does maintain Logical/Physical Hierarchy
54
Master/Clone impact on log verbosity

Reporting information on how many clones were detected for the cells listed
in the partition_list_file option.
Current log :
*info: reading partition list file partitions.txt
**WARN: Ignoring multi-instantiated partition seq_logic
*info: 1 clock net
excluded from eco_opt_design operation.
**WARN: (ENCECO-560):
Netlist is not unique. Cell "seq_logic" is a multiinstantiated cell. Uniquify your netlist to avoid the problem.
*info: 4 ununiquified hinsts
New log :
*info: reading partition list file partitions.txt
*info: 1 clock net
excluded from eco_opt_design operation.
*info: following replicated instances will be optimized in Master-Clone mode

*info: module seq_logic (4 replicated instances)
55
Master/Clone impact on failure diagnostic

In the diagnostic report, each failure category will now also report how many nets
are in replicated hierarchies.
Without Master/Clone support :
*info:
*info:
*info:
4000 net(s): Could not be fixed because they would "degrade design setup WNS".
32 net(s): Could not be fixed because hold improving moves not found.
662 net(s): Could not be fixed because they are in or around non-unique modules.
With Master/Clone support :

*info:
4615 net(s) ( 615 master clone net(s) ): Could not be fixed because they would
"degrade design setup WNS".
*info:
47 net(s) ( 47 master clone net(s) ): Could not be fixed because they would
"Degrade DRV violations".
*info:
32 net(s): Could not be fixed because hold improving moves not found.
For each remaining violated cloned net, the clone causing the reason for not
fixing the violation is printed .
CPU1/N122 (In context CPU3)
CPU2/N23143 (In context CPU3)
Note : Failure report on nets inside clones is printed only one time and not as
many times as there are clones.
56
8. Selected Endpoints Optimization
57
Selected endpoints optimization & Margins

specification
Supported for hold/setup optimization
Endpoint based inclusion/exclusion per view
Endpoint based slack adjustment per view (both +ve and -ve adjustments )
Option to fix only register to register paths
Specification of endpoints can be done by:
o list of space separated endpoints : E1 E2 E3
o E* for all endpoints
o slack range : <minSlack> <maxSlack> (specified in nanosecond)
View specification can be done by:
o View name
o V* for all views ( may not be applicable in some scenarios )
58
Endpoint based inclusion/exclusion per view

Use model:
set_eco_opt_mode -select_hold_endpoints <file containing
inclusion/exclusion configuration for hold fixing>
set_eco_opt_mode -select_setup_endpoints <file containing
inclusion/exclusion configuration for setup fixing>
Format :
<View> include/exclude <Endpoints>
create a file ( for inclusion/exclusion for hold ) where lines starting with # are
comments and would be skipped
# Exclude endpoints inst1/SE and inst2/SE from view VIEW1
VIEW1 exclude inst1/SE inst2/SE
# Include only the endpoints that have slacks >= -0.5 ns and <= 0.04 ns for view VIEW2
VIEW2 include -0.5 0.04
59
Endpoint specific slack adjustment per view

Use Model:
set_eco_opt_mode -specify_hold_endpoints_margin <file
containing margin configuration for hold fixing>
set_eco_opt_mode -specify_setup_endpoints_margin <file
containing margin configuration for setup fixing>
Format :
<View> <margin> <EndPoints>
<margin> is a float value and is in nanoseconds. Margin value is subtracted
from the endpoint slack so a positive margin means that the endpoint slack
would be degraded by the margin amount.
60
Endpoint specific slack adjustment per view Contd.

Create a file for hold or setup margins where lines starting with # are
comments and would be skipped
# Apply margin of 0.1ns to all endpoints that have slacks between (

inclusive ) -0.07 to -0.03 for all views
V* 0.1 -0.07 -0.03
# Apply margin of 0.2 nanosecond to all endpoints for view VIEW1
VIEW1 0.2 E*
# Apply margin of 0.6 ns to endpoints inst1/SE and inst2/SE in view
VIEW2
VIEW2 0.6 inst1/SE inst2/SE
61
Priority Order for Margin Specification

View specific margin for endpoint where view and endpoints are both
specified by names ( view is not V*, endpoint is not E* or slack range )
VIEW1 0.05 inst1/SE
Margin for a specific endpoint ( endpoint is specified by name ) for all views
V* 0.02 inst1/SE
View specific margin for endpoints specified as slack range
VIEW2 0.05 -0.02 0.5
Margin for endpoints specified as slack range for all views
V* 0.05 -0.02 0.5
View specific margin for all endpoints ( specified as E* )
VIEW1 0.03 E*
Margin specified for all views for all endpoints
V* 0.01 E*
62
Register to Register paths optimization

Fix only register to register paths during hold/setup fixing
Other selected endpoint configurations would be ignored in this mode.
Timing for non register to register paths for fixing mode ( hold or setup ) would
be adjusted to 0 but the timing for other mode ( setup during hold fixing/hold
during setup fixing ) is not affected.
Use Model:
set_eco_opt_mode -optimize_core_only <true/false>
63
Available Transforms in TSO

Buffer Addition
o set_eco_opt_mode -add_inst
Cell
Resize (Upsize only for setup/DRV and buffer to

delay for hold)
o set_eco_opt_mode resize inst
VT Swap
o set_eco_opt_mode swap_inst
64
Whats New in Tempus 14.1 TSO
65
Whats New
1. Improved Setup timing optimization

2. Along the route buffering
3. Allowing instances overlap
4. New solution to assemble very large hierarchical design
5. Miscellaneous
66
Improved QOR/TAT/MEM for Setup fixing

The Setup timing closure algorithm has been re-worked. It is highly
recommended to run it with Vth-swapping, resizing and buffering turned on.
set_eco_opt_mode swap_inst true resize_inst true add_inst true
Average CPU runtime improvement of 2X and Memory reduction of 10%
Improved Quality of Results for Setup fixing (average over 31 designs) :

Similar or better WNS
5 %TNS improvement
50 % less instances resized
CPU runtime reduction in 14.1 vs 13.2
25 % less inserted buffers
on 31 real customer designs
90%
80%
70%
60%
TBD
50%
40%
30%
20%
2x gain
10%
0%
1
67
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
Enabling buffering along the route

set_eco_opt_mode -along_route_buffering true
Description: When set to true, eco_opt_design will use nodes location provided
through the parasitic data in order to be able to insert buffers along the
routing topology and not only at the start or the end of the net. This
helps to better balance the slew or the load for long nets, which is
typically needed for Setup timing optimization or DRV fixing.
Default: false
Examples:
set_eco_opt_mode along_route_buffering true

This will perform DRV fixing in a mode where buffering will also be able to insert buffers along
the route topology.
Notes:
68
To benefit from this feature, user must provide parasitic data containing node locations. See next
slides.
Along the route buffering example

Designer received a late functional ECO change which is causing a long net to
be routed over the floorplan to reach the IO boundary
Traditional approach would only insert a buffer at the start or/and end of this net,
or insert buffers somewhere intermediate by loosing Signoff timing accuracy.
69
Along the route buffering example (2)

Designer received a late functional ECO change which is causing a long net to
be routed over the floorplan to reach the IO boundary
In Tempus14.1, buffering can happen all along the route topology with signoff
parasitic and timing accuracy. This greatly helps to close Setup/DRV violations
on such cases where buffering needs more flexibility.
70
How to generate node locations in parasitic

Generating node locations is done by default using EDI RC/TQRC/IQRC
engines. That information is saved automatically inside the RCDB file.
Standalone QRC can generate SPEF with node location. One needs to apply
the following option in the QRC command file :
output_db -type spef -subtype starN
Note: To pass a command file to QRC when running it from EDI cockpit :
setExtractRCMode qrcCmdFile <file>
StarRC can also generate SPEF with nodes location.

SPEF files containing nodes location must be loaded with the starN option
of read_spef command.
A SPEF with node location will have extra lines with *N prefix in CONN section:
*CONN
*I *15488:Z O *C 71.65 237.505 *L 0 *D MUX2_X1
*I *15465:D I *C 73.035 236.08 *L 0.00316 *D SDFFR_X1
*N *907:2 *C 72.675 236.95 //CDNZ 1
*N *907:3 *C 72.675 236.95 //CDNZ 2
*N *907:4 *C 72.675 235.76 //CDNZ 2
71
Allowing instances overlap during ECO fixing

set_eco_opt_mode legal_only false
Description: When set to false, eco_opt_design will not check for legal location
although Physical data are provided. It will behave like in a pure Logical
mode flow, meaning that Physical data will be ignored so it might create
instance overlap and will not check local density when inserting buffers.
Default: true
Examples:
set_eco_opt_mode legal_only false

This will perform Hold fixing more aggressively by ignoring the Physical data and not checking
for legal location.
Notes:
72
The recommended flow is to first run ECO fixing in the legal-only mode (which is the default
mode) and then, if failure catalogue is reporting many remaining violated nets due to missing
legal location, you may perform an incremental run by setting the -legal_only to false.
An ECO file generated with set_eco_opt_mode legal_only false will require
placement refinement when sourcing it in the implementation tool and that can have some
negative impact on timing.
Support for context aware rules

At 20nm/16nm nodes, placement rules are getting more complex :
-
Special/Power nets check

Double patterning check
Diffusion layers check
Implant layer check
Pin access check
Special DRC check
Filler gap check
All those are honored during

Tempus ECO timing closure.
Same code is shared between EDI
and Tempus
Filler Gap rule : set_place_mode -fillerGapEffort high fillerGapMinGap 0.18
Initial floorplan
Buffer
insertion
Instances are
abutted
Gap not large
enough
Honoring all placement rules

during ECO closure leads to
great timing predictability
73
Min gap rule

honored
Tempus How to Quickly Ramp-up?

Go to http://support.cadence.com
Search for Tempus Rapid Adoption Kit (also called RAK)
74
Tempus Summary
Productivity
ECO efficiency via P&R integration
Advanced node signoff support

16nm support
Statistical modeling (SOCV)
Accelerate Time-to-Closure
Improve PPA with PBA-based optimization
Advanced ECO capability
Tempus 14.1 The New Standard in Timing Signoff & Closure

75
EDI 14.1 Signoff Timing Closure

using TSO
76
Agenda
Why TSO inside EDI
Architecture overview
New commands / options

Use model summary
Miscellaneous information
Template scripts
77
Why the need of TSO in EDI

EDI
routeDesign
How to
hanlde
netlist with
+50M insts ?
optDesign postRoute
Does this timing match

exactly what I would get
in Tempus signOff ?
optDesign postRoute -hold

timeDesign -signOff
What if there are

replicated hierarchies in
design ?
What if I need to
enable many MMMC
views for SignOff ?
GDSII
How can I enable Path Based Analysis mode ?
Need a solution to time and optimize a design in SignOff mode

from EDI cockpit
78
TSO within EDI cockpit

signOff RC extract
QRC
CPU1
CPU n
Two new commands to time and

optimize the design in signOff mode
RCDB
Tempus
ECO Timing DB
Tempus
CPU1
CPU n
Setup/Hold
Timing Graph
Setup/Hold
Timing Graph
TSO
EDI
ecoRoute
routeDesign
ECO
Timing DB
Timing
Reports
QRC
signOff RC extract
CPU1
optDesign postRoute
RCDB

setSignoffOptMode ...
Tempus/QRC
Tempus/QRC
Tempus
Tempus
CPU1
CPU n
Setup/Hold
Timing Graph
Setup/Hold
Timing Graph
signoffTimeDesign
signoffOptDesign
Same overall use model as

timeDesign and optDesign
79
CPU n
Timing Reports
GDSII
TSO within EDI cockpit (2)
QRC
signOff RC extract
CPU1
CPU n
RCDB
Tempus
Tempus
EDI
routeDesign
CPU1
CPU n
Setup/Hold
Timing Graph
Setup/Hold
Timing Graph
optDesign postRoute
ECO Timing DB
TSO
ecoRoute
Tempus/QRC
signoffOptDesign
QRC
signOff RC extract
CPU1
RCDB
GDSII
Tempus
If no ECO Timing DB are available, the

signoffOptDesign command will auto
generate them under the hood
CPU n
Tempus
CPU1
CPU n
Setup/Hold
Timing Graph
Setup/Hold
Timing Graph
Timing Reports
80
SignOff STA and Opt on existing parasitic

With reportOnly option, EDI will
save RCDB that will then be used by
Tempus slaves
EDI
spefIn rc_corner r1 r1.spef
RCDB

Tempus
signoffTimeDesign -reportOnly
signoffOptDesign -hold
GDSII
81
Tempus
CPU1
CPU n
Setup/Hold
Timing Graph
Setup/Hold
Timing Graph
ECO Timing DB
Timing Reports
ECO routing and extraction manually

EDI
signoffOptDesign hold -noEcoRoute
In case specific steps/options

should be performed
before/during ECO routing, this
step can be called manually
ecoRoute
extractRC
signoffTimeDesign reportOnly -noEcoDb
To avoid running QRC in signOff

mode, you can choose any other
mode and call it manually
GDSII
Flexible flow to accommodate any specific methodology

before/during/after ECO routing or parasitic extraction
82
Apply SignOff STA settings early in the flow

EDI
Any settings that would
be mandatory
for
User
may replace blocks
signOff
be
ILM/Libs STA
by realshould
netlist and
enable
all views
needed
set
earlier
in the
flowforto
SignOff STA
ensure best possible
timing convergence
setDelayCalMode
setAnalysisMode
timeDesign -postRoute
optDesign -postRoute
signoffTimeDesign
GDSII
83
Maybe not all the signoff STA related settings

would be honored in the postRoute stage, but at
least EDI will have a knowledge on what will be
ultimately applied for the signoff flow steps
Passing specific settings to Tempus slaves

User can pass any specific SignOff STA
options/globals to Tempus slaves through a TCL file
QRC
signOff RC extract
CPU1
CPU n
RCDB
Tempus
EDI
setSignoffOptMode\
-preStaTcl sta.tcl
signoffTimeDesign
CPU1
CPU n
sta.tcl
sta.tcl
Setup/Hold
Timing Graph
Setup/Hold
Timing Graph
ECO
Timing DB
Note : The sta.tcl file may even contain commands/options to reset

Tempus settings to their default and then re-apply fresh ones, to avoid
reusing EDI specific data
84
Tempus
Timing
Reports
Signoff Timing analysis in EDI using GTD

Global Signoff Timing Debug
EDI
routeDesign
Choose between any

path_group analysis
optDesign postRoute
Path Histogram
(pass/fail)
signoffTimeDesign
Paths groups
Machine Readable
timing reports
Paths List
load_timing_debug_report
Note: The Global Timing Debug can also be called after signoffOptDesign
since that command will generate .mtarpt files too.
Example to visualize Hold violated paths in GTD :
foreach mtarpt_file [glob -nocomplain signoffTimingReports/*_early_detailed.mtarpt] \
{load_timing_debug_report -NAME early $mtarpt_file}
analyze_paths_by_view
85
Enabling PBA timing analysis and opt

EDI
setSignoffOptMode \
-retime aocv_path_slew_propagation
-check_type both
signoffTimeDesign
This will generate

Signoff STA and ECO
Timing DB in Path
Based Analysis mode
for both Setup and Hold
Note : user can also directly call signoffOptDesign which

would then auto generate the ECO Timing DB in PBA mode
Options specific to PBA mode:
signoffOptMode
retime
#default none
To enable PBA and select the mode
checkType
#default early
To select whether PBA is applied to Setup or Hold or both
maxSlack
#default 0
To specify max slack to be considered for retiming
maxPaths
#default 500000
To specify max number of paths to be retimed in total
nworst
#default 50
To specify number of paths to be retimed for each endpoint
The runtime in PBA mode is proportional to the amount of paths to be retimed.

You should adjust above values depending on the actual timing state
86
Typical examples of optimization in signOff

Example to fix Hold
violations reported in
signOff STA mode
EDI
Example to fix DRV, Setup

and Hold violations in
incremental mode on a
signOff STA
EDI
Example to optimize
leakage in signOff STA
mode
EDI
routeDesign
routeDesign
routeDesign
optDesign postRoute
optDesign postRoute
optDesign postRoute
signoffOptDesign drv -noEcoRoute
signoffOptDesign -leakage
signoffOptDesign setup -noEcoRoute
GDSII
GDSII
87
GDSII
Summary of the use model (1/2)

Two new commands with similar use model as timeDesign/optDesign
signoffTimeDesign
-help
-noEcoDb
-noExpandedViews
-outDir <string>
-reportOnly
#
#
#
#
#
Prints out the command usage

Do not generate ECO Timing DB
Do not print expanded timing per view
Reports would be saved in this directory
Skip parasitic extraction
Description: This command will generate signoff STA reports and ECO Timing DB for
both Setup and Hold timing mode.
signoffOptDesign
-help
-drv
-hold
-leakage
-noEcoRoute
-setup
#
#
#
#
#
#
Prints out the command usage

DRV Fixing
Hold Fixing
Leakage Fixing
No ECO-routing after optimization
Setup Fixing
Description: This command will optimize timing or leakage based on Signoff STA timing.
When using noEcoRoute option, user can make multiple incremental call
to this command to fix DRV/Setup/Hold violations in incremental mode.
88
Summary of the use model (2/2)

One new command to pilot them, with same use model as set_eco_opt_mode
already available in Tempus
setSignoffOptMode
-addInst true
-bufferCellList {}
-checkType early
-drvMargin 0
-ecoFilePrefix {}
-fixHoldAllowSetupTnsDegrade false
-fixHoldWithMargin 0
-holdTargetSlack 0
-loadEcoOptDb ecoTimingDB
-maxPaths 500000
-maxSlack 0
-numReportPaths 50
-nworst 50
-optimizeCoreOnly false
-optimizeSequentialCells false
-partitionListFile {}
-postStaTcl {}
-prefixName ESO
-preStaTcl preStaTcl.tcl
-resizeInst false
-retime none
-routingCongestionAware false
-saveEcoOptDb ecoTimingDB
-setupTargetSlack 0
-swapInst false
-verbose false
89
# default=true
# default=""
# {early late both}, default=early
# default=0
# default=""
# default=false
# default=0
# default=0
# default=
# default=500000
# default=0
# default=50
# default=50
# default=false
# default=false
# default=""
# default=""
# default=ESO
# default=""
# default=false
# {none aocv path_slew_propagation
aocv_path_slew_propagation waveform_propagation
aocv_waveform_propagation}, default=none
# default=false
# default=ecoTimingDB
# default=0
# default=false
# default=false
Miscellaneous information
For large designs or when many views are enabled, make sure to have enough
CPUs available to distribute STA and multi-thread it too.
The methodology is to enable only the dominant views during postRoute optimization
stage, while all views can be enabled for the Signoff optimization stage
Apply the command setMultiCpuUsage to select how many local CPU or machines
should be used to perform Signoff STA.
Ex : setMultiCpuUsage -remoteHost 3 -cpuPerRemoteHost 4
It is recommended to use Tempus14.1 with this new feature, but using

Tempus13.2 is also supported
By default, all timing reports are stored in signoffTimingReports/ directory
In PBA mode, if -checkType both is used, Setup view names must be different
from Hold view names
The timeDesign signoff command will be obsolete in EDI14.1
90
Some template scripts

GBA Signoff STA followed by Setup and Hold opt
source postRoute.enc
setMultiCpuUsage -localCpu 6
setSignoffOptMode -preStaTcl preStaTcl.tcl
signoffTimeDesign
signoffOptDesign -setup -noEcoRoute
signoffOptDesign hold
Note : The preStaTcl.tcl script allows user

to apply any Signoff STA related settings
or even to reset any set*mode commands
GBA Signoff STA followed by Setup opt all based on TQRC

setExtractRCMode -coupled true -engine postRoute -effortLevel medium
extractRC
signoffTimeDesign -reportOnly
signoffOptDesign -setup -noEcoRoute
ecoRoute
extractRC
signoffTimeDesign reportOnly -noEcoDb
Signoff STA followed by Hold opt in PBA Setup and PBA Hold
setSignoffOptMode -retime aocv_path_slew_propagation checkType both
signoffTimeDesign
signoffOptDesign hold
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Tempus 14.

Copyright 2014 Cadence Design Systems, Inc. All Rights Reserved.

Whats New in Tempus 14.1 TSO

Copyright 2014 Cadence Design Systems, Inc. All Rights Reserved.

Copyright 2014 Cadence Design Systems, Inc. All Rights Reserved.

Tempus TSO Advanced Capabilities

Built-in signoff delay and SI analysis

Distributed or concurrent MMMC

Physically aware optimization

Legalized / DRC clean placement directives

Hierarchical or flat ECO generation

Optimized MMMC timing graph for fast and

Graph or path based optimization

Common timing engine within

New Features in Tempus TSO 14.1

Master / Clone support

Multi-threaded ECO db generation

20nm/16nm design rule compliant

Copyright 2014 Cadence Design Systems, Inc. All Rights Reserved.

Place and route

Timing Closure Flow

POST ROUTE FLOW

POST CTS FLOW

PRE CTS FLOW

Copyright 2014 Cadence Design Systems, Inc. All Rights Reserved.

Hierarchical Timing Closure Flow

Copyright 2014 Cadence Design Systems, Inc. All Rights Reserved.

ASSEMBLY & SIGNOFF

In a hierarchical design flow,

Why Tempus TSO?

Complementary solution to the timing closure at implementation stage.

Copyright 2014 Cadence Design Systems, Inc. All Rights Reserved.

Tempus TSO Features Highlights

Copyright 2014 Cadence Design Systems, Inc. All Rights Reserved.

Front-to-back Physical Aware Timing Closure

Copyright 2014 Cadence Design Systems, Inc. All Rights Reserved.

RC-EDI-Tempus Front to Back

Traditional Front to Back implementation flow

Benefit of Tempus TSO Physical-awareness

Taking in account routing information when adding buffer.

Copyright 2014 Cadence Design Systems, Inc. All Rights Reserved.

Difficult to predict the timing impact of placement refinement !

Buffer is already getting legal location from Tempus

No move would happen later on in place&route

Routing estimations are more precise

On Which Design Style Can It Be Used?

Very large flat netlist

Fix the inter-partition timing

Fix the real remaining

Flat implementation of very

Need precise fixing

Above several 100k

Integrated solution enables Signoff Timing Closure in different design

Copyright 2014 Cadence Design Systems, Inc. All Rights Reserved.

Tempus TSO Architecture

Physically aware for

Distributed MMMC Timing/SI Analysis

Optimization across all

MMMC Optimization Engine

Single-pass MMMC Signoff ECOs

Copyright 2014 Cadence Design Systems, Inc. All Rights Reserved.

Copyright 2014 Cadence Design Systems, Inc. All Rights Reserved.