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PLL Frequency Synthesizer with Multi-Programmable Divider

Yasuaki SUMI"', Kouichi SYOUBU"", Shigeki OBOTE**, Yutaka FUKUI**


"Tottori SANYO Electric Co.,LTD ""Faculty of Engineering, Tottori University
Abstract The lock-up time of a PLL frequency
synthesizer depends on each loop gain. In this
paper, we pay attention to the gain of a
programmable divider which is one of the
important elements of PLL, and propose a new
method for improving the gain of programmable
divider. In order to achieve the increase in gain of
the programmable divider, we propose a new PLL
frequency synthesizer with multi-programmable
divider by which the gain is increased even when
the same reference frequency and the same
division ratio as usual are used. It will be shown
by the theoretical considerations and
experimental results that a higher speed lock-up
time can be achieved.
1. Introduction
As the communication technology advances, a
PLL frequency synthesizer is being required
with higher speed lock-up time, lower power
consumption and smaller size. Various methods
have been proposed for attaining a higher speed
lock-up time in a PLL frequency synthesizer
[ 11-[41.
In order to achieve a higher speed lock-up
time, it is necessary to increase the loop gain of
the PLL[5][6]. For example, the fractional
division method has been proposed to increase
the loop gain[7]. However, since this method
uses two different division ratios alternately,
more spurious noise occurs around the reference
frequency due to the phase noise even under the
steady state in the loop. In a conventional PLL,
once the phase detector or programmable divider
is chosen as an element of the PLL, the loop
gain of PLL becomes fixed.
In this paper, we propose a new PLL
frequency synthesizer with multi-programmable
divider method which can attain a higher speed
lock-up time.
Proposed PLL can increase the loop gain
without the increase of reference frequency.
Effectiveness of PLL with multi-programmable
divider and multi-phase detector will be shown
by the theoretical considerations and experimental results.

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2. PLL frequency synthesizer


Figure 1 shows the block diagram of the
conventional Phase Locked Loop (PLL)
frequency synthesizer[5]. This circuit has been
used as a local oscillator of the transmitters or
receiver and as timing elements of digital
equipment, and so on. It consists of a phase
detector, a Charge pump, a Low Pass Filter
(LPF), a Voltage Controlled Oscillator (VCO),
and a programmable divider. The output
frequency fvco is an integral multiple of the
reference frequency fREF as given in Eq. (1).

t
t"
Programmable

divider

1/N
Fig. 1 PLL frequency synthesizer

3. Transient Response of PLL


Since the PLL frequency synthesizer is the
second-order control system including the
feedback element, we can analyze it based on
the automatic control theory[5] [6][SI.
In Fig. 1, the transfer functions of a phase
detector, VCO, a programmable divider are
given by K , KVCO,and 1/N, respectively. And
K and KVCOshow sensitivity of phase detector
and VCO, and UN is the division ratio of a
programmable divider. The total gain M(s) of
PLL is given by Eq. (2) using above transfer
functions.
K F(s)s
M ( s ) = _____
s + KF(s)

where, F(s) is the gain of LPF, and K is the loop


gain. In this paper given by

IV-612

(3)

Let us consider the transient response of the


active LPF in Fig. 2. The transfer function F(s)
of LPF is given by

the proposed method, the gain of the programmable divider 1/N is increased four times bigger
than that of the conventicinal method.

where,

Substitution of Eq. (4) into Eq. (2) gives


M ( s ) = s-

K
K

,s+

s2 i-2

Fig. 2 Ac:tive filter

,,siC(1)K
-

where,

[I
Lock-up time

is the natural angular frequency and


is
the damping factor. The transient response of the
second-order system is determined by these
parameters.
Let us consider the transient response for the
frequency step input function given by
I s2 .
Performing an Inverse Laplace Transform, we
have

J-7
vsin
"

sinh

It

Now, we may neglect the cases of

= 1 and

> 1, and consider the case of < 1.


The increase in ,, , that is increase in K or
decrease in , , is considered to be effective for
improving the lock-up time defined in Fig. 3. In

0v

7
i

Time

Fig. 3 Frequency alcquisition property.

4. Multi-programmable divider method


4.1 Increase of gain in programmable divider
It is evident that the increase of , by the
increase of the total loop gain K or the decrease
of
is necessary for the improving of lock-up
time. It can be seen from Eq. (3) that the
increase of K , Kvco and 1M leads to the
increase of K. In this paper, we propose a new
multi-programmable diviider method as a mean
of enhancing 1N.

4.2 Multi-programmable divider method


Fig. 4 shows the block diagram of the PLL
frequency synthesizer wjth multi-programmable
divider and Fig. 5 is the operation time chart. It
is composed of four programmable dividers,
four phase detectors and four charge pumps. The
reference signals which are shifted respectively
by using the delay circuit are fed to each phase
detector. Fig. 6 shows Delay circuit. Then, each
reference signal and feedback signal are
compared each other independently. In a
conventional phase comparator, the phase
detector becomes the state of standby after the

IV-613

comparison operation until the rising edge of the


following reference signal comes. However, in
the proposed method, successive comparison
operations are performed in the standby of phase
detector 1. In addition, in case that the phase
difference is longer than one cycle of the
reference signal, Pu or Pd signal overlaps at the
same time because the charge pump is composed
of four-fold as shown in Fig. 4. Therefore, the
amount of the charge and discharge to LPF are
multiplied by a factor of four compared with the
case of Pu or Pd in a single system.
VCO output fvco is fed to each programmable
divider through the respective gate. A
programmable divider is composed of four-fold
PDI-PD4, where fvco is divided independently.
Then, the phase comparison is performed in
every / 2 o f f R E F .

LPF

Fig. 4 PLL frequency synthesizer with multiprogrammable divider.

f,, I

fREF4

f,,

fRBF3

c(r)K
__

Loop gain=K
Loop gain=4K

l
0
r
Time

Fig. 7 Effect of loop gain on lock-up time.


Since a programmable divider has been
composed four-fold in the proposed method, the
loop gain K becomes four times bigger than that
of the conventional method.
Now, In Eq. ( 3 ) , 1/N becomes (4*1/N).
Analyzing it in similar way as from Eq. (2) to
Eq. (9), we have

Therefore, the lock-up time of PLL becomes


four times higher than the conventional method
as shown in Fig. 7.
The most important point is that the lock up
time by the proposed method becomes four times
higher than conventional under the same
reference frequency. A fractional-N division
method is also introduced in order to speed up
the lock up time with higher reference
frequency[9]. The proposed method is also
applicable to a fractional-N programmable
divider to attain a faster lock up time.

Fig.5 Timing chart.


in, 1

f RLF

fREF

fRW2
fRPF4

Fig. 6 Delay circuit.

4.3 Effect of loop gain on lock-up time

5. Experimental results
Figs 8 and 9 are the experimental results of
the lock-up time by the conventional method and
the proposed method, respectively. We used the
AM frequency band to measure a basic
performance characteristic of the proposed PLL.
The reference frequency IOkHz and frequency
shift from 800kHz to 2.2MHz are set in the
experiment. We can see that the frequency lockup time of a conventional method and of a
proposed method are about 8.0ms and 2.0ms,
respectively.
Fig. 10 shows frequency spurious characteris-

W-614

tics of the proposed PLL frequency synthesizer


when the loop is in a steady state.
It is observed from these experimental results
that the proposed method can achieve a higher
speed lock-up time keeping good spurious
characteristics.

6. Conclusion
In this paper, we have proposed a new PLL
frequency synthesizer with multi-programmable
divider which can increase the loop gain by
using four programmable dividers keeping same
reference frequency and division ratio as
conventional.
It has been observed from the experimental
result that a higher speed lock-up time can be
achieved by using the proposed method.
Since the programmable divider, phase
detector and charge pump are four-fold,
reduction of power consumption must be studied
further.

Locked Loop," IEICE, Trans.C, C-I,


Vol.J76-C-I, N0.11, pp.445-452, NOV.1993.
[8] H. Shirahama, K. Taniguchi, and K. Nakashi,
"A New Fast Pull-hi PLL Using FrequencyDifference-Detector.,"IEICE, Trans.C, C-11,
Vol.J76-C-II, NO.10, pp.679-687, Oct. 1993.
[9] Wing S. Djen, .Daniel J. Linebarger,
"Fractional-N PLL Provides Fast, LowNoise Synthesis," Microwave & RF, vo1.3,
No.5, pp95-102, May 1994.

P'

, ,

, 1 0 0V

M,' 00, C h l

I , 760;Vl

Time (2msldlv)

Fig.8 Lock-up time (Conventional).

Reference
[1] Y. Sumi, K. Syoubu, S. Obote, and Y. Fukui,
"PLL Frequency Synthesizer Using MultiPhase Detector," Technical Report of IEEJ,
ECT-97-14, pp.77-82, Jan. 1997.
[2] M. Hagiwara, and Y. Suzuki, "Practical
PLL frequency synthesizer," Sougou-denshi
inc., 1995.
[3] Y. Sumi, S. Obote, K. Narai, K. Tsuda, K.
Syoubu, and Y. Fukui, "Fast Frequency
Acquisition in the PLL Frequency Synthesizer Suppressing the Transient Response of
the Second Order System," Technical Report
of IEICE, CAS96-98, pp.69-76, Mar. 1997.
[4] Y. Sumi, S. Obote, K. Tsuda, K. Syoubu,
and Y. Fukui, "A New Low Pass Filter for
the Fast Frequency Acquisition of the PLL
Frequency Synthesizer," 1st Analog VLSI
Workshop proceedings, ECT-97-54, pp. 1 15120, May. 1997.
[5] T. Ozawa, "Circuit Design of PLL Frequency Synthesizer," Sougoudensi Inc.,
1994.
[6] T. Yanagisawa,"PLL Application Circuits,"
Sougoudensi Inc., 1995.
[71 H. Adachi, H. Kosugi, T. Uwano, and K,
Nakabe, "High-speed Frequency Switching
Synthesizer Using Fractional N Phase

A7-6 15

<I

Time (2msIdiv)

Fig.9 Lock-up time (Proposed method).

Fig. 10 Spurious characteristics.

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