Professional Documents
Culture Documents
t
t"
Programmable
divider
1/N
Fig. 1 PLL frequency synthesizer
IV-612
(3)
the proposed method, the gain of the programmable divider 1/N is increased four times bigger
than that of the conventicinal method.
where,
K
K
,s+
s2 i-2
,,siC(1)K
-
where,
[I
Lock-up time
J-7
vsin
"
sinh
It
= 1 and
0v
7
i
Time
IV-613
LPF
f,, I
fREF4
f,,
fRBF3
c(r)K
__
Loop gain=K
Loop gain=4K
l
0
r
Time
f RLF
fREF
fRW2
fRPF4
5. Experimental results
Figs 8 and 9 are the experimental results of
the lock-up time by the conventional method and
the proposed method, respectively. We used the
AM frequency band to measure a basic
performance characteristic of the proposed PLL.
The reference frequency IOkHz and frequency
shift from 800kHz to 2.2MHz are set in the
experiment. We can see that the frequency lockup time of a conventional method and of a
proposed method are about 8.0ms and 2.0ms,
respectively.
Fig. 10 shows frequency spurious characteris-
W-614
6. Conclusion
In this paper, we have proposed a new PLL
frequency synthesizer with multi-programmable
divider which can increase the loop gain by
using four programmable dividers keeping same
reference frequency and division ratio as
conventional.
It has been observed from the experimental
result that a higher speed lock-up time can be
achieved by using the proposed method.
Since the programmable divider, phase
detector and charge pump are four-fold,
reduction of power consumption must be studied
further.
P'
, ,
, 1 0 0V
M,' 00, C h l
I , 760;Vl
Time (2msldlv)
Reference
[1] Y. Sumi, K. Syoubu, S. Obote, and Y. Fukui,
"PLL Frequency Synthesizer Using MultiPhase Detector," Technical Report of IEEJ,
ECT-97-14, pp.77-82, Jan. 1997.
[2] M. Hagiwara, and Y. Suzuki, "Practical
PLL frequency synthesizer," Sougou-denshi
inc., 1995.
[3] Y. Sumi, S. Obote, K. Narai, K. Tsuda, K.
Syoubu, and Y. Fukui, "Fast Frequency
Acquisition in the PLL Frequency Synthesizer Suppressing the Transient Response of
the Second Order System," Technical Report
of IEICE, CAS96-98, pp.69-76, Mar. 1997.
[4] Y. Sumi, S. Obote, K. Tsuda, K. Syoubu,
and Y. Fukui, "A New Low Pass Filter for
the Fast Frequency Acquisition of the PLL
Frequency Synthesizer," 1st Analog VLSI
Workshop proceedings, ECT-97-54, pp. 1 15120, May. 1997.
[5] T. Ozawa, "Circuit Design of PLL Frequency Synthesizer," Sougoudensi Inc.,
1994.
[6] T. Yanagisawa,"PLL Application Circuits,"
Sougoudensi Inc., 1995.
[71 H. Adachi, H. Kosugi, T. Uwano, and K,
Nakabe, "High-speed Frequency Switching
Synthesizer Using Fractional N Phase
A7-6 15
<I
Time (2msIdiv)