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BTS721L1
Overload protection
Current limitation
Short-circuit protection
Thermal shutdown
Overvoltage protection
(including load dump)
Fast demagnetization of inductive loads
Reverse battery protection1)
Undervoltage and overvoltage shutdown
with auto-restart and hysteresis
Open drain diagnostic output
Open load detection in ON-state
CMOS compatible input
Loss of ground and loss of Vbb protection
Electrostatic discharge (ESD) protection
Product Summary
Overvoltage Protection
Operating voltage
active channels:
On-state resistance RON
Nominal load current IL(NOM)
Current limitation
IL(SCr)
Vbb(AZ)
43
V
Vbb(on)
5.0 ... 34
V
two parallel four parallel
one
100
50
25
m
2.9
4.3
6.3
A
8
8
8
A
P-DSO-20
Application
General Description
N channel vertical power FET with charge pump, ground referenced CMOS compatible input and diagnostic
feedback, monolithically integrated in Smart SIPMOS technology. Providing embedded protective functions.
1)
Symbol Function
Vbb
Positive power supply voltage. Design the
wiring for the simultaneous max. short circuit
currents from channel 1 to 4 and also for low
thermal resistance
IN1
Input 1 .. 4, activates channel 1 .. 4 in case of
IN2
logic high signal
IN3
IN4
OUT1
Output 1 .. 4, protected high-side power output
OUT2
of channel 1 .. 4. Design the wiring for the
OUT3
max. short circuit current
OUT4
ST1/2
Diagnostic feedback 1/2 of channel 1 and
channel 2, open drain, low on failure
ST3/4
Diagnostic feedback 3/4 of channel 3 and
channel 4, open drain, low on failure
GND1/2 Ground 1/2 of chip 1 (channel 1 and channel 2)
GND3/4 Ground 3/4 of chip 2 (channel 3 and channel 4)
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
Vbb
Vbb
OUT1
OUT2
Vbb
Vbb
OUT3
OUT4
Vbb
Vbb
With external current limit (e.g. resistor RGND=150 ) in GND connection, resistor in series with ST
connection, reverse load current limited by connected load.
Semiconductor Group
1 of 15
2003-Oct-01
BTS721L1
Block diagram
Four Channels; Open Load detection in on state;
Voltage
source
Overvoltage
protection
Current
limit 1
+ V bb
Gate 1
protection
V Logic
IN1
IN2
ST1/2
Voltage
Level shifter
sensor
Rectifier 1
Logic
ESD
Signal GND
Chip 1
Current
limit 2
Level shifter
Rectifier 2
GND1/2
OUT1
18
Temperature
sensor 1
Open load
Short to Vbb
detection 1
Charge
pump 1
Charge
pump 2
Limit for
unclamped
ind. loads 1
Leadframe
Channel 1
Gate 2
protection
Limit for
unclamped
ind. loads 2
Open load
Short to Vbb
detection 2
Chip 1
Channel 2
OUT2
17
Load
Temperature
sensor 2
R
R
O1
O2
GND1/2
Load GND
+ V bb
Leadframe
Channel 3
OUT3
14
(equivalent to chip 1)
7
IN3
IN4
ST3/4
Channel 4
OUT4
Load
GND3/4
PROFET
Signal GND
Chip 2
13
Chip 2
R
O3
O4
GND3/4
Load GND
Semiconductor Group
2003-Oct-01
BTS721L1
Maximum Ratings at Tj = 25C unless otherwise specified
Parameter
Symbol
Vbb
Vbb
Values
Unit
43
34
V
V
self-limited
60
A
V
Tj
Tstg
Ptot
-40 ...+150
-55 ...+150
3.7
1.9
EAS
0.3
0.65
1.5
VESD
1.0
kV
V
mA
15
41
34
K/W
IL
VLoad
4)
dump
VIN
IIN
IST
Thermal resistance
junction - soldering point5),6)
junction - ambient5)
2)
3)
4)
5)
6)
each channel:
one channel active:
all channels active:
Rthjs
Rthja
Supply voltages higher than Vbb(AZ) require an external current limit for the GND and status pins, e.g. with a
150 resistor in the GND connection and a 15 k resistor in series with the status pin. A resistor for input
protection is integrated.
RI = internal resistance of the load dump test pulse generator
VLoad dump is setup without the DUT connected to the generator per ISO 7637-1 and DIN 40839
Device on 50mm*50mm*1.5mm epoxy PCB FR4 with 6cm2 (one layer, 70m thick) copper area for Vbb
connection. PCB is vertical without blown air. See page 15
Soldering point: upper side of solder edge of device pin 15. See page 15
Semiconductor Group
2003-Oct-01
BTS721L1
Electrical Characteristics
Parameter and Conditions, each of the four channels
Symbol
Tj =-40...+150C:
Tj =-40...+150C:
Tj =-40...+25C:
Tj =+150C:
Undervoltage restart of charge pump
see diagram page 14
Tj =-40...+150C:
Undervoltage hysteresis
Vbb(under) = Vbb(u rst) - Vbb(under)
Overvoltage shutdown
Tj =-40...+150C:
Overvoltage restart
Tj =-40...+150C:
Overvoltage hysteresis
Tj =-40...+150C:
8
)
Overvoltage protection
Tj =-40...+150C:
I bb = 40 mA
Standby current, all channels off
Tj =25C:
VIN = 0
Tj =150C:
7)
8)
Values
min
typ
max
--
Unit
85
170
100
200
2.5
3.8
5.9
43
22
2.9
4.3
6.3
50
25
--
--
--
10
mA
ton
toff
80
80
200
200
400
400
dV/dton
0.1
--
V/s
-dV/dtoff
0.1
--
V/s
Vbb(on)
Vbb(under)
Vbb(u rst)
5.0
3.5
--
----
V
V
V
Vbb(ucp)
--
5.6
34
5.0
5.0
7.0
7.0
Vbb(under)
--
0.2
--
Vbb(over)
Vbb(o rst)
Vbb(over)
Vbb(AZ)
34
33
-42
--0.5
47
43
----
V
V
V
V
---
28
44
60
70
IL(NOM)
IL(GNDhigh)
Ibb(off)
At supply voltage increase up to Vbb = 5.6 V typ without charge pump, VOUT Vbb - 2 V
see also VON(CL) in circuit diagram on page 8.
Semiconductor Group
2003-Oct-01
BTS721L1
Parameter and Conditions, each of the four channels
Symbol
Values
min
typ
max
Unit
--
--
12
---
2
8
3
12
mA
---
3.8
3
---
ms
--
47
--
150
--
-10
---
C
K
---
-610
32
--
V
mV
VON(CL)
Tjt
Tjt
Reverse Battery
Reverse battery voltage 12)
Drain-source diode voltage (Vout > Vbb)
IL = - 2.9 A, Tj = +150C
-Vbb
-VON
9)
Semiconductor Group
2003-Oct-01
BTS721L1
Parameter and Conditions, each of the four channels
Symbol
Values
min
typ
max
Diagnostic Characteristics
Open load detection current, (on-condition)
20
-400
each channel, Tj = -40C: I L (OL)
20
-300
Tj = 25C:
20
-300
Tj = 150C:
twice the current of one channel
two parallel channels
four times the current of one channel
four parallel channels
13
)
Open load detection voltage
Tj =-40..+150C: VOUT(OL)
2
3
4
Internal output pull down
(OUT to GND), VOUT = 5 V
Tj =-40..+150C: RO
4
10
30
1
Unit
mA
V
k
RI
2.5
3.5
VIN(T+)
1.7
--
3.5
VIN(T-)
1.5
--
--
-1
0.5
--
-50
V
A
20
50
90
td(ST OL4)
100
320
800
td(ST OL5)
--
20
td(ST)
--
200
600
5.4
---
6.1
---
-0.4
0.6
Tj =-40..+150C:
13)
14)
VIN(T)
IIN(off)
IIN(on)
VST(high)
VST(low)
External pull up resistor required for open load detection in off state.
If ground resistors RGND are used, add the voltage drop across these resistors.
Semiconductor Group
2003-Oct-01
BTS721L1
Truth Table
Channel 1 and 2
Channel 3 and 4
(equivalent to channel 1 and 2)
IN1
IN3
Chip 1
Chip 2
IN2
IN4
OUT1
OUT3
OUT2
OUT4
ST1/2
ST3/4
BTS 721L1
Normal operation
Open load
Channel 1 (3)
Channel 2 (4)
Channel 1 (3)
Channel 2 (4)
Overtemperature
both channel
Channel 1 (3)
Channel 2 (4)
Undervoltage/ Overvoltage
L = "Low" Level
H = "High" Level
L
L
H
H
L
L
H
L
H
L
H
L
H
X
L
L
H
H
Z
Z
H
L
H
L
H
L
H
X
L
H
X
L
L
H
L
L
H
L
H
X
L
H
X
H
H
H
Z
Z
H
L
H
X
L
H
X
L
X
H
L
H
X
X
X
L
L
H
L
H
X
X
X
L
H
X
L
H
X
L
L
L
L
L
X
X
L
H
H
H
L
L
L
X
X
L
L
L
H
H
H
H
H(L15))
H
L
H(L15))
H
L
L16)
H
H(L17))
L16)
H
H(L17))
H
L
L
H
L
H
L
H
X = don't care
Z = high impedance, potential depends on external circuit
Status signal valid after the time delay shown in the timing diagrams
Parallel switching of channel 1 and 2 (also channel 3 and 4) is easily possible by connecting the inputs and
outputs in parallel (see truth table). If switching channel 1 to 4 in parallel, the status outputs ST1/2 and ST3/4
have to be configured as a 'Wired OR' function with a single pull-up resistor.
Terms
V
Ibb
bb
V
ON1
V
ON2
Leadframe
I IN1
I IN2
I ST1/2
V
IN1 VIN2 VST1/2
3
5
4
Vbb
IN1
IN2
OUT1
PROFET
Chip 1
OUT2
ST1/2 GND1/2
I L1
17
I L2
I IN3
I IN4
I ST3/4
V
OUT1
2
R
18
I
GND1/2
VON3
V
ON4
Leadframe
V
IN3 VIN4 VST3/4
7
9
8
Vbb
IN3
IN4
OUT3
PROFET
Chip 2
ST3/4 GND3/4
I L3
13
I L4
V
OUT3
VOUT2
GND1/2
OUT4
14
I
GND3/4
VOUT4
GND3/4
15)
Semiconductor Group
2003-Oct-01
BTS721L1
Overvoltage protection of logic part
GND1/2 or GND3/4
+ V bb
ESD-ZD I
RI
IN
Z2
IN
Logic
GND
ST
R ST
Z1
GND
R GND
Signal GND
+5V
R ST(ON)
ST
5V
GND
ESDZD
R ST
IN
ESD-Zener diode: 6.1 V typ., max 5.0 mA; RST(ON) < 380
at 1.6 mA, ESD zener diodes are not to be used as voltage
clamp at DC conditions. Operation in this mode may result in
a drift of the zener voltage (increase of up to 1 V).
- Vbb
RI
Logic
ST
OUT
Power
Inverse
Diode
GND
RGND
Signal GND
OUT1...4
RL
Power GND
+Vbb
VZ
V ON
OUT
PROFET
Power GND
Semiconductor Group
2003-Oct-01
BTS721L1
Open-load detection, OUT1...4
ON-state diagnostic condition:
VON < RONIL(OL); IN high
+ V bb
Vbb
IN2
PROFET
ST
GND
OUT1
IN1
V
VON
ON
IN1
OUT2
IN2
OUT
Open load
detection
Logic
unit
V
bb
ST
GND
Any kind of load. If VGND > VIN - VIN(T+) device stays off
Due to VGND > 0, no VST = low signal available.
EXT
Vbb
IN2
PROFET
ST
GND
OUT1
high
OFF
V
Logic
unit
IN1
Open load
detection
OUT2
OUT
bb
Signal GND
GND disconnect
Consider at your PCB layout that in the case of Vbb disconnection with energized inductive load the whole load
current flows through the GND connection.
Ibb
bb
IN1
Vbb
IN2
PROFET
ST
GND
OUT1
OUT2
V
V
IN1 IN2 ST
V
GND
Semiconductor Group
2003-Oct-01
BTS721L1
Inductive load switch-off energy
dissipation
E bb
E AS
IN
PROFET
ELoad
Vbb
OUT
L
ST
GND
ZL
{
R
EL
ER
EL = 1/2LI L
While demagnetizing load inductance, the energy
dissipated in PROFET is
EAS= Ebb + EL - ER= VON(CL)iL(t) dt,
with an approximate solution for RL > 0 :
EAS=
IL L
(V + |VOUT(CL)|)
2RL bb
ln (1+ |V
ILRL
OUT(CL)|
1000
100
10
1
1
IL [A]
Semiconductor Group
10
2003-Oct-01
BTS721L1
Typ. standby current
RON [mOhm]
300
Ibb(off) [A]
60
50
250
200
40
Tj = 150C
150
30
85C
25C
100
20
-40C
50
10
0
0
10
20
30
0
-50
40
50
100
150
Tj [C]
Vbb [V]
IL(OL) [mA]
220
toff(SC) [msec]
4
200
-40C
no-load detection not specified
for V bb < 6 V
180
160
140
120
100
80
60
200
3.5
3
25C
2.5
2
85C
Tj = 150C
1.5
1
40
0.5
20
0
0
10
15
20
25
30
Vbb [V]
Semiconductor Group
11
0
-50
50
100
150
200
Tj,start [C]
2003-Oct-01
BTS721L1
Timing diagrams
Timing diagrams are shown for chip 1 (channel 1/2). For chip 2 (channel 3/4) the diagrams
are valid too. The channels 1 and 2, respectively 3 and 4, are symmetric and consequently
the diagrams are valid for each channel as well as for permuted channels
Figure 2b: Switching an inductive load
IN
IN2
V bb
t d(ST)
ST
*)
OUT1
OUT
OUT2
IL
I L(OL)
ST open drain
IN
IN1
ST
I
V
L1
OUT
L(SCp)
I
L(SCr)
ST
t off(SC)
t
t
The initial peak current should be limited by the lamp and not by
the initial short circuit current IL(SCp) = 14 A typ. of the device.
Semiconductor Group
12
2003-Oct-01
BTS721L1
Figure 5a: Open load: detection in ON-state, open
load occurs in on-state
IN1
IN1/2
IN2
I
+I
L1
L2
I L(SCp)
VOUT1
I L(SCr)
channel 1:
open
load
IL1
t
ST1/2
off(SC)
t d(ST OL1)
open
load
normal
load
t d(ST OL2)
t d(ST OL1)
t d(ST OL2)
ST
t
t
td(ST OL1) = 30 s typ., td(ST OL2) = 20 s typ
IN1
IN
IN2
ST
V
OUT1
OUT
L1
d(ST)
d(ST OL4)
d(ST)
d(ST OL5)
ST
t
The status delay time td(STOL4) allows to distinguish between the
failure modes "open load in ON-state" and "overtemperature".
Semiconductor Group
13
2003-Oct-01
BTS721L1
Figure 5c: Open load: detection in ON- and OFF-state
(with REXT), turn on/off to open load
VON(CL)
V on
IN1
off-state
OUT1
I L1
bb(u rst)
V
ST
t d(ST)
d(ST)
t d(ST OL5)
bb(over)
off-state
on-state
IN2
bb(o rst)
bb(u cp)
bb(under)
V bb
t
IN = high, normal load conditions.
Charge pump starts at Vbb(ucp) = 5.6 V typ.
IN
Vbb
bb
V
bb(under)
V ON(CL)
Vbb(over)
V bb(o rst)
Vbb(u cp)
Vbb(u rst)
V
OUT
V OUT
ST
ST open drain
t
t
Semiconductor Group
14
2003-Oct-01
BTS721L1
Published by
Infineon Technologies AG,
St.-Martin-Strasse 53,
D-81669 Mnchen
Infineon Technologies AG 2001
All Rights Reserved.
Ordering Code
Q67060-S7002-A2
Attention please!
The information herein is given to describe certain components and
shall not be considered as a guarantee of characteristics.
Terms of delivery and rights to technical change reserved.
We hereby disclaim any and all warranties, including but not limited
to warranties of non-infringement, regarding circuits, descriptions
and charts stated herein.
Infineon Technologies is an approved CECC manufacturer.
Information
For further information on technology, delivery terms and conditions
and prices please contact your nearest Infineon Technologies Office
in Germany or our Infineon Technologies Representatives worldwide
(see address list).
Warnings
Due to technical requirements components may contain dangerous
substances. For information on the types in question please contact
your nearest Infineon Technologies Office.
Infineon Technologies Components may only be used in life-support
devices or systems with the express written approval of Infineon
Technologies, if a failure of such components can reasonably be
expected to cause the failure of that life-support device or system, or
to affect the safety or effectiveness of that device or system. Life
support devices or systems are intended to be implanted in the
human body, or to support and/or maintain and sustain and/or
protect human life. If they fail, it is reasonable to assume that the
health of the user or other persons may be endangered.
Pin 15
Semiconductor Group
15
2003-Oct-01