General application with special gates

2014

ABSTRACT
The objective of this report is turn on and off a 120V light bulb by the
implementation of digital-analog circuits, the process to turn on and off the
bulb depend of the output of the circuits: parity detector, infrared detector
and light sensor. Where a control stage generate a priority for one at a time
of the circuits. Finally there is a final stage composed by a relay which
generate a DC-AC interface guaranteeing the on-off of the light bulb.

INTRODUCTION
The laboratory consists of three initial stages which are parity detection, the
4 -bit input and an only one output, an infrared detector, which detect
blockage of light output generates a zero ( 0) and bearing no obstruction
generates a one (1), by the way a Schmitt trigger generates an investment
in late departures; finally a binary circuit that delivers a one ( 1) logical
when an enclosure is in low light, and a logical zero (0), when it has a high
light by the use of a photoresist, at the end there is and control stage, which
allows only one output of the three circuits supplied. In this laboratory we
are applying some concepts that will be seen below:
Logic gates are a block of circuitry that produces logic output signals (1 or 0)
if the input conditions are met. A logical 1 is a high state which satisfies 5V,
and a logic 0 is a status under which meets at 0V

AND GATE: The AND gate serves as a logical multiplication. That is

making the values that apply to your inputs and multiplies.

OR GATE: An OR gate is a circuit that produces a high output (logic

1) when any of the input variables is 1.

XOR GATE: Unlike the OR gate, the XOR gate has an output equal to
"0" when its inputs are equal to 1.

XNOR GATE: Is a digital logic gate whose function is the negation of

exclusive OR gate (XOR).

ODD PARITY: In asynchronous communication systems, odd parity refers to

parity checking modes, where each set of transmitted bits has an odd

number of bits. If the total number of ones in the data plus the parity bit is
an odd number of ones, it is called odd parity. If the data already has an odd
number of ones, the value of the added parity bit is 0, otherwise it is 1.
SCHMITT TRIGGER: Most CMOS, BiCMOS and TTL devices require fairly fast
edges on the high and low transitions on their inputs. If the edges are too
slow they can cause excessive current, oscillation and even damage the
device. A Schmitt trigger type device is used to translate the slow or noisy
edges into something faster that will meet the input rise and fall specs of
the following device. A true Schmitt trigger input will not have risen and fall
time limitations.
ANALYSIS AND RESULTS
The first task was the design and implementation of a combinational circuit
which generate an odd parity bit from four input bits, which works as a
switch activating a relay to switch-on a 120V light bulb. For this was made a
table of true in which it is intended that the total number of ones (1) present
in the input plus the output is odd.
The next one is the table of true made:
TABLE1. Truth Table odd parity
A

OU
T
1

MINTE
RMS

0
0
0

0
0
0

0
1
1

1
0
1

0
0
1

A B CD

0
0

1
1

0
0

0
1

0
1

A B C D

A BC D

0
1
1

1
0
0

1
0
0

1
0
1

0
0
1

A B C D

A B C D

1
1

0
1

1
0

1
0

0
1

AB C D

1
1
1

1
1
1

0
1
1

1
0
1

0
0
1

ABCD

A B C D

The disjunctive canonical form (SOP) was used to then simplify using
Boolean algebra.

Obtaining this:
(1)

) +( A B
C
D ) + ( A B C D
)+ ( AB C
D
) +( ABCD )
( A B C D )+ ( A B CD ) + ( A B C D ) + ( A BC D
(2)

)+ A B
(C
D+C D
) + AB ( C D+CD)

) + A B ( C D+C D
A B ( C D+CD
(3)
(4)
(5)
(6)

D ) + AB ( C
D )+ A
B ( C D )+ A B ( C D )
A B ( C
D ) ( A B+
AB ) + ( C D ) ( A
B+ A B )
(C
D ) ( A B
)+ ( C D )( A B )
(C
(C D)
( A B )

After getting the minterms of the table of truth and realize the SOP, the
expression (1) was obtained. Then using the distributive postulate, the

expression (2) was obtained. Knowing that ( a b+ ab ) is equal to XNOR (

a b
), and ( a b+ a b ) is equal to XOR ( a b ), the expression (3) was
obtained. Using again the distributive postulate the expression (4) was
obtained. Knowing the description of the logic gates previously described
(XOR and XNOR), the expressions (5) and (6) were obtained.

Having the simplified expression, the simulation was realized in the software
QUARTUS II:

This prove that the simulation coincide with the table of truth.
The second task was the design and implementation of a binary object
detector circuit using an infrared emitter and receptor where the output is a
logic one (1) when the passage of light is interrupted. This circuit works as a
switch which active a relay and allow the on-off of a 120V light bulb.
The next one is the designed circuit:

In this circuit the transistor Works in commutation mode. When the light
passage between the emitter and receptor is not interrupted, the base of
the transistor is not polarized and it works on saturation and the output is a
logic one (1). When the light passage is interrupted, the base of the
transistor is polarized and it works on cut-off mode giving an output of a
logic zero (0). This output is connected to a Schmitt trigger, which allow the
obtaining of ones and zeros well defined in the presence of noise signals. It
also negate the output so the real output is a logic one (1) when the light
passage is interrupted and a logic zero (0) when is not.

The third task was the design and implementation of a binary circuit that
delivers a logic one (1) logical when an enclosure is low brightness and a
logic zero (0) when is high brightness by the using a photoresist sensitivity
controlling by a potentiometer, the value of the photoresist varies with the
light, thus increasing the light its resistance decreases, creating a
polarization current in the allowing the transistors operation, generating
logic 1 for a one and a zero as possible as it can. A Smith fired was used to
improve the accuracy of the logic states and also to generate a negation
output signal. Like the previous two circuits this circuit functions as a switch
to activate a relay subsequently activates a light bulb 120V.

Because there is three circuits which have the capacity to activate a relay
by generating a logic one (1), its necessary to design and implement a
control stage with two input bits and one output bit. Each of the outputs of
the previous circuits go to a three-state gate with the finality of allowing the
pass of the signal corresponding to the active output. This stage ensure that
there is no more than one switch activated simultaneously, determining
which of the outputs of the three previous circuits is the one who have
influence in a determinate moment and impose the state of the output.
A table of truth was made every output to determine this control stage:
C1
0
0
1
1

C2
0
1
0
1

S1
0
1
0
0

C1
0
0
1
1

C2
0
1
0
1

S3
0
0
0
1

C1
0
0
1
1

C2
0
1
0
1

S2
0
0
1
0

Using (SOP) the next expressions were obtained:

S 1=C 1 C 2
S 2=C 1 C 2
S 3=C 1 C 2
The control stage can be implemented by using NOT and AND gates.

The next one is the simulation of the control stage using the software
QUARTUS II:

This prove that the simulation coincide with the table of truth.
CONCLUTION
The objectives of the practice can be achieved using the knowledge learned
in class, however they must be deepened with the help of other media, and
thus achieve compliance with the task.
The combination of knowledge previously learned in the course of analog
electronics plus new themes and concepts of digital electronics are essential
to the realization of the proposed practices.
The laboratory practice help us to dispel many doubts and improves
understanding of the digital logic circuits, assembly of various components
help us to understand its operation and speeds up analysis in problem
solving.
Digital circuitry opens the door to the control process and automation
facilitating the creation and implementation of many objects of daily life.