University of Nebraska - Lincoln

ELEC 470 Project Report

Four-bit ALU Schematic and Layout Simulation with Cadence

Dongpu Jin
Professor: Dr. Sina Balkir
5/3/2012
Spring 2012

Contents
Abstract ........................................................................................................................................... 3
1. Introduction ................................................................................................................................. 3
2. Implementation ............................................................................................................................ 5
2.1 Four-bit ALU Layout ............................................................................................................. 5
2.2 Four-bit ALU Schematic........................................................................................................ 6
3. Results ......................................................................................................................................... 6
3.1. Test Bench ............................................................................................................................ 6
3.2. Post Simulation..................................................................................................................... 7
4. Discussion ................................................................................................................................. 11
5. Conclusion ................................................................................................................................. 11
6. Reference ................................................................................................................................... 11
Appendix........................................................................................................................................ 12
1. Inverter .................................................................................................................................. 12
2. AND Gate .............................................................................................................................. 13
3. OR Gate ................................................................................................................................. 16
4. Transmission Gate ................................................................................................................. 18
5. XOR Gate .............................................................................................................................. 19
6. Two-to-One Mux.................................................................................................................... 21
7. Four-to-One Mux .................................................................................................................. 23
8. Full Adder.............................................................................................................................. 24

Abstract
ALU stands for Arithmetic Logic Unit, which is a digital circuit that performs
arithmetic and logical operations. In this project, a four-bit ALU is designed,
implemented and simulated using the Cadence software. Cadence is an electronic design
automation software that supports circuits schematic and layout design and circuit
simulation.

1. Introduction
The four-bit ALU [1] in this project supports addition, 2's complement subtraction,
overflow detection, bitwise invert, bitwise logic AND, bitwise logic OR and bitwise logic
XOR operations. The high level circuit diagram of the four-bit ALU is shown in Figure 1.

Figure 1 four bit ALU circuit diagram

Note that in the circuit diagram above, unnecessary wire connections are
eliminated so that it is easier to read. As we can see from Figure 1, the diagram can be
roughly divided into four sections. They are arithmetic section (blue), overflow section
(yellow), logical section (red) and selection section (green).
The blue section is a chain of full adders. It is responsible for addition (ADD),
subtraction (SUB) and invert (INV) operations. The ADD operation requires Binv set to

low, such that it functions like a ripple adder. For SUB operation, it uses 2's compliment
and thus, A-B becomes A + (-B). The usage of Binv has two folds. Firstly, when Binv is
high, B will be inverted (through the inverter and MUX) before going into the full adder.
Secondly, Binv also serves as the initial carry-in for 2's complement. To perform bitwise
INV, input A needs to be set to zero and Binv set to high to invert input B. As a result, B
first got invert to -B and the operation becomes 0 + (-B) = -B.
The yellow section reports if there's any overflow occurs throughout an operation.
Overflow happens when adding two positive numbers but the result is negative (the most
significant bit is 1). For instance, 0101 + 0011 = 1000, the resulting value 1000 is
negative in 2's compliment, so overflow has occured. We want to set the overflow bit (V)
to high when such situation happens. The carry out from last two full adders can be XOR
together. The result would be the overflow bit.
The red section performs bitwise logical operations, including AND, OR and
XOR. Since each gate handles only one bit, in order to handle four-bit inputs, we need to
place four gates of the same kind in parallel.
The green section is select section, which determines which operation results go
to the output. There are two bit select line (SEL0, SEL1) that select different operations.
The mapping of selection bits and operations is summarized in Table 1.
ALU Select
00
01
10
11

Operation
ADD, SUB, INV
AND
OR
XOR

Table 1 Mapping of ALU selection bits to operations

The design flow of this project can be briefly summarized as the following. First,
the schematic of the four-bit ALU (i.e., the circuit diagram) is developed and simulated
under Cadence's [2] schematic environment. Once the simulation results are correct and
error free, it leads to the next step of drawing the layout representation of the ALU under
Cadence's layout environment. The layout environment uses ami06 technologies and it
enforces many spacing constraints, such as the minimum channel length constraint. After
drawing the layout representation of the ALU, it needs to be mapped to the schematic
representation of the ALU that is developed earlier. In Cadence, LVS (Layout Versus
Schematic) check is used for the mapping. If the layout doesn't match the schematic,
errors will occur in the LVS report. If they successfully match, the next step is postsimulation, which verifies if the layout behaves the same as the schematic. A config view
test bench is used for the post-simulation.
The rest of report is organized as follows. Section 2 shows the implementation
using the Cadence software. Section 3 shows the simulation results. Section 4 discusses

some issues, road blocks and future work. Section 5 concludes the report. Section 6 lists
the references.

2. Implementation
This project is carried out using modular and hierarchical design methodology. To
be more specific, the whole ALU is broke down into many small pieces as described in
the previous section. Each piece consists of many gates that are built using standard cells.
The advantage of standard cells s that it maintains the consistency of the project since all
the cells have the same height and it increases the reusability of components because all
standard cells can be reused in a hierarchical manner.

2.1 Four-bit ALU Layout

Figure 23 Four-bit ALU layout

2.2 Four-bit ALU Schematic

Figure 34 Four-bit ALU schematic

3. Results
Once the layout of the four-bit ALU is completed, circuit components need to be
extracted from the layout. Then, the extracted circuit is LVS checked against with the
schematic of the ALU. Errors such unmatched terminals, unmatched number of nets,
flipped connections, etc, are identified in the LVS report. Those errors need to be
corrected before moving to the next phase - post simulation. In post simulation, the
analog version of the ALU is extracted. The config view of the test benched is established
for the simulation as well. This section mainly explains the post simulation of the four-bit
ALU.

3.1. Test Bench

The following is the test bench setup for post simulation. Both the schematic
symbol (top box) and the analog extracted layout (bottom box) of the four-bit ALU are
inserted into this test bench, such as we can simulate and compare both schematic and
layout simultaneously. As it is shown in the opened window, the config view need to be
selected and the simulation type is set to tran (transient). Input signals are provided via
vpulse voltage sources that produce square waves. There are total 11 input signals,
including four-bit input A, four-bit input B, Binv, and two-bit select line. The four-bit
output and overflow bit are observed for output.

Figure 4 Post simulation test bench

3.2. Post Simulation

The post simulation of this project is conducted under the Virtuoso analog design environment. The simulations waveforms
below demonstrate that the ALU is functioning as expected. In the simulation, the value of input A is 0101 (5 in decimal) and the

value of input B is 0011 (3 in decimal). Two selection bits are permutated with all the combinations, such that all the operation outputs
can be observed.

Figure 5 Four-bit input A is 0101

Figure 6 Four-bit input B is 0011

Figure 7 Permutation of selection bits

Test case 1 (Binv is low):

In this test case, Binv is set to low, which means that B is not inverted before going into each full adder. As the result, when selection
is 00, it computes 0101 + 0011 = 1000, which causes overflow; when selection is 01, it computers 0101 AND 0011 = 0001; when
selection is 10, it computes 0101 OR 0011 = 0111 and when selection is 11, it computes 0101 XOR 0011 == 0110.

Figure 8 Binv is low, input B is not inverted

Figure 9 Post simulation results of test case 1

Test case 2 (Binv is high):

In this test case, Binv is set to high, which means that B is inverted before going into each full adder. As the result, when selection is
00, it computes 0101 - 0011 = 0010, where overflow does not occur. The rest of the results stay as the same as the previous test case

since both input A and input B are the same (when selection is 01, it computers 0101 AND 0011 = 0001; when selection is 10, it
computes 0101 OR 0011 = 0111 and when selection is 11, it computes 0101 XOR 0011 == 0110).

Figure 10 Binv is high, input B is inverted

Figure 11 Post simulation result for test case 2

4. Discussion
The trickiest part of this project would definitely be the layout design. Since there
are many spacing rules the design must follow, it becomes very difficult to plan out the
entire layout all at once, especially for a large circuit such as a four-bit ALU. I found it is
helpful to draw the small parts of the layout on sketch papers before going into Cadence
layout drawing tool. Those sketches provide a rough idea about how the layout should be
drawn. Another useful strategy would be running design rule check (DRC) as often as
possible, such that design rule errors can be resolved as early as possible.
The space utilization of this version of design is not the optimum. There are still
plenty of empty spaces exist in the layout that can be shrunk down. In addition, I used
30um as the height of standard cells, which is not optimum neither. For the future work,
both the empty spacing and standard cell height of this four-bit ALU may be optimized to
further reduce the chips area.

5. Conclusion
In summary, a four-bit ALU that is capable with arithmetic operations including
addition, 2's complement subtraction, overflow detection and logical operations including
bitwise invert, bitwise AND, bitwise OR and bitwise XOR is design and implemented
using Cadence software. Both the schematic design and layout design of the ALU are
simulated. The post simulation result shows that the ALU functions correctly as expected.

6. Reference
[1] ALU Wikipedia: http://en.wikipedia.org/wiki/Arithmetic_logic_unit
[2] Cadence: http://www.cadence.com/us/pages/default.aspx

11

Appendix
1. Inverter
Inverter is the most basic building block of digital circuit. It can be viewed as a
PMOS and a NMOS connected in series. The schematic, layout and simulation results for
a inverter are shown as follows.

Figure 12 Inverter schematic

Figure 13 Inverter layout

Figure 14 Inverter simulation

2. AND Gate
AND gate is built based on NAND gate. Their schematic, layout and simulation result are shown
below.

Figure 15 NAND schematic

Figure 16 NAND layout

Figure 17 NAND simulation

Figure 18 AND schematic

Figure 19 AND layout

Figure 20 AND simulation

3. OR Gate
Similar to AND gate, OR is also built on other gate, NOR gate. Their schematic, layout,
and simulation results are shown below.

Figure 21 NOR schematic

Figure 22 NOR layout

Figure 23 NOR simulation

Figure 24 OR schematic

Figure 25 OR layout

Figure 26 OR simulation

4. Transmission Gate

Figure 27 Transmission gate schematic

Figure 28 Transmission gate layout

Figure 29 Transmission gate simulation

5. XOR Gate
XOR gate is built using transmission gates and inverters.

Figure 30 XOR schematic

Figure 31 XOR layout

Figure 32 XOR simulation

6. Two-to-One Mux

Figure 33 Two to One Mux schematic

Figure 34 Two to One Mux layout

Figure 35 Two to One Mux simulation

7. Four-to-One Mux

Figure 36 Four-to-One Mux schematic

Figure 37 Four-to-One Mux layout

Figure 38 Four-to-One Mux simulation (top half)

Figure 39 Four-to-One Mux simulation (bottom half)

8. Full Adder

Figure 40 Full Adder schematic

Figure 41 Full adder layout

Figure 42 Full adder simulation