TRNG I HC BCH KHOA TP.

HCM
KHOA IN IN T
B MN IN T

TP.HCM, 2011

Ni dung
1. Gii thiu KIT DE1
2. Hng dn thit k vi phn mm Quartus II
3. V d

Ni dung
1. Gii thiu KIT DE1
2. Hng dn thit k vi phn mm Quartus II
3. V d

Ni dung
1. Gii thiu KIT DE1
2. Hng dn thit k vi phn mm Quartus II
3. V d

Hng dn thit k vi phn mm

Quartus II ca Altera
Khi to mt Project
Thit k u vo dng
Verilog (hoc VHDL)
Bin dch mch
c thit k
Gn chn
(pins assignment)
M phng mch
c thit k
Np chng trnh
ln KIT& kim tra

Hng dn thit k vi phn mm

Quartus II ca Altera
Khi to mt Project
Thit k u vo dng
Verilog (hoc VHDL)
Bin dch mch
c thit k
Gn chn
(pins assignment)
M phng mch
c thit k
Np chng trnh
ln KIT& kim tra

1. Khi to mt Project (1/10)

1. Khi to mt Project (2/10)

FileNew Project Wizard

1. Khi to mt Project (3/10)

Click vo hp (box) Dont show me this introduction again

Tip theo nhp Next

1. Khi to mt Project (4/10)

Lu : tn Project khng c dng khong trng

1. Khi to mt Project (5/10)

Xut hin thng bo:

Nhn Yes

1. Khi to mt Project (6/10)

Tip tc nhn Next

1. Khi to mt Project (7/10)

Chn chip Cyclone II EP2C20F484C7 (FPGA c s dng trn board DE1)

Chn chip Cyclone II EP2C35F672C6 (FPGA c s dng trn board DE2)

Nhn Next

1. Khi to mt Project (8/10)

Khng cn chn EDA (Electronic Design Automation) Tool no

Nhn Next

1. Khi to mt Project (9/10)

Bng tm tt cc thng s ci t cho Project

Nhn Finish

1. Khi to mt Project (10/10)

Hin th ca Quartus II cho Project c to ra

Hng dn thit k vi phn mm

Quartus II ca Altera
Khi to mt Project
Thit k u vo dng
Verilog (hoc VHDL)
Bin dch mch
c thit k
Gn chn
(pins assignment)
M phng mch
c thit k
Np chng trnh
ln KIT& kim tra

2. Thit k u vo dng Verilog (hoc VHDL)

(1/7)
V d ta thit k mch sau dng ngn ng Verilog

f = x1 x2

2. Thit k u vo dng Verilog (hoc VHDL)

(2/7)
FileNew

2. Thit k u vo dng Verilog (3/7)

Trong ca s New chn Verilog HDL File

Nhn OK

Nu vit bng VHDL

th chn VHDL File

2. Thit k u vo dng Verilog (4/7)

Vng son tho

2. Thit k u vo dng Verilog (5/7)

2. Thit k u vo dng Verilog (6/7)

FileSave

File name: lu tn trng vi tn ca module

Save as type: Verilog HDL File

Check chn Add file to current project

2. Thit k u vo dng Verilog (7/7)

Sau khi lu file

Hng dn thit k vi phn mm

Quartus II ca Altera
Khi to mt Project
Thit k u vo dng
Verilog (hoc VHDL)
Bin dch mch
c thit k
Gn chn
(pins assignment)
M phng mch
c thit k
Np chng trnh
ln KIT& kim tra

3. Bin dch mch c thit k (1/4)

Click chut vo biu tng khoanh vng trn mu (Start Compilation)

Hoc vo Processing Start compilation

3. Bin dch mch c thit k (2/4)

Ch bin dch cho n khi xut hin thng bo

Nu bo NOT successful th ta tin hnh sa li

chng trnh ri bin dch li

3. Bin dch mch c thit k (3/4)

3. Bin dch mch c thit k (4/4)

Double click vo thng bo li (dng ch mu ) xc nh v tr li

Trong v d trn th l li c php (syntax error), thiu du ;

Hng dn thit k vi phn mm

Quartus II ca Altera
Khi to mt Project
Thit k u vo dng
Verilog (hoc VHDL)
Bin dch mch
c thit k
Gn chn
(pins assignment)
M phng mch
c thit k
Np chng trnh
ln KIT& kim tra

4. Gn chn (pins assignment) (1/4)

Chn Assignments Import Assignments

4. Gn chn (pins assignment) (2/4)

Chn ng dn cha file DE1_pin_assignments.csv

(nu dng KIT DE1) hoc file DE2_pin_assignments.csv
(nu dng KIT DE2)

Nhn OK

4. Gn chn (pins assignment) (3/4)

Chn Assignments Assignment Editor

4. Gn chn (pins assignment) (4/4)

Trong khung Category chn: Pin

Double click vo SW[0] chn x1 (dng SW[0] lm ng vo x1),
tng t ta c SW[1] x2, LEDR[0] f

Nhn Save, ri bin dch li chng trnh

Lu : nu ta t tn cc bin ng vo, ra ca module trng vi tn

cc chn trn KIT th ta b qua bc ny (tn cc chn trn KIT xem
file DEx_pin_assignments.csv, vi x l 1 hoc 2)

Hng dn thit k vi phn mm

Quartus II ca Altera
Khi to mt Project
Thit k u vo dng
Verilog (hoc VHDL)
Bin dch mch
c thit k
Gn chn
(pins assignment)
M phng mch
c thit k
Np chng trnh
ln KIT& kim tra

5. M phng mch c thit k (1/11)

Chn File New Vector Waveform File

Nhn OK

5. M phng mch c thit k (2/11)

Ca s Waveform Editor

5. M phng mch c thit k (3/11)

Chn thi gian m phng t 0 n 200ns bng cch vo:
Edit End Time

Trong khung Time nhp vo: 200, chn n v l ns

Nhn OK

5. M phng mch c thit k (4/11)

Chn View Fit in Window

5. M phng mch c thit k (5/11)

Chn Edit Insert Insert Node or Bus

Nhn Node Finder

5. M phng mch c thit k (6/11)

Khung Filter chn: Pins:all

Nhn List

Chn cc ng vo, ra trong khung Name ri nhn biu tng >>

Nhn OK

5. M phng mch c thit k (7/11)

5. M phng mch c thit k (8/11)

Xc nh cc gi tr lun l c dng cho tn hiu u vo x1 v x2
trong qu trnh m phng

Lu vector waveform file

5. M phng mch c thit k (9/11)

Chn Assignments Settings

Click vo Simulator Settings trong khung Category

Khung Simulation mode chn: Functional

Khung Simulation input chn ng dn lu file *.vwf (trong * l tn ca
vector waveform file)

Khung End simulation at nhp thi gian kt thc m phng

Nhn OK

5. M phng mch c thit k (10/11)

Chn Processing Generate Functional Simulation Netlist

Sau khi thng bo successful, click OK

Chn Processing Start Simulation

5. M phng mch c thit k (11/11)

Simulation result

Hng dn thit k vi phn mm

Quartus II ca Altera
Khi to mt Project
Thit k u vo dng
Verilog (hoc VHDL)
Bin dch mch
c thit k
Gn chn
(pins assignment)
M phng mch
c thit k
Np chng trnh
ln KIT& kim tra

6. Np chng trnh ln KIT& kim tra (1/2)

Trn KIT DE1 bt SW12 v tr RUN (KIT DE2 bt SW19
v tr RUN ) Ch JTAG

Kt ni cp USB t my tnh vi USB-Blaster trn KIT
DE1 (i vi KIT DE2 cn phi cp thm ngun 9VDC)

Bt nt ngun (nt mu )

Chn Tools Programmer

Nhn Start

6. Np chng trnh ln KIT& kim tra (2/2)

Ni dung
1. Gii thiu KIT DE1
2. Hng dn thit k vi phn mm Quartus II
3. V d

V d

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