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861125598
EE 120A Section 24
Lab 4 -- Sequential Logic Design
Lab Partner: Claire Yang

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Overview
This lab was intended to provide familiarity with clock synchronous state machine design and
the following synthesis and implementation of the design and the usage of a function generator
for external "clock" inputs for Basys-2 FPGA boards through PMOD input/output connectors.
This lab also provides familiarity with using buses in schematic capture and vector entries in
configuration files and the control of external clocks. This is done through implementing and
testing a flight attendant call system and an LED display time multiplexing circuit. This is done
through the use of Xlinx, ModelSim, and Adept software.
New Concepts
wire splitter: inputs one wire and all outputs are the same as the input
buffer: temporarily stores data
excitation equation: designed to get the minimum amount of inputs required to get to a certain
designated state
Analysis
Truth table for flight attendant call system

Call
0
0
0
0
1
1
1
1

Cancel
0
0
1
1
0
0
1
1

Q
0
1
0
1
0
1
0
1

D
0
1
0
0
1
1
1
1

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Experiment 1:
The task was to design a schematic for a flight attendant call system with a given output and
transition table and then implement and test the design by using the SYNC output as an external
driving clock. The design specifications are that when the call button is pressed, a light turns on
and when released, the light stays on until the cancel button is pressed. To implement this design,
a schematic was created using Xlinx software as seen in Figure 1. The design included a clock, a
three input AND gate and a 2 input OR gate. To test the validity of our design, a .vhd file was
created and clock signals were programmed into that file to create a test bench using ModelSim
software. As seen in Figure 2, our design was verified due to the fact that when cancel, call, and
clk are set to 1, 1, and 0, respectively, the value of the led is 1. A user constraint file was then
created as seen in Figure 3 where we had designated two switches to act as the call and cancel in
the flight attendant system and one led light to act as our corresponding led for our design. Once
a programming file was generated, a .bit file was created and was loaded into the Adept software.
Once uploaded to Adept, we were able to validate our results using the corresponding switches
on our Basys-2 boards.
Truth table for LED display time multiplexing circuit
Binary Inputs
D0
0
0
0
0
0
0
0
1
1

D1
0
0
0
0
1
1
1
0
0

D2
0
0
1
1
0
0
1
0
0

Decoder Outputs
D3
0
1
0
1
0
1
0
0
1

A
1
0
1
1
0
1
1
1
1

B
1
1
1
1
1
0
0
1
1

C
1
1
0
1
1
1
1
1
1

D
1
0
1
1
0
1
1
1
1

E
1
0
1
0
0
0
1
1
0

7-Seg Outputs
F
1
0
0
0
1
1
1
1
1

G
0
0
1
1
1
1
1
1
1

0
1
2
3
4
5
6
7
8
9

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Experiment 2:
The task in the third part of lab 4 was to create a LED display time multiplexing circuit. A
multiplexing circuit is used to in order to decrease the amount of used FPGA input and out pins.
To do this, an eight to one wire splitter is created so that the four displays share eight common
active low signals to light the segments. Before a design was implemented, a truth table was
drafted which had 4 inputs, D0 through D3 and 8 outputs from the decoder which was A through
G. The decoder outputs correspond to the output that displays on the LED displays. Before the
full schematic was created, a separate wire splitter schematic was created in order to build a
more compact wire splitter schematic symbol. The wire splitter was designed through the use of
8 input buffers which were one bit each and bus taps which outputted one 8 bit output. The wire
splitter schematic symbol was then created in Xlinx and to complete the multiplexing circuit, a
two to four decoder , a four to one multiplexer, and a clock signal were added as seen in Figure
4. To verify the schematic, a user constraint file was created and a corresponding .bit file was
generated. The bit file was then loaded into the Adept software.

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Records

Figure 1: Flight attendant call system schematic

Figure 2:Part 1 test bench

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Figure 3: Part 1 .ucf file

Figure 4: LED Display Time Multiplexing Circuit

Discussion
The first part of this lab worked as per the specifications and was able to be verified using a test
bench in the ModelSim software and through testing on our Basys-2 FPGA boards. However,
due to Xlinx error, the third part of this lab was not able to be completed as per the specifications
in the time allotted.

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Conclusion
Through this lab, we have gotten more familiar with the creation of schematic symbols, using
buses, and using a function generator's SYNC output as an external driving clock. This was done
through the implementation and simulation of a flight attendant call system and a LED display
time multiplexing circuit. The implementation was done through the use of Xlinx and ModelSim
software. The simulation was done through using Adept software and connecting wires to a
function generator from our Basys-2 FPGA boards.
Questions
1. What will happen if the clock signal is of very low frequency (1 Hz)?
The clock signal will transmit much better to the Basys-2 FPGA board if the frequency is lower.