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EE 120A Section 24
Lab 7 -- Register File Design
Lab Partner: Claire Yang

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Overview
This lab was intended to provide familiarity with the design, synthesis, and implementation of a
register file and the emulation of the register file's performance. As per the specifications, a
2^2x4 register file was designed using Xilinx software, and then a waveform was generated that
served as a test bench using ModelSim software to verify our design was working. The
implementation was done on a Basys-2 FPGA board using Adept software.
New Concepts
register file: efficient design that allows for one-at-a-time read and write of many registers
Analysis
2 to 4 decoder truth table
I0
I1
0
0
0
1
1
0
1
1
4 to 1 multiplexer truth table
Enable
S1
0
X
1
0
1
0
1
1
1
1
D Flip Flop truth table
Enable
0
1
1

D0
0
0
0
1
S0
X
0
1
0
1

D0
X
1
X
X
X
I0
X
0
1

D1
0
0
1
0

D2
0
1
0
0

D1
X
X
1
X
X

D2
X
X
X
1
X
I1
X
^
^

D3
1
0
0
0
D3
X
X
X
X
1

Output
0
1
1
1
1
Q
0
1

The task in this lab was to design a register file of the size 2^2 x 4. The overall design consists of
4 registers, a 2x4 decoder, a 4x1 multiplexer, and 3 wire splitters as seen in Figure 3. The
schematic design was done using Xilinx software. The 4 bit register was created using 4 somg;e
D flip flops and bus taps for the inputs and the outputs so the bit widths would be correct as seen
in Figure 1. A 1 to 4 wire splitter was also created and turned into a schematic symbol using the
Xilinx schematic design symbol. as seen in Figure 2. A 2 to 4 decoder was used which served as
our write function and write enable. Each of the decoders 4 outputs directly connected to the
write data input on our register. The 4 bit input on each of the registers corresponded to a

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different switch. The clock signals on each of the registers were connected together and each of
the 4 bit outputs connected to an input on a 4x1 multiplexer. The output of the multiplexer were
4 led lights. Instead of using a decoder for the write functions, 3 wire splitters were used which
served as our write enable and 2 write functions. The two write functions connected into the two
select lines on the multiplexer and the write enable connected to the enable on the multiplexer.
To verify our design, a .vhd file was generated and using ModelSim software, we generated a
waveform which served as a test bench to validate our schematic design. As seen in Figure 4, our
test bench waveform worked as per the specifications. A user constraints file was then created as
seen in Figure 5 where we chose 4 switches for our read and write functions, 2 buttons for our
read and write enables, and 6 led lights for the 4 bit output and 2 for addresses. A programming
file was then created and the bit file was then loaded into the Adept software. We then
implemented our design using our Basys-2 FPGA board and our design was able to be validated.

Records

Figure 1: 4 bit register

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Figure 2: 4 to 1 wire splitter

Figure 3: Register file schematic

Figure 4: Waveform test bench

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Figure 5: User constraints file

Discussion
Our 2^2 x 4 register file design worked as per the specifications and the design was able to be
verified using a test bench in ModelSim software and through implementation done on a Basys-2
FPGA board. Our initial design included our two select lines connecting to two outputs of a 2 to
4 decoder. However, that design did not work for us and instead, we used three wire splitters for
our read enable and two reads for our register file. Once this was completed, we were able to
verify our design using a test bench and implement our design on a Basys-2 board.
Conclusion
Through this lab, we gained knowledge on how a register file works and its performance through
the design, synthesis, and implementation of a 2^2 x 4 register file. We were able to see the trade
offs of using a register file in that it is fast and flexible, but only for small and temporary storage.
Questions
n/a