Cost Effective Spread Spectrum

Clock Generator Design

Chulwoo Kim, Minyoung Song, Sewook Hwang
Advanced Integrated Systems Lab.
Korea University, Seoul, Korea

Outline

Introduction
Spread Spectrum Clock Generation
Frequency Modulation Profile
Design Approaches for SSCG
Cost-Effective Design of SSCG
Conclusions

Outline

Introduction
Spread Spectrum Clock Generation
Frequency Modulation Profile
Design Approaches for SSCG
Cost-Effective Design of SSCG
Conclusions

Introduction
Electromagnetic Interference (EMI)
Severe at the higher frequency spectral
component
System-level and chip-level
High performance design
high integrated and high speed

Various EMI reduction techniques

Shielding
External filtering
Spread spectrum clock generation

Methods for EMI Reduction (1)

Shielding
Hard to apply to inter-chip communications
Cost-expensive

EMI Shielding w/ Metal Caps

CX2520SB (Kyocera)

EMI Shielding w/ Lids

Methods for EMI Reduction (2)

Low voltage differential clocking

Decreasing the signal level directly

Cost of level conversion and complex routing
Reduced spectrum amplitude
SNR decrease as well as EMI reduction
A/N
A
A/N
t

A
A/N
f

Methods for EMI Reduction (3)

External filtering
Increasing the rise and fall times of the clock.
The larger rise and fall times, the lower highfrequency spectral components
Expensive
Hard to apply for high-frequency applications
Tr

Tf

Tr=Tf

in

-20 dB/decade

FILTER

out

-20 dB/decade
-40 dB/decade

1
T

1 1
T Tr

Outline

Introduction
Spread Spectrum Clock Generation
Frequency Modulation Profile
Design Approaches for SSCG
Cost-Effective Design of SSCG
Conclusions

Spread Spectrum Clock Generation :

EMI Reduction of the Clock Itself
Motivation
To use lower high-frequency spectral signal
directly
To be more effective as well as simple and costefficient solution

Spread spectrum clock generation

(SSCG)
To shape its clock spectrum itself and reducing its
peak
To spread its spectrum itself, its output frequency
should be changed slightly

Carsons Rule
Carsons rule gives the BW of frequency
modulated waveform
Total energy of original signal is kept unaffected.
The 98% of the total energy is contained inside a
BW calculated :

BW 2 f c f m
SSCGs use the modulation frequency more than
30 kHz
To avoid audible band (20 ~ 20kHz)
Typical values of mod. freq.: 30k ~ 250kHz

Equations for SSCG Output

SSCG output frequency and modulated phase
fCKout t Vs / 2 cos 2 fc t t Vs / 2
t f m , t dt 0
t

fm: The modulation frequency

Decide how often the output frequency is changed

: The frequency deviation

Decide how much the frequency is changed
f c f c

Some wireline applications (SATA, DisplayPort, etc. )

fm and as 30k ~ 33 kHz and 5000ppm, respectively

Spectra Analysis (1)

fm

BW

fm defines the distance b/w consecutive

harmonics (ripples).
fm and RBW of spectrum analyzer affect the
measured peak values.

Spectra Analysis (2)

fm

RBW >>fm

BW

RBW <<fm

Two extreme cases regarding RBW

RBW >fm :The measured values will be higher than theoretical values
by means of BPF characteristics
RBW <fm :The measured values will be matched to theoretical values
However, in general, it is enough to use the first case
if RBW < BW
fm increased Peak reduction decreased
increased Peak reduction increased

Spectra Analysis (3)

[Komatsu, ASSCC 2007]

Peak reduction:

fc
S 10 log

f
m

Outline

Introduction
Spread Spectrum Clock Generation
Frequency Modulation Profile
Design Approaches for SSCG
Cost-Effective Design of SSCG
Conclusions

Frequency Modulation Profile (1)

The frequency modulation profile
To decide the shape of the spectrum EMI reduction

Conventional profiles
The sinusoidal modulation
Easy to implement with analog circuit
Hard to implement with digital circuit

The triangular modulation

Simple but not optimum for EMI reduction.

The Hershey-Kiss modulation

Better EMI performance
Complex due to its non-linearity

Modulating waveform
0.2

0.1

0.1

0.1

0
-0.1
-0.2

Deviation (%)

0.2

0
-0.1
-0.2

5
time (ms)

10

0
-0.1
-0.2

-6

x 10

Modulating waveform integral

5
time (ms)

100

x 10

80

9
-6

x 10

50

40

40
30
20

20

20

60

60

Angle (rad)

Angle (rad)

40

5
time (ms)

Modulating waveform integral

80
60

-6

Modulating waveform integral

10

0
1

5
time (ms)

10

-6

x 10

After modulation

5
time (ms)

10

-20

-40

-40

-60
-80
-100
-120

Amplitude (dBV)

-20

-40

-60
-80
-100
-120

1.48

1.485

1.49

1.495
1.5
1.505
Side-band harmonics (GHz)

Sinusoidal

1.51

1.515

1.52

1.525
9

x 10

-140
1.475

5
time (ms)

9
-6

x 10

After modulation

-20

-140
1.475

-6

x 10

After modulation

Amplitude (dBV)

Amplitude (dBV)

Amplitude (dBV)

Modulating waveform

0.2

Deviation (%)

Deviation (%)

Modulating waveform

Angle (rad)

Angle (rad)

Deviation (, %)

Frequency Modulation Profile (2)

-60
-80
-100
-120

1.48

1.485

1.49

1.495
1.5
1.505
Side-band harmonics (GHz)

Triangular

1.51

1.515

1.52

1.525
9

x 10

-140
1.475

1.48

1.485

1.49

1.495
1.5
1.505
Side-band harmonics (GHz)

Hershey-Kiss

1.51

1.515

1.52

1.525
9

x 10

Displacement of Spectrum

Down
Spreading

Center
Spreading

Up
Spreading

Profiles also affect the displacement of spread

spectrum
Down spreading is preferable to guarantee
setup/hold time margins

Outline

Introduction
Spread Spectrum Clock Generation
Frequency Modulation Profile
Design Approaches for SSCG
Cost-Effective Design of SSCG
Conclusions

Clock Generation Architecture

A DLL-based clock generator
Hard to implement a finer frequency control
Changing its delay rather than frequency itself

A PLL-based clock generator

Finer frequency control is available.
Frequency-controllable PLL
REF
CK

OUTPUT
CK
PFD

CP

VCO

DIVIDER

Design Approaches for SSCG

Method I:
Modulating input voltage of VCO
directly

PFD

CP

VCO
LF

DIVIDER
Method II:
Controlling the division ratio of feedback
divider

Direct control of input of VCO

Controlling the CP current
Feeding external control voltage

Control the division ratio of the programmable

feedback divider
Controlling the division ratio

SSCG Using a Programmable CP

Main Divider

PFD

CP1

VCO
Output CK

Divider

Programmable
Charge Pump

Control Signals

[Chang, JSSC 2003]

PLL loop characteristic does not affect the SS

modulation.
Suffers from PVT variations of CP, LF & VCO
gain and generates additional jitter.

SSCG Using a Programmable Divider

Input CK

PD

LPF

VCO

Output CK

DIVIDER

Profile

[Kokubo, ISSCC 2005]

modulator : To filter out quantization noise

Quantization noise issues
Similar to fractional-N PLL
Solution
PLL loop bandwidth small enough to filter out the quantization
noise
To design a modulator to shape the quantization noise
better.

Outline

Introduction
Spread Spectrum Clock Generation
Frequency Modulation Profile
Design Approaches for SSCG
Cost-Effective Design of SSCG
Piecewise Linear Modulation
Newton-Raphson Profile Generator

Conclusions

A Cost-Effective Design of SSCG

Trade-off
EMI performance vs. circuit complexity

The piecewise linear modulation profile (PWL)

Linear operation
Simpler than Hershey-Kiss modulation

Higher EMI reduction

Amplitude

Increasing the slopes near the maximum and minimum peaks

compare to triangular modulation

2Am

[Song, CICC 2008]

Am

Tm
Am 1

Tm
Am 1

T1

Tm
4
1
T2
Tm
2

-Am

T1

T2

T1

time

4 T1 2 T2 Tm

1
fm

Optimum
To find optimal value
Condition
-18

-20

-22

Amplitude [dBV]

Tm
A

1
0
m
4

1 2

4 Am 1 Tm
1
1 Tm

-24

-26

-28

-30
1
0.8

9
0.6

8
7

0.4
6
0.2
; Ratio Between T1 and T2

x 10

5
0

1; Slope of The Linear Signal During T1

PWL Modulator

Controller

Modulation
Profile

Register
CK

Simple implementation with digital circuits

Synthesizable
Sync with SSCG reference clock

The -controller
Generating an add value () to change the slope of
the modulation profile
The more # of , the higher EMI reduction

Proposed Fractional Divider

Ckvco<0:9>

MUX

Phase Mixer
2

Mx

/60

CKfb

En
En
Sel

Controller

DR

The higher resolution of division ratio, the lower

quantization noise
Fractional dividing with 10-multi-phase clock
Phase mixer : increases the resolution of division ratio

Dividing with Phase Selecting

T
CKvco<0>
CKvco<1>

Shift -3
phases
CKvco<6>
CKvco<7>

Shift -3
phases
CKvco<4>

Shift -3
phases
CKvco<1>

7/10*T

7/10*T

7/10*T

CKout

Phase selecting
A resolution of division ratio is improved by 10 times.

Phase Mixing
Ckvco<0:9>

MUX

Phase Mixer
2

Mx

/60

CKfb

En
En

Controller

Sel

Sel

Sel<M>

Sel<M-2>

Sel<M-5>

En

0.75xT

DR

0.75xT

Mx
59.75xT
CKfb

Trade-off: VCO multi-phase vs. Phase noise

20 effective clock phases generated without
increasing the number of VCO delay line

Ex. SSCG Spectrum Results

Non-modulated spectrum

PWL modulated spectrum

9.7dB of peak reduction at 270MHz with down

spreading can be achieved from this figure.

Ex. Die Photo

Careful for clock skew and noise

Performance Comparisons
Sugawara
SOVC 02

Aoyama
SOVC 03

Kokubo
ISSCC 05

Lee
ISSCC 05

Ebuchi
JSSC 09

TCAS 08

Song
CICC 08

Modulation
Profile

Triangular

Triangular

Triangular

Triangular

Triangular

Triangular

Piecewise Linear

Freq. Deviation /
Modulation Freq.

-5150~-350ppm
30.3 ~ 33.3us

-5000 ~ 0ppm
32us

-5000 ~ 0ppm
32us

-5000 ~ 0ppm
33us

-20000 ~
0ppm
7.4 ~ 196us

-7500 ~
7500 ppm
-

-5000 ~ 0ppm
32us

Modulation
Method

Phase
Interpolation

Phase
Interpolation

Delta-Sigma

Delta-Sigma

Delta-Sigma

VCO

Delta-Sigma

Peak Reduction

7dB

5.43dB

10dB[12]

9.8dB

10.9dB @ 104M

16.3dB

14.2dB

Output Frequency

1.5GHz

1.5GHz

1.5GHz

1.5GHz

125 ~ 1250MHz

400MHz

1.5GHz

Peak to peak jitter*

57.2ps

41.01ps

80ps

67ps

27.88ps

RMS jitter*

9.3ps

3.07ps

10.7ps

10.7ps

3.77ps

Process

0.13um

0.15um

0.15um

0.18um

0.35um

0.18um

Area

0.42mm2

0.31mm2

0.47mm2

0.65mm2

0.49mm2

Power

54mW

15.6mW

27.5mW

40mW

*A jitter w/o spread-spectrum mode

Hsieh

Outline

Introduction
Spread Spectrum Clock Generation
Frequency Modulation Profile
Design Approaches for SSCG
Cost-Effective Design of SSCG
Piecewise Linear Modulation
Newton-Raphson Profile Generator

Conclusions

Newton-Raphson Profile Generator

- Newton-Raphson formula

- Proposed formula

1
x
yn1 yn x
2
yn

[Hwang, ISSCC 2011]

a 2 X [ n]
Y [ n]
X [n] AB s

2A
X [n] AB

Newton-Raphson Profile Generator

i) 0 n (Tm / 4)
X [n] STEP CNT [n]
ii) (Tm / 4) n (Tm / 2)
X [n] CNTMAX - STEP CNT [n]
where n k TN - R (k 0,1, 2,...)
- Up/Down Counter
- STEP : Slope of X

Newton-Raphson Profile Generator

2A

A2 X [n]
Y [ n]
X [n] AB S

2A
X [n] AB

- A[4:0] : Profile Resolution

- B[3:0] : Profile Slope

- S[5:0] : Profile Scale Factor

Newton-Raphson Profile Generator

A2 X [n]
Y [n] X [n] AB S

X [n] AB

- Shifter (A=25)
- Adder

- Shifter (A=25)
- Divider
- Shifter (S=25)

- Adder

Newton-Raphson Profile Generator

i) 0 < n < (Tm / 4), (3 Tm / 4) < n < Tm
NR[n] y[n]
ii) (Tm / 4) < n < (3 Tm / 4)

NR[n] 216 1 y[n]

SWC

- Subtractor

Newton-Raphson Profile Generator

i) 0 < n < (Tm / 4), (3 Tm / 4) < n < Tm
NR[n] y[n]
ii) (Tm / 4) < n < (3 Tm / 4)

NR[n] 216 1 y[n]

Memory is not required

in this process!!

Measured Modulation Profile

Proposed Architecture

Double binary-weighted DAC modulates the frequency information inside the

frequency-to-voltage converter (FVC) in the frequency-locked loop (FLL).
Newton-Raphson modulation profile is generated and transferred to the FLL
by the digital spread-spectrum controller (DSSC).

Measured EMI Reduction

42 cases : 14 and 3 fm
EMI Reduction : 19.14dB ~ 23.73dB

Measured Spectra

Die Micrograph

Process : 1P6M 0.13m CMOS

Area : 447.6m X 169.7m = 0.076mm2

Comparison with Other Works

Outline

Introduction
Spread Spectrum Clock Generation
Frequency Modulation Profile
Design Approaches for SSCG
A Cost-Effective Design of SSCG
Conclusions

Conclusions
SSCG
A powerful solution to reduce EMI reduction
Becoming essential to many applications
EMI reduction affected by the freq. modulation profile

Future Trends
Proposal of new profile and its optimization
The SSCG is also a clock source as well as EMI reducing device.
it is also required to enhance jitter performance.
A technique to reduce quantization noise should be also developed.

New EMI reduction mechanism.

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