International Conference on Power, Signals, Controls and Computation (EPSCICON), 8 10 January 2014

A Dynamic Voltage Restorer with an Improved PLL

for Voltage Sensitive Loads
Ramesh.K.Govindarajan, Pankaj Raghav.P* and G. Saravana Ilango, Member, IEEE
Department of Electrical and Electronics Engineering
National Institute of Technology, Tiruchirappalli
Tiruchirappalli, India
E-mail : pankaj.sarathy1992@gmail.com
AbstractDynamic Voltage Restorers (DVR) are commonly
used in the distribution network to protect voltage sensitive loads
from the effects of voltage sags, swells and imbalances. This
paper presents the modelling and control principle of a battery
based DVR. The energy storage element is used to absorb and
inject active power during steady-state operation. Finite Impulse
Response(FIR) lter based PLL is used for generating a reliable
voltage reference. The control strategy uses an inner current
control loop and an outer voltage control loop for generating
the inverter switching pulses. The performance of the system
is investigated by MATLAB simulations and is validated using
experimental results obtained from a 230 V system equipped with
a 60 V/60 V, 1 kVA injection transformer. The response of the
DVR to various voltage disturbances are presented.

I.

I NTRODUCTION

Custom power using power electronics is an emerging

area used to prevent the degradation of power quality[1].
Custom power equipment include dynamic voltage restorer
(DVR), distribution static compensator (DSTATCOM), series
and shunt active lters (Universal custom power conditioner).
Out of all the custom power devices, DVR is most useful in
mitigating voltage quality problems- Voltage sags and Voltage
swells [2],[3]. During sag, the RMS value of the voltage
decreases while in swell it increases. Industries employing
process controllers, programmable logic controllers, adjustable
speed drives are severely affected because of these voltage
quality issues [4].
Power Quality (PQ) mainly deals with issues like maintaining a xed voltage at the Point of Common Coupling (PCC)
for various distribution voltage levels irrespective of voltage
uctuations. DVR acts as a voltage source at the bus, which is
connected in series with the system thereby removing the voltage sags and swells[5]. There are four different congurations
of DVR available out of which the DVR with Battery storage
is used in this paper [6]. This topology is useful as battery
is a source of real power and hence can effectively mitigate
voltage sags even for unity or almost unity power factor loads
[7]. Also energy storages such as batteries are required to
compensate large temporary voltage sags [8]. They also help
mitigating voltage swells by acting as power sinks, absorbing
real power. Since the voltage in the distribution network can be
categorized as low voltage and the voltage to be compensated
is even smaller, battery becomes the ideal choice for the low
voltage compensation. Due to these numerous advantages, this
topology is preferred. The basic system model of a battery
based DVR is given in Fig. 1.

978-1-4799-3612-0/14/$31.002014 IEEE

Vinj
ZS = RS + jXS
Supply
Voltage (Vs)

VL

Voltage
Sensitive
Load

Battery
1- Inverter

Fig. 1.

Basic system model of a DVR

A proper reference waveform is required to determine the

appropriate frequency and phase angle at which the voltage
is to be injected during voltage unbalances. Synchronous
reference frame (SRF) phase locked loop (PLL) is one of
the most extensively used techniques to generate the voltage
reference waveform in three phase systems[9]. Though the
SRF PLL works satisfactorily during balanced condition, its
performance deteriorates under distorted supply [10]. Since
voltage disturbances are predominantly single phase occurrences, a reliable reference waveform immune to voltage
unbalances is required. An improved PLL with the addition
of a Finite impulse response (FIR) based lter to the system
eliminates the ripples due to the distortions in utility [11]. This
paper presents a battery based DVR with Improved PLL for
compensating voltage sags and voltage swell. The performance
of the control technique is studied using simulations and the
results obtained are corroborated using experiments.
The dc-link is maintained at around 100 V by batteries.
During voltage sag compensation, the battery discharges. It
is then recharged gradually during normal conditions. Hence
the State of Charge (SoC) of the battery is maintained at an
optimum level (70 to 80%) so that real power can be injected
as well as absorbed to accommodate both voltage swells and
sags. The DVR is designed to protect a 1-kVA load from a 25%
voltage sag or swell. If the voltage sag is deeper or the load
is higher, only partial voltage compensation can be provided.
This paper is divided in to six sections. Starting with
an introduction, the next section describes the generation of
a Voltage reference. Section III presents the Modelling and
control of the DVR. Section IV shows the various simulations
performed to verify the working of the system, which are validated by laboratory experimental results presented in Section
V. The concluding remarks are presented in Section VI.

International Conference on Power, Signals, Controls and Computation (EPSCICON), 8 10 January 2014

Block diagram of Improved PLL with FIR lter

PLL Output (p.u)

Input signal (p.u)

Fig. 2.

Unbalance

Unbalance
0
-2

Va
0.2

0.24

0.26

0.28

0.3
time (s)

Vc

cos T

0
-2

0.2

Fig. 3.

0.22

Vb

0.22

0.24

0.26

0.28

0.3
time (s)

Simulation and experimental results of the Improved PLL

II.

VOLTAGE REFERENCE GENERATION

A voltage reference waveform is required to inject the voltage at the appropriate frequency and phase angle. PLL is one
of the commonly used methods to generate voltage references
for three phase systems. Synchronous Reference Frame(SRF)
PLL is a simple and widely used technique and it works
well under balanced conditions. The PLL consists of a phase
detector, a lter and a Voltage Controlled Oscillator(VCO). It
involves transformation of the rotating three axis abc reference
frame to the dq rotating two axis reference(Clarke and Park
transformation). The phase angle is calculated from the dq
axis voltages. Since the q-axis voltage (Vq ) is proportional
to the phase angle error(), it is made zero using a PI
compensator. When the estimation error in the phase angle is
eliminated, a voltage reference in phase lock with the supply
voltage is obtained.
Though the SRF PLL works well under balanced conditions, its performances degrades during voltage unbalances.
The presence of unbalance gives rise to a ripple of 2 in
the d and q axis voltages which results in estimation error.
If this ripple is ltered out and eliminated, the performance
of the PLL model can be further enhanced. To achieve this,
a linear phase Finite Impulse Response lter is used as a low
pass lter. Finite impulse response (FIR) lter is a type of
digital lter, with its impulse response having a nite number
of nonzero entries. The FIR lter is superior to analog lters in

terms of higher attenuation over a wide range of frequencies.

Thus by adding a FIR lter, the PLL is made immune to
unbalances, offsets, harmonics and phase jumps in the supply.
In the Improved PLL, the FIR lter is cascaded with the PI
compensator to lter out the distortions. The structure of the
Improved PLL is shown in Fig. 2.
The performance of the improved PLL is studied using
MATLAB and the results for voltage unbalances are presented.
It is seen from Fig. 3 that the PLL with FIR lter effectively
tracks the phase angle even during distortions in the supply.
The voltage reference is unaltered by variations in the supply
voltage. Using the unit cosine waveform, the voltage reference
Vref is generated. This reference value is the constant voltage
to be maintained at the PCC. The voltage value to be injected,
Vo(ref ) is the difference between the reference Vref and the
actual voltage Vac .
III.

M ODELING AND C ONTROL OF THE DVR

The Dynamic Voltage Regulator(DVR) is a series active

lter connected in series with the utility and the load through
a single phase injection transformer as it was shown in Fig. 1.
A single phase inverter is connected in each of the three phases
to dynamically compensate voltage unbalances. The primary
side of the injection transformer is taken to be in series with
the power line carrying a current It and the secondary is
connected to the inverter via a LC lter. A 1 : 1 transformer is

International Conference on Power, Signals, Controls and Computation (EPSCICON), 8 10 January 2014

Vo (ref)

Vref

Fig. 5.

PI

Vinj

Vac

Iref
It

Vi (ref)

PI
Ii

1-) Vi
Inverter

PWM
Generator

Vinj

Ii

Vinj

The double loop control scheme for the DVR

considered here. Sinusoidal PWM technique is used to re the

four switches at high frequencies (2 to 10 kHz). The output
of the inverter is ltered by LC-lters in order to reduce the
inuence of harmonics from the high frequency switching.

be gerenrated Vi(ref ) can be computed as given in the Eq. 2.

There are different techniques proposed for the detection of

voltage unbalances[12]. In this work, detection of voltage sags
and swells is done by comparing the instantaneous value of the
source voltages with the voltage reference generated from the
abc-dq Clarke-Park transformation. This method gives a good
performance as the voltage values are monitored continuously
for variations. When the difference in voltage increases beyond
predened threshold values, the controller activates the DVR
to compensate the voltage unbalances. The control objective is
to maintain the phase voltage within the acceptable range by
injecting the appropriate voltage. A double loop control using
PI compensators is employed for effective and dynamic control
of the DVR. Since the inverter current is the fastest changing
parameter, the inner loop involves current control and voltage
is controlled in the outer loop. The inverter reference current
Iref can be derived from the voltage reference Vo(ref ) using
Eq. 1.

where Ii is the measured inverter current and TL is the time

constant. The Sinusoidal PWM (SPWM) technique is used to
generate the inverter voltage Vi by giving appropriate ring
pulses to the IGBT switches. The control strategy is depicted in
Fig. 5. The PI controllers are tuned using symmetrical optimum
method [13]. At steady state, the injected voltage becomes
equal to Vo(ref ) and the error becomes to zero.

(1)

where It is the transformer secondary current, Vinj is

the measured secondary voltage and Tc is the time constant.
Neglecting the resistance of inductor, the inverter voltage to

(2)

S IMULATION S TUDY

The proposed control strategy is tested with simulations in

MATLAB. The battery DC link voltage of the DVR is set at
around 100 V dc. The output of the series active lter consists
of a low pass lter with Linv = 3.9 mH and Cinv = 11 F.
A diode rectier with a R load of 100 ohms has been used
as a local load. The response of the DVR to voltage sags and
voltage swells are given in subsequent gures. The voltage
unbalances considered here are symmetrical in nature.
Voltage (V)

Cinv
(Vo(ref ) Vinj ) + It
Tc

IV.

Linv
(Iref Ii ) + Vinj
TL

Time (s)
(a)

Voltage (V)

Iref =

Vi(ref ) =

Grid

Time (s)

Voltage (V)

(b)

Time (s)
(c)

Fig. 6.

Simulation response for voltage sag

A. Voltage Sag Mitigation

Load

Fig. 4.

Circuit diagram of the DVR

Initially the system is operated under balanced condition.

At t = 65 ms a voltage dip of 20% is initiated and at t =
150 ms normalcy is restored. During sag, the DVR injects a
voltage in phase with the voltage at PCC, such that the voltage

Voltage (V)

International Conference on Power, Signals, Controls and Computation (EPSCICON), 8 10 January 2014

Time (s)

Voltage (V)

(a)

Time (s)

Voltage (V)

(b)

Time (s)
(c)

Fig. 7.

Simulation response for voltage swell

at PCC is maintained constant throughout the operation. Fig. 6

shows the waveforms of the source voltage, the load voltage
and the injected voltage of the system. It is observed that the
response time, including the voltage dip detection time and the
controller response is less than one cycle at the fundamental
frequency which conrms the effectiveness of the proposed
control technique for the compensation of voltage dips.
B. Voltage Swell Mitigation
Initially the system is operated under balanced condition.
At t = 65 ms a over voltage of 10% is initiated and at t =
145 ms normalcy is restored. During swell the series inverter
injects a voltage out of phase with the voltage at PCC, such
that the voltage at PCC is maintained constant throughout the
operation. Fig. 7 shows the waveforms of the source voltage,
the load voltage and the injected voltage of the system. It
is observed that the response time, including the over voltage
detection time and the controller response is less than one cycle
at the fundamental frequency which conrms the effectiveness
of the proposed control technique for the compensation of over
voltage.
V.

R ESULTS AND D ISCUSSIONS

The experimental setup of the DVR is shown in the Fig. and

its schematic layout is shown in the Fig. 8. The experimental
setup consists of three single-phase IGBT based inverters, a
battery bank, three single phase series injection transformers
and a three phase auto transformer. A three phase resistive
load is used as a local load. Auto transformers are used to
protect the system operating voltage level. Three single phase
transformers of 60 V/60 V, 1 kVA rating are used as series
injection transformers to inject the inverter voltage.
The inverter output is connected to the transformer through
a LC lter. The LC lter was appropriately designed and the
values of Linv , Cinv are 4 mH and 22 F respectively. The
ring pulses to the IGBTs of the inverter are generated using
an Altera Cyclone II series FPGA. The switching frequency
for the IGBTs was chosen as 10 kHz. The voltage set value
is chosen as 155 V and the experimental results are presented
for different kinds of single phase voltage disturbances.

Fig. 8.

Experimental Setup of the DVR

A. Voltage Sag Condition

Initially the system is operated under balanced condition.
At t = 95 ms, sag is initiated at the source side with the voltage
falling from 155 V to 135 V. In order to maintain the load
voltage constant, the DVR starts injecting voltage dynamically
which is in phase with the source voltage. The DVR provides
the compensation of 20 V, maintaining the PCC voltage at
set value of 155 V. The corresponding waveforms are shown
in Fig. 9(a)(b). It can be seen from Fig. 9(c) that the Total
Harmonic Distortion (THD) of the injected voltage is only
about 5%. This indicates that the DVR injects power into the
system at high quality.
B. Voltage Swell Condition
The performance of the system is also tested for voltage
swells. Initially the system is operated under balanced condition. After sometime swell is initiated at the source side with
one of the phase voltages increasing from 155 V to 175 V. In
order to maintain the voltage at the set value, the DVR starts
injecting voltage dynamically, which is out of phase with the
source voltage. The corresponding waveforms are shown in
the Fig. 9(d). It can be seen that the DVR injects 20 V out of
phase to maintain the load voltage at 155 V.
C. Voltage Imbalance Condition
The controller performance is also analyzed by introducing
sudden voltage disturbances. The voltage prole is abruptly
changed from sag to swell at t = 165 ms. The DVR which was
inititally providing a compensation voltage of 20 V in phase
with the supply, dynamically responds and injects voltage out
of phase. Fig. 9(e)(f) shows the response of the DVR when the
voltage is changed from 135 V to 175 V. It can be seen that the
control algorithm stabilizes the Load voltage within one cycle
and produces a stable output. This veries the effectiveness
of the control technique in dynamically compensating voltage
unbalances.

International Conference on Power, Signals, Controls and Computation (EPSCICON), 8 10 January 2014

VS=135V

VS=155V t=95ms Vinj=20V VS=135V

(a)

Vinj=20V
(b)

VS=175V

Vinj=20V

(c)

VS=135V

Vinj

(d)

VS=175V

VS=135V

(e)

Vinj

VS=175V
(f)

Fig. 9. Experimental results for DVR - a) Voltage waveforms under Voltage Sag (CH1,CH2: 50V/div, Time: 30 ms/div), b) Magnied view of Voltage waveforms
during sag (CH1,CH2: 50V/div, Time: 10 ms/div), c) THD plot of Injected voltage, d) Voltage waveforms during Swell (CH1,CH2: 50V/div, Time: 30 ms/div),
e) Voltage waveforms Imbalance (CH1,CH2: 50V/div, Time: 30 ms/div), f) Magnied view of Voltage waveforms during Imbalance (CH1,CH2: 50V/div, Time:
10 ms/div)

VI.

C ONCLUSION

A battery based DVR design with an Improved PLL to

mitigate voltage sags and swells in a distribution system has
been presented. The modelling of the DVR is described and a
double loop control strategy to mitigate voltage unbalances is
discussed. The battery proves to be effective in providing the
real power requirement during the different voltage unbalance
phenomena. Simulation studies for three phase symmetrical
voltage unbalances indicate that the system responds quickly
to changes in voltage magnitude. Practical implementation of

the control algorithm is carried out in a Field Programmable

Gate Array (FPGA). The experimental results conrm that the
algorithm is effective in mitigating the voltage disturbances.
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International Conference on Power, Signals, Controls and Computation (EPSCICON), 8 10 January 2014

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