John W.

Arens
917 Leah Drive
Cary, IL 60013
(847) 462-8601
OBJECTIVE
Seeking a position where I can use my quantitative abilities for analysis and trading.
EDUCATION
Master of Science, Operations Research, 1988, GPA 6.9/8.0
University of Michigan, Rackham Graduate School, Ann Arbor, MI
Optimization: Linear, Nonlinear, Integer, and Dynamic Programming.
Mathematics: Modern and Linear Algebra, Advanced Calculus, Probability and Statistics.
Bachelor of Science, Electrical Engineering, 1985, GPA 4.4/5.0
University of Illinois, College of Engineering, Urbana, IL
Major Studies: Linear Systems Theory, Digital Signal Processing, Control Systems, and Communication Systems.
Participated in the Cooperative Education program with IBM, Manassas.

EXPERIENCE
GETCO LLC
Quantitative Analyst / Trader

June 2009 - Present

FINRA General Securities Representative (Series 7)

FINRA Equity Securities Trader (Series 55)
Eurex Trader Certification

Developed trading models and signals for U.S. Equity products.

Performed quantitative analysis to address PNL, risk and system performance issues.
Architected high performance computing platform for quantitative analysis and model generation.
Developed software to perform statistical regression and cross validation.
Investigation of cointegrated time series relationships (VAR, VECM models).
Portfolio risk analysis and trade development.
Developed darkpool trading models and strategies.
Production trading of U.S. Indices products (Model Management and PNL Optimization)
Performed Open Order Risk Reduction Analysis

GETCO LLC
High Performance Platform Development

June 2007 - May 2009

Developed high performance, ultra low-latency, quote services for CME, ICE, ARCA, NASDAQ,
BATS.
Developed specialized infrastructure to reduce latency of quotes.

Xilinx Corporation
Senior Staff DSP Specialist

January 2006 - May 2007

Provided technical sales support for North Central US supporting Xilinx FAEs and Regional
Sales Management in the sales process by providing expertise in DSP and FPGA design and
development.
Assisted customers with technical issues associated with designing Xilinx FPGAs using System
Generator, Accel DSP, and HDL design flows.
Provide technical expertise for digital communications systems, multimedia, video, and imagiing
application.
Designed Digital Downconverter for cellular basestation.
Designed symbol synchronizer for next generation GPS receiver for commercial aviation.
Designed 2D image filter block for electronic countermeasures system.
Designed Driver Awarenesss FPGA for automotive application which interfaced to LVDS camera
and VGA display.
Designed polyphase video scaler for video resizing for video conferencing systems which interfaced
to the DVI interface.
Supervise a team of strategic applications engineers and field applications engineers when projects
require multiple design disciplines.
Actel Corporation
Principal Design Engineer

July 2000 - January 2006

Race Car Video System

Architected race car video system that collects video from 4 CMOS cameras and formats the
cameras images into a single image that is sent to NTSC video encoder and MPEG2 encoder
via BT-656 video format.
Developed video synchronization scheme used to synchronize up to 4 cameras.
Designed the following FPGA blocks using VHDL: 200 Mbps LVDS serial communication link
with error detection and correction capabilities; SDRAM controller; versatile video assembler
capable of display from 1 to 4 camera images in a variety of formats; and BT-656 video
formatter.
Airbus A380 Flight Surface Monitoring and Control
Designed FPGA that monitored temperature and pressure of various flight systems.
Designed FPGA based motor controller which drives a 3-phase motor that drives the pneumatically controlled flight surfaces.
Designed A/D and D/A converter interfaces and serial communications.
Designed FPGA based 2nd order feedback control system and CORDIC algorithm implementation.
Documented design to DO-254 standard for safety critical applications.

Infrared Camera
Designed FPGA controller for infrared camera and generated NTSC video output image.
Interfaced TI320C6700 DSP to infrared camera for post image processing.
Designed hardware circuitry for DSP subsystem and CCD image sensor.
Data Acquisition
Designed FPGA datapath processor for triggering data acquisition based on triggering events.
Interfaced FPGA to PLX 9054 PCI interface chip and used DMA mode to transfer data to /
from the PCI bus.
Designed hardware circuitry for PCI bus interface.
Mid-Air Refueling Tanker Video System
Designed a Xilinx FPGA using Verilog which reduced XGA video image to 1/4 size and
mosiaced 4 imaged together to display 4 video images on a single LCD display.
Designed a Xilinx FPGA using Verilog which converted SMPTE 292 video to XGA video.
Designed a Xilinx FPGA using Verilog which converted XGA video to SMPTE 292 video.
Dual-Mode (GSM, TDMA) Cellular Phone ASIC
From floating point MATLAB implementation of dual-mode receiver, determined finite precision implementation and resource sharing, and datapath design.
Designed using VHDL the following blocks: quadrature demodulator, symbol synchronizer,
frequency correction estimator, and numerically controlled oscillator.
Developed Matlab / ModelTech ModelSim verification environment to perform functional
verification of ASIC.
Verified ASIC timing using Synopsys PrimeTime for static timing analysis.
Developed multi-cellular phone standard DSP prototype using Xilinx Virtex1000 FPGA.
Actel Corporation
September 1997 - June 2000
High Level Design Consultant, Design Consulting Services
Sales Support
Provided technical sales support for Central US. Supporting Actel FAEs and Regional Sales
Management in the sales process.
Taught VHDL and Verilog language and FPGA Design Methodology courses to Actel customers.
Performed system administration of SUN Solaris and WindowNT network along with EDA
tool administration.
Technical Support
Assisted customers with technical issues associated with design with Actel products.
Provided techical support for Synopsys, Exemplar, and Synplicity synthesis tools and Synopsys, Cadence, and Model Tech ModelSim simulators.

 Member of the Actel Intellectual Property steering committee. Provided direction to marketing and sales on strategic projects.
Worked on customer designs in order to achieve area and timing constraints.
Designed 33 MHz, 32 bits PCI core based design.
Designed 200MHz counter and 140 MHz twos complement multiplier using VHDL.
Developed designs for testing of the ProASIC product line. Developed Synopsys synthesis
scripts and performed static timing analysis using Synopsys PrimeTime. Helped define the
Synopsys synthesis methodology.
Certified Synopsys ACE by Synopsys.
Additional Employment Information Available By Request
PATENTS
Inventor of 7 U.S. Patents
5,301,364 Method and apparatus for digital automatic gain control in a receiver
5,499,273 Method and apparatus for symbol clock recovery from signal having
wide frequency possibilities
5,559,806 Transceiver having steerable antenna and associated method
5,621,766 Method and apparatus for burst detecting
5,706,313 Soft decision digital communication method and apparatus
5,768,684 Method and apparatus for bi-directional power control in a digital communication system
5,930,268 Transceiver and associated method for surviving fades