EC604

USN

M S RAMAIAH INSTITUTE OF TECHNOLOGY

(AUTONOMOUS INSTITUTE, AFFILIATED TO VTU)
BANGALORE - 560 054
SEMESTER END EXAMINATIONS - JUNE 2011
Course & Branch B.E. - Electronics and Communication Engineering Semester : VI
Subject :

Analog and Mixed Mode VLSI Design Max. Marks: 100

Subject Code: EC604

Duration: 3 Hrs

Instructions to the Candidates:

Answer one full question from each unit.
UNIT - I
1. a) State and explain the specifications of ADC with neat sketches? (12)
b) State the reasons for pedestal error, droop aperture error and sampling (08)
error.
2. a) Discuss the issues involved in mixed signal circuit layout and explain the (12)
techniques used to overcome these issues?
b) Determine the maximum INL (in LSB's) for a 3-bit DAC which has the (08)
following characteristics. Does the DAC have 3-bit accuracy? If not, what is
the resolution of the DAC having this characteristic?
0/p
volta g e
Dig I

000

001

010

011

100

101

110

111

OV

0.625V

1.5625

2.OV

2.5V

3.125V

3.4375

4.375

UNIT - II
3. a) Explain binary weighted change scaling DAC and derive an expression for (12)
output voltage and discuss the layout issues.
b) Design a 3-bit DAC using R-2R architecture with R=1kS2, RF=2kc and (08)
VRef=SV. Assume that resistances of the switches are negligible. Determine
the value of iTO,. for each digital input and corresponding output voltage.
4. a) Explain the principle and operation of a pipe-line DAC with relevant sketches (12)
with an example.
b) Find the value of output voltage at the end of each clock cycle for a 6-bit (08)
cyclic-DAC when input is 110101 assume Vfef=5V.
UNIT -III
5. a) Explain the principle of pipeline ADC and derive an expression for IDNL1max.? (12)
b) Design a 2-step ADC with 4-bit resolution. Make a table listing MSB's and (08)
LSB's and V1, VZ, V3 for V;n=2,4,9 and 15V, Vref=16v.
6. a) Explain the principle of single slope ADC and the problems associated with it? (10)
b) Draw the block-diagram for 8-bit successive approximation ADC with (10)
Vref=SV. Explain the same and trace the output at various stages for Vin=1VUNIT - IV
7. a) Explain the principle of current-mode R-2R-DAC and describe the problems (10)
associated with it.
b) Explain with relevant sketches the principle and operation of a fully (10)
differential sample and hold circuit which uses capacitors and OP-Amp.

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EC604
8. a) With a neat diagram explain the principle of the cyclic ADC. (08)
b) An 8-bit current mode R-2R DAC has Vfef+=1.5v, and Vref =0v. What are the (08)
voltages on each of the R-2R resistor tap?
c) Discuss the advantages and disadvantages of wide swing current mode DAC (04)
compared to the traditional current mode DAC.

UNIT - V
9. a) Describe CMOS process flow with neat sketches. (10)
b) Explain how MOSFET behaves as a capacitor. Also explain floating MOS (10)
capacitor.
10. a) Implement and explain dynamic full adder using dynamic logic. (10)
b) Discuss different types of sub-micron CMOS capacitors with neat sketches. (10)

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