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8-Bit Microcontroller
Features
Operating voltage:
fSYS=4MHz: 3.3V~5.5V
fSYS=8MHz: 4.5V~5.5V
Low voltage reset function
25 bidirectional I/O lines (max.)
1 interrupt input shared with an I/O line
8-bit programmable timer/event counter with
overflow interrupt and 8-stage prescaler
On-chip RC oscillator, external crystal and
RC oscillator
32768Hz crystal oscillator for timing
purposes only
Watchdog Timer
204814 program memory ROM
General Description
remote controllers, fan/light controllers, washing machine controllers, scales, toys and various subsystem controllers. A HALT feature is
included to reduce power consumption.
Rev. 1.10
July 2, 2001
HT48R30A-1
Block Diagram
IN T /P G 0
In te rru p t
C ir c u it
P ro g ra m
R O M
S T A C K
4 L e v e ls
P ro g ra m
C o u n te r
T M R 0
IN T C
T M R /P C 0
T M R 0 C
P G 0
In s tr u c tio n
R e g is te r
P r e s c a le r
M P
U
X
D A T A
M e m o ry
W D T P r e s c a le r
W D T
fS
Y S
S Y S C L K /4
E N /D IS
W D T S
M
U
R T C
X
O S C
W D T O S C
P A C
M U X
In s tr u c tio n
D e c o d e r
A L U
T im in g
G e n e ra to r
S h ifte r
P A
O S
P
R
V
V
Rev. 1.10
C 1 /
G 1
E S
D D
S S
P B C
P G 1
P G 2
P O R T B
P B
P O R T C
P C
A C C
In te rn a l
R C O S C
P A 0 ~ P A 7
B Z /B Z
S T A T U S
P C C
O S C 2 /
P G 2
P O R T A
O p tio n R O M
O T P o n ly
P G C
P G
P O R T G
P B 0 ~ P B 7
P C 0 ~ P C 5
P G 0 ~ P G 2
July 2, 2001
HT48R30A-1
Pin Assignment
P B 5
1
2 8
P B 6
P B 4
2
2 7
P B 7
P B 5
1
2 4
P B 6
P A 3
3
2 6
P A 4
P B 4
2
2 3
P B 7
P A 2
4
2 5
P A 5
P A 3
3
2 2
P A 4
P A 1
5
2 4
P A 6
P A 2
4
2 1
P A 5
P A 0
6
2 3
P A 7
P A 1
5
2 0
P A 6
P B 3
7
2 2
O S C 2 /P G 2
P A 0
6
1 9
P A 7
P B 2
8
2 1
O S C 1 /P G 1
P B 3
7
1 8
O S C 2 /P G 2
P B 1 /B Z
9
2 0
V D D
P B 2
8
1 7
O S C 1 /P G 1
P B 0 /B Z
1 0
1 9
R E S
P B 1 /B Z
9
1 6
V D D
V S S
1 1
1 8
P C 5
P B 0 /B Z
1 0
1 5
R E S
P G 0 /IN T
1 2
1 7
P C 4
V S S
1 1
1 4
P C 2
P C 0 /T M R
1 3
1 6
P C 3
P G 0 /IN T
1 2
1 3
P C 0 /T M R
P C 1
1 4
1 5
P C 2
H T 4 8 R 3 0 A -1
2 4 S K D IP -A /S O P -A
H T 4 8 R 3 0 A -1
2 8 S K D IP -A /S O P -A
Pin Description
Pin Name I/O
ROM Code
Option
Description
PA0~PA7
PB0/BZ
PB1/BZ
PB2~PB7
I/O
Pull-high*
PB0 or BZ
PB1 or BZ
Bidirectional 8-bit input/output port. Software instructions determine the CMOS output or Schmitt trigger input with
pull-high resistor (determined by pull-high options).
The PB0 and PB1 are pin-shared with the BZ and BZ, respectively. Once the PB0 or PB1 is selected as buzzer driving outputs, the output signals come from an internal PFD generator
(shared with timer/event counter).
VSS
PG0/INT
PC0/TMR
PC1~PC5
Rev. 1.10
I/O
I/O
Pull-high*
Pull-high*
July 2, 2001
HT48R30A-1
Pin Name I/O
ROM Code
Option
Description
RES
VDD
OSC1/PG1
OSC2/PG2
I
O
OSC1, OSC2 are connected to an RC network or Crystal (determined by ROM code option) for the internal system clock. In the
Pull-high*
case of RC operation, OSC2 is the output terminal for 1/4 system clock. These two pins can also be optioned as an RTC oscilCrystal
lator (32768Hz) or I/O lines. In these two cases, the system
or RC
or Int. RC+I/O clock comes from an internal RC oscillator whose frequency has
4 options (3.2MHz, 1.6MHz, 800kHz, 400kHz). If the I/O option
or Int.
is selected, the pull-high options can also be enabled or disRC+RTC
abled. Otherwise the PG1 and PG2 are used as internal registers (pull-high resistors are always disabled).
Note: * The pull-high resistors of each I/O port (PA, PB, PC, PG) are controlled by 1-bit ROM code
option.
CMOS or Schmitt trigger option of port A is controlled by 1-bit ROM code option.
Note: These are stress ratings only. Stresses exceeding the range specified under "Absolute Maximum Ratings" may cause substantial damage to the device. Functional operation of this device
at other conditions beyond those listed in the specification is not implied and prolonged exposure to extreme conditions may affect device reliability.
D.C. Characteristics
Symbol
Parameter
Ta=25C
Test Conditions
VDD
Conditions
Min.
Typ.
Max.
Unit
VDD1
Operating Voltage
fSYS=4MHz
3.3
5.5
VDD2
Operating Voltage
fSYS=8MHz
4.5
5.5
IDD1
Operating Current
(Crystal OSC)
3.3V
mA
mA
IDD2
Operating Current
(RC OSC)
3.3V
mA
mA
IDD3
Operating Current
(Crystal OSC)
mA
ISTB1
3.3V
Standby Current
No load, system HALT
(WDT Enabled RTC Off) 5V
mA
10
mA
Rev. 1.10
5V
5V
5V
No load, fSYS=4MHz
No load, fSYS=4MHz
No load, fSYS=8MHz
July 2, 2001
HT48R30A-1
Symbol
Parameter
Test Conditions
Conditions
VDD
Min.
Typ.
Max.
Unit
ISTB2
3.3V
Standby Current
No load, system HALT
(WDT Disabled RTC Off) 5V
mA
mA
ISTB3
3.3V
Standby Current
No load, system HALT
(WDT Disabled, RTC On) 5V
mA
10
mA
VIL1
0.3VDD
VIH1
0.7VDD
VDD
VIL2
0.4VDD
VIH2
0.9VDD
VDD
IOL
3.3V VOL=0.1VDD
mA
VOL=0.1VDD
10
20
mA
IOH
3.3V VOH=0.9VDD
-2
-4
mA
VOH=0.9VDD
-5
-10
mA
RPH
Pull-high Resistance
40
60
80
kW
VLVR
5V
5V
3.3V
5V
3.3V option
10
30
50
kW
2.7
3.0
3.3
A.C. Characteristics
Symbol
Parameter
fSYS1
System Clock
(Crystal OSC)
fSYS2
fSYS3
fTIMER
tWDTOSC
Watchdog Oscillator
tWDT1
Rev. 1.10
Ta=25C
Test Conditions
VDD
Conditions
3.3V
400
4000
kHz
5V
400
8000
kHz
3.3V
400
4000
kHz
5V
400
8000
kHz
kHz
3.3V
5V
3.2MHz option
kHz
3.3V
4000
kHz
5V
8000
kHz
3.3V
43
86
168
ms
5V
36
72
144
ms
11
22
43
ms
18
37
ms
July 2, 2001
HT48R30A-1
Symbol
Test Conditions
Parameter
Conditions
VDD
tWDT2
Without WDT
prescaler
1024
tSYS
tWDT3
Without WDT
prescaler
7.812
ms
tRES
ms
tSST
1024
tSYS
tINT
ms
Functional Description
specify a full range of program memory.
Execution flow
The system clock for the microcontroller is derived from either a crystal or an RC oscillator.
The system clock is internally divided into four
non-overlapping clocks. One instruction cycle
consists of four system clock cycles.
The conditional skip is activated by instructions. Once the condition is met, the next instruction, fetched during the current
instruction execution, is discarded and a
dummy cycle replaces it to get the proper instruction. Otherwise proceed with the next instruction.
Program counter - PC
The program counter (PC) controls the sequence in which the instructions stored in the
program ROM are executed and its contents
S y s te m
O S C 2 (R C
C lo c k
T 1
T 2
T 3
T 4
T 1
T 2
T 3
T 4
T 1
T 2
T 3
T 4
o n ly )
P C
P C
F e tc h IN S T (P C )
E x e c u te IN S T (P C -1 )
P C + 1
F e tc h IN S T (P C + 1 )
E x e c u te IN S T (P C )
P C + 2
F e tc h IN S T (P C + 2 )
E x e c u te IN S T (P C + 1 )
Execution flow
Rev. 1.10
July 2, 2001
HT48R30A-1
The lower byte of the program counter (PCL) is
a readable and writeable register (06H).
Moving data into the PCL performs a short
jump. The destination will be within the current program ROM page.
0 0 0 H
0 0 4 H
E x te r n a l In te r r u p t S u b r o u tin e
0 0 8 H
T im e r /E v e n t C o u n te r
In te r r u p t S u b r o u tin e
n 0 0 H
The program memory is used to store the program instructions which are to be executed. It
also contains data, table, and interrupt entries,
and is organized into 204814 bits, addressed
by the program counter and table pointer.
L o o k - u p T a b le ( 2 5 6 w o r d s )
n F F H
7 0 0 H
L o o k - u p T a b le ( 2 5 6 w o r d s )
7 F F H
1 4 b its
N o te : n ra n g e s fro m
Location 000H
0 to 7
Program memory
This area is reserved for program initialization. After chip reset, the program always begins execution at location 000H.
ter interrupt service program. If a timer interrupt results from a timer/event counter
overflow, and if the interrupt is enabled and the
stack is not full, the program begins execution
at location 008H .
Location 004H
This area is reserved for the external interrupt service program. If the INT input pin is
activated, the interrupt is enabled and the
stack is not full, the program begins execution
at location 004H.
Table location
Location 008H
P ro g ra m
M e m o ry
Program Counter
*10
*9
*8
*7
*6
*5
*4
*3
*2
*1
*0
Initial Reset
External Interrupt
Skip
PC+2
Loading PCL
*10
*9
*8
@7
@6
@5
@4
@3
@2
@1
@0
#10
#9
#8
#7
#6
#5
#4
#3
#2
#1
#0
S10
S9
S8
S7
S6
S5
S4
S3
S2
S1
S0
Program counter
Note: *10~*0: Program counter bits
July 2, 2001
HT48R30A-1
stack pointer (SP) and is neither readable nor
writeable. At a subroutine call or interrupt acknowledge signal, the contents of the program
counter are pushed onto the stack. At the end of
a subroutine or an interrupt routine, signaled
by a return instruction (RET or RETI), the program counter is restored to its previous value
from the stack. After a chip reset, the SP will
point to the top of the stack.
Table Location
*10
*9
*8
*7
*6
*5
*4
*3
*2
*1
*0
TABRDC [m]
P10
P9
P8
@7
@6
@5
@4
@3
@2
@1
@0
TABRDL [m]
@7
@6
@5
@4
@3
@2
@1
@0
Table location
Note: *10~*0: Table location bits
July 2, 2001
HT48R30A-1
general purpose data memory, addressed from
20H to 7FH, is used for data and control information under instruction commands.
In d ir e c t A d d r e s s in g R e g is te r
0 1 H
M P
All of the data memory areas can handle arithmetic, logic, increment, decrement and rotate
operations directly. Except for some dedicated
bits, each bit in the data memory can be set and
reset by "SET [m].i" and "CLR [m].i". They are
also indirectly accessible through memory
pointer registers (MP).
0 2 H
0 3 H
0 4 H
0 5 H
A C C
0 6 H
P C L
0 7 H
T B L P
0 8 H
T B L H
0 9 H
W D T S
0 A H
S T A T U S
0 B H
IN T C
0 C H
0 D H
T M R
0 E H
T M R C
S p e c ia l P u r p o s e
D A T A M E M O R Y
Accumulator
The accumulator is closely related to ALU operations. It is also mapped to location 05H of the
data memory and can carry out immediate data
operations. The data movement between two
data memory locations must pass through the
accumulator.
0 F H
1 0 H
1 1 H
1 2 H
P A
1 3 H
P A C
1 4 H
P B
1 5 H
P B C
1 6 H
P C
1 7 H
P C C
1 8 H
1 9 H
: U n u s e d
1 A H
1 B H
R e a d a s "0 0 "
1 C H
SBC, DAA)
1 D H
1 E H
P G
1 F H
2 0 H
P G C
7 F H
8 0 H
G e n e ra l P u rp o s e
D A T A M E M O R Y
(9 6 B y te s )
The ALU not only saves the results of a data operation but also changes the status register.
F F H
RAM mapping
Rev. 1.10
July 2, 2001
HT48R30A-1
important and if the subroutine can corrupt the
status register, precautions must be taken to
save it properly.
Interrupt
The device provides an external interrupt and
internal timer/event counter interrupts. The
Interrupt Control Register (INTC;0BH) contains the interrupt control bits to set the enable/disable and the interrupt request flags.
All these kinds of interrupts have a wake-up capability. As an interrupt is serviced, a control
Labels
Bits
Function
C is set if the operation results in a carry during an addition operation or if a borrow does not take place during a subtraction operation; otherwise C is cleared. C
is also affected by a rotate through carry instruction.
AC
AC is set if the operation results in a carry out of the low nibbles in addition or no
borrow from the high nibble into the low nibble in subtraction; otherwise AC is
cleared.
OV
OV is set if the operation results in a carry into the highest-order bit but not a
carry out of the highest-order bit, or vice versa; otherwise OV is cleared.
PD
TO
TO is cleared by system power-up or executing the "CLR WDT" or "HALT" instruction. TO is set by a WDT time-out.
Rev. 1.10
10
July 2, 2001
HT48R30A-1
other interrupt acknowledge signals are held
until the "RETI" instruction is executed or the
EMI bit and the related interrupt control bit are
set to 1 (if the stack is not full). To return from
the interrupt subroutine, "RET" or "RETI" may
be invoked. RETI will set the EMI bit to enable
an interrupt service, but RET will not.
INTC
(0BH)
External Interrupt
04H
Timer/event
Counter Overflow
08H
Bit No.
Label
Function
EMI
EEI
ETI
EIF
TF
INTC register
Rev. 1.10
11
July 2, 2001
HT48R30A-1
and ignores an external signal to conserve
power.
used to control the enabling/disabling of interrupts. These bits prevent the requested interrupt from being serviced. Once the interrupt
request flags (TF, EIF) are set, they will remain
in the INTC register until the interrupts are
serviced or cleared by a software instruction.
Oscillator configuration
There are 3 oscillator circuits in the
microcontroller.
V
O S C 1
D D
O S C 1
4 7 0 p F
O S C 2
C r y s ta l O s c illa to r
( In c lu d e 3 2 7 6 8 H z )
fS Y S /4
N M O S O p e n D r a in
O S C 2
R C
O s c illa to r
The oscillator is a free running on-chip RC oscillator, and no external components are required.
Even if the system enters the power down mode,
the system clock is stopped, but the oscillator still
works within a period of 72ms. The WDT oscillator can be disabled by ROM code option to conserve power.
System oscillator
All of them are designed for system clocks,
namely the external RC oscillator, the external
Crystal oscillator and the internal RC
oscillator, which are determined by ROM code
option. No matter what oscillator type is selected, the signal provides the system clock.
The HALT mode stops the system oscillator
S y s te m
R T C
C lo c k /4
O S C
W D T
O S C
R O M
C o d e
O p tio n
S e le c t
W D T P r e s c a le r
8 - b it C o u n te r
7 - b it C o u n te r
8 -to -1 M U X
W S 0 ~ W S 2
W D T T im e - o u t
Watchdog Timer
Rev. 1.10
12
July 2, 2001
HT48R30A-1
WDTS register
If the device operates in a noisy environment, using the on-chip RC oscillator (WDT OSC) or
32kHz crystal oscillator (RTC OSC) is strongly
recommended, since the HALT will stop the system clock.
WS2
WS1
WS0
Division Ratio
1:1
1:2
1:4
1:8
1:16
1:32
1:64
1:128
Rev. 1.10
July 2, 2001
HT48R30A-1
SP; the others remain in their original status.
The port A wake-up and interrupt methods can
be considered as a continuation of normal execution. Each bit in port A can be independently
selected to wake up the device by ROM code option. Awakening from an I/O port stimulus, the
program will resume execution of the next instruction. If it awakens from an interrupt, two
sequence may occur. If the related interrupt is
disabled or the interrupt is enabled but the
stack is full, the program will resume execution
at the next instruction. If the interrupt is enabled and the stack is not full, the regular interrupt response takes place. If an interrupt
request flag is set to "1" before entering the
HALT mode, the wake-up function of the related interrupt will be disabled. Once a
wake-up event occurs, it takes 1024 (system
clock period) to resume normal operation. In
other words, a dummy period will be inserted
after a wake-up. If the wake-up results from an
interrupt acknowledge signal, the actual interrupt subroutine execution will be delayed by
one or more cycles. If the wake-up results in the
next instruction execution, this will be executed
immediately after the dummy period is finished.
TO PD
RESET Conditions
tS
S T
S S T T im e - o u t
C h ip
R e s e t
Reset
D D
R E S
Rev. 1.10
Reset circuit
from HALT will enable the SST delay.
14
July 2, 2001
HT48R30A-1
H A L T
W a rm
R e s e t
W D T
R E S
O S C 1
S S T
1 0 - b it R ip p le
C o u n te r
S y s te m
C o ld
R e s e t
R e s e t
Reset configuration
Rev. 1.10
15
PC
000H
Interrupt
Disable
Prescaler
Clear
WDT
Timer/event
Counter
Off
Input/output
Ports
Input mode
SP
July 2, 2001
HT48R30A-1
The states of the registers is summarized in the table.
Reset
(Power On)
WDT Time-out
(Normal
Operation)
RES Reset
(Normal
Operation)
RES Reset
(HALT)
WDT
Time-out
(HALT)*
TMR
xxxx xxxx
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
TMRC
00-0 1000
00-0 1000
00-0 1000
00-0 1000
uu-u uuuu
000H
000H
000H
000H
000H
MP
-xxx xxxx
-uuu uuuu
-uuu uuuu
-uuu uuuu
-uuu uuuu
ACC
xxxx xxxx
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
TBLP
xxxx xxxx
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
TBLH
--xx xxxx
--uu uuuu
--uu uuuu
--uu uuuu
--uu uuuu
STATUS
--00 xxxx
--1u uuuu
--uu uuuu
--01 uuuu
--11 uuuu
INTC
--00 -000
--00 -000
--00 -000
--00 -000
--uu uuuu
WDTS
0000 0111
0000 0111
0000 0111
0000 0111
uuuu uuuu
PA
1111 1111
1111 1111
1111 1111
1111 1111
uuuu uuuu
PAC
1111 1111
1111 1111
1111 1111
1111 1111
uuuu uuuu
PB
1111 1111
1111 1111
1111 1111
1111 1111
uuuu uuuu
PBC
1111 1111
1111 1111
1111 1111
1111 1111
uuuu uuuu
PC
--11 1111
--11 1111
--11 1111
--11 1111
--uu uuuu
PCC
--11 1111
--11 1111
--11 1111
--11 1111
--uu uuuu
PG
---- -111
---- -111
---- -111
---- -111
---- -uuu
PGC
---- -111
---- -111
---- -111
---- -111
---- -uuu
Register
Program
Counter
Rev. 1.10
16
July 2, 2001
HT48R30A-1
The internal clock source can be selected as
coming from fSYS (can always be optioned) or
fRTC (enabled only system oscillator in the Int.
RC+RTC mode) by ROM code option. The external clock input allows the user to count external
events, measure time intervals or pulse widths,
or to generate an accurate time base and PFD
signals.
Timer/Event Counter
Timer/event counters (TMR) is implemented in
the microcontroller. The timer/event counter
contains an 8-bit programmable count-up counter and the clock may come from an external
source or from the system clock or RTC.
Using the internal clock sources, there are 2
reference time-bases for timer/event counter.
Label (TMRC)
PSC0~PSC2
Bits
0~2
Function
To define the prescaler stages, PSC2, PSC1, PSC0=
000: fINT=fSYS/2 or fRTC/2
001: fINT=fSYS/4 or fRTC/4
010: fINT=fSYS/8 or fRTC/8
011: fINT=fSYS/16 or fRTC/16
100: fINT=fSYS/32 or fRTC/32
101: fINT=fSYS/64 or fRTC/64
110: fINT=fSYS/128 or fRTC/128
111: fINT=fSYS/256 or fRTC/256
TE
TON
6
7
TM0
TM1
TMRC register
fS
Y S
fR
T C
(1 /2 ~ 1 /2 5 6 )
U
8 - s ta g e P r e s c a le r
X
f IN
8 -1 M U X
R O M
D a ta B u s
T
T M 1
T M 0
C o d e O p tio n
P S C 2 ~ P S C 0
T M R
T im e r /E v e n t C o u n te r
P r e lo a d R e g is te r
R e lo a d
T E
T M 1
T M 0
T O N
P u ls e W id th
M e a s u re m e n t
M o d e C o n tro l
T im e r /E v e n t
C o u n te r
O v e r flo w
to In te rru p t
1 /2
B Z
B Z
Timer/Event Counter
Rev. 1.10
17
July 2, 2001
HT48R30A-1
reset by instructions. The overflow of the
timer/event counter 0/1 is one of the wake-up
sources. No matter what the operation mode is,
writing a 0 to ETI can disable the corresponding interrupt services.
In the case of timer/event counter OFF condition, writing data to the timer/event counter
preload register will also reload that data to
the timer/event counter. But if the timer/event
counter is turned on, data written to it will only
be kept in the timer/event counter preload register. The timer/event counter will still operate
until overflow occurs (a timer/event counter reloading will occur at the same time). When the
timer/event counter (reading TMR) is read, the
clock will be blocked to avoid errors. As clock
blocking may results in a counting error, this
must be taken into consideration by the programmer.
The bit0~bit2 of the TMRC can be used to define the pre-scaling stages of the internal clock
sources of timer/event counter. The definitions
are as shown. The overflow signal of
timer/event counter can be used to generate
PFD signals for buzzer driving.
Input/output ports
There are 25 bidirectional input/output lines in
the microcontroller, labeled from PA to PC and
PG, which are mapped to the data memory of
[12H], [14H], [16H] and [1EH] respectively. All of
these I/O ports can be used for input and output
operations. For input operation, these ports are
non-latching, that is, the inputs must be ready at
the T2 rising edge of instruction "MOV A,[m]"
(m=12H, 14H, 16H or 1EH). For output operation, all the data is latched and remains unchanged until the output latch is rewritten.
Each I/O line has its own control register (PAC,
PBC, PCC, PGC) to control the input/output
configuration. With this control register,
CMOS output or Schmitt trigger input with or
without pull-high resistor structures can be reconfigured dynamically (i.e. on-the-fly) under
software control. To function as an input, the
corresponding latch of the control register must
write "1". The input source also depends on the
control register. If the control register bit is "1",
18
July 2, 2001
HT48R30A-1
the input will read the pad state. If the control
register bit is "0", the contents of the latches
will move to the internal bus. The latter is possible in the "read-modify-write" instruction.
For output function, CMOS is the only configuration. These control registers are mapped to
locations 13H, 15H, 17H and 1FH.
After a chip reset, these input/output lines remain at high levels or floating state (depending
on the pull-high options). Each bit of these input/output latches can be set or cleared by "SET
[m].i" and "CLR [m].i" (m=12H, 14H, 16H or
1EH) instructions.
Some instructions first input data and then follow the output operations. For example, "SET
[m].i", "CLR [m].i", "CPL [m]", "CPLA [m]" read
the entire port states into the CPU, execute the
defined operations (bit-operation), and then
write the results back to the latches or the accumulator.
Each line of port A has the capability of wakPB0 I/O
PB1 I/O
PB0 Mode
PB1 Mode
PB0 Data
D0
PB1 Data
D1
D0
D1
Rev. 1.10
19
July 2, 2001
HT48R30A-1
P G 1 /P G 2 I/O
C o n tr o l B it
D a ta B u s
P U
C K
S
C h ip R e s e t
R e a d C o n tr o l R e g is te r
P A 0
P B 0
P C 0
P G 0
D a ta B it
Q
D
~ P A
~ P B
~ P C
~ P G
7
7
5
2
C K
W r ite D a ta R e g is te r
S
( P B 0 , P B 1 O n ly )
D D
Q
D
W r ite C o n tr o l R e g is te r
m o d e o n ly
P B 0
E X T
M
R e a d D a ta R e g is te r
S y s te m W a k e -u p
( P A o n ly )
U
X
E X T E N
( P B 0 , P B 1 O n ly )
X
O P 0 ~ O P 7
IN T fo r P G 0 O n ly
E X T = B Z fo r P B 0 o n ly , E X T = B Z fo r P B 1 o n ly , c o n tr o l= P B 0 d a ta r e g is te r
Input/output ports
voltage state does not exceed 1ms, the LVR
will ignore it and do not perform a reset function.
The LVR uses the OR function with the external RES signal to perform chip reset.
O P R
5 .5 V
L V R
3 .3 V
3 .0 V
0 .9 V
Rev. 1.10
20
July 2, 2001
HT48R30A-1
V
D D
5 .5 V
L V R
L V R
D e te c t V o lta g e
0 .9 V
0 V
R e s e t S ig n a l
N o r m a l O p e r a tio n
R e s e t
R e s e t
*1
*2
Option
PA CMOS/SCHMITT input
BZ/BZ enable/disable
LVR enable/disable
System oscillator
Ext. RC, Ext.crystal, Int.RC+RTC or Int.RC+PG1/PG2
10
11
Lock: unlock/lock
Rev. 1.10
21
July 2, 2001
HT48R30A-1
Application Circuits
RC oscillator for multiple I/O applications
D D
V D D
1 0 0 k W
5 1 k W ~
1 M W
0 .1 m F
4 7 0 p F
0 .1 m F
N M O S
o p e n d r a in
D D
P A 0 ~ P A 7
V D D
P B 2 ~ P B 7
P B 2 ~ P B 7
1 0 0 k W
C 1
P C 1 ~ P C 5
O S C 1
P B 0 /B Z
C 2
O S C 2
0 .1 m F
P B 1 /B Z
R E S
V S S
P C 1 ~ P C 5
O S C 1
0 .1 m F
O S C 2
P A 0 ~ P A 7
R E S
V S S
P C 0 /T M R
IN T /P G 0
P B 0 /B Z
P B 1 /B Z
P C 0 /T M R
IN T /P G 0
H T 4 8 R 3 0 A -1
H T 4 8 R 3 0 A -1
D D
V D D
P A 0 ~ P A 7
V D D
P B 2 ~ P B 7
1 0 0 k W
D D
P B 2 ~ P B 7
1 0 0 k W
P C 1 ~ P C 5
P C 1 ~ P C 5
O S C 1 /P G 1
O S C 1
0 .1 m F
0 .1 m F
O S C 2 /P G 2
0 .1 m F
R E S
V S S
P A 0 ~ P A 7
P B 0 /B Z
0 .1 m F
P B 1 /B Z
3 2 7 6 8 H z
O S C 2
R E S
V S S
P C 0 /T M R
IN T /P G 0
P B 0 /B Z
P B 1 /B Z
P C 0 /T M R
IN T /P G 0
H T 4 8 R 3 0 A -1
H T 4 8 R 3 0 A -1
Note: The resistance and capacitance for reset circuit should be designed in such a way as to ensure
that the VDD is stable and remains within a valid operating voltage range before bringing
RES to high.
Rev. 1.10
22
July 2, 2001
HT48R30A-1
Instruction Set Summary
Mnemonic
Description
Instruction
Cycle
Flag
Affected
1
1(1)
1
1
1(1)
1
1
1(1)
Z,C,AC,OV
Z,C,AC,OV
Z,C,AC,OV
Z,C,AC,OV
Z,C,AC,OV
Z,C,AC,OV
Z,C,AC,OV
Z,C,AC,OV
1
1(1)
Z,C,AC,OV
Z,C,AC,OV
1(1)
1
1
1
1(1)
1(1)
1(1)
1
1
1
1(1)
1
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
1
1(1)
1
1(1)
Z
Z
Z
Z
Arithmetic
ADD A,[m]
ADDM A,[m]
ADD A,x
ADC A,[m]
ADCM A,[m]
SUB A,x
SUB A,[m]
SUBM A,[m]
SBC A,[m]
SBCM A,[m]
DAA [m]
Logic Operation
AND A,[m]
OR A,[m]
XOR A,[m]
ANDM A,[m]
ORM A,[m]
XORM A,[m]
AND A,x
OR A,x
XOR A,x
CPL [m]
CPLA [m]
Rev. 1.10
23
July 2, 2001
HT48R30A-1
Instruction
Cycle
Flag
Affected
1
1(1)
1
None
None
C
1(1)
1
1(1)
1
C
None
None
C
1(1)
1
1(1)
1
None
None
None
1(1)
1(1)
None
None
Jump unconditionally
Skip if data memory is zero
Skip if data memory is zero with data movement
ACC
Skip if bit i of data memory is zero
Skip if bit i of data memory is not zero
Skip if increment data memory is zero
Skip if decrement data memory is zero
Skip if increment data memory is zero with result
ACC
Skip if decrement data memory is zero with result
ACC
Subroutine call
Return from subroutine
Return from subroutine and load immediate data
ACC
Return from interrupt
to
2
1(2)
1(2)
None
None
None
in
1(2)
1(2)
1(3)
1(3)
1(2)
None
None
None
None
None
in
1(2)
None
to
2
2
2
None
None
None
None
Mnemonic
Description
Rotate
RRA [m]
RR [m]
RRCA [m]
RRC [m]
RLA [m]
RL [m]
RLCA [m]
RLC [m]
Data Move
MOV A,[m]
MOV [m],A
MOV A,x
Bit Operation
CLR [m].i
SET [m].i
Branch
JMP addr
SZ [m]
SZA [m]
SZ [m].i
SNZ [m].i
SIZ [m]
SDZ [m]
SIZA [m]
SDZA [m]
CALL addr
RET
RET A,x
RETI
Rev. 1.10
24
July 2, 2001
HT48R30A-1
Mnemonic
Description
Instruction
Cycle
Flag
Affected
2(1)
None
2(1)
None
1
1(1)
1(1)
1
1
1
1(1)
1
1
None
None
None
TO,PD
TO(4),PD(4)
TO(4),PD(4)
None
None
TO,PD
Table Read
TABRDC [m] Read ROM code (current page) to data memory and
TBLH
TABRDL [m] Read ROM code (last page) to data memory and TBLH
Miscellaneous
NOP
CLR [m]
SET [m]
CLR WDT
CLR WDT1
CLR WDT2
SWAP [m]
SWAPA [m]
HALT
No operation
Clear data memory
Set data memory
Clear Watchdog Timer
Pre-clear Watchdog Timer
Pre-clear Watchdog Timer
Swap nibbles of data memory
Swap nibbles of data memory with result in ACC
Enter power down mode
: If a loading to the PCL register occurs, the execution cycle of instructions will be delayed
for one more cycle (four system clocks).
(2)
: If a skipping to the next instruction occurs, the execution cycle of instructions will be delayed for one more cycle (four system clocks). Otherwise the original instruction cycle is unchanged.
(3) (1)
(4)
and (2)
: The flags may be affected by the execution status. If the Watchdog Timer is cleared by
executing the CLR WDT1 or CLR WDT2 instruction, the TO is set and the PD is cleared.
Otherwise the TO and PD flags remain unchanged.
Rev. 1.10
25
July 2, 2001
HT48R30A-1
Instruction Definition
ADC A,[m]
Description
The contents of the specified data memory, accumulator and the carry flag
are added simultaneously, leaving the result in the accumulator.
Operation
ACC ACC+[m]+C
Affected flag(s)
TC2
TC1
TO
PD
OV
AC
ADCM A,[m]
Description
The contents of the specified data memory, accumulator and the carry flag
are added simultaneously, leaving the result in the specified data memory.
Operation
[m] ACC+[m]+C
Affected flag(s)
TC2
TC1
TO
PD
OV
AC
ADD A,[m]
Description
The contents of the specified data memory and the accumulator are added.
The result is stored in the accumulator.
Operation
ACC ACC+[m]
Affected flag(s)
TC2
TC1
TO
PD
OV
AC
ADD A,x
Description
The contents of the accumulator and the specified data are added, leaving
the result in the accumulator.
Operation
ACC ACC+x
Affected flag(s)
Rev. 1.10
TC2
TC1
TO
PD
OV
AC
26
July 2, 2001
HT48R30A-1
ADDM A,[m]
Description
The contents of the specified data memory and the accumulator are added.
The result is stored in the data memory.
Operation
[m] ACC+[m]
Affected flag(s)
TC2
TC1
TO
PD
OV
AC
AND A,[m]
Description
Data in the accumulator and the specified data memory perform a bitwise
logical_AND operation. The result is stored in the accumulator.
Operation
Affected flag(s)
TC2
TC1
TO
PD
OV
AC
AND A,x
Description
Data in the accumulator and the specified data perform a bitwise logical_AND operation. The result is stored in the accumulator.
Operation
Affected flag(s)
TC2
TC1
TO
PD
OV
AC
ANDM A,[m]
Description
Data in the specified data memory and the accumulator perform a bitwise
logical_AND operation. The result is stored in the data memory.
Operation
Affected flag(s)
Rev. 1.10
TC2
TC1
TO
PD
OV
AC
27
July 2, 2001
HT48R30A-1
CALL addr
Subroutine call
Description
Operation
Stack PC+1
PC addr
Affected flag(s)
TC2
TC1
TO
PD
OV
AC
CLR [m]
Description
Operation
[m] 00H
Affected flag(s)
TC2
TC1
TO
PD
OV
AC
CLR [m].i
Description
Operation
[m].i 0
Affected flag(s)
TC2
TC1
TO
PD
OV
AC
CLR WDT
Description
The WDT and the WDT Prescaler are cleared (re-counting from 0). The
power down bit (PD) and time-out bit (TO) are cleared.
Operation
Affected flag(s)
Rev. 1.10
TC2
TC1
TO
PD
OV
AC
28
July 2, 2001
HT48R30A-1
CLR WDT1
Description
The TO, PD flags, WDT and the WDT Prescaler has cleared (re-counting
from 0), if the other preclear WDT instruction has been executed. Only execution of this instruction without the other preclear instruction just sets the
indicated flag which implies this instruction has been executed and the TO
and PD flags remain unchanged.
Operation
Affected flag(s)
TC2
TC1
TO
PD
OV
AC
0*
0*
CLR WDT2
Description
The TO, PD flags, WDT and the WDT Prescaler are cleared (re-counting
from 0), if the other preclear WDT instruction has been executed. Only execution of this instruction without the other preclear instruction, sets the indicated flag which implies this instruction has been executed and the TO and
PD flags remain unchanged.
Operation
Affected flag(s)
TC2
TC1
TO
PD
OV
AC
0*
0*
CPL [m]
Description
Each bit of the specified data memory is logically complemented (1's complement). Bits which previously contained a 1 are changed to 0 and vice-versa.
Operation
[m] [m]
Affected flag(s)
Rev. 1.10
TC2
TC1
TO
PD
OV
AC
29
July 2, 2001
HT48R30A-1
CPLA [m]
Description
Each bit of the specified data memory is logically complemented (1's complement). Bits which previously contained a 1 are changed to 0 and vice-versa.
The complemented result is stored in the accumulator and the contents of
the data memory remain unchanged.
Operation
ACC [m]
Affected flag(s)
TC2
TC1
TO
PD
OV
AC
DAA [m]
Description
The accumulator value is adjusted to the BCD (Binary Coded Decimal) code.
The accumulator is divided into two nibbles. Each nibble is adjusted to the
BCD code and an internal carry (AC1) will be done if the low nibble of the accumulator is greater than 9. The BCD adjustment is done by adding 6 to the
original value if the original value is greater than 9 or a carry (AC or C) is set;
otherwise the original value remains unchanged. The result is stored in the
data memory and only the carry flag (C) may be affected.
Operation
Affected flag(s)
TC2
TC1
TO
PD
OV
AC
DEC [m]
Description
Operation
[m] [m]-1
Affected flag(s)
Rev. 1.10
TC2
TC1
TO
PD
OV
AC
30
July 2, 2001
HT48R30A-1
DECA [m]
Description
Operation
ACC [m]-1
Affected flag(s)
TC2
TC1
TO
PD
OV
AC
HALT
Description
This instruction stops program execution and turns off the system clock. The
contents of the RAM and registers are retained. The WDT and prescaler are
cleared. The power down bit (PD) is set and the WDT time-out bit (TO) is
cleared.
Operation
PC PC+1
PD 1
TO 0
Affected flag(s)
INC [m]
TC2
TC1
TO
PD
OV
AC
Description
Operation
[m] [m]+1
Affected flag(s)
TC2
TC1
TO
PD
OV
AC
INCA [m]
Description
Operation
ACC [m]+1
Affected flag(s)
Rev. 1.10
TC2
TC1
TO
PD
OV
AC
31
July 2, 2001
HT48R30A-1
JMP addr
Directly jump
Description
Bits of the program counter are replaced with the directly-specified address
unconditionally, and control is passed to this destination.
Operation
PC addr
Affected flag(s)
MOV A,[m]
TC2
TC1
TO
PD
OV
AC
Description
The contents of the specified data memory are copied to the accumulator.
Operation
ACC [m]
Affected flag(s)
TC2
TC1
TO
PD
OV
AC
MOV A,x
Description
The 8-bit data specified by the code is loaded into the accumulator.
Operation
ACC x
Affected flag(s)
TC2
TC1
TO
PD
OV
AC
MOV [m],A
Description
The contents of the accumulator are copied to the specified data memory (one
of the data memories).
Operation
[m] ACC
Affected flag(s)
NOP
TC2
TC1
TO
PD
OV
AC
No operation
Description
Operation
PC PC+1
Affected flag(s)
Rev. 1.10
TC2
TC1
TO
PD
OV
AC
32
July 2, 2001
HT48R30A-1
OR A,[m]
Description
Data in the accumulator and the specified data memory (one of the data
memories) perform a bitwise logical_OR operation. The result is stored in the
accumulator.
Operation
Affected flag(s)
TC2
TC1
TO
PD
OV
AC
OR A,x
Description
Data in the accumulator and the specified data perform a bitwise logical_OR
operation. The result is stored in the accumulator.
Operation
Affected flag(s)
TC2
TC1
TO
PD
OV
AC
ORM A,[m]
Description
Data in the data memory (one of the data memories) and the accumulator
perform a bitwise logical_OR operation. The result is stored in the data
memory.
Operation
Affected flag(s)
TC2
TC1
TO
PD
OV
AC
RET
Description
The program counter is restored from the stack. This is a 2-cycle instruction.
Operation
PC Stack
Affected flag(s)
Rev. 1.10
TC2
TC1
TO
PD
OV
AC
33
July 2, 2001
HT48R30A-1
RET A,x
Description
The program counter is restored from the stack and the accumulator loaded
with the specified 8-bit immediate data.
Operation
PC Stack
ACC x
Affected flag(s)
TC2
TC1
TO
PD
OV
AC
RETI
Description
The program counter is restored from the stack, and interrupts are enabled
by setting the EMI bit. EMI is the enable master (global) interrupt bit (bit 0;
register INTC).
Operation
PC Stack
EMI 1
Affected flag(s)
TC2
TC1
TO
PD
OV
AC
RL [m]
Description
The contents of the specified data memory are rotated 1 bit left with bit 7 rotated into bit 0.
Operation
Affected flag(s)
TC2
TC1
TO
PD
OV
AC
RLA [m]
Description
Data in the specified data memory is rotated 1 bit left with bit 7 rotated into
bit 0, leaving the rotated result in the accumulator. The contents of the data
memory remain unchanged.
Operation
Affected flag(s)
Rev. 1.10
TC2
TC1
TO
PD
OV
AC
34
July 2, 2001
HT48R30A-1
RLC [m]
Description
The contents of the specified data memory and the carry flag are rotated 1 bit
left. Bit 7 replaces the carry bit; the original carry flag is rotated into the bit 0
position.
Operation
Affected flag(s)
TC2
TC1
TO
PD
OV
AC
RLCA [m]
Description
Data in the specified data memory and the carry flag are rotated 1 bit left. Bit
7 replaces the carry bit and the original carry flag is rotated into bit 0 position. The rotated result is stored in the accumulator but the contents of the
data memory remain unchanged.
Operation
Affected flag(s)
TC2
TC1
TO
PD
OV
AC
RR [m]
Description
The contents of the specified data memory are rotated 1 bit right with bit 0
rotated to bit 7.
Operation
Affected flag(s)
Rev. 1.10
TC2
TC1
TO
PD
OV
AC
35
July 2, 2001
HT48R30A-1
RRA [m]
Description
Data in the specified data memory is rotated 1 bit right with bit 0 rotated into
bit 7, leaving the rotated result in the accumulator. The contents of the data
memory remain unchanged.
Operation
Affected flag(s)
TC2
TC1
TO
PD
OV
AC
RRC [m]
Description
The contents of the specified data memory and the carry flag are together rotated 1 bit right. Bit 0 replaces the carry bit; the original carry flag is rotated
into the bit 7 position.
Operation
Affected flag(s)
TC2
TC1
TO
PD
OV
AC
RRCA [m]
Description
Data of the specified data memory and the carry flag are rotated 1 bit right.
Bit 0 replaces the carry bit and the original carry flag is rotated into the bit 7
position. The rotated result is stored in the accumulator. The contents of the
data memory remain unchanged.
Operation
Affected flag(s)
Rev. 1.10
TC2
TC1
TO
PD
OV
AC
36
July 2, 2001
HT48R30A-1
SBC A,[m]
Description
The contents of the specified data memory and the complement of the carry
flag are subtracted from the accumulator, leaving the result in the accumulator.
Operation
ACC ACC+[m]+C
Affected flag(s)
TC2
TC1
TO
PD
OV
AC
SBCM A,[m]
Description
The contents of the specified data memory and the complement of the carry
flag are subtracted from the accumulator, leaving the result in the data
memory.
Operation
[m] ACC+[m]+C
Affected flag(s)
TC2
TC1
TO
PD
OV
AC
SDZ [m]
Description
The contents of the specified data memory are decremented by 1. If the result
is 0, the next instruction is skipped. If the result is 0, the following instruction, fetched during the current instruction execution, is discarded and a
dummy cycle is replaced to get the proper instruction (2 cycles). Otherwise
proceed with the next instruction (1 cycle).
Operation
Affected flag(s)
Rev. 1.10
TC2
TC1
TO
PD
OV
AC
37
July 2, 2001
HT48R30A-1
SDZA [m]
Description
The contents of the specified data memory are decremented by 1. If the result
is 0, the next instruction is skipped. The result is stored in the accumulator
but the data memory remains unchanged. If the result is 0, the following instruction, fetched during the current instruction execution, is discarded and
a dummy cycle is replaced to get the proper instruction (2 cycles). Otherwise
proceed with the next instruction (1 cycle).
Operation
Affected flag(s)
TC2
TC1
TO
PD
OV
AC
SET [m]
Description
Operation
[m] FFH
Affected flag(s)
TC2
TC1
TO
PD
OV
AC
SET [m].i
Description
Operation
[m].i 1
Affected flag(s)
TC2
TC1
TO
PD
OV
AC
SIZ [m]
Description
The contents of the specified data memory are incremented by 1. If the result
is 0, the following instruction, fetched during the current instruction execution, is discarded and a dummy cycle is replaced to get the proper instruction
(2 cycles). Otherwise proceed with the next instruction (1 cycle).
Operation
Affected flag(s)
Rev. 1.10
TC2
TC1
TO
PD
OV
AC
38
July 2, 2001
HT48R30A-1
SIZA [m]
Description
The contents of the specified data memory are incremented by 1. If the result
is 0, the next instruction is skipped and the result is stored in the accumulator. The data memory remains unchanged. If the result is 0, the following instruction, fetched during the current instruction execution, is discarded and
a dummy cycle is replaced to get the proper instruction (2 cycles). Otherwise
proceed with the next instruction (1 cycle).
Operation
Affected flag(s)
TC2
TC1
TO
PD
OV
AC
SNZ [m].i
Description
If bit "i" of the specified data memory is not 0, the next instruction is skipped.
If bit "i" of the data memory is not 0, the following instruction, fetched during
the current instruction execution, is discarded and a dummy cycle is replaced to get the proper instruction (2 cycles). Otherwise proceed with the
next instruction (1 cycle).
Operation
Skip if [m].i0
Affected flag(s)
TC2
TC1
TO
PD
OV
AC
SUB A,[m]
Description
The specified data memory is subtracted from the contents of the accumulator, leaving the result in the accumulator.
Operation
ACC ACC+[m]+1
Affected flag(s)
TC2
TC1
TO
PD
OV
AC
SUBM A,[m]
Description
The specified data memory is subtracted from the contents of the accumulator, leaving the result in the data memory.
Operation
[m] ACC+[m]+1
Affected flag(s)
Rev. 1.10
TC2
TC1
TO
PD
OV
AC
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July 2, 2001
HT48R30A-1
SUB A,x
Description
The immediate data specified by the code is subtracted from the contents of
the accumulator, leaving the result in the accumulator.
Operation
ACC ACC+x+1
Affected flag(s)
TC2
TC1
TO
PD
OV
AC
SWAP [m]
Description
The low-order and high-order nibbles of the specified data memory (1 of the
data memories) are interchanged.
Operation
[m].3~[m].0 [m].7~[m].4
Affected flag(s)
TC2
TC1
TO
PD
OV
AC
SWAPA [m]
Description
The low-order and high-order nibbles of the specified data memory are interchanged, writing the result to the accumulator. The contents of the data
memory remain unchanged.
Operation
ACC.3~ACC.0 [m].7~[m].4
ACC.7~ACC.4 [m].3~[m].0
Affected flag(s)
TC2
TC1
TO
PD
OV
AC
SZ [m]
Description
If the contents of the specified data memory are 0, the following instruction,
fetched during the current instruction execution, is discarded and a dummy
cycle is replaced to get the proper instruction (2 cycles). Otherwise proceed
with the next instruction (1 cycle).
Operation
Skip if [m]=0
Affected flag(s)
Rev. 1.10
TC2
TC1
TO
PD
OV
AC
40
July 2, 2001
HT48R30A-1
SZA [m]
Description
The contents of the specified data memory are copied to the accumulator. If
the contents is 0, the following instruction, fetched during the current instruction execution, is discarded and a dummy cycle is replaced to get the
proper instruction (2 cycles). Otherwise proceed with the next instruction (1
cycle).
Operation
Skip if [m]=0
Affected flag(s)
TC2
TC1
TO
PD
OV
AC
SZ [m].i
Description
If bit "i" of the specified data memory is 0, the following instruction, fetched
during the current instruction execution, is discarded and a dummy cycle is
replaced to get the proper instruction (2 cycles). Otherwise proceed with the
next instruction (1 cycle).
Operation
Skip if [m].i=0
Affected flag(s)
TC2
TC1
TO
PD
OV
AC
TABRDC [m]
Move the ROM code (current page) to TBLH and data memory
Description
The low byte of ROM code (current page) addressed by the table pointer
(TBLP) is moved to the specified data memory and the high byte transferred
to TBLH directly.
Operation
Affected flag(s)
TC2
TC1
TO
PD
OV
AC
TABRDL [m]
Move the ROM code (last page) to TBLH and data memory
Description
The low byte of ROM code (last page) addressed by the table pointer (TBLP)
is moved to the data memory and the high byte transferred to TBLH directly.
Operation
Affected flag(s)
Rev. 1.10
TC2
TC1
TO
PD
OV
AC
41
July 2, 2001
HT48R30A-1
XOR A,[m]
Description
Data in the accumulator and the indicated data memory perform a bitwise
logical Exclusive_OR operation and the result is stored in the accumulator.
Operation
Affected flag(s)
TC2
TC1
TO
PD
OV
AC
XORM A,[m]
Description
Data in the indicated data memory and the accumulator perform a bitwise
logical Exclusive_OR operation. The result is stored in the data memory. The
0 flag is affected.
Operation
Affected flag(s)
TC2
TC1
TO
PD
OV
AC
XOR A,x
Description
Data in the accumulator and the specified data perform a bitwise logical Exclusive_OR operation. The result is stored in the accumulator. The 0 flag is
affected.
Operation
Affected flag(s)
Rev. 1.10
TC2
TC1
TO
PD
OV
AC
42
July 2, 2001
HT48R30A-1
Rev. 1.10
43
July 2, 2001