Cadence Commands

ssh -X cadence@ua023.cs.york.ac.uk
Cad3nce
nautilus
irun -hal -v 93 test.v
rc
source ../../tcl/setlibs.tcl
read_hdl src/lut2.v -v2001
elaborate lut2
source ../../tcl/timing.tcl
synthesize -to_generic
synthesize -to_mapped
gui_show
gui_hide
report area > area.rpt
report timing > timing.rpt
report gates > gates.rpt
report power > power.rpt
write_hdl > synth/lut2.v
exit

Commands are:
Analysis
===========================================================================
===================================
all_connected reports the list of all connected objects of the specified object
check_design reports information on design state
clock_ports
finds clock ports of the design
fanin
traces fanin from a pin or port
fanout
traces fanout from a pin or port
report
generates one of various reports
validate_timing generates an Encounter Timing System timing report
ChipWare
===========================================================================
===================================
cwd
creates various HDL objects for ChipWare developer
hdl_create creates various HDL objects for ChipWare developer
Constraint
===========================================================================

===================================
clock_uncertainty specifies the uncertainty on the clock network
define_clock
defines and apply a clock waveform
define_cost_group defines a new goal for timing optimization
derive_environment derives the environment of an instance
external_delay
specifies delay that is outside the design
multi_cycle
overrides default clock edge selection
path_adjust
adjusts path constraints for timing analysis
path_delay
constrains certain paths for timing analysis
path_disable
disables timing analysis for certain paths
path_group
assigns certain paths to a cost group
specify_paths
describes a set of timing paths for a timing exception or a report
Customization
===========================================================================
===================================
add_command_help
adds a help string for a new command
define_attribute
defines a new attribute
delete_unloaded_undriven disconnects subports and hierarchical pins connected to constants and
that do not
fanout to anything, and deletes unloaded and undriven subports from the design
mesg_make
generates new messages in message archive
mesg_send
sends out generated message from message archive
parse_options
parses arguments to a tcl procedure
Design Explorer
===========================================================================
===================================
dex_create_exploration_scenarios creates the exploration scenarios for the specified design
dex_define_exploration_power_domain creates an exploration power domain
dex_execute_exploration_scenarios execute the different scenarios
dex_report
print the design explorer report(s)
dex_write_scenario
generates a basic run script and CPF file for the specified scenario
Design Manipulation
===========================================================================
===================================
change_link
changes the reference of a instance with a new design or subdesign or
libcell.
change_names
change names of select objects
edit_netlist
edits a gate-level design
insert_tiehilo_cells
replaces constants 1'b0 and 1'b1 with tie-cells
mv
renames a design object
remove_assigns_without_optimization replaces assign statements with buffers
reset_design
resets a design
rm
removes an object
ungroup
ungroups one or more instances.
Design for Test
===========================================================================
===================================
add_opcg_hold_mux
replaces a single scan flop by opcg equivalent flop
analyze_scan_compressibility
performs a scan-based compressibility analysis of the
design
and produces actual compression results for each compression

analyze_testability

setting

performs ATPG analysis of the design in either assume or

fullscan mode
check_atpg_rules
generates Encounter Test script files to check if a design is
ATPG ready
check_dft_pad_configuration
checks and reports the data direction control of the pad
logic for the test I/O ports
check_dft_rules
checks for DFT rule violations
check_mbist_rules
checks for MBIST rule violations
compress_block_level_chains
inserts compression logic into actual (existing) scan chains
for lower blocks in hierarchical compression flow
compress_scan_chains
inserts compression logic into actual (existing) scan chains
concat_scan_chains
concatenates actual scan chains for a specific test mode of
operation
configure_pad_dft
configures pads into input or output mode for DFT
connect_compression_clocks
connects mask and misr clocks at the block level to the top
level compression clocks in hierarchical flow
connect_opcg_segments
connects OPCG logic into scan chains
connect_scan_chains
connects scan registers and segments which pass DFT rules
into scan chains
define_dft
defines a DFT object
dft_trace_back
trace back one level from a given pin
fix_dft_violations
fixes DFT rule violations
fix_scan_path_inversions
fixes inversions in the scan path
identify_multibit_cell_abstract_scan_segments identifies abstract_segments for multibit scan cells
identify_shift_register_scan_segments
identifies functional shift-register(s) in the design and
defines those as scan segment(s)
identify_test_mode_registers
identifies fixed value registers in the design, and
auto-asserts them as internal test mode signals.
insert_dft
inserts a DFT object
map_mbist_cgc_to_cgic
map MBIST clock gating logic to integrated clock gating cells
read_dft_abstract_model
reads in abstraction models used for top-level scan chain
stitching
read_io_speclist
reads an IOSpecList file for boundary scan insertion
replace_opcg_scan
replaces domain blocking scan flops by their opcg equivalent
flops
replace_scan
replaces non-scan flops which pass DFT rules by their scan
equivalent flops
reset_opcg_equivalent
removes the scan cells from the opcg-equivalency table which
was previously defined using a (number of)
set_opcg_equivalent commands
reset_scan_equivalent
removes the specified non-scan library cells from the
scan-equivalency table which was previously defined using a
(number of) set_scan_equivalent command(s)
set_compatible_test_clocks
define the set of compatible test clocks
set_opcg_equivalent
controls the opcg cell type that is used during the
conversion of a scan flip-flop by the 'replace_opcg_scan'
command
set_scan_equivalent
controls the scan-equivalent cell type that is used during
the conversion of a non-scan flip-flop which passes the DFT
rule checks to a scan flop
update_scan_chains
updates specified flops in to existing scan chains
write_atpg
describes scan chains for ATPG interface
write_bsdl
writes out BSDL information for a design
write_compression_macro
writes the RTL for the compression macro

write_dft_abstract_model
write_dft_rtl_model
write_et
write_et_atpg
write_et_bsv
write_et_dfa
write_et_lbist
write_et_mbist
write_et_rrfa
write_io_speclist
write_logic_bist_macro
write_mbist_testbench

write_scandef

writes an abstract model description of the actual scan chains

writes an RTL model of the design in Verilog assuming DFT RTL
insertion flow has been enabled and DFT insertion commands
supporting the RTL update flow have been run
writes out data and script files for Encounter Test ATPG and
RRFA analysis and BSV verification
writes out data and script files for Encounter Test ATPG
analysis
writes out data and script files for Encounter Test BSV
verification
writes out data and script files for Encounter Test for DFA
writes out data and script files for Encounter Test for LBIST
writes out data and script files for Encounter Test for MBIST
writes out data and script files for Encounter Test RRFA
analysis
writes an IOSpecList output file which describes the boundary
scan architecture of the design
writes out the LBIST macro
generates mbist Verilog testbenches by executing the
Encounter Test commands: build_model, create_embedded_test
and write_vectors. If there are ROMs in the design, ensure
the rompath and romcontentsfile keywords are passed to
create_embedded_test via the -create_embedded_test_options
keyword.
writes scandef information of the actual scan chains for
physical reordering

GUI
===========================================================================
===================================
gui_balloon_info
retrieve text from last info balloon
gui_hide
hide all windows
gui_hv_clear
remove file data in HDL viewer
gui_hv_get_file
return name of file loaded into HDL viewer
gui_hv_load_file
load a file into HDL viewer
gui_hv_set_indicators
set line and column numbers in HDL viewer
gui_info
set GUI persistent info message
gui_legend
add a legend dialog
gui_pv_airline_add
add an airline between two objects in physical viewer
gui_pv_airline_add_custom
add a customized airline between two objects in physical viewer
gui_pv_airline_delete
delete an airline in physical viewer
gui_pv_airline_display
display airlines in physical viewer
gui_pv_airline_raw_add
add an airline between two points in physical viewer
gui_pv_airline_raw_add_custom add a customized airline between two points in physical viewer
gui_pv_clear
clear selection from physical viewer
gui_pv_connectivity_airlines add connectivity airlines from object in physical viewer
gui_pv_deselect
deselect objects in physical viewer
gui_pv_display_collection
display a collection of objects in physical viewer
gui_pv_draw_box
draw a box in physical viewer
gui_pv_draw_circle
draw a circle in physical viewer
gui_pv_draw_line
draw a line in physical viewer
gui_pv_draw_triangle
draw a triangle in physical viewer
gui_pv_highlight
highlight objects in physical viewer
gui_pv_highlight_update
update object highlight in physical viewer
gui_pv_label
add a label to physical viewer

gui_pv_preferences
gui_pv_redraw
gui_pv_select
gui_pv_selection
gui_pv_snapshot
gui_pv_steiner_tree
gui_pv_update
gui_pv_zoom_box
gui_pv_zoom_fit
gui_pv_zoom_in
gui_pv_zoom_out
gui_pv_zoom_to
gui_raise
gui_reset
gui_resume
gui_selection
gui_show
gui_status
gui_suspend
gui_sv_clear
gui_sv_cone
gui_sv_get_instance
gui_sv_grey
gui_sv_highlight
gui_sv_load
gui_sv_snapshot
gui_update

configure physical viewer preferences

redraw physical viewer contents
select objects in physical viewer
returns physical viewer selection list
create a snapshot of physical viewer
add steiner tree from object in physical viewer
update physical viewer
zoom to specified box in physical viewer
perform 'zoom fit' in physical viewer
perform 'zoom in' in physical viewer
perform 'zoom out' in physical viewer
zoom to bounding box around selected objects in physical viewer
raise main window
reset GUI busy indicators
resume automatic GUI updates
return selection list
show all windows
set GUI status message
suspend automatic GUI updates
clear schematic viewer selection and highlight
load an instance into a cone schematic viewer
returns current instance displayed in schematic
configure schematic viewer grey mode
highlight objects in schematic viewer
load a hierarchical instance or design in schematic viewer
create a snapshot of main schematic viewer
force synchronization of primary viewers with current design database

General
===========================================================================
===================================
?
alias for 'help' command
all_inputs
returns all the input ports.
all_outputs
returns all the output ports.
apropos
search for strings in attributes and commands
attribute_exists
check if an attribute exists
clear
clear terminal window
date
print date
enable_transparent_latches disable En to D paths for transparent latches
exit
exit this program
get_attribute
returns an attribute value from an object
help
provides help for specified command
include
reads in a command file
lcd
changes the UNIX working directory to the specified directory
license
manages license check-in and check-out
lls
lists the contents of the specified UNIX directory
lpopd
remove top of UNIX directory stack and cd to it
lpushd
push current UNIX directory onto stack and cd to new directory
lpwd
returns the UNIX working directory
man
returns information about the specified command, attribute, or message
more
emulates UNIX shell 'more' command
quit
exits this program
redirect
redirects stdout to a file or variable temporarily
reset_attribute
resets an attribute to its default value
sdc_shell
opens the SDC shell. All SDC commands can be used without the dc:: prefix
inside
the SDC shell
set_attribute
sets an attribute value on objects
shell
executes a UNIX shell command from within the tool
statistics
read/write/log QOR statistics at various stages of synthesis
string_representation
convert Tcl object into a string
suppress_messages
disables printing of specified messages.
suspend
brings up a Tcl prompt within a sourced script
timestat
reports the runtime and memory used up to this stage
unsuppress_messages
enables printing of messages that were disabled by the
suppress_messages command.
Input and Output
===========================================================================
===================================
check_cpf
checks the validity of the CPF rules against the design
compare_sdc
checks the impact of updating the SDC constraints with respect to the known
golden sets to validate the correctness of the revised SDC file
decrypt
decrypts a Tcl file generated with the 'encrypt' command
encrypt
encrypts a Tcl or HDL design file
exec_embedded_script
execute the embedded scripts found in given design or subdesign. To
execute the
scripts on all top-designs and their subdesigns, run 'exec_embedded_script'
without any arguments
export_critical_endpoints generates a 'path_adjust' file by comparing RC and Encounter endpoint
timing
reports.
generate_constraints
verifies the design constraints specified in the SDC file and generates any

missing functional false paths or multi-cycle paths

generate_ple_model
creates PLE correlation data for the design and stores this data in the
specified
file
get_read_files
returns information on files that have been read
propagate_constraints
propagates the block level design constraints to top level and integrates
them to
generate an SDC at chip level
read_db
read a netlist in internal database format
read_dfm
reads in yield coefficient file
read_hdl
reads in Verilog or VHDL files
read_netlist
reads (and elaborates) Structural Verilog(v1995) files
read_sdc
reads in design constraints in SDC format
split_db
splits a database into a setup script and a reduced database without root
attributes
validate_constraints
validates the design constraints specified in the SDC file, against RTL or
netlist
verify_power_structure verifies whether the low power cells in the design conform to the CPF file
write_db
write a netlist in internal database format
write_design
generates design snapshot
write_do_ccd
writes out a CCD command file
write_do_clp
generates a dofile for Conformal Low Power Extended Checks
write_do_lec
writes out an LEC command file
write_do_verify
writes out a dofile for Conformal Verify
write_ett
writes out test design constraints in ETT format
write_hdl
writes out a design or a subdesign in Verilog
write_script
writes design constraints in the tools native format
write_sdc
writes out design constraints in SDC format
write_sdf
writes out delay information into a Standard Delay Format (SDF) file
write_set_load
generates set_load values for all nets
write_sv_wrapper
writes out a wrapper SystemVerilog module for a design. Such a wrapper
module
helps in doing comparative simulation of output netlist (from RC) versus input
RTL design, especially when the design description in input RTL has complex ports.
write_template
writes out a template script file for running the tool with the necessary
commands and attributes
Low Power
===========================================================================
===================================
build_rtl_power_models
builds detailed power models for more accurate RTL power analysis.
The
models are used in subsequent RTL power analysis reports.
check_library
allows you to check specific information in the loaded libraries with
regard to level shifters, isolation cells, and state retention cells.
The report also lists the unusable cells.
clock_gating
performs a clock_gating command
commit_cpf
inserts isolation and level shifter logic based on CPF rules
read_cpf
reads in CPF files
read_saif
reads in switching activities in SAIF format
read_tcf
reads in switching activities in TCF format
read_vcd
reads in Value Change Dump (VCD) file for power analysis
reload_cpf
re-applies rules from CPF files read in earlier to newly added design
objects
remove_inserted_sync_enable_logic removes timing critical synchronous enable logic of flops

inserted by
state_retention
write_cpf
write_forward_saif
write_saif
write_tcf

tools through sequential analysis of RTL

performs a state_retention command
writes out updated CPF file(s)
writes out the library forward SAIF file
writes out switching activities in SAIF format
writes out switching activities in TCF format

Multiple Supply Voltage

===========================================================================
===================================
create_library_domain creates a new library domain
isolation_cell
performs isolation cell insertion
level_shifter
performs a level shifter command
Navigation
===========================================================================
===================================
basename
removes leading directory names and returns the object name
cd
sets position in object hierarchy
dirname
removes the object name and returns the directory name
dirs
lists directory stack
filter
filters objects based on attribute value
find
finds an object by type and name
inout_mate returns the other half of an inout object
ls
browses an object or directory
popd
removes top of directory stack and cd to it
pushd
pushes current dir onto stack and cd to new dir
pwd
returns current position in object hierarchy
vdir_lsearch does lsearch of a vdir type object in a list of objects
vname
return the Verilog name of an object
what_is
returns an object's type
what_is_list returns an object's type
Physical
===========================================================================
===================================
check_placement
check placement legality and highlight illegal objects
create_group
create a physical group
create_placement_blockage
create a placement blockage
create_placement_halo_blockage create a placement halo blockage
create_region
create a physical region
create_routing_blockage
create a routing blockage
create_routing_halo_blockage create a routing halo blockage
create_row
create a physical row
create_track
create a physical track
generate_reports
generates the QoS statistics at any stage in the flow. Statistics include
Timing, Area, Instance count, Utilization, Congestion and Power details.
This command is followed by summary_table command to generate a summary
table for these QoS statistics.
move_blockage
change the location of a blockage
move_instance
change the location of an instance
move_port
change the location of a port
move_region
change the location of a region
predict_qos
predicts design QoS

read_def
reads in a DEF file
read_encounter
read in Encounter data files
read_spef
reads the parasitics in SPEF format
resize_blockage
resize a blockage
resize_region
resize a region
restore_congestion_map
restore congestion map data
restore_design
loads an encounter saved database into RC
save_congestion_map
save congestion map data
specify_floorplan
specify design floorplan
summary_table
generates a summary table including various QoS numbers for various
stages
in RC flow. This command has to be preceded with generate_report command,
which creates the QoS statistics to be used by this command.
update_congestion_map
update congestion map data
update_gcell_congestion
update gcell congestion values
update_gcell_pin_density
update gcell pin density values
update_gcell_utilization
update gcell utilization values
write_def
exports floorplan in DEF format
write_encounter
write out Encounter data files
write_spef
writes the parasitics in SPEF format
SDP
===========================================================================
===================================
read_sdp_file reads in an SDP file
write_sdp_file writes out an SDP file
Synthesis
===========================================================================
===================================
elaborate
elaborates previously read HDL files and creates corresponding design and
subdesigns
get_remove_assign_options get options set for replacement of assign statements during synthesis
merge_to_multibit_cells replace n 1-bit cells with a single n-bit cell
retime
retimes the design
set_remove_assign_options controls replacement of assign statements during synthesis
synthesize
synthesizes the design