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Original Russian Text A.S. Korotkov, M.M. Pilipko, D.V. Morozov, J. Hauer, 2010, published in Mikroelektronika, 2010, Vol. 39, No. 3, pp. 230240
AbstractThe results are presented of a design effort concerned with a deltasigma modulator with a 50
MHz clock rate and a 128 oversampling ratio. Its prototype is fabricated in 0.18m CMOS technology and
is powered by a 1.8V unipolar supply. It provides a 9bit resolution, while consuming 33 mW of power.
DOI: 10.1134/S106373971003008X
1. INTRODUCTION
Tracking analogtodigital converters (ADCs)
using deltasigma modulation compare favorably
with the other types of ADC in terms of power con
sumption and size [1, 2]. Deltasigma ADCs have
recently become popular in mobile phones. For exam
ple, singleconversion receivers with zero intermedi
ate frequency employ a deltasigma ADC resolution
of 812 bits to convert constant signal levels in the
communication channel.
Deltasigma ADCs are based on the concept of
delta modulation, in which a continuous signal under
goes clocked conversion into a sequence of voltage
pulses, whose height represents the sign of the incre
ment of the original signal at each clock instant, rela
tive to the preceding value of the signal. If a signal has
a uniform spectrum or contains a constant compo
nent, its conversion involves a deltasigma modulator,
which operates in oversampling mode, i.e., well above
the Nyquist rate, and therefore requires a decimation
filter. This tends to be implemented as a standard
design, e.g., a finiteimpulseresponse filter. However,
the performance of a deltasigma ADC is mainly
determined by its deltasigma modulator, since the
latter is solely responsible for analogtodigital con
version, the decimation filter reducing output pulse
rate and doing serialtoparallel code conversion. This
consideration explains why designing a deltasigma
modulator plays such an important part in building a
deltasigma ADC. Theoretical research on delta
sigma modulators was reviewed by Korotkov and
Telenkov [1]. Note that a deltasigma modulator can
be implemented from a programmable analog inte
grated circuit [3] or as an applicationspecific inte
grated circuit (ASIC).
This paper describes a newly designed deltasigma
modulator having a clock rate of 50 MHz, an oversam
210
in out+
ph1
ph1
C5
C7
C9
out vref
vref+
I3
I2
ph1
ph2
ph2
C6
in+ out
ph2
ph2
agnd
C3
agnd
in
ph1
ph1
C2
in+
ph2
211
S1
ph2
ph1
I1
ph1
C1
ph2
agnd
in+ out
in+
in out+
in
out
out
ph1
ph1
agnd
ph1
agnd
agnd
C4
ph2
C10
C8
ph2
ph2
S2
out vref+
vref
vdd
M5
M7
M3
M4
vbp
vbp
M1
M9
in
vbn
vbn
vb1
M11
M8
M2
in+
out
M6
out+
M10
M13
vcmfb1
vcmfb1
M12
vss
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agnd
KOROTKOV et al.
agnd
212
vcm1
ph2
ph2
ph2
out
ph1
C4
ph1
C2
ph1
vcmfb1
ph1
C3
out+
C1
ph2
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vc+
Wn/Ln
M6
M1
M2
2Wn/Ln
213
vss
Wn/Ln
2
M4
M3
2Wp/Lp
Wp/Lp
vc
M5
Wp/Lp
vdd
vdd
M4
vcmfb2
n+
M8 M9
M10 M11
nx
nx+
M8
ph2
M7
M18
M22
M19
M23
I1
D
in
vdd
M3
M2
M12
ph2
M13
in+
nq+
M20
M24
M21
M25
out
vss
Q
M1
nq
ph1
ph2
vb2
M5
M14 M15
M16M17
vss
Fig. 5. Comparator.
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KOROTKOV et al.
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0
20
dB
40
60
80
100
120
102
103
104
105
Frequency, Hz
106
107
Fig. 6. Simulated output spectrum of the deltasigma modulator with a sinusoidal input.
0
20
40
60
80
100
120
102
103
104
105
Frequency, Hz
106
107
Fig. 7. Input spectrum of the deltasigma modulator in the case of the sinusoidal signal of Fig. 6 with additive white noise.
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KOROTKOV et al.
0
20
dB
40
60
80
100
120 2
10
103
104
105
Frequency, Hz
106
107
Fig. 8. Simulated output spectrum of the deltasigma modulator in response to the input displayed in Fig. 7.
4. TESTING A PROTOTYPE
OF THE DELTASIGMA MODULATOR
Figure 11 presents a photograph of a prototype chip
layout for the deltasigma modulator, implemented in
0.18m CMOS technology. The prototype was tested
in the arrangement shown in Fig. 12 (the contact pads
are designated as in Fig. 11). The contact pads vddd
70
60
50
40
30
20
10
0
10
70
60
50 40 30 20
Input signal strength, dB
10
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70
60
50
dB
40
30
20
10
0
10
210
180
Degrees
150
120
90
60
30
0
100
101
102
103
104
105
106
107
Hz
Fig. 10. Simulated magnitude response and phase response for the OTA.
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KOROTKOV et al.
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1.8 V 1.8 V
0.9 V
+
+
vdd
vref+
agnd
1.8 V
+
vref
vddd
in+
v3io
in
out
1.8 V
+
vss
ib
vssd
cib
pd
Agilent 16702A
Logic Analysis
System
clock
20
dB
40
60
80
100
120
102
103
104
105
Frequency, Hz
106
107
Fig. 13. Example of a measured output spectrum from the prototype deltasigma modulator.
5. CONCLUSIONS
The results are presented of a design effort con
cerned with a switchedcapacitor balanced delta
sigma modulator with a 50MHz clock rate and a 128
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7.
REFERENCES
1. Korotkov, A.S. and Telenkov, M.V., AnalogtoDigital
Converters Based on DeltaSigma Modulators, Zarubezh.
Radioelektron. Usp. Sovremennoi Radioelektron., 2002, no.
12, pp. 5372.
2. Shakhov, E.K., ADCs: Oversampling, Quantization
Noise Shaping, and Decimation, Datchiki Sist., 2006, no.
11, pp. 5057.
3. Barkanov, A.V. and Korotkov, A.S., DeltaSigma Modu
lator Implemented in a Programmable Analog Integrated
Circuit, in Materialy 3ei NTK Novye metodologii proek
tirovaniya izdelii mikroelektroniki (Proc. 3rd Tech. Conf.
on Novel Microelectronic Design Methodologies),
Vladimir State Univ., 2004, pp. 4346.
4. Rogatkin, Yu.B., CMOS SwitchedCapacitor Integrator,
Mikroelektronika, 2003, vol. 32, no. 6, pp. 414420 [Russ.
Microelectron. (Engl. Transl.), vol. 32, no. 6, pp. 333338].
5. Carrillo, J.M., Montecelo, M.A., Neubauer, H., Hauer,
H., and DuqueCarrillo, J.F., 1.8V SecondOrder
Modulator in 0.18m CMOS Technology, in Proc. Euro
pean Conf. on Circuit Theory and Design, 2005, vol. 1,
pp. 197200.
6. Korotkov, A.S. and Pilipko, M.M., ExpandedBandwidth
DeltaSigma Modulator for Use in ADCs, in Trudy SPb
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