EuCARD BOO 2010 004 PDF

EuCARD-BOO-2010-004
European Coordination for Accelerator Research and Development
PUBLICATION
Front-end Electronics for Multichannel

Semiconductor Detector Systems;
EuCARD Editorial Series on Accelerator
Science and Technology, Vol.08
Grybos, P (AGH-UST, Krakow, Poland)
17 August 2012
The research leading to these results has received funding from the European Commission
under the FP7 Research Infrastructures project EuCARD, grant agreement no. 227579.
This work is part of EuCARD Work Package 4: AccNet: Accelerator Science Networks.
The electronic version of this EuCARD Publication is available via the EuCARD web site
<http://cern.ch/eucard> or on the CERN Document Server at the following URL :
<http://cdsweb.cern.ch/record/1473436
EuCARD-BOO-2010-004
Pawe Grybo
Front-end Electronics
for Multichannel
Semiconductor
Detector Systems
Editorial Series on ACCELERATOR SCIENCE
Institute of Electronic Systems

Warsaw University of Technology Warsaw 2010
Kazimierz Korbel
Andrzej Napieralski
the part of 64-channel DEDIX integrated circuit

(photo courtesy of Luciano Ramello)
Front-end electronics for multichannel semiconductor detector systems
CONTENTS
Acknowledgements ...................................................................................................................... iii
List of symbols ..............................................................................................................................iv
Abbreviations and acnonyms used in the text..............................................................................viii
1. Introduction ................................................................................................................................1
2. Semiconductor detectors.............................................................................................................5
2.1. Materials for semiconductor detectors ............................................................................6
2.2. Reverse bias p-n junction ................................................................................................8
2.3. Charge generation in detector........................................................................................13
2.4. Charge transport ............................................................................................................15
2.5. Ramo theory and signal formation ................................................................................19
2.6. Detector geometry .........................................................................................................21
2.7. Important detector parameters.......................................................................................23
3. Architecture of front-end electronics ........................................................................................27
3.1. Types of amplifiers........................................................................................................29
3.2. Charge sensitive amplifier.............................................................................................31
3.2.1. Ideal charge sensitive amplifier .........................................................................31
3.2.2. Realistic charge sensitive amplifier ...................................................................33
3.2.3. Examples of core amplifier architectures...........................................................37
3.2.4. Feedback configuration......................................................................................40
3.2.5. Test injection circuit ..........................................................................................42
3.3. Shaper............................................................................................................................43
3.3.1. Signal shaping....................................................................................................44
3.3.2. Noise analysis ....................................................................................................56
3.4. Noise optimization of CSA input transistor ..................................................................62
3.4.1. Strong inversion region......................................................................................63
3.4.2. Moderate and weak inversion regions ...............................................................66
3.5. Aspect of fast signal processing ....................................................................................70
3.5.1. Pulse pile-ups at CSA output .............................................................................71
3.5.2. Pole-zero cancellation circuit.............................................................................72
3.5.3. Base line restorer ...............................................................................................75
3.6. Further signal processing...............................................................................................80
3.6.1. Discriminators....................................................................................................83
3.6.2. Peak Detector Derandomizer .............................................................................86
4. Important aspect of multichannel low noise mixed-mode integrated circuits..........................89
4.1. Noise modeling in MOS transistors ..............................................................................91
4.1.1. Channel thermal noise........................................................................................91
4.1.2. Flicker noise.......................................................................................................94
4.1.3. Short channel effects..........................................................................................96
ii
4.2. Cross-talk in mixed mode circuits.................................................................................98

4.2.1. Generation, transmission and reception of switching noise ...............................98
4.2.2. Reducing the noise generation .........................................................................102
4.2.3. Increasing the immunity of analog part ...........................................................103
4.2.4. Isolation techniques .........................................................................................103
4.2.5. Summary of crosstalk reduction techniques ....................................................106
4.3. Random matching and offsets .....................................................................................107
4.3.1. Mismatch parameters of MOS transistors........................................................109
4.3.2. Transistor matching in various processes ........................................................112
4.3.3. Current matching in MOS transistors ..............................................................114
4.3.4. Random matching in circuits ...........................................................................115
4.3.5. Layout rules for good matching .......................................................................116
4.3.6. Matching on multichip modules ......................................................................118
4.3.7. Mismatch simulation using Monte Carlo analysis ...........................................119
5. Radiation damage in silicon detectors and readout electronics...............................................121
5.1. Total dose effects ........................................................................................................122
5.1.1. Displacement damage ......................................................................................122
5.1.2. Ionization effects..............................................................................................123
5.2. Single event effects .....................................................................................................127
5.3. Radiation tolerant design of readout electronics .........................................................128
6. Examples of multichannel counting IC for X-ray applications...............................................131
6.1. Requirements for multichannel counting systems.......................................................132
6.2. ASIC for strip detectors...............................................................................................135
6.3. Solutions for pad detectors and small array of pixel detectors ....................................141
6.4. Solutions for pixel detectors........................................................................................148
7. References ..............................................................................................................................173
iii
Acknowledgements
This monograph is the result of countless interactions with many people who devoted their precious time and effort trying to teach me electronics. At various occasions
I have met them at universities, research institutes, conferences, meetings, or just on the
web. I would like to thank them all for their open mind, patience and cordial assistance.
I have also benefited from suggestions made by my reviewers: Prof. Kazimierz Korbel
and Prof. Andrzej Napieralski.
I wish to extend my appreciation to Robert Szczygie for proof-reading and Marcin Grybo for his help with drawing figures. I am also grateful to Janusz Ole and Boena Bryzek-Ole for linguistic corrections. Finally, I would like to thank my wife Joanna
and family for their continuous support.
The part of the work presented in this monograph was supported by the Ministry
of Science and Higher Education, Poland, Projects no. N515 262 235 in the years
20082010 and Project no. N515 243 037 in the years 20092011.
Pawe Grybo
iv
LIST OF SYMBOLS
A
AF
A
ACox
A
Ai
AL
A
AP
AW
AVT0
a
N
b
n, p
C
Cb
Cbu
C , CVT0
Cc
Cdet
CF
Cgs
Cgd
Cin
Cn
Cnu
Cox
Cov
Cpar
CT
Ctest
C1
D
De,Dh
DI
d
E, Emax, Emin
Eg
Eph
Ew
ENC
ENCf
ENCi
ENCw
Si
ox
fitting parameter
SPICE exponent constant for flicker noise
area proportionality constant of variation of current factor
area proportionality constant of variation of gate oxide capacitance
area proportionality constant of variation of body factor
real part of pole
proportionality constant of variation of channel length
area proportionality constant of variation of mobility
area proportionality constant of variation of parameter P
proportionality constant of variation of channel width
area proportionality constant of variation of threshold voltage
constant
exponent constant of flicker noise
fitting parameter
constant
current factor in MOS transistor
beta of transistor npn, beta of transistor pnp
capacitance
capacitance to the backplane
capacitance to the backplane per unit strip length
matching parameters
coupling capacitance
detector capacitance
feedback capacitance
gate-source capacitance
gate-drain capacitance
input amplifier capacitance
capacitance to the neighbour strip (interstrip capacitance)
capacitance to the neighbour strip per unit strip length
oxide capacitance per unit area
overlap gate-diffusion capacitance per channel width
parasitic capacitance of connection detector - CSA
sum of capacitances Cdet, C1 and Cpar
test capacitor
input transistor capacitance
spacing distance
diffusion coefficient for electrons, holes
threshold adjust implant dose
detector thickness
electric field, maximum electric field, minimum electric field
energy bandgap
photon energy
weighting field
equivalent noise charge
ENC contribution from flicker voltage noise
ENC contribution from current noise
ENC contribution from thermal voltage noise
silicon permittivity
oxide permittivity
Front-end electronics for semiconductor detector systems

F
F()
Fv,Fvf, Fi
f
fin
fD
f0
fnoiMod
F
MS
T
GBW
GDSNIO
gds
gm
gmb
H0
H(s)
IBEAM, IBEAM0
ID0
IDB
Idet
IDS
iD
ik
if
inoW
di 2
df
j
J
JR, JRg
k
K
Kf
Kfn , Kfp
KF
Kv
K0
L
Leff
Lind
Lmin
att
e , h
eff
Fano factor
amplitude characteristics
filter constants for ENCw, ENCf, ENCi
frequency
average frequency of input pulses
duty factor of input pulses
noise count rate at zero threshold level
switch for flicker noise model in BSIM4
Fermi potential
gate-semiconductor work function difference
thermal voltage T=kT/q
gain bandwidth product
channel thermal noise coefficient in HSPICE
source-drain conductance
gate transconductance
body transconductance
constant
filter transfer function
body factor
thermal noise factor changing from weak to strong inversion
beam intensity, primary beam intensity
process dependent parameter for subthreshold current
drain-bulk current
detector leakage current
drain-source current
detector current pulse
current induced at k electrode
normalized forward current
ratio of if /W
power spectral density of current noise
imaginary unit
current density
reverse current density, reverse generation current density
Boltzman constant
constant
flicker noise constant
flicker noise constants of NMOS and PMOS transistors
SPICE flicker noise constant
voltage gain
DC gain
channel length
effective channel length
inductance
minimum channel length
channel length modulation parameter
fitting parameter
mobility
attenuation coefficient
mobility of electrons, holes
effective mobility
vi
after
NA
Na
ND
Neh
Nit
Not
NLEV
NOIA, NOIB, NOIC
NTNOI
n, nG
ni
ns
npo
P
p
p0
pi
pno
q
Q
Q(s)
Qc
Qin
Qinv
Qox
Qtot
Qtest
R
Rbias
RDS
Rin
Rpz
Rsu
Rf
rds
r
S
S
SP
SVT0
s
si
n
photo
T
Tepi
t
timp
mobility after irradiation

acceptor doping density
channel dopant density
donor doping density
number of electron-hole pairs
number of interface traps
number of oxide traps
switch for noise model parameter in HSPICE
parameters for flicker noise in BSIM4
parameter for more accurate fitting of thermal noise in BSIM4
number (i.e. filter order)
intrinsic carrier concentration
subthreshold slope factor
electron concentration in p-type semiconductor in thermal equilibrium
parameter
p = s
real pole in Ohkawa method p0=A0
complex poles in Okhawa method (i =1,2.3 ..) and pi = Ai Wi
hole concentration in n-type semiconductor in thermal equilibrium
resistivity of n-type silicon
elementary charge
charge
polynomial
charge associated with the depletion region
input charge
total inversion channel charge
fixed oxide charge density
total charge
injected charge via test capacitor Ctest
resistance
detector bias resistance
bias dependent drain-source resistance in BSIM4 model
input amplifier resistance
effective resistance in PZC circuit
effective resistance of strip per unit strip length
effective CSA feedback resistance
small signal drain-source resistance
spread of charge carriers with respect to trajectory without diffusion
variation of the current factor with a distance
variation of the body factor with a distance
variation of the parameter P with a distance
variation of the threshold voltage with a distance
s = j
pole
conductivity or rms deviation of normal distribution
voltage noise rms
photoabsorption cross section
absolute temperature
epi-layer thickness
time
charge collection time at detector electrode

te, th
temax, thmax
tox
tm
tp
tp1
tp2
txo
tnoiMod
e , h
g
f, HP, LP, 1, 2,in
u, ue, uh
W
Wdep
Wi
WSIopt
WSI
0, 1, 2
V
Vbi
Vdep
VDS
VDSsat
VGS
Vosr
VR
Vref
VT
VT0
VTH
Vtest
VSB
collection time for electron, holes

maximum collection time for electron, holes
oxide thickness
width of the pulse at the fraction m of its peak height, where m is specified as 0.1, 0.01 etc.
pulse peaking time, measured from 1% of the peak height to the centre
of the peak
bipolar pulse peaking time, measured from 1% of the peak height to the
center of its peak
bipolar pulse peaking time, measured from 1% of the peak height of the
primary lobe to the peak of the undershoot
crossover time of a bipolar pulse
switch for thermal noise model in BSIM4
time constant
carrier lifetime for electrons, carrier lifetime for holes
carrier generation lifetime
time constants
charge velocity, electron velocity, hole velocity
channel width
width of depletion region
imaginary part of pole
optimum transistor width for minimum ENCw - strong inversion case
optimum transistor width for minimum ENCw
angular frequency
poles of transfer function
potential
built-in potential
depletion voltage
drain-source voltage
drain-source saturation voltage
gate-source voltage
random offset
reverse bias voltage
reference voltage
threshold voltage
threshold voltage for VSB = 0
comparator threshold voltage
voltage step applied to test capacitor Ctest
source-bulk voltage
dv 2
df
power spectral density of voltage noise
vin
vout
ydep
Z
Zin
input voltage signal

output voltage signal
average channel thickness
atomic number
input impedance
vii
viii
ABBERIVATIONS AND ACRONYMS

USED IN THE TEXT
ADC
AGH UST
AMS
ASIC
ATLAS
BLH
BLR
BNL
BSIM
CASTOR
CCD
CERN
CIX
CMOS
CMS
CPPM
CSA
DAC
DEDIX
DDR
DPAD
DxCTA
EKV
e-h
ELT
ENC
FEOL
FNAL
HEP
IC
LDD
LET
LHC
IGFET
LVDS
MBU
MEDIPIX
MIP
MOS
MOSFET
MPEC
MPW
NIEL
NMOS
OTA
PD
PILATUS
Analog-to-Digital Converter
AGH University of Science and Technology
austriamicrosystems
Application Specific Integrated Circuit
A Toroidal Lhc ApparaturS
Base Line Holder
Base Line Restorer
Brookhaven National Laboratory
Berkeley Short-channel IGFET Model
Counting and Amplifying SysTem fOr Radiation detection IC
Charge Coupled Devices
European Organization for Nuclear Research
Counting and Integrating X-ray IC
Complementary Metal Oxide Semiconductor
Compact Muon Solenoid
Centre de Physique des Particules de Marseille
Charge Sensitive Amplifier
Digital-to-Analog Converter
Dual Energy Digital Imaging of X-ray IC
Double Data Rate
Digital Pixel Array Detector
chip name
mathematical model of MOSFET developed by C.C. Enc, F. Krummenacher and A. E. Vittoz
electron-hole
Enclosed Layout Transistor
Equivalent Noise Charge
Front-End-Of Line
Fermi National Accelerator Laboratory
High Energy Physics
Integrated Circuit
Light Doped Drain
Linear Energy Transfer
Large Hadron Collider
Isolation Gate Field Effect Transistor
Low Voltage Differential Signaling
Multiple Bit Upsets
Medical Pixel Chip
Minimum Ionizing Particle
Metal Oxide Semiconductor
MOS Field Effect Transistor
Multi Picture Element Counters IC
Multi-Project-Wafer run
NonIonizing Energy Loss
N-channel MOSFET
Operational Transconductance Amplifier
Peak Detector
PIxeL ApparaTUs for the SLS

PIXSCAN
PMOS
PSD
PSI
PX90
PZC
RAM
RELAXD
sd
SEBO
SEE
SEFI
SEGR
SEL
SES
SET
SEU
SHE
SLS
SOI
SPECTRE
SPICE
SRAM
SSD
STM
TIMEPIX
ToT
TSMC
TSV
VIPIC
VLSI
XPAD
XPCS
small animal X-ray CT-scaner

P-channel MOSFET
Position Sensitive Detector
Paul Scherrer Institute
Pixel Xray readout 90 nm IC
Pole-Zero Cancellation
Random Access Memory
high REsolution Large Area X-ray Detectors
standard derivation
Single Event Burt-Out
Single Event Effect
Single Event Function Interrupt
Single Event Gate Rupture
Single Event Latchup
Single Event Snapback
Single Event Transient
Single Event Upset
Single Hard Error
Swiss Light Source
Silicon In Isolator
simulation program for circuit analysis
Simulation Program with IC Emphasis
Static Random Access Memory
Silicon Strip Detector
STMicroelectronics
chip developed at CERN
Time-over-Threshold
Taiwan Semiconductor Manufacturing Company
Through Silicon Vias
Vertically Integrated Pixel Imaging Chip
Very Large Scale Integration
Xray Pixel Advanced Detector
X-ray Photon Correlation Spectroscopy
ix
Introduction
1. INTRODUCTION
The history of semiconductor detectors started in 1951 when K. McKay noticed

that the german diode could be used for detection of particles [1]. A reversely biased
diode proved to be the best solution for particle and radiation detection. The sixties and
seventies saw the development of both semiconductor detectors and readout electronics,
optimized mainly for spectroscopy applications. In those times, a classical detector system consisted of a single detector and a single readout channel. The theory connected
with a signal shaping, a noise optimization, pile-up effects in the front-end electronics
were being intensely developed then [2].
Another important step was the use of the planar process by J. Kemmer [3] to produce a strip detector. Since then semiconductor detectors with many electrodes and with
the pitch typically in the range from 50 m to 200 m have been used as position sensitive devices. Fast development of the VLSI technology has allowed designing multichannel integrated readout electronics for these detectors according to the rule stating
Introduction
that each detector electrode is readout by an independent electronic channel. Such position sensitive semiconductor systems have been used for many years in High Energy
Physics (HEP) experiments, where the number of readout electronic channels comes up
to several millions [4,5]. Nowadays, similar systems are used in different X-ray imaging
techniques in solid-state physics, material science, medicine, etc. In these applications,
the trend is to build the position sensitive detection system, which will provide also information about energy of photons.
For many years, the author has worked on different aspects related to front-end
electronics for semiconductor detector systems, namely:
designing and testing silicon position sensitive detectors for HEP experiments and
X-ray imaging applications,
designing and testing of multichannel readout electronics for semiconductor detectors
used in X-ray imaging applications, especially for noise minimization, fast signal processing, crosstalk reduction and good matching performance,
optimization of semiconductor detection systems in respect to the effects of radiation
damage.
The presented monograph is the result of the author's experience in the
above-mentioned areas and it is an attempt of a comprehensive presentation of issues
related to the position sensitive detection system working in a single photon counting
mode and intended to X-ray imaging applications. The structure of this book is schematically shown in Fig. 1.1.
Fig. 1.1. Book structure.
Introduction
The source of the signal is a semiconductor detector, which is described in Chapter 2 together with its equivalent electric model. The theory of the signal shaping and
noise optimization is presented in Chapter 3. During the design of multichannel integrated circuits for detector systems certain important aspects connected with VLSI technologies must be taken into account, i.e. noise modeling, crosstalk between digital and
analog parts of an integrated circuit and the problem of mismatch. These aspects for
CMOS bulk technology are discussed in Chapter 4. Because the detector and readout
electronics operate in radiation fields they suffer from radiation damages, and a brief
description of these effects is given in Chapter 5. The best source of knowledge on how
to solve various problems of readout electronics are working multichannel ASICs used
in detector systems. Detailed descriptions of them can be found in journals (mainly
IEEE TNS, NIM A), conference proceedings, technical reports or PhD theses. The solutions for high energy physics are also described in excellent books, like [4,5]. However,
the last decade has also brought a dynamic development of applications using strip and
pixel semiconductor detectors for different X-ray imaging techniques. The examples of
multichannel readout electronics working in single photon counting mode for X-ray
imaging applications have been dealt with in Chapter 6.
The author hopes that this monograph will help young designers of VLSI electronics who frequently join scientific laboratories after graduation and work on semiconductor detectors and readout electronics. Their task is often to design multichannel
Application Specific Integrated Circuits (ASIC) for strip or pixel semiconductor detector, and they often raise the question how to design successfully the analog part of multichannel front-end electronics. There are two aspects to be smoothly inter-connected in
such a design, namely:
theory of signal processing in detector readout electronics which was developed many
years ago,
VLSI technology, which, despite its obvious advantages has also some relevant limitations.
Semiconductor detectors
2. SEMICONDUCTOR DETECTORS
Semiconductor Position Sensitive Detectors (PSD) have been successfully used in

particle physics experiments for more than two decades. From the wide variety of these
detectors, the following are most frequently used:
strip/pixel detectors,
charge coupled devices (CCD),
silicon drift chambers,
monolithic active pixels.
This chapter focuses on the first group of detectors, which is the most popular for particle physics experiments and also more frequently used in X-ray imaging applications.
The strip/pixel detector is an array of individual sensor elements which in response to
a single particle/photon produce a short current pulse on a given electrode. The position
of this electrode determines the hit position. The further pulse processing in a front-end
electronics can provide not only binary information (YES/NO pulse on a given electrode) but also information about energy deposited in the detector or about time event.
In particle physics experiments several layers of such detectors allow to reconstruct the
particle track. In X-ray imaging techniques these detectors can work in a single photon
counting mode providing information about the spatial photon distribution and sometimes also about photon energies. An advantage of single photon counting detectors is
essentially an infinite dynamic range contrary to the integration-type detectors (like
those used in CCD cameras), which usually have problems with a limited dynamic range
and a low contrast of an image.
This chapter presents briefly basic physic phenomena in a semiconductor detector
together with a process of pulse generation in the detector medium. Different possible
geometry (strip, pixel, pad) of these detectors is presented. The detector geometry and
the type of material used determine not only spatial resolution of the detector and its
efficiency, but also influence its electrical parameters like capacitance or leakage current
per single electrode. These parameters can be modeled in an equivalent electric scheme
of the sensor and later, easily implemented together with the front-end electronics during numerical simulation.
2.1. MATERIALS FOR SEMICONDUCTOR DETECTORS
A good material for a solid-state detector should possess the following features:
large signal in response to particle/photon deposited energy, which requires
a small energy bandgap of a given material to ensure low average energy for the
hole-electron generation,
low atomic number Z and low density in case of tracking application for particle
physic experiments (particle energy is measured in the calorimeter system),
high atomic number Z and high density in case of X-ray and -ray spectroscopic
and imaging applications; high density leads to a large energy loss per traversed
length and higher probability of absorbing all photons in a beam,
high mobility of charge carriers and no trapping effects to collect all the generated charge in a short period of time (important for an operation with high radiation intensity),
large carrier lifetime to increase so-called charge collection efficiency, defined
as a collected charge on the electrode to a total deposited charge,
low leakage current in room temperature; too small bandgap can result in a significant thermally generated current,
large and high quality crystal (good homogeneity, low impurity levels, high resistivity) to produce a large area detector,
radiation hardness especially in case of new accelerator experiments where radiation doses are really high,
stable and matured industrial fabrication and processing with relatively low cost
and good availability.
Table 2.1 shows the main parameters of different semiconductor materials and
diamond (insulator) often used to produce Position Sensitive Detector (PSD).
Parameter
Si
Average Z
14
Energy bandgap [eV]
1.12
Density [g/cm3]
2.3
Energy for electron-hole
3.64
pair generation [eV]
Mobility at T =300K [cm2/Vs]
- electrons
1350
- holes
480
Carrier lifetime [s]
250
#
Diamond is classified as an insulator
Table. 2.1. Important parameters of materials used for detector.

Ge
GaAs
CdTe
CdZnTe
Diamond#
32
31/33
48/52
48/30/52
6
0.67
1.43
1.44
5.48
1.6
5.3
5.4
6.1
5.8
3.5
2.96
4.2
4.43
4.6
13.1
1900
3900
250
8000
400
0.0010.01
1100
100
0.12
1000
100
0.12
1800
1200
0.001
For nearly three decades, the silicon has been the most popular material used for
semiconductor detectors [3, 6]. A very advanced silicon technology is driven by electronics industry. The silicon material fulfills nearly all of the above points, with the exception of high Z and radiation hardness. Because of low Z =14 and matured stable
technology, it is very attractive for a tracking detector in particle physics experiments.
These experiments are often performed on high luminosity machines like the Large
Hadron Collider (LHC), where the expected radiation doses are very high. For silicon
tracker doses up to 10 Mrad of ionizing particles and fluences of 10131014 neutron/cm2
are expected in over ten years of LHC operation [7]. In such conditions both the bulk
damages [8, 9] and ionization effects in silicon oxide [10, 11] are observed. The low
Z and low silicon density limit its X-ray applications mainly to low energy photons.
A standard 300 m thick detector converts nearly all 8 keV X-ray, but only 26.7% of
20 keV X-ray and 2% of 60 keV X-ray. Therefore, many laboratories make an effort to
produce detectors more efficient for high X-ray energy, with the use of other semiconductor materials [12, 13], such as high purity germanium (Ge) and compound semiconductors, like gallium arsenide (GaAs), cadmium telluride (CdTe), cadmium zinc telluride (CdZnTe).
Germanium has smaller bandgap than silicon (0.67eV vs. 1.12eV for Si) and has
a very good energy resolution [14]. However, low energy bandgap greatly increases
a reverse current and a Ge detector typically is cooled to nitrogen temperature (77 K).
Germanium, because of high photoabsorption cross section photo Z 4-5, is more attractive for higher X-ray energies than silicon [15].
Gallium arsenide has been studied as the material for a semiconductor detector
for -ray since the early 1960s [12, 13, 16]. Because of its potential radiation hardness,
it is also used in military applications and tested for possible applications in particle
physics experiments. GaAs has relatively high mobility. Because of impurities in the
order of 1015 cm-3, its carrier lifetime is only 10 ns. Due to trapping effects, it also suffers from an incomplete charge collection.
CdTe and CdZnTe have high density and high Z (ZCd = 48, ZTe = 52, ZZn =30).
Because of large photon absorption cross section and possibility of operation at room
temperature, they are used for X-ray and -ray spectroscopic and also for medical imaging applications [17-19]. CdTe and CdZnTe generally suffer from poor hole collection.
The hole mobility is very low h 100 cm2/Vs and tends to be much smaller than for
electrons e 1000 cm2/Vs. The detectors with CdTe Schottky contacts have lower
leakage currents than ohmic devices. However, Schottky detectors have a problem with
polarization effects [20]. The technology of CdTe and CdZnTe detectors is still limited
to small crystal and the connections with front-end electronics are more difficult than in
case of Si detectors.
Diamond, as a material with low Z, is a good candidate for tracking applications
in particle physics [21]. It has very good radiation hardness, even for radiation expected
at LHC. Diamond is classified as an insulator and in order to create hole-electron pair,
an average energy of 13.1 eV is required. Large detector samples have not been
achieved yet. Because of very long trapping times, the signal from a diamond detector
increases during radiation ("pumping" or "priming" effect [22]).
2.2. REVERSE BIAS P-N JUNCTION

A reversed biased pn junction is a basic element for silicon detector and its parameters influence the detector characteristics. Let us consider an abrupt p+n junction
under the reversed bias as shown in Fig. 2.1. The following assumption is made: constant doping densities of ND in the n-type side (i.e. ND = 1012 atoms/cm3) and NA in the
p-type side (i.e. NA = 1016 atoms/cm3). Even for zero applied bias voltage, there is a region at the junction where the mobile charges (electrons and holes) are removed, leaving
fixed acceptor and donor ions. This region is called the depletion region or space charge
region. Because of the fixed ions in this area, there is a built-in potential equal to [23,
24]:
Vbi = T ln
N AND
ni2
(2.1)
where T = kT/q 26 mV (at T = 300 K) and ni is the intrinsic carrier concentration in

pure silicon (ni 1.451010 cm-3 at T = 300 K). The above numbers of ND and NA give
Vbi 1 V. If we apply reversed bias voltage VR , the total voltage across the junction
increases to VR+Vbi. The overall charge neutrality requires that
W1 N D = W2 N A
(2.2)
where W1 and W2 are the width of the depletion region in p+ an n side of the junction.
Because NA >> ND the depletion region extends predominantly into the n-side region and
the width of depletion layer Wdep = W1 + W2 W1.
Fig. 2.1. The abrupt p+n junction under the reversed bias condition: a) junction, b) charge density,
c) electric field, d) potential.
10
The potential is described by Poisson's equation
qN D
d 2V
=
2
Si
dx
for
d 2V qN A
=
Si
dx 2
W1 x < 0
0 < x W2
for
(2.3)
(2.4)
where q is electron charge and Si is the permittivity of silicon (1.0410-12 F/cm). Integration of the above equations with boundary conditions E = 0 for x =W1 and x =W2
gives
E ( x) =
qN D (x + W1 )
for
Si
E ( x) =
qN A (x W2 )
Si
for
W1 x < 0
(2.5)
0 < x W2
(2.6)
and the maximum Emax of the electric field is at x = 0
E max =
qN DW1
Si
qN AW2
Si
(2.7)
Integration of equations (2.5) and (2.6) gives voltage drops in the p+ side and n side of
the junction equal to
V1 =
qN DW12
2 Si
(2.8)
V2 =
qN AW22
2 Si
(2.9)
Using the eq. (2.2), (2.8) and (2.9) the total voltage drop across the junction is:
Vbi + VR =
qN DW12
2 Si
N
1 + D
NA
11
(2.10)
Because for asymmetrical p+n junction (NA >> ND), the above equation can be rewritten
as
Vbi + VR =
qN DW12
2 Si
(2.11)
The width of a depletion layer Wdep W1 is given as:
Wdep =
2 Si (Vbi + VR )
qN D
(2.12)
There are two important conclusions from the above equation. The first conclusion is
that for the abrupt junction, the width of depletion region is proportional to square root
of the applied reversed voltage VR. The second one is that a depletion voltage Vdep,
which guarantees the total depletion of the whole detector area (with the thickness d), is
lower for a purer detector material (lower ND or higher resistivity silicon). The full depletion voltage is given as:
Vdep = VR |Wdep = d =
qN D d 2
2 Si
Vbi
(2.13)
For detector production silicon wafers with resistivity in the range from 5 to 10 kcm
are used. The relation between the resistivity n (n-type silicon) and the dopant concentration ND is
n =
1
qe N D
(2.14)
where e is the mobility of electrons (for low electric field e is equal to 1350 cm2/Vs at
T = 300 K). Using formulae (2.13) and (2.14) the depletion voltage Vdep can be rewritten
12
Vdep =
d2
2 Si n e
Vbi
(2.15)
For example, for the given above resistivity of a detector wafer of 300 m thick (based
on n-type material) the depletion voltage Vdep is in the range from about 31 V to 63 V.
The depleted junction volume is free from the mobile charges and forms a capacitor. Since there is a voltage-dependent charge QC associated with the depletion region,
the junction capacitance can be calculated as
C=
d (qN DWdep )
dQC
=
= Si =
2
dVR
qN W Wdep
d D dep
2 Si
q Si N D
2(VR + Vbi )
(2.16)
According to the above equation, the capacitance is inversely proportional to square root
of the applied reversed voltage VR .
The reversed bias junction has always a dark or leakage current which can be approximated by the sum of diffusion components in the neutral region and the generation
current in the depletion region (for pno >> npo and |VR| > 3kT/q) [23]
JR = q
Dh ni2 qni Wdep

+
p ND
g
(2.17)
where JR is the reversed current per unit area, ni is the intrinsic carrier concentration,
g is the carrier generation lifetime, Dh is diffusion coefficient for holes and h is carrier
lifetime for holes. In case of semiconductor with small values of ni (like Si), the generation current may dominate [23]. The additional components to the detector leakage current are surface generation current and avalanche breakdown current at high voltage.
A method to reduce the detector current is to reduce the temperature. Consider the
generation current JRg where the temperature dependence is hidden in the intrinsic carrier
concentration ni and in the generation lifetime g.The JRg is proportional to [4]
E
J Rg T 2 exp g
2kT
(2.18)
13
where Eg is the energy bandgap and k is the Boltzman constant. For silicon
(Eg = 1.12 eV) the temperature drop by every 8 K means the generation current reduction by factor of 2. So, in order to reduce the detector leakage current and noise associated with it, the detector is often cooled.
2.3. CHARGE GENERATION IN DETECTOR

An interaction of a charge particle or electromagnetic radiation with sensor material is a basis for their detection. The mechanism of this interaction is different, depending on particle or photon energy.
Electromagnetic radiation interacts with the detector material via several main
processes, depending on photon energies, namely: photoelectric effect, coherent scattering, incoherent scattering and pair production. During the photoelectric effect or pair
production, the photon is absorbed in the sensor material, while it is scattered and
changes its direction in Compton effect. The photon beam going through the sensor does
not change its energy but is attenuated according to the absorption law [25]
I BEAM ( x) = I BEAM 0 exp( att x )
(2.19)
where IBEAM0 is the primary beam intensity and IBEAM(x) is beam intensity after crossing
the detector medium in x distance and att is an attenuation coefficient. The photon cross
section vs. energy in silicon is shown in Fig. 2.2.
Fig. 2.2. The photon cross section vs. energy in silicon.
14
The average number of e-h pairs produced by a single photon of energy Eph absorbed in a semiconductor detector is given as
N=
E ph
(2.20)
Eeh
where Eeh is energy needed for ionization (energy required to create an e-h pair). In silicon Eeh = 3.6 eV and it is different from band gap energy Eg = 1.12 eV because an excitation of an electron to a conduction band requires a simultaneous transfer of both energy and momentum. In silicon the minimum of the conduction band and the maximum
of the valence band have a wave vector offset and during the excitation the momentum
is transferred to lattice vibration [4]. For example, the X-ray photon of 8 keV (absorbed
in Si by photoelectric effect) produces about 2200 e-h pairs and the charge deposition is
located nearly in a single point (see Fig. 2.3(a)). The number of produced pairs is also
subject to statistical fluctuation described by Fano factor F according to [26]
N eh2 = FN eh
(2.21)
The Fano factor is a function of temperature and for Si the measured F value is between
0.07 and 0.16 [2729].
(a)
(b)
Fig. 2.3. Generation of a hole-electron pair in silicon strip detector for: a) low energy X-ray - charge is
generated nearly in a single point, b) minimum ionization particle - charge is generated along particle
track.
A high energy charge particle (like in high energy physics experiments) traverses
the sensor and deposits there a part of its energy. The energy is deposited by many scattering processes with electrons of sensor material and the energy deposition is described
by "long" Bethe-Bloch formula [30]. Along the particle trajectory hole-electron pairs are
15
produced (see Fig. 2.3(b)). A minimum ionizing particle produces about 77 e-h pairs per
m path length in Si, which means about 23000 e-h pairs for the popular 300 m thick
silicon detector. This is only the most probable value of generated charge because the
process of energy deposition for minimum ionizing particles is subject to statistical fluctuation described usually by Landau-Vaviliov distribution (or Bichsel distribution - see
Fig. 2.4). These distributions show a long tail, so there is a significant probability of
higher energy deposition and more generated charge.
Fig. 2.4. A comparison of noiseless Bichsel and Vavilov distributions for a single 300 m long track
segment (reprinted from [31] 1995, with permission from Elsevier,
http://www.sciencedirect.com/science/journal/ ).
2.4. CHARGE TRANSPORT

There are two mechanisms of charge carrier transport drift and diffusion. In the
presence of an external field the charge moves parallel to the electric field and it is accelerated between random collisions with the lattice. The average carrier drift velocity is
given by
r
ue = e E
r
uh = h E
(2.22)
(2.23)
In silicon at low field (up to about 104 V/cm) the mobility is constant. At 300 K
the mobility is 1350 cm2/Vs for electrons and 480 cm2/Vs for holes. For high electric
field (E > 105V/cm) the carrier drift velocity saturates at the level of 107 cm/s. The holes
and electrons move in opposite directions and the time required for carriers to traverse
16
the detector volume is called collection time. Collection time depends on a charge generation point, detector thickness and the applied electric field.
The electric field in reversed biased p+n diode depends on the applied VR voltage.
Fig. 2.5 shows only the n-side of the diode for three different cases: partial depletion
voltage, full depletion voltage and overdepleted voltage. Compared to Fig. 2.1 the x-axis
is shifted of detector thickness to simplify the further calculations.
(a)
(b)
(c)
Fig. 2.5. Electric field in a reversed biased diode (only n-side is shown) for different values of applied
voltages VR : a) VR < Vdep , b) VR = Vdep , c) VR > Vdep .
To shorten collection time the overdepleted case with VR > Vdep is mostly used. In
that case the field distribution can be written as
E ( x) =
qN D
Si
x + E min
(2.24)
where
Emin
VR Vdep
d
(2.25)
Let us consider a pair of carriers (electron and hole) generated at point x0 (see
Fig. 2.5(c)). The motion equations are the following [32]
qN
dx
= h D x + Emin for hole
dt
Si
(2.26)
qN
dx
= e D x + Emin for electron
dt
Si
(2.27)
17
Integrating the above equations with the initial condition x = x0 at t = 0 one obtains for
hole 0 t th
q N
Emin + x0 + Si Emin exp h D t

qN D
qN D
Si
Si
xh =
(2.28)
and for electron 0 t te
q N
Emin + x0 + Si Emin exp e D t

qN D
qN D
Si
Si
xe =
(2.29)
The velocities uh = dxh/dt and ue = dxe/dt as a function of time are
q N
qN D
uh = h Emin +
x0 exp h D t
Si
Si
(2.30)
q N
qN D
ue = e Emin +
x0 exp e D t
Si
Si
(2.31)
The collection times th and te can be calculated directly from (2.28) and (2.29)
th =
te =
Si
ln
d + ( Si / qN D )Emin
x0 + ( Si / qN D )Emin
(2.32)
Si
ln
x0 + ( Si / qN D )Emin
( Si / qN D )Emin
(2.32)
h qN D
e qN D
For holes the collection time is the longest if x0 = 0 and then
th max =
Si
h qN D
ln
( Si / qN D )Emin
(2.33)
18
For electrons the collection time is the longest if x0 = d and then
te max =
Si
e qN D
ln
( Si / qN D )Emin
(2.34)
The examples of the maximum charge collection time (assuming that charge cross the
whole detector thickness) for different bias voltages of the detector are calculated in
Table 2.2. For the calculation it is assumed that the silicon resistivity is 10 kcm
(Vdep = 31 V) and the detector thickness is d = 300 m.
Table. 2.2. Examples of the maximum collection times in Si detector with Vdep = 31 V and d = 300 m
calculated according to equations (2.33) and (2.34).
Applied voltage VR [V]

45
60
90
120
180
temax for electrons [ns]

17.9
12.1
7.6
5.6
3.7
thmax for holes [ns]

50.2
34.1
21.5
15.9
10.5
The long collection time can influence the energy resolution of the position sensitive detector because of a diffusion process. In case of gradient concentration, the random movement of the charge carries is more probable in the direction of lower concentration. So, the cloud of charge carriers spreads out with respect to the trajectory without
diffusion. The average square deviation r 2 during the time interval t is [32]
r 2 = 2 De, ht
(2.35)
where De is a diffusion coefficient for electrons and Dh is a diffusion coefficient for

holes. In position sensitive detector, like a strip or a pixel detector, the diffusing cloud of
charge carriers can be divided between neighboring detector electrodes. This effect is
called charge sharing or charge division and in case of a small pitch between detector
electrodes it deteriorates the detector energy resolution [33, 34]. The relationship between diffusion coefficient and mobility is the following [23]
kT
De , h = e , h
q
(2.36)
19
In silicon the diffusion coefficients are De 35 cm2/s (3.5 m2/ns) for electrons and
Dh 12 cm2/s (1.2 m2/ns) for hole. The spread of thermal diffusion is larger for longer
time collections, so for this reason, in position sensitive detectors the collection time
should be minimized.
The second important case where collection time plays an important role, is the
case of using very fast readout electronics. The shaping time in the readout electronics
should be longer than the collection time to integrate all the charge generated in the detector. Otherwise, the pulse amplitude in the readout electronics is proportional only to
the fraction of generated charge and this phenomenon is called ballistic deficit [4].
2.5. RAMO THEORY AND SIGNAL FORMATION

After the charge generation, the holes and electrons start to move in the detector
medium because of the applied electric field. A movement of generated charge carriers
induces current pulse in detector electrodes (a current flow i(t) in the circuit connected
to the detector electrode). The current flow begins instantaneously and finishes when all
the charges (both electrons and holes) are collected. The polarity of induced currents by
holes and electrons on a given detector electrode are the same, because the charges of
opposite signs move in opposite directions. The current ik(t) induced at k electrode of the
detector by the infinitesimal movement of the charge q is described by the Ramo theorem [35]
i k (t ) = quk Ew
(2.37)
where uk is drift velocity and Ew is a weighting field. The weighting field is obtained
by applying unit potential to k electrode and zero to all other electrodes and it is different from the electric field inside the sensor. For practical cases (such as strip or pixel
detector) the numerical calculation is necessary to obtain pulse shape at different electrodes. The pulse shape strongly depends on initial distribution of electrons and holes,
detector geometry and electric field distribution [32, 36].
Consider the simple case with parallel plate geometry and linear field distribution
for VR > Vdep as shown in Fig. 2.5(c). The weighting field is in this case Ew = 1/d. According to the Ramo theorem the following expression can be written for current induced by the motion of charge carriers (see eq. (2.30)(2.31))
20
ih (t ) =
q N
q
qN
h Emin + D x0 exp h D t
d
Si
Si
(2.38)
ie (t ) =
q N
q
qN
e Emin + D x0 exp e D t
d
Si
Si
(2.39)
The examples of generated current pulse are shown in Fig. 2.6(a).

In case of very large overbias of a detector (VR >> Vdep) the electric field in the detector can be approximated as a uniform field E VR /d. The weighting field is in this
case Ew = 1/d and velocity is u = VR /d. Using the Ramo theorem one obtains
ih (t ) =
q
hVR
d2
(2.40)
ie (t ) =
q
eVR
d2
(2.41)
The examples of the current pulses for the uniform field are shown in Fig. 2.6(b).
(a)
(b)
Fig. 2.6. Examples of pulse shapes for parallel plate geometry and: a) linear field distribution, b) uniform
field [32, 37].
21
2.6. DETECTOR GEOMETRY

A position sensitive semiconductor detector is an array of individual sensor elements and, in most cases, each element is readout by an individual electronic channel
(other solutions using charge division effect are also possible [38, 39]). In case of silicon, the detectors are built as matrices of reverse biased diodes processed on common
high-resistivity substrate (510 kcm) of 250500 m thick. The sensitive area can be
divided into individual diodes of the shapes according to the geometrical requirements
of the experiment, concerning the area to be covered and the spatial resolution. The examples of a strip detector are shown in Fig. 2.7. Single sided strip detectors (mostly with
strip pitch in the range from 20 m to 200 m - see Fig 2.7(a)) provide one dimensional
information and requires a relatively low number of readout electronic channels per
detector area. Sometimes in X-ray imaging systems the silicon strip detector is illuminated from the edge (so that photons enter the detector along the strips) [40,41]. The
using of detector in edge-on configuration increases the photon absorption for higher
X-ray energies.
(a)
(b)
Fig. 2.7. Simplified view of strip position sensitive detector: a) single sided strip, b) double sided strip.
Fig. 2.8. Ambiguity of position reconstruction in double sided silicon strip detectors.
22
The double sided detector (see Fig. 2.7(b)) is an interesting option for 2-D imaging. The second orthogonal set of strips is made on the backside of the detector, however this solution is limited to a low intensity radiation experiment [42]. Assume that
two photons hit the detector at the same time (see Fig. 2.8). The two photons produce
signals in two upper and bottom strips. From the reconstruction of the hits, four positions are possible: two real hits and two "ghost" hits. To minimize the number of "ghost"
hits, radiation intensity must be limited or a very fast and precise coincidence system
has to be used.
Fig. 2.9. Simplified view of 2D position sensitive pad detector.
Fig. 2.10. Hybrid pixel detector - sensor and readout chip are connected together using bump-bond
technique.
A real two dimensional imaging is possible using pad or pixel detector - see
Fig. 2.9 and Fig. 2.10. A pad detector requires a trace to each electrode, because the
readout electronic channels are connected at one, two or four sides of this detector (usually by a simple wire bonging technique) [43]. This limits the maximum number of the
readout channels (to about several hundreds of channels). A pixel detector does not have
23
such limitations. For an X-ray imaging application a pixel area as small as

55 m 55 m [44] is used, however larger pixels like 130 m 130 m [45] or
172 m 172 m [46] are more popular. For HEP application, a rectangle pixel shape is
also used like, for example 150 m 100 m [47], 400 m 50 m [48] or
425 m 50 m [49]. The pixel architecture requires that the pixel size of the detector
and the pixel size of a single readout electronic channel must be identical (see Fig. 2.10).
Power limitation and area limitation for pixel readout electronic are really challenging
[50]. Additionally, a bump-bonding process [5, 51] (to connect a sensor and a readout
chip together) is not cheap process.
Spatial resolution of position sensitive detectors shown in Fig. 2.7 and Fig. 2.9 is
determined not only by geometry of the detector (strip/pixel pitch) but also by:
intrinsic spatial resolution of a detector resulting from the interaction of photons with
the detector material and charge transport processes (diffusion spread, charge sharing,
etc.) [33, 52],
parameters of the readout electronic system, especially signal to noise ratio (SNR) is
discussed in detail in Chapter 3.
2.7. IMPORTANT DETECTOR PARAMETERS

The 3-D model of a DC coupled Si strip detector is shown in Fig. 2.11 [53]. The
components shown in this scheme represent:
Cbu - capacitance to the backplane per unit strip length,
Cnu - capacitance to the neighbour strips per unit strip length (interstrip capacitance),
Rsu - effective resistance of strip per unit strip length.
The effective strip resistance is a parallel connection of a highly doped semiconductor
strip (diffusion/implantation p+ or n+ type) and a low resistivity metal strip. The resistance of the metal strip (usually Al) per unit length depends on the metal thickness and
width. For example, for 1 m thick and 20 m wide Al strip has resistance of
1520 /cm.
Fig. 2.11. Simplified 3D model of DC-coupled strip detector.
24
(a)
(b)
Fig. 2.12. Simplified model of position sensitive detector: a) DC-coupled, b) AC-coupled.
If the current pulse shape is not important for the performed experiment (in most
cases the current pulse is integrated in a charge sensitive amplifier), then the strip resistance can be neglected and the model can be significantly simplified to the scheme
shown in Fig. 2.12(a), where Cb and Cn represent the total capacitance of the strip to the
backplane and to the neighbour strips respectively. An AC-coupled detector model
(Fig. 2.12(b)) contains additionally coupling capacitance Cc (between p+ strip and metal
strip) and the bias resistance Rbias.
The parameters of the detector are usually measured before connections of the
readout integrated circuit, however, some of them can be approximated in advance. The
backplane capacitance per strip length is
Cb Si p
l
d
(2.42)
where p is the strip pitch and d is the detector thickness. This capacitance slightly depends also on the strip width. For example, for a 280 m thick detector with 50 m pitch
the measured Cb/l is 0.150.18 pF/cm (for strip width w is in the range from 1030 m)
[53]. The capacitance to the neighbour strip (interstrip capacitance) in a Si detector can
be approximated as [54]
Cn
w + 20m
= 0.03 + 1.62
l
p
(2.43)
where, in the above formula, the strip width and pitch in m and Cn/l are obtained in
pF/cm. This capacitance depends on the quality of field oxide between strips and usually
increases after strong irradiation. In most cases this capacitance is in the range of
0.81.5 pF/cm [5255].
25
In case of an AC-coupling detector, one should also take into account also decoupling capacitance Cc/l = 10-30 pF/cm and bias resistance Rbias. The bias resistance
depends on the used structure to bias the detector (diffusion resistor, FOXFET structure,
etc.) and it varies in the range from 200 k up to over 100 M.
An additional detector parameter is detector leakage current Idet which strongly
depends on the bulk material quality (high resistivity Si is better but more expensive),
process production, temperature and radiation damage. For example, for a good new Si
detector with 50 m pitch and standard 300 m thickness, this leakage current should be
below 100 pA/cm (at room temperature).
A simplified model for a pixel detector is similar to the one shown in
Fig. 2.12 (a). The capacitance to the backplane for pixel area A is
Cb
Si A
d
(2.44)
For example, for a 300 m thick detector with the pixel area A equals to
100100 m2, this capacitance is about 3.5 fF. The more important component is capacitance to the neighbour pixel and it strongly depends on implant/diffusion area. One
has to expect the total capacitance for a 125125 m2 square pixel is of 100 fF, and of
about 200 fF for a long and narrow 40050 m2 pixel [5]. Because the capacitance of
a pixel detector itself is really small, other parasitic components of the closely spaced
detector readout electronics should be taken into account (capacitance between the
detector and ground/bias plane of readout IC, capacitance of bump bonds etc.).
As for the noise performance of the detector readout system, three parameters of
position sensitive detector are important:
total capacitance per strip/pixel (sum of bulk capacitance, interstrip capacitance, parasitic capacitance of the connection with readout IC),
shot noise of detector leakage current (per strip/pixel),
thermal noise of the bias resistor (AC coupled detectors only).
The noise performance of readout electronics is discussed in detail in Chapter 3.
The second effect related to detector capacitance is the crosstalk between detector
electrodes. Due to interstrip/interpixel capacitance, the charge deposited on a single
electrode can induce parasitic signals on neighboring strips/pixels. Consider the simple
scheme shown in Fig. 2.12(a). In most systems, the relationship between input capacitance Cin of readout electronics and detector capacitances are the following
Cin >> 2Cn > Cb
(2.45)
26
Fig. 2.13. Simplified model of one detector electrode together with the input capacitance Cin of readout
electronics.
The simplified scheme of one electrode node can be drawn as shown in Fig. 2.13.
The charge Qtot deposited at node X leads to the voltage
VX =
Qtot
Cin + 2Cn + Cb
(2.46)
The charge Qin which flows to the readout electronics is
Qin =
Qtot
2Cn + Cb
Cin = Qtot 1
Cin + 2Cn + Cb
Cin + 2Cn + Cb
(2.47)
The remaining charge fraction (Qtot Qin) is located by half on left and right electrodes. To minimize this crosstalk between the electrodes, the effective input capacitance Cin of readout electronics must be much higher than the total strip/pixel capacitance (2Cn + Cb).
Architecture of front-end electronics
27
3. ARCHITECTURE OF FRONT-END
ELECTRONICS
The current pulse provided by the sensor is amplified and shaped in the front-end
electronics. Different modes of signal acquisition are possible: current mode, voltage
mode or mode with Charge Sensitive Amplifier (CSA) at the input. An example of
front-end electronics using the mode with CSA is schematically shown in Fig. 3.1.
A current signal generated in the silicon strip/pixel detector is integrated in a charge
sensitive preamplifier. At the output of the preamplifier one obtains a voltage step with
amplitude proportional to the total charge generated in the detector. The voltage step is
fed to the main amplifier called a shaper, which provides pulse shaping according to the
timing requirements and the filtration of noise to maximize the signal to noise ratio.
Further processing of the shaped signal can be done in different ways depending
on specific applications. Possible options are schematically shown in Fig. 3.1. The first
one is based on so-called binary readout architecture. In that case the comparator detects
28
the presence of the signal of amplitude above the preset threshold and in response provides 1-bit yes/no information. The second way of processing the shaped signal employs
an analog-to-digital converter (ADC), where the amplitude of the signal corresponding
to each individual photon is measured, and then the information is stored and used for
off-line processing. The third option is used for timing measurements - determination of
the time of occurrence.
Fig. 3.1 Example of a front-end electronics used in a detector readout system.
The number of front-end channels in readout systems in most cases is equal to the
number of strips/pixels in the semiconductor detector. In case of readout electronics for
strip detector, multichannel integrated circuits are mostly designed as 32, 64 or 128
channels integrated circuits, which are the basis for building larger modules consisting
of several hundreds up to a few thousands readout channels (see Fig. 3.2) [56].
Fig. 3.2. Fragment of multichip module: 512- strip detector connected to eight 64-channel readout ASICs.
29
3.1. TYPES OF AMPLIFIERS

The signal reception from a detector can be realized in the front-end electronics in
three main modes [32, 37]:
current mode: to preserve pulse shape,
voltage mode: to obtain high signal amplitude at the amplifier input,
mode with charge sensitive amplifier to integrate a detector current pulse.
As the option with the CSA is most widely used in the front-end electronic system
it is presented in detail in the next chapter. To distinguish between the current and voltage modes, a simplified scheme of a detector and input amplifier is useful (see Fig. 3.3).
The capacitance CT is a sum of detector capacitance Cdet, input transistors capacitance C1
and stray capacitance Cpar of the connection between the detector and front-end electronics. The resistance Rin represents the input resistance of the amplifier. For the detector
pulse, the current iD provided to the amplifier can be written as
i R ( s ) = iD ( s )
1
1 + sCT Rin
(3.1)
Fig. 3.3. Simplified scheme of a detector and input amplifier [37].
In the current mode the signal from the detector is amplified without change in its
shape. This requires a very low input time constant in= RinCT and this means the requirements of small input resistance Rin of the amplifier.
In the voltage mode the voltage signal produced at the input of the amplifier is
much higher thanks to high value of the input resistance Rin and it can be written as
30
v R ( s ) = iD ( s )
1
Rin
1 + sCT Rin
(3.2)
However, the above increase of pulse amplitude vR results in long time constant
in at the amplifier input and the detector pulse shape is no longer preserved but it is
determined by this long time constant. The possible practical realization of current and
voltage modes are schematically shown in Fig. 3.4 (timp is the charge collection time at
detector electrode).
(a)
(b)
Fig. 3.4. The examples of realization of an input stage of front-end electronics: a) current configurations,
b) voltage configurations.
31
3.2. CHARGE SENSITIVE AMPLIFIER
3.2.1. Ideal charge sensitive amplifier

The option with ideal charge sensitive amplifier at the input is shown in Fig. 3.5.
The capacitance CF is connected in the feedback of the core amplifier with the gain of
K0.
Fig. 3.5. Simplified scheme of a charge sensitive amplifier.
Summing the current at the CSA input one obtains
iD ( s ) =
v
vout
sCT + out vout sC F
K0
K0
(3.3)
where vout is the voltage at CSA output. The above equation gives the CSA transfer
function
vout ( s )
1
K0
=
iD ( s )
s ( K 0 + 1)C F + CT
which for K0 >> 1 simplifies to:
(3.4)
32
vout ( s)
1
iD ( s )
sCF
(3.5)
Using the eq. (3.4) the signal at CSA output can be written as
vout (t ) =
K0
( K 0 + 1)C F + CT
timp
(t )dt
(3.6)
where timp is the charge collection time at the detector electrode. Assuming at the input
the delta-like current pulse iD(t) = Qin(t) one obtains at the CSA output the voltage step
which is proportional to total charge carried by the detector pulse
vout (t ) =
K0
Qin
( K 0 + 1)CF + CT
(3.7)
For K0 >> 1 the above equation can be simplified to
vout (t ) =
Qin
CF
(3.8)
The important feature of an ideal CSA is an independence of the output voltage to

the detector capacitance which is guaranteed by the requirement
( K 0 + 1)CF >> CT
(3.9)
For the ideal integrator its input impedance Zin is capacitive and the effective high
input capacitance is guaranteed by the high gain K0 of the amplifier (due to the Miller
effect [24])
Z in ( s ) =
1
1
( K 0 + 1) sCF K 0 sCF
(3.10)
The large input capacitance of CSA and the requirements (3.9) guarantee that
most of the charge produced by the detector is transferred to the amplifier (see
eq. (2.47)).
33
3.2.2. Realistic charge sensitive amplifier

In a realistic CSA two additional aspects should be taken into account:
feedback capacitance CF has to be discharged to avoid saturation of the amplifier, e.g.
by the effective resistance Rf connected in parallel to CF,
the core amplifier has frequency-dependent voltage gain, which in the simplest form
with one pole can be written as
v out ( s )
K0
= KV =
vin ( s)
1 + s 0
(3.11)
where K0 is the DC gain and 0 is the dominant pole of the amplifier. The gain bandwidth product of the amplifier is GBW = K00. With the above aspects in mind let us
consider the CSA scheme shown in Fig. 3.6 with additional unity gain buffer to ensure
small output impedance [5]
Fig. 3.6. Charge sensitive amplifier based on a core amplifier with frequency dependent voltage gain.
Summing the currents in the input node one obtains
1
iD ( s ) = vin ( s) sCT + (vin ( s ) vout ( s ) )
+ sCF
(3.12)
34
Substitution in (3.12) the vin(s) from eq. (3.11) results in
vout ( s )
K0
=
iD ( s )
1 + K0
1 2 CT + CF
+ s CT + (1 + K 0 )CF +
+s
0 R f
0
Rf
(3.13)
Because K0 >> 1 and assuming that the requirement ( K 0 + 1)C F >> C D is fulfilled the equation (3.13) can be rewritten as
vout ( s )
iD ( s )
Rf
1 2 (CT + CF )R f
1 + s R f CF +
+s
GBW
GBW
(3.14)
The above transfer function has two poles 1 and 2 which are usually real and
widely separated (1 << 2). The denominator of this function can be written as
1
1
s
s
s2
s
s2
D ( s ) = 1 + 1 + = 1 + s + +
1+ +
1 12
1 2
1 2 12
(3.15)
Therefore the dominant pole of CSA is
1 =
1
1
R f CF +
GBW
(3.16)
Because the feedback time constant R f CF is much higher than 1/GBW the dominant
pole can be rewritten as
1
R f CF
(3.17)
35
The second high-frequency pole according to (3.13) - (3.16) is given by
2 GBW
CF
CT + CF
(3.18)
There are two time constants connected with the above poles feedback time constant f = 1/1 and 2 = 1/2 and the transfer function of the CSA can be rewritten as
Rf
vout ( s )
1 f f
2
(1 + s f )(1 + s 2 ) CF f 2 1 + s f 1 + s 2
iD ( s )
(3.19)
In the time domain in response to the input current pulse iD(t) = Qin(t) one obtains at the CSA output
vout (t ) =
Qin f
exp( t f ) exp( t 2 )
CF f 2
(3.20)
The exemplary time responses are shown in Fig. 3.7. The time constant f is responsible for slow signal decay and 2 determines the rise time at CSA output.
For very high feedback resistance Rf (according to (3.17) the time constant
f ) one obtains
vout (t )
Qin
[1 exp( t 2 )]
CF
(3.21)
For a very fast core amplifier GBW (according to (3.18) the time constant
2 0) and finite f the equation (3.20) simplifies to
vout (t ) =
Qin
exp( t f )
CF
(3.22)
36
(a)
(b)
Fig. 3.7. Time response of the CSA for different time constants (horizontal scales in both figures are
different): a) f is responsible for slow signal decay, (b) 2 determines the rise time at CSA output.
The realistic CSA amplifier has also different input impedance than specified by
eq. (3.10). For low frequency << 0 the input impedance is given as
Z in ( s )
Rf
1
K 0 1 + sCF R f
(3.23)
For large Rf the above equation gives the same result as eq. (3.10) and the input
impedance appears capacitive with the effective input capacitance Cin K0CF.
For high frequency >> 0 the gain drops linearly with frequency and it can be
expressed as
KV
K 00
GBW
=
s
s
(3.24)
Assuming large Rf and for high frequency >> 0 the input impedance of CSA is
Z in ( s )
1
1
s
=
GBW sC F C F GBW
(3.25)
37
This impedance appears as a resistance Rin = (CF GBW)-1. The situation at the input of the amplifier becomes similar to situation shown in Fig. 3.3. The time constant at
the CSA input in= RinCT equals
in =
CT
C F GBW
(3.26)
In order to transfer quickly the charge generated by the detector to the charge sensitive
amplifier, the GBW of the core amplifier must be sufficiently large.
3.2.3. Examples of core amplifier architectures

Cascode amplifier architecture is one of most commonly used solutions for CSA
core [5769] because of its simplicity, high output resistance, reduction of unwanted
Miller multiplication of gate-drain capacitance Cgd of the input transistor and possible
operation at high frequency. A differential amplifier configuration is also used especially in case of required good power supply rejection ratio [44, 6871], however it
gives worse noise performance than single ended stages. There are also some successful
designs using a CMOS inverter for CSA core (NMOS and PMOS transistors with both
gates connected at the input and their drains connected as an output). This solution provides low noise performance, however with limited open-loop gain [72,73].
(a)
(b)
Fig. 3.8. Examples of core amplifiers: a) cascode stage, b) folded cascode stage.
38
The simple cascode is shown in Fig. 3.8(a). The main transistor M1 sometimes
operates at lower supply voltage to save power consumption. Its dimensions are sized
according to input detector capacitance to minimize the noise (see Chapter 3.3.2). The
primary function of M2 is to keep small signal resistance at the drain of M1 low. Therefore, the cascode transistor M2 has sufficiently high transconductance and collects all
signal current from M1. In the simple cascode the same current flows through M3 and
M1 transistors, which makes it difficult to obtain simultaneously high transconductance
gm1 of input transistor M1 and high output resistance rds3 of transistor M3 at the same
time. An additional current source connected like transistor M4, can help in this case
[61, 74]. The M4 which sinks the significant part of current from transistor M1 and allows obtaining high gm1/gds3 ratio and high gain in low frequency region. The output
source follower M5M6 works as an output buffer.
For a connection of DC feedback loop and for an operation of the input transistor
with lower supply voltage, the folded cascode configuration (shown in Fig. 3.8(b)) is
more convenient. To obtain higher output resistance of the folded cascode stage a current cascode source is often used, instead of a simple current mirror M4.
The input transistor of the cascode stage can be NMOS or PMOS and the choice
of the transistor type depends on:
noise performance of both types of transistor in the selected technology,
sensitivity of a given transistor type to a substrate noise,
other aspects, for example, quality of NMOS or PMOS current sources in case of using enclosed gate transistor layout, etc.
Taking into account the folded cascode only i.e. the transistors M1M4 (without
output source follower M5-M6 and neglecting the bulk effect of M2 gmb2 = 0) the low
frequency voltage gain can be written as
vX
g m1 ( g m 2 + g ds 2 )
=
vin
g ds 2 ( g ds1 + g ds 4 ) + g ds 3 ( g m 2 + g d 1 + g ds 2 + g ds 4 )
(3.27)
where gm1 gm4 are transconductances of transistors M1M4 and gds1 gds4 are their output conductances. Assuming that gm2 >> gds1, gds2, gds4 and gds3 gds2 , the above equation can be rewritten as
vout
g
m1
vin
g ds 3
(3.28)
The dominant pole of the folded cascode can be expressed as
0 =
1
C X RX
(3.29)
39
where the total capacitance seen from the node X equals to CX. RX is given as
RX rds 3 || {(rds1 || rds 4 ) + [g m 2 (rds1 || rds 4 ) + 1]rds 2 }
(3.30)
The simplified noise scheme of the folded cascode is shown in Fig. 3.9. The noise
calculated to the cascode input is given as
dvn2 dvn21 (g ds1 + g ds 4 ) dvn22 g m2 3 dvn23 g m2 4 dvn24

=
+
+ 2
+ 2
df
df
g m2 1
df
g m1 df
g m1 df
2
(3.31)
where gds1 =1/rds1 and gds4=1/rds4. In a good design the dominant part of the noise comes
from the main transistor M1, because gm1 is high. However, special attention should be
paid to current source M4 and its reference (not shown in Fig. 3.8(b)). The problem is
that drain currents of transistors M1 and M4 (for cascode design used in CSA application) are nearly equal and to reduce the last term in eq. (3.31), a designer should keep
the transconducance gm4 of current source M4 as small as possible (i.e. using transistor
M4 with relatively long channel L4).
Fig. 3.9. Simplified noise scheme of a folded cascode stage.
40
3.2.4. Feedback configuration

After integration of a current pulse in the CSA, the feedback capacitor CF should
be discharged by the reset block (Fig. 3.5) during a short period of time to prevent saturation of the amplifier [75]. There are two basic techniques implemented for discharging
the feedback capacitance: switch reset and continuous discharge.
(a)
(b)
(c)
(e)
(d)
(f)
Fig. 3.10. Most frequently used reset systems in CSA feedback - see description in text below.
A switch reset technique is shown schematically in Fig. 3.10(a) [76, 77].

A switching circuit periodically resets the feedback capacitor. The trigger signal for
discharging the capacitors can be provided by the central clock of an experiment or generate individually in each channel. In case of X-ray measurements the signals appear
randomly in time and independently in each channel. After receiving a signal from the
detector electrode, the circuit has to generate a trigger signal to discharge the capacitor.
In order to generate such a trigger signal one needs to implement a threshold discriminator in every channel. One can also apply a reset signal to all channels synchronously,
after a certain period of time, having in mind the maximum rate of input pulses and
41
a saturation limit of the CSA, however such a solution results in additional deadtime of
the whole system. The disadvantages of this solution are sampled noise and a possible
problem with charge injection from switch control voltage.
Continuous discharging can be completed either by a resistor parallel to the capacitor or by a controlled current source (see Fig. 3.10(b)(f)). In either case, the discharging component contributes to the parallel noise at the CSA input. In order to limit
this noise source, one should use a large value resistor or a low discharging current.
Using a physical resistor (Fig. 3.10(b)) seems to be a simple solution, however the resistance should be in the range from hundreds of k to a few G (resistor value depends
on noise requirement of an experiment and a peaking time of the shaper). It is difficult
to obtain large value resistance in a monolithic process with a low parasitic capacitance.
Instead of a simple resistor, many designers use a feedback MOS transistor working in
triode or saturation region [57, 78, 79]. This is a compact solution with the possibility to
control feedback resistance, however nonlinear effects must be taken into account.
More complex feedback solutions are shown in Fig. 3.10(d)(f):
the configuration shown in Fig. 3.10(d) uses a current conveyor feedback [80, 81]. In
response to a signal at CSA output a reference current is produced in a low value resistor
R. This reference current is significantly reduced in the network based on current mirror
and discharges the feedback capacitor,
the technique shown in Fig. 3.10(e) is also based on a current mirror and uses a current source [82, 83]. With no activity, the feedback transistor M2 stays in the linear region. When the signal appears, the M2 enters the saturation region and the copy of bias
current Ibias discharges the capacitor,
discharge system shown in Fig. 3.10(f) uses a differential stage. The baseline recovery after signal integration is achieved by the low frequency feedback loop that sets the
output voltage of the CSA to the reference voltage VREF [84]. Proper circuit compensation is an important issue in this case. The effective feedback resistance is equal to
Rf = 2/gm1. Other solutions using a differential stage are also possible [58, 85], but without the mentioned above low frequency feedback.
There are also two aspects which should be taken into account while choosing one
of the above options as reset system in given applications, namely:
for a DC coupled detector leakage current should be automatically accommodated by
the CSA - the good candidates are e.g. the solutions in Fig. 3.10(c) (especially with the
feedback transistor working in saturation region) and in Fig. 3.10(f),
the long decay time constant of the preamplifier output signal, which produces the
limitations of the pulse rate due to the pulse pile-ups. The implementation of the PoleZero Cancellation (PZC) circuit can significantly help in this case (see Chapter 3.4.2)
and adding of a PZC circuit is relatively easy in the cases shown in Fig. 3.10(b) and
3.10(c).
42
3.2.5. Test injection circuit

As discussed before, the detector can be considered as a source of a charge signal.
Thus, for measuring analog parameters one has to inject some charge to the CSA input.
It is important to verify the correct operation of an integrated circuit on the wafer level
or later, when the integrated circuit is mounted in the module and the detector has still
not been connected. This is typically done by applying a voltage step Vtest through
a small test capacitor Ctest at the input of the CSA as shown in Fig. 3.11.
Fig. 3.11. Small capacitor Ctest at CSA input can work as charge injector.
The injected charge is equal to
Qtest = Vtest
1+
Cdet
Ctest
Vtest Ctest
Ctest
+ (KV + 1)CF
(3.32)
Since in practice Ctest << Cdet << (KV+1)CF the injected charge Qtest is totally fed
into the CSA. The voltage step Vtest can be applied externally or internally. The possible options of internal implementation of the chopper circuits are shown in
Fig. 3.12(a)(b).
In the first option a step signal is produced on resistor R in response to STROBE
signal. The step value is controlled by changing the value of a current source in the
differential amplifier. In the second option the STROBE_P and STROBE_N signals
switch the test capacitor Ctest between two lines CAL_P and CAL_N with different DC
potentials. In both options it is easy to generate square wave signals, which means that
for the rising edge of the test pulse the charge is injected to the CSA and for the falling
edge of the test pulse it is extracted. In most cases it is enough to test a basic
functionality of the front-end electronics. However, in other cases it is insufficient, for
instance, for checking high rate performance of the front-end electronics. The
43
application of voltage step function seems more appropriate in this case. Generating
a voltage step function inside the integrated circuit is difficult, but it can be applied
using an external arbitrary waveform generator. Another option is to feed a known small
current Iinj to the preamplifier input during a known time interval Tinj. The injection
charge is equal to Qtest = IinjTinj.
(a)
(b)
Fig. 3.12. Possible realization of the test injection circuits: a) generation of voltage steps on resistor R [86],
b) switching between two lines with different DC potentials [87].
3.3. SHAPER
The shaper stage after the CSA is added to perform the following tasks:
to filter the CSA output signal in order to improve the signal to noise ratio in the system,
to add more gain in the signal processing chain,
to shorten the pulse duration and to reduce the possibility of pile-up pulses.
The choice of the filter type, order and its time constants strongly depends on
specified energy resolution of the readout system and its high rate operation requirements [2, 32, 8892]. There is a wide range of shapers built in hybrid technologies and
which use components of the shelf. However, in case of a multichannel ICs there are
additional very strong requirements on a low power budget and a small area occupied by
the single channel, and a practical realization of all filter types in the IC technology is
limited. For the purpose of this book three types of filters often used in the multichannel
ICs are described:
44
unipolar semi-Gaussian pulse shaper CR-(RC)n,

bipolar semi-Gaussian shaper with two high-pass sections (differentiators) and n integrators of type CR2-(RC)n,
nearly true Gaussian shaper obtained using Ohkawa synthesis method [93].
At first, the transient response of these filters to a voltage step (obtained at a CSA
output) is described. In Chapter 3.3.2 the improvement of the signal to noise ratio in the
detector system by using the filters is analyzed in detail.
Definitions used in the pulse shaping time are as follows (see Fig. 3.13) [94, 95]:
tp: pulse peaking time, measured from 1% of the peak height to the center of the peak,
tp1: bipolar pulse peaking time, measured from 1% of the peak height to the center of
its peak,
tp2: bipolar pulse peaking time, measured from 1% of the peak height of the primary
lobe to the peak of the undershoot,
txo: crossover time of a bipolar pulse,
tm: width of the pulse at the fraction m of its peak height, where m is specified as 0.1,
0.01 etc.
(b)
(a)
Fig. 3.13. Timing definition in pulse shaping: a) unipolar pulse, b) bipolar pulse [94, 95].
3.3.1. Signal shaping

Unipolar semi-Gaussian pulse shaper. A simple semi-Gaussian pulse shaper of
type CR-(RC)n, which consists of one CR differentiator and n integrators (Fig. 3.14),
becomes one of the most popular in the multichannel ICs.
45
Fig.3.14. Semi-Gaussian pulse shaper of type CR-(RC)n.
For the CR-(RC)n filter with the same integrator and differentiator time constants
i = d = the transfer function is given by [92, 96]
s 1
H ( s) =
1 + s 1 + s
(3.33)
Assuming an ideal unity voltage step at the shaper input and taking the transfer
function of the filter given by (3.33), one obtains the shaper output signal in the time
domain as
n
1t
t
vout (t ) = exp
n!

(3.34)
The peak amplitude of the signal is
vmax =
nn
n!e n
(3.35)
with the peaking time tp = n . The family of shaper output pulses for a given time constant is shown in Fig. 3.15(a). Increasing the filter order results in decreasing the signal amplitude, but makes the pulse more symmetrical. Higher filter order is more suitable for high rate application, however to obtain the same peaking time for the higher
shaper order, one should shorten the time constant of the filters. The family of the pulses
with the normalized amplitude and the time scale, but different orders, is shown in
Fig. 3.15(b). For higher order filters the shaper output pulse returns to the baseline
faster, and this directly influences the high rate operation and reduces the probability of
pile-up pulses.
46
(a)
(b)
Fig. 3.15. Examples of shaper output for different CR-(RC) filter orders with: a) the same time constant ,
b) normalized output .
n
The pulse width t0.01 (calculated according the criteria 1% to 1% of the maximum
pulse amplitude) for different filter order as the ratio to peaking time is summarized in
Table 3.1.
Table 3.1. Pulse width for different filter CR-(RC)n.
Filter order n
t0.01/tp
1
7.66
2
5.04
3
4.17
5
3.46
7
3.14
Higher filter order requires more power and occupies more silicon area. For that
reason many multichannel readout ICs use simple CR-(RC)2 shaper, while the readout
electronics for pixel detector has a very simple shaper stage or has nearly no separate
shaper stage at all.
Bipolar semi-Gaussian pulse shaper. The semi-Gaussian pulse shaper of type
(CR) -(RC)n, consists of two CR differentiators and n integrators (see Fig. 3.16). For the
same integrator and differentiator time constants i = d = the transfer function is given
by [5, 92]
2
s 1
H ( s) =

1 + s 1 + s
Fig. 3.16. Semi-Gaussian pulse shaper of (CR)2-(RC)n type.
(3.36)
47
Assuming an ideal unity voltage step at the shaper input and taking into account
the above transfer function of the filter, one obtains the shaper output signal in the time
domain as
n
vout (t ) =
(n + 1) t t
t
exp
(n + 1)!

(3.37)
This pulse has a negative undershoot and crosses zero at tox = (n+1), and the maximum
and minimum pulse values are obtained at time coordinates
(
= (n + 1 +
)
n + 1)
tmax = n + 1 n + 1
(3.38)
tmin
(3.39)
The family of bipolar pulses at shaper output for a given time constant is shown
in Fig. 3.17(a). The family of the pulses with the normalized amplitude and the time
scale, but different filter orders, is shown in Fig. 3.17(b).
(b)
(a)
Fig. 3.17. Examples of shaper output for different (CR)2-(RC)n filter orders with: a) the same time constant
, b) normalized output.
The pulse width t0.01 for different filter order as the ratio to tp1 is summarized in
Table 3.2. The ratio of amplitude overshoot to pulse amplitude is also given in the table
below.
Table 3.2. Pulse width for different (CR)2-(RC)n filter.
Filter order n
t0.01/tp1
|vmin/vmax|
1
16.6
0.344
2
9.85
0.436
3
7.67
0.495
5
5.96
0.569
7
5.22
0.616
48
The bipolar shaping results in a longer pulse width than unipolar shaping. As
shown later, the bipolar shaper offers also a worse signal to noise ratio. However, the
bipolar shaping has two advantages:
zero crossing time txo does not depend on pulse amplitude and this feature of bipolar
shaper is used in timing measurements,
it eliminates the problem of a baseline shift (for high rate of input pulses) in the system with AC coupling [97].
Nearly true Gaussian filter obtained using Ohkawa synthesis method [93]. In
order to minimize the effects of pile-up pulses, the minimum pulse width t0.01 is preferable, as for example in the case of Gaussian shaped pulses. Using CR-(RC)n configuration to obtain the true Gaussian pulse shape, a CR differentiator and the infinitely large
number of RC integrators are necessary. Some systematic studies can be found in literature (in time or frequency domain) to obtain the optimal pulse shaping network, e.g.
[98, 99]. However, some results of these studies are difficult to implement in integrated
circuits (i.e. filters contain inductors).
An interesting approach for the Gaussian filter which can be applicable in the IC
can be found in [93]. A nearly true Gaussian filter with a limited number of stages can
be realized using active filters with resistors and capacitors. The filters have complex
poles which are obtained on the basis of the frequency domain analysis. Let us analyze
shortly the idea of this kind of filter according to [93].
The pulse after charge sensitive amplifier is fed to the shaper which is assumed to
be composed of an ideal differentiator, followed by the network whose pulse response is
the Gaussian waveform
t2
(3.40)
vout (t ) = a0 exp
2
2
where a0 is a constant and is the rms deviation of the normal distribution. The above
Gaussian waveform has a peak a0 at t = 0. In the frequency domain the above equation
can be written as
2 2
F ( ) = a0 2 exp
2
(3.41)
Let us assume the following transfer function of the Gaussian filter
H (s) =
H0
Q( s)
(3.42)
where s = j, H0 is a constant and Q(s) is a Hurwitz polynomial (polynomial whose

coefficients are positive real numbers and whose zeros are located in the left half-plane
49
of the complex plane). As it can be easily shown [93] there is the following relation
between the transfer function and amplitude characteristics
H ( j ) H ( j ) = [F ( )]
(3.43)
Taking into account eq. (3.41) and (3.42), the above relation can be rewritten as
1
Q( s )Q( s ) =
2
H0
a0
exp( 2 s 2 )
(3.44)
By proper normalization the above equation can be transformed into
Q( p )Q( p ) = e p
(3.45)
and p = s. The above exponential function can be approximated by the finite terms of
Taylor series as
Q( p)Q( p ) = 1 p 2 +
p4 p6
p 2 nG
+ ... + (1) nG
2! 3!
nG !
(3.46)
For nG = 1 the above equation is
Q( p )Q( p) = 1 p 2
(3.47)
and the Hurwitz polynomial is
Q( p) = 1 + p
(3.48)
and the network function has the real pole at -1 on the p plane.
For nG = 2 the equation (3.46) gives
p4
Q( p )Q( p) = 1 p +
2!
2
(3.49)
In this case the polynomial Q(p) is equal to
Q( p) =
1
2 + (2 + 2 2 ) p + p 2
(3.50)
50
and the network function has the conjugate pole pair at
p1 =
(2 + 2 2 )
1
2
)]
2 1
(3.51)
For higher order nG = 37 the pole constellation can be obtained by numerical

analysis. The pole constellation plotted on the complex plane p is shown in Fig. 3.18.
Poles are also listed in Table 3.3, where the real pole is p0 = A0 , Ai and the complex
pole pairs are pi = Ai Wi .
Fig.3.18. Pole constellation of the Gaussian filter [93].
Table 3.3. Pole locations of the Gaussian filters (reprinted from [93] 1997, with permission from
Elsevier, http://www.sciencedirect.com/science/journal/ ).
nG = 3
nG = 4
nG = 5
nG = 6
1.4766878
nG = 7
A0
1.2633573
1.6610245
A1
1.1490948
1.3553576
1.4166647
1.5601279
1.6229725
W1
0.7864188
0.3277948
0.5978596
0.2686793
0.5007975
A2
1.1810803
1.2036832
1.4613750
1.4949993
W2
1.0603749
1.2994843
0.8329565
1.0454546
A3
1.2207388
1.2344141
W3
1.5145343
1.7113028
With the pole locations, the transfer function of the H(s) filter for the odd number
nG of poles can be expressed as
A0 (Ai2 + Wi 2 )
51
H (s) =
i =1
k
(s + A0 ) [(s + Ai )
+ Wi
i =1
(3.52)
For the even number nG of poles the transfer function is
(A
k
H (s) =
2
i
+ Wi 2 )
i =1
[(s + A )
k
i =1
+ Wi
(3.53)
The constants in the numerators of equations (3.52) and (3.53) are added to normalize
the H(s) value to 1 when s = 0.
Ohkawa et al. [93] use of an equal-area time constant to CR-RC filter in order to
compare different waveforms. The area of the pulse after CR-RC filter with peak height
1 is given by
t
t
dt = eC x Rx
exp
SCR = e
CR
C x Rx
0 x x
(3.54)
The area of the Gaussian waveform with peak height 1 is given by
SG =
t2
exp
2 2 dt = 2
(3.55)
Assuming the equal areas SCR = SG the is given by
e
C x Rx = 0 x
2
(3.56)
where x = CxRx is time constant of the CR-RC filter and 0 = e/(2) = 1.0844 is so
called an equal-area time constant.
52
The pulse response approaches the Gaussian waveform when the filter order increases (see Fig. 3.19), so for the pulse shaping the preferable filter order is nG 5.
Fig. 3.19. Pulse responses for a different filter order as a function of time normalized with 0 (reprinted
from [93] 1997, with permission from Elsevier, http://www.sciencedirect.com/science/journal/ ).
Let us follow now the procedure of Gaussian active filter design. The common
practice in nuclear amplifier to obtain a differentiator is to use a simple CR circuit with
zero at origin and a real pole which determines the time constant. For this type of
a shaper, the pole constellations with a real pole such as nG = 5 or nG = 7 are very convenient (see Table 3.3). The relations between the time constant C0R0 of the differentiator and the real pole from Table 3.3 are as follows
C0 R0 = 0 x A0
(3.57)
The next step is to build stages with complex poles. There are different types of
filters with complex pole pairs. Some examples together with the schemes (see
Fig. 3.20, Fig. 3.21 and Fig. 3.22.) and equations for transfer functions and poles are
presented below.
53
Fig. 3.20. Active filter with multiple negative feedbacks.
The transfer function and pole positions for an active filter with multiple negative
feedback are
H (s) =
1
R1
R3 1 + sC1R1 + s 2C1R1C2 R2
4C R
1
1 j 2 2 1
s1 =

C1R1
2C2 R2
(3.58)
(3.59)
Fig. 3.21. Active filter with bridged-T feedback.
The transfer function and pole positions for an active filter with bridged-T feedback are
54
R1 R2
+1
R1 + R2
R1 + R2
H (s) =
R3 1 + sC1 (R1 + R2 ) + s 2C1 R1C2 R2
(3.60)
4C2 R1 R2
R + R2
1 j
1
s1 = 1
2
2C2 R1 R2
C1 (R1 + R2 )
(3.61)
sC2
Fig. 3.22. Active filter with positive feedback.
The transfer function and pole positions for an active filter with positive feedback
are
H (s) =
1 + sC2 (R1 + R2 ) + s 2C1 R1C2 R2
4C1R1R2
R + R2
1 j
s1 = 1
1
2C1R1R2
C2 (R1 + R2 )
(3.62)
(3.63)
55
Let us consider an active filter with multiple negative feedbacks (Fig. 3.20) to
build the Gaussian filter. The real and imaginary parts of the complex poles are in the
following relations to the coefficient in Table 3.3
Ai =
0 x
(3.64)
2C2 R2

Wi = 0 x
2C2 R2
4C2 R2
C1 R1
(3.65)
From the above equations C2R2 and C1R1 can be calculated
C2 R2 =
C1R1 =
0 x
(3.66)
2 Ai
4C2 R2
2
1 + (Wi Ai )
(3.67)
The example of the Gaussian filter for nG = 7 realized according to the procedure
described is shown in Fig. 3.23 and the exemplary values of resistors and capacitors are
shown in Table 3.4. For x = 100 ns the peaking time of this Gaussian filter is about
tp = 330 ns.
Fig. 3.23. Gaussian filter amplifier for nG = 7 [93].
56
Table 3.5. Exemplary values of calculated resistors and capacitors of the Gaussian filter for nG = 7.
Pole
n=7
C0R0
from eq.
(3.57)
C2R2
from eq.
(3.66)
C1R1
from eq.
(3.67)
Examples of calculated Ci and

Ri
for x = 100 ns
A0
1.6610245
0.652850x
C0 = 13.057 pF , R0 = 5 k
A1
1.6229725
0.334078x
C2C = 8.148 pF , R2C = 4.1 k
W1
0.5007975
1.220138x
C1C = 8.134 pF , R1C = 15 k
A2
1.4949993
0.362676x
C2B = 6.476 pF , R2B = 5.6 k
W2
1.0454546
0.974266x
C1B = 6.495 pF , R1B = 15 k
A3
1.2344141
0.439237x
C2A = 3.993 pF , R2A = 11 k
W3
1.7113028
0.601302x
C1A = 4.009 pF , R1A = 15 k
R1C/R3C, R1B/R3B, R1A/R3A set the filter gain, for example, these resistors can be R3C = R3B = R3A = 4.7 k.
The pulse width t0.01 for the Gaussian filter is significantly smaller than in case of
CR-(RC)n filter, so they are better for applications working with high rate of input pulses
(see Table 3.6).
Table 3.6. Pulse width for the Gaussian filter.
Filter order nG
t0.01/tp
5
2.84
7
2.55
3.3.2. Noise analysis

The main noise contribution to the detector readout system comes from the detector itself and from components of the charge sensitive amplifier. The simplified noise
model of a detector and the CSA is shown in Fig. 3.24. The noise performance of this
system can be analyzed using the equivalent input current and voltage noise sources.
Fig. 3.24. Equivalent noise scheme of the CSA.
57
A current noise is associated with the detector leakage current Idet, the detector
bias resistance Rbias (in case of an AC coupling detector only) and the effective feedback
resistance Rf in the CSA, so the power spectral density is given by
din2
df
= 2qI det +
4kT 4kT
+
Rbias
Rf
(3.68)
and it can be rewritten in a shorter form as
din2
df
=a
(3.69)
In the well-designed CSA the voltage noise is dominated by an input transistor.

For CMOS technology, the voltage noise of the input MOS transistor can be expressed
as [96]
dvn2
df
= 4kT
n
g m1
Kf 1 1
Cox2 WL f
(3.70)
where k is the Boltzman constant, T is temperature, gm is transistor transconductance,

n ranges from 1/2 (weak inversion) to 2/3 (strong inversion), Cox is the gate oxide capacitance per area, W and L are the width and length of the input transistor, Kf is the
flicker noise coefficient and f is frequency. In the above formula short channel effects
are neglected, because we assume that the charge amplifier in multichannel systems is
designed to operate with low current density in the input transistor and at low drainsource voltage. The equation (3.70) can be shortened to
dvn2
df
=b+
AF
f
(3.71)
where constants b and AF are responsible for the thermal and flicker noise respectively.
If the current and voltage noise sources are uncorrelated, they can be calculated to
the CSA output independently. The parallel current noise is multiplied by a square of
module of CSA transfer function (see eq. (3.5)) and this gives
58
2
dvCSAout
_ parrallel
df
a
a
=
2
CF (2fCF )2
(3.72)
To transfer the amplifier voltage noise to the CSA output let us look at first at the
relationship between CSA input voltage and CSA output voltage (for K0 >> 1), which
are given by simple impedance divider
vin
1 sCT
CF
=
=
vout 1 sCT + 1 sCF CT + CF
(3.73)
The gate itself of input transistor works as virtual ground and therefore the series
voltage noise gives at the CSA output
2
dvCSAout
_ series
df
A C + CF
= b + F T
f CF
(3.74)
The total noise at the CSA output is the sum of eq. (3.72) and (3.73)
2
dvCSAout
df
a
A C + CF
=
+ b + F T
2
(2fCF ) f CF
(3.75)
The noise at CSA output is filtered by the following shaper stage. For the gain of
the CSA which is high enough and careful design of the shaper stage, the noise of the
shaper stage can be negligible.
Let us consider first a simple RC-CR filter (with the identical time constants
i = d = ) where the peaking time is equal to filter time constant tp = . The module of
its transfer function is given by
H (2f ) =
2ft p
1 + (2ft p )
(3.76)
59
The rms value of noise at the shaper output with the above assumption can be calculated as
a
A C + CF
=
+ b + F T
2
f CF
0
(2fCF )
2
dvSHout
2ft p
df
(
)
1 + 2ft p
(3.77)
The solution of the above integral is given by the following equations [37]
2
=
dvSHout
1 at p
AF
2 b
(
)
+
+
+
C
C
F
T
8t
2
CF2 8
p
(3.78)
In the front-end electronics the noise from the shaper output is recalculated to the
CSA input. Because the input signal is a charge pulse, the noise calculated to the CSA
input is expressed as Equivalent Noise Charge (ENC). The ENC is equal to the detector
signal that yields the signal-to-noise ratio of 1. The ENC is expressed in electrons or in
Coulombs, or sometimes in equivalent energy (eV) deposited in the detector. For this
calculation the gain of the chain CSAshaper is necessary. At the output of the CSA the
signal step is equal to Qin/CF and at the shaper output the peak amplitude is proportional
to the charge Qin generated in the detector. In practice, the ENC of the detector system is
calculated as the ratio of the total integrated rms noise at the shaper output to the peak
amplitude (at the shaper output) for an input charge Qin of 1 electron (1.60210-19 C)
ENC =
2
dvSHout
vSH max (Qin = 1 electron)
(3.79)
In the case of simple RC-CR filter analyzed above, the output signal in the time
domain (according the eq. (3.34) (3.35)) is given as
vout = vSH max
t
t
exp
t
tp
p
(3.80)
with peak amplitude
vSH max (Qin = 1 electron) =
1
e CF
1
(3.81)
60
Using the equations (3.78), (3.79) and (3.81) results, the ENC is given as
at
A
2 b
ENC 2 = e 2 p + (CF + CT )
+ F
8t
2
8
p
(3.82)
To analyze the obtained results let us split the above equations to three components: ENCi due to current parallel noise component (eq. (3.68) and (3.69)), ENCw due
to voltage thermal noise component (the first term in eq. (3.70) and (3.71)) and ENCf
due to voltage flicker noise component (the second term in eq. (3.70) and (3.71))
ENC 2 = ENCi2 + ENCw2 + ENC 2f
(3.83)
ENCi2 = 0.924t p a
(3.84)
where
ENC
2
w
2
(
CF + CT )
= 0.924
b
tp
ENC 2f = 3.695(CF + CT ) AF
2
(3.85)
(3.86)
Three immediate observations based on formulae (3.84)(3.86) are important for

the optimization of the front-end circuit (see also Fig. 3.25):
contribution of the input current noise is independent of the input capacitance and
proportional to the square root of the peaking time,
contribution of the input voltage white noise is proportional to the total input capacitance and inversely proportional to the square root of the peaking time,
contribution of the input voltage flicker noise is proportional to the total input capacitance and independent of the peaking time.
One can now optimize the front-end system taking into account various requirements and constraints implied by a particular application. There are two parameters determined by the detector geometry: detector capacitance and detector leakage current.
Both parameters are proportional to the strip/pixel area and depend on the detector
fragmentation which directly influences position sensitive resolution of the system. Ad-
61
ditionally, the detector leakage current is a strong function of temperature, so lowering

the temperature is the way to reduce the leakage current and the associated shot noise.
From formulae (3.68)(3.84) it is obvious that the values of detector bias resistor Rbias
and feedback resistor Rf should be relatively high (in the range of tens or hundreds of
M depending on tp) in order not to contribute to the noise. In case of Rf, the situation is
more complex, because the high value of this resistor limits the high rate performance of
the signal processing chain.
Fig. 3.25. Contributions of different noise components to the total ENC vs. peaking time.
The next parameter which should be considered as an input to formulae

(3.82)(3.86) is peaking time tp. When there is no constraint on the peaking time, as for
any low rate experiments, one can find the optimal peaking time (which gives the minimum of ENC) for other given parameters, voltage and current noise spectral densities
and detector capacitance [100102]. However, in many applications high rate capability
is a serious requirement which has to be taken into account as a limitation for the maximum permitted peaking time.
A similar analysis like one for the CR-RC filter can be performed for any type of
a filter. Generally, the equations (3.84)(3.86) can be rewritten as
ENCi2 = Fi t p a
ENCw2 = Fv
(3.87)
(CF + CT )2 b
tp
ENC 2f = Fvf (CF + CT ) AF

2
(3.88)
(3.89)
62
where constants Fi , Fv , Fvf for semi-Gaussian pulse shapers analyzed earlier are summarized in Table 3.7.
Table. 3.7. Noise coefficients for a different filter type.
Filter type
CR-RC
CR-(RC)2
CR-(RC)3
CR-(RC)5
CR-(RC)7
(CR)2-RC
(CR)2-(RC)2
(CR)2-(RC)3
(CR)2-(RC)5
(CR)2-(RC)7
Fi
0.92
0.64
0.52
0.40
0.34
1.00
0.72
0.60
0.48
0.41
Fv
0.92
0.85
0.93
1.11
1.27
1.03
1.16
1.44
2.00
2.52
Fvf
3.70
3.41
3.32
3.25
3.22
4.70
4.89
5.12
5.49
5.75
The following conclusions can be drawn from the table above:

in the case of CR-(RC)n the higher filter orders (more suitable for high rate applications) have better noise performance, however these filters require more silicon area and
result in higher power consumption,
CR-(RC)n filters have better noise coefficients than (CR)2-(RC)n filters, however the
bipolar filters has unique advantages mentioned earlier in Chapter 3.3.1.
It is worth mentioning that there is a theory of the optimum filter for a given input
signal spectra with white noise [103], however, this filter is not physically realizable.
3.4. NOISE OPTIMIZATION OF CSA INPUT

TRANSISTOR
The dimensions of the MOS transistor determine both transistor transconductance
and transistor capacitance. Let us assume that the input transistor M1 has dimensions
W1/L1, transconductance gm1 and the gate capacitance C1 and that the capacitance is approximated to CT Cdet +C1 (Cpar is negligible). Table 3.8 summarizes some of the results presented in the previous chapter concerning the voltage noise produced by the
input MOS transistor.
On one hand, the increase of W1/L1 ratio increases the transistor transconductance
gm1 (and reductes transistor thermal noise) and the increase of the transistor area W1L1
reduces 1/f noise. On the other hand, the capacitance of the input transistor C1 should be
small (W1 and L1 should be small) in order to reduce the Power Spectral Density (PSD)
63
of noise at CSA output (and also ENC at CSA input). This means that there is the optimal transistor dimensions for which the PSD of the noise at CSA output and the ENC is
minimal. Let us analyze this problem for the cases when the input transistor operates in
strong, moderate or weak inversion regions.
Noise
PSD of MOS transistor
dvn2
df
=b+
Table 3.8. Summary of voltage noise performance of system CSA-shaper

Thermal noise
1/f noise
b = 4kT
AF
f
PSD at CSA output
g m1
C + C1 + CF
b det
CF
ENC2 for RC-CR filter
0.924
Term to be optimized
for transistor dimensions
AF K f 1 1
= 2
f
Cox WL f
(Cdet + C1 + CF )2 b
tp
AF
f
Cdet + C1 + CF
CF
3.695(Cdet + C1 + C F ) AF
2
(Cdet + C1 + CF )2
(Cdet + C1 + CF )2
g m1
W1L1
3.4.1. Strong inversion region

Thermal noise component. Let us assume that a transistor operates in the strong
inversion region. Its transconductance is given as
g m1 = 2 Cox
W1
I DS 1
L1
(3.90)
The transistor input C1 capacitance may be calculated as
2
C1 = CoxW1L1 + 2CovW1
3
(3.91)
where Cov is the overlap gate-diffusion capacitance per channel width unit (Cov is assumed to be the same for drain and source). From the second column of Table 3.8 one
concludes that the ratio (Cdet+C1+CF)2/gm1 should be minimized and two observations are
obvious:
the drain current of the input transistor should be kept as high as possible taking into
account the power limit per single channel in the multichannel system,
64
the minimum transistor gate length L1 = Lmin is desired. However, for some technologies and bias conditions, the choice of minimum transistor length results in noise increase due to short channel effect (see discussion in the Chapter 4.1.3). In such cases the
noise measurements of the MOS transistors in a given technology (with the dimensions
and bias conditions similar to the application in the CSA) are necessary [104106] and
the L1 has to be chosen as small as possible to make the excessive noise connected with
the short channel effects negligible.
Calculating from equation (3.91) the transistor width is
W1 =
C1
2
3 C ox L1 + 2C ov
(3.92)
and assuming that L1 = Lmin , the transconductance can be rewritten as
g m1 = 2 Cox
I DS 1
C1
2
Lmin 3 Cox Lmin + 2Cov
(3.93)
The ENC component from voltage noise thermal is proportional to
ENC
2
w
2
(
Cdet + C1 + CF )
~
C1
(3.94)
The minimum value of the ENCw is calculated by solving the equation of the derivative
of (3.94) with respect to C1. It results in
C1 =
Cdet + C F
3
(3.95)
The optimal WSIopt in strong inversion from (3.92) and (3.94) is given as
WSIopt =
Cdet + CF
2Cox Lmin + 6Cov
(3.96)
65
Flicker noise. Calculating the flicker noise factor AF as a function of detector capacitance and assuming L1 = Lmin , one obtains
AF =
Kf
2
ox
C Lmin
2
3
Cox L1 + 2Cov
C1
(3.97)
The equivalent noise charge of voltage noise flicker component is proportional to
ENC 2f ~
(Cdet + C1 + CF )2
C1
(3.98)
The minimum value of the ENCf is calculated by solving the equation of the derivative of (3.98) with respect to C1. It results in
C1 = Cdet + CF
(3.99)
The equation for the optimum input transistor capacitance is different for thermal
and flicker noise. For the CSA analyzed above, with the input MOS transistor operating
in strong inversion, the optimum value of input transistor capacitance is in the range of
(Cdet+CF)/3 to (Cdet+CF) - see Fig. 3.26. Because for short peaking time the voltage
thermal noise dominates over the flicker noise, the optimum transistor capacitance is
closer to eq. (3.95), while for the longer peaking time the formula (3.99) is more appropriate [97].
Fig. 3.26. ENC as a function of C1/(Cdet+CF) ratio. Simulation performed for NMOS transistor with
Lmin = 0.35 m and IDS1= 1 mA. Other parameters: Cdet = 2 pF, CF = 0.1 pF, CR-(RC)2 shaper with
tp = 300 ns.
Another aspect is the choice between NMOS or PMOS transistor as an input device. Usually, a PMOS transistor with smaller Kf decreases flicker noise, however its
transconductance in strong inversion region is smaller than an NMOS transistor (with
66
the same W/L ) and an NMOS transistor will have smaller thermal noise. So, the choice
between input transistor types is not so obvious, and depends on: technology, peaking
time, current density in the input transistor and methodology of protection of an input
device from substrate noise (see Chapter 4.2) [104109].
3.4.2. Moderate or weak inversion regions

For a CSA followed by a fast shaper (with short peaking time tp) the ENC is usually dominated by the voltage noise of the input transistor and is given as (see formulae
(3.70), (3.71), (3.88) and (3.89))
ENC Cin
K
Fv
4kT n + Fvf 2 f
tp
gm
CoxWL
(3.100)
For a really short peaking time, if
tp <
Fv
C 2 WL
4kT n ox
Fvf
gm
Kf
(3.101)
the contribution of 1/f noise is always much smaller than the channel thermal noise
which dominates [109]. The formula (3.96) was derived with the assumption that the
input transistor works in strong inversion and then the appropriate equations for gm1 and
C1 were used (eq. (3.90) and (3.91)). However, in a modern multichannel CSA it is frequent that the input transistor operates in moderate or weak inversion regions, where the
above mentioned formulae are not valid.
An adequate variable used to determine the actual inversion level of a MOS transistor operating in saturation is its normalized forward current if [110]
if =
I DS
2ns Cox (W / L)T2
(3.102)
where IDS is the drain current, ns is the subthreshold slope factor (usually in the range
1.1 to 1.3), is the carrier mobility, T is the thermal voltage.
67
Fig. 3.27. Limits of a moderate inversion region calculated from eq. (3.102) at if = 0.1 and at if =10. The
calculations were performed for three CMOS technology generations 0.13 m, 0.35 m and 0.8 m,
assuming in each case the minimum transistor length available [109] 2007, IEEE.
It is commonly assumed that weak inversion takes place for if < 0.1, while strong
inversion region is for if > 10 [111]. Therefore, an MOS transistor has a two-decade
current transition region called moderate inversion region bounded by if = 0.1 and
if = 10. In a modern multichannel CSA the input transistor often operates in this region
(see Fig. 3.27). The if current is relatively low due to the following factors:
high density front-end systems are designed for a low-power operation, so the IDS
current is strongly limited,
thermal noise optimization of the CSA input transistor often leads to a high value of
gm and large W/L ratio,
in modern submicron technologies, smaller channel length L and higher capacitance
Cox are available.
Calculation of optimum transistor width using an EKV model. In order to account for the changes of gm, Cg and n when departing from a strong inversion region
the simplified analytical EKV model is used [109, 110, 113]. The EKV model with its
relatively simple formulae is found to be quite successful in a moderate inversion region
[111]. In its simplified version the basic parameters gm, Cgs, Cgb, n of the MOS transistor operating in saturation, may be calculated as shown below. Transconductance is
given by
gm =
where
I DS
f (i f )
nsT
(3.103)
68
f (i f ) =
(3.104)
i f + 0 .5 i f + 1
Total gate capacitance is the sum of gate-source capacitance Cgs, gate-bulk capacitance Cgb and overlap capacitance
C g = C gs + C gb + 2CovW
(3.105)
where
3
1
C gs = CoxW L +
2 i f (i )
f
f
C gb = CoxW L
i f f (i f )
ns 1
1
n s 1 + 1.5i f f (i f )
(3.106)
(3.107)
Gamma factor is given by
n =
1 1 if
+
2 6 if +1
(3.108)
In order to calculate these MOS parameters one needs to have two additional
technological parameters Cov and subthreshold slope factor ns. These parameters can be
extracted from numerical simulations.
Having the analytical expression for gm, C1 and n , the function of the ENC as the
transistor width can be easily plotted as shown in Fig. 3.28. These plots can also be easily obtained with numerical simulations (with the use of the HSPICE or SPECTRE).
From the results in Fig. 3.28 the optimum transistor Wopt width can found.
69
Fig. 3.28. ENC vs. PMOS transistor width for detector capacitance Cdet =2 pF, feedback capacitance CF
= 100 fF and drain current IDS = 500 A. The points denote HSPICE simulations and the lines simplified
EKV model calculations [109] 2007, IEEE.
Fig. 3.29. Optimum PMOS transistor width for 0.35 m process vs. drain current for Cdet = 2 pF and
CF = 100 fF [109] 2007, IEEE.
From the simulations for a given detector capacitance and different drain currents
(see Fig. 3.29) it can be noticed that:
optimum transistor width depends on the drain current. It is not predicted by the
strong inversion formula (3.96),
wide flat ENC range around Wopt exists (marked as error bars - changing the channel
width inside these limits results in the noise increase below 3%). This means that there
is a large margin for the choice of the input transistor width around Wopt, in which the
ENC is practically not affected. It should be pointed out that a similar, very broad minimum for a product called "timing noise factor" (input referred, noise voltage spectral
density multiplied by the total input capacitance) is also reported in [112].
Universal formula for Wopt. As shown in [109], it possible to find a new analytical formula for Wopt, which with the results of eq. (3.94) allows to calculate the optimal
transistor width also for moderate and weak inversion operation of an MOS transistor.
This formula is as follows
70
Wopt = WSIopt
1
W
1 + A SIopt
inoW
(3.109)
where
inoW =
I DS
2n Cox (1 / L)T2
(3.110)
and m = 0.61 and A = 0.25 are the fitting parameters (obtained by checking different
technologies). This formula is valid for input transistor working in weak, moderate and
strong inversion. The comparisons of the results obtained from above formula with numerical simulations (HSPICE - transistor model BSIM3v3) and analytical calculation
using an EKV model are shown in Fig. 3.30.
(a)
(b)
Fig. 3.30. Optimum width of PMOS transistors for two CMOS technologies (minimum transistor length is
used): a) 0.35 m, b) 0.13 m (dotted lines show the limits of moderate inversion region) [109] 2007,
IEEE.
3.5. ASPECTS OF FAST SIGNAL PROCESSING

During the designing stage of low noise readout electronics for high-rate operation, negative effects of pulse pile-up in the signal processing chain should be taken into
account. There are two types of pile-ups
71
on pulse tail - see Fig. 3.31(a),

on pulse undershoot - see Fig. 3.31(b).
The pile-up on pulse tail produces the "positive" base line shift (with the same
sign as a pulse amplitude). This type of pulse pile-ups can take place both at the CSA
and shaper outputs. In case of shaper output the pulse pile-up is reduced by using the
filter of a proper type and order to obtain short peaking time tp and short pulse
width t0.01.
The pile-up on pulse undershoots is mainly observed in AC coupled amplifiers.
The remedy for this effect is to use pole-zero cancellation circuit (see Chapter 3.5.2) and
base line restores (see Chapter 3.5.3).
(b)
(a)
Fig. 3.31. Two types of pulse pile-up: a) on pulse tail at CSA output, b) on pulse undershoot at shaper
output.
3.5.1. Pulse pile-ups at CSA output

Let us consider a simple CSA with a feedback capacitance CF and a parallel feedback resistance Rf to discharge CF capacitor and to avoid amplifier saturation. The CSA
response to a negative -like current pulse carrying charge Qin can be written as
VoutCSA (t)
Qin
exp( t / f )
CF
(3.111)
where f = CF Rf and the negative charge at the input is assumed to simplify further
equations and plots. Noise optimization of the CSA stage together with the feedback
circuit often gives the feedback resistance in hundreds of M range and then the feed-
72
back time constant f is consequently long. The train of input pulses of high average
frequency fin generates a "positive" DC voltage shift VshiftCSA at the CSA output (pile-up
on pulse tail), which can be calculated as [114]
VshiftCSA f in VoutCSA (t)dt
(3.112)
Using the formula (3.111) and assuming that all the input pulses carry the same
charge Qin , the equation (3.112) can be rewritten as
VshiftCSA Qin R f f in
(3.113)
From the above equation it can be seen that the DC voltage shift VshiftCSA is proportional to the charge Qin of the input pulse, the average frequency fin and to the feedback
resistance Rf. A compromise should be found for the Rf value in order to obtain an acceptable VshiftCSA without significant deterioration of circuit noise.
Let us estimate the influence of feedback resistance on the voltage shift at the
CSA output and the noise performance, considering the following example: charge pulses of Qin = 1 fC arrive at the CSA input with the average frequency fin = 2 MHz, while
the CSA has an ideal feedback resistance of Rf = 200 M and a RC-(CR)2 shaper has
a peaking time tp = 100 ns. For these conditions, according to formula (3.113), the DC
voltage shift is VshiftCSA = 400 mV, while the contribution feedback resistance Rf is
ENCi 15 e rms [79].
The baseline shift at CSA output is non-negligible in modern CMOS technologies
which are usually characterized by a low value of power supply voltage. It must also be
taken into account in case of active elements in CSA feedback (see Fig. 3.10), because
this DC voltage shift VshiftCSA can modify the effective feedback resistance.
3.5.2. Pole-zero cancellation circuit

When the feedback capacitor CF is discharged with the effective resistance Rf, the
CSA pulse output decays exponentially with a time constant f = CFRf (see equation
(3.111)). In most cases, the following stage is a semi-Gaussian pulse shaper consisting
of one RC differentiator and n integrators with the same time constant. In most cases
the condition << f is true. If CSA output pulse with a long tail is fed into a popular
RC-(CR)2 filter the answer at the shaper output is
voutSH (s) =
s
1
Qin
1
1
Cf s +
s+
CF R f
CR
sCR + 1
73
(3.114)
In the time domain the above pulse has a long "negative" undershoot, whose amplitude and width depend on the time constant f and its relation to filter time constant
- see Fig. 3.32.
(a)
(b)
Fig. 3.32. Pulses for different CSA feedback time constant: a) at the CSA output, b) at the shaper output the second order shaper with tp 180 ns.
At low rates of input pulses, this pulse overshoot is usually tolerable, however, in
high rate experiments the consecutive input pulses produce a negative baseline shift at
the shaper output and loss of the amplitude resolution of the system (see Fig. 3.33(a)).
Additionally, if the readout system operates at high fluctuating random rates, a significant base line variation is produced. The undershoots can be eliminated (see
Fig. 3.33(b)) by applying the pole-zero cancellation circuit [115,116].
(a)
(b)
Fig. 3.33. Examples of waveforms at shaper output for high rate of input pulses:
a) without PZC circuit, b) with PZC circuit.
74
The idea of a PZC circuit is shown in Fig. 3.34. By adding an extra resistor Rpz
(parallel to capacitor C) the long time constant f at CSA output can be cancelled by the
subsequent stage if the following condition is fulfilled
C F R f = CR pz
(3.115)
Fig. 3.34. PZC after CSA stage.
Then the pulse at the shaper output is given by
1
2
CR pz
Q
1
1
voutSH ( s) = in
1
CF s + 1
sCR + 1
s+
CF R f
C (R pz || R )
s+
(3.116)
and because CFRf = CRpz , the above equation can be rewritten as
Q
voutSH ( s ) = in
CF s +
1
1
C (R pz || R )
sCR + 1
(3.117)
The "pole" of the CSA is cancelled by the "zero" of the PZC circuit. The new time constant after the PZC is equal to C(Rpz||R) and it is smaller than f.
Different practical implementation of the PZC circuit for an integrated circuit can
be found in [62, 78, 79, 81, 115119]. One of the most popular solutions in an integrated circuit is to use MOS transistors in CSA feedback and a PZC circuit working in
linear or saturation region - see Fig. 3.35. The response at the shaper output is
voutSH ( s ) = Qin
sC R pz + 1
Rf
Z1
sCF R f + 1
R pz
(3.118)
75
and the above equation can be rewritten as
voutSH ( s) = Qin
C
CF
Z1
(3.119)
where Rf and Rpz represent equivalent small signal channel resistance of the MF and
MPZ transistors respectively.
Fig. 3.35. Possible implementation of PZC circuit in IC.
3.5.3. Base line restorer

The baseline problem is less severe when bipolar shaping is employed. However,
the unipolar pulse shaping is more advantageous than bipolar shaping when considering
noise performance and pulse width. Adding a PZC block (like one in Fig. 3.34 or
Fig. 3.35) means that the CSAshaper block becomes DC coupled (without Rpz the
CSA-shaper block was AC coupled). The AC coupling between the stages in the frontend electronics is often used in multichannel systems to avoid offset propagation
through the entire signal path and to minimize the problem of the leakage current in case
of a DC coupled detector. A sequence of unipolar pulses passing through an AC coupled
stages leads to the base line shift. Similar effects occur in the systems with a continuous
DC path from input to output which modify the frequency response of the front-end
electronics through feedback network (usually to reduce the gain in low frequency
range). In these cases the restoration of the base line is necessary and Base Line Restorers (BLR) or a Base Line Holder (BLH) are used for this purpose. The idea of the BLR
is shown in Fig. 3.36. The basic components of the BLR are memory C capacitor and
a switch of small resistance R. Between the pulses, the switch is closed along the baseline. When the signal arrives the switch opens and the output signal is given by the input
signal minus its base line [120,121].
76
Fig. 3.36. Basic idea of the BLR.
Four basic configurations of the BLR are shown in Fig. 3.37. The BLR shown in
Fig. 3.37(a) works with a signal of positive polarity and clipping diode shorts to ground
the negative undershoots. These circuits work effectively for input pulse of amplitude
considerably higher than
vmax >>
kT
q
(3.120)
where kT/q = 26 mV in room temperature. Applying here bipolar pulses at the input can
lead to double pulses at the output [37].
The circuit shown in Fig 3.37(b) was suggested by Robinson, et al. [122] and it
works for input pulses of both polarities. In the base configuration the current I2 = ID is
a half of the current I1 = 2ID. Without input signals, both diodes are forward bias, each
carrying current ID and the node X is shorted to ground via small rD resistance of bias
forward diodes. The time constant of the input circuit is 2rDC. Input signals (greater
than a few hundreds mV) of either polarity cut off one of the diodes and change the time
constant . Positive input signals cut off the diode D1 and the current I2 = ID flows into
the coupling capacitor C. Negative input signals cut off the diode D2 and the current
ID = I1I2 charges coupling capacitor C. The output pulse is given as
vout (t ) = vin (t )
1
I Dt
C
(3.121)
Between pulses the charge leaks off through small resistance rD of two series of
connected diodes and a small residual baseline shift is observed even for the quite high
rate of input pulses [123]
Vshift =
2rD I D f D 2 Kf D
=
1 fD
1 fD
(3.122)
where fD is the duty factor of input pulses and diode resistance rD = K/ID (for semiconductor diodes the K value is between 25 mV and 50 mV).
77
(a)
(b)
(c)
(d)
Fig. 3.37. Examples of different configurations of the BLR: a) with a clipping diode, b) Robinson
configuration with a two diodes, c) Chase-Poulo restorer, d) Gere-Miller restorer.
Together with the increase of the duty factor fD > 10% the performance of the
Robinson restorer becomes significantly degraded because of the finite diode incremental resistance. A modification to decrease the effective diode resistance was proposed by Chase and Poulo [123] - see Fig. 3.37(c). By adding an amplifier with diodes
in the feedback loop their effective dynamic resistance is decreased by the factor equal
to the amplifier gain, without increasing the diode current.
An interesting concept of the BLR was proposed by Gere and Miller [124] - see
Fig. 3.37(d). Between the signals current Ig is pulled from the amplifier input. The current value is chosen so that Ig > C(dVin/dt)max and the diode remains closed and the node
X is held at ground potential. Sometime before the peak of the input pulse the gate current is switched off. For the negative-going input pulse the point X remains at ground.
However, as soon as the input signals starts to go positive, the diode opens. As a result,
the full peak-to-peak amplitude is obtained at the output.
78
Fig. 3.38. BLR with switch and transconductor structure [121] 2005, IEEE.
Development of high rate spectrometry has caused that there are some new realizations of the circuits which are BLR or perform similar function [121, 125132].
Let us analyze two examples of these circuits which were realized in CMOS technology. The first circuit (0.35 m CMOS technology) was suggested by Pulia, et al.
[121] and is presented in Fig. 3.38. The BLR consists of memory capacitor C, switch S
and an active circuit (amplifier A1, transistors M1M6) which works as unity gain
buffer or large value resistor. A two-position switch S is driven by the arrival of the
input signal. When the switch is closed to position a the transconductor (A1-M1-R)
together with two current mirrors (M2M3 with ratio K1 = 25 and M4M5 with the
ratio K2 = 20) is equivalent to large dynamic resistance Req connected to node a given as
Req = R K1 K 2
(3.123)
For the integrated resistor R = 60 k the above equivalent resistance Req equals
30 M. When the switch is connected to node c, the voltage drop across the capacitor C
is frozen, and the structure A1-M1-R works like a unity gain buffer. The switch S is
driven by discriminator A2 which compares the input current with a preset threshold
current Ith.
The BLRs have usually large bandwidth in order to provide a quick return to
baseline between the pulses. A different concept is used in the base line holder (BLH) as
proposed by Geronimo, et al. [132, 133]. The BLH concept is based on the feedback
loop closed on shaper amplifier and the output stage - see Fig. 3.39. The BLH loop consists of a differential amplifier, non-linear buffer and low-pass filter. The output voltage
79
Vout is compared to the reference voltage. The following non-linear buffer reduces the
gain of the feedback loop only in the presence of a large and fast signal. The loop pass
filter reduces the loop bandwidth and ensures the stability of the loop. The current IF
(produced by a low pass filter) is subtracted from the main signal current IIN at the
shaper input (input of the shaper is assumed to be virtual ground).
Fig. 3.39. Simplified scheme of part of front-end channel containing BLH [132] 2000, IEEE.
A detailed scheme of the BLH is shown in Fig. 3.40. The non-linear buffer is
based on transistor M1 with controlled bias current (M2 controlled by Vg1) and C1B capacitor. Low bias current of source follower M1-M2 and relatively large C1B cause that
the response of the buffer to large and fast pulses is one directional slew-rate limited to
IdM1/C1B (IdM1 is a bias current of M1 transistor). The next source follower M3 (bias from
current source M4) with the capacitance C2B forms a low pass filter. Low bias current of
this stage and properly set C2B provide the dominant pole of the loop at very low frequency. The transistors M5 are used for voltage to current conversion. For small and
slow signals the high loop gain keeps Vout = VBL (no slew rate limit occurs). Large and
fast signals are unaffected by the BLH. The main drawback of this solution is residual
fluctuation of the baseline discussed in detail in [132].
Fig. 3.40. Detailed scheme of the BLH [132] 2000, IEEE.
80
3.6. FURTHER SIGNAL PROCESSING

Further signal processing at the shaper outputs in the multichannel chip depends
strongly on specific requirements of the foreseen applications. The ideal system should
ensure position, energy and timing measurements. And that means that each channel
should contain fast high resolution analog-to-digital converter (ADC), time-to-digital
converter (TDC) and a big memory buffer. Nowadays, the constraints associated with
the area and power consumption of multichannel IC make this approach difficult to realize in practice. Instead, the existing multichannel ASICs for fast digital imaging use an
intermediate solutions, which reduce the energy (or timing) resolution or single channel
maximum throughput.
Let us concentrate on applications for fast X-ray digital imaging. Solutions most
frequently used include:
one or a few discriminators per single channel [44, 46, 134, 135] - see Fig. 3.41,
a simple low resolution ADC per single channel [3941] - see Fig. 3.42,
multiplexing technique with high resolution ADC [42,43] - see Fig. 3.43.
Fig. 3.41. Binary readout architecture.
The architecture with one or a few amplitude discriminators per single channel is
used in various imaging techniques, where it is sufficient to measure spatial distributions
of the X-rays of energies above a given threshold or within a given energy window. The
existing solutions have up to 9 discriminators per single channel [135]. The counters
after the discriminators store the information about the number of signals, which have
been higher than the given threshold level. As each channel works independently, this
81
solution is suitable for very high intensity of X-rays (even more than 1 Mcps per single
channel). This is a significant advantage in systems comprising hundreds or thousands
of channels. Additionally, using this simple approach, by scanning the discriminator
threshold level and measuring the integral distribution of pulse amplitudes, one could
extract spectroscopic information of X-ray radiation. Examples of discriminator architectures are presented in Chapter 3.6.1.
The requirement concerning the resolution of the ADC in multichannel system
strongly depends on applications and in practice it is in the range from 4 to 12 bits. The
most often used converter architectures in nuclear electronics are:
successive approximation ADC [136, 137],
Wilkinson ADC [138140],
pipeline ADC [141,142],
flash ADC [83,143],
time-over-threshold method [144146].
The details of architecture and design of the above ADCs can be found in classical
books on analog electronics, like, for example [147, 148]. The only exception is timeover-threshold (ToT) method. The idea is shown schematically in Fig. 3.42.
Fig. 3.42. Architecture employing time-over-threshold method.
In the time-over-threshold method [144, 145], the analog signal from the frontend circuit is applied to a simple threshold discriminator. Signals above the threshold
generate a logic pulse at the discriminator output. The duration time of this pulse is
measured in a simple way by counting pulses from the clock generator over the period
equal to the duration of the discriminator response. The width of the discriminator pulse
is a non-linear function of pulse amplitude and knowing this function for a given pulse
shape one could determine the pulse amplitude at discriminator input. The basic limitations of ToT processor are: the measurement range limited by the discrimination level,
82
low accuracy for small signals just above the threshold and sensitivity to the time jitter
of the discriminator, especially for low amplitudes. The system with a ToT processor is
relatively simple and because of low power consumption it can be implemented in every
channel. This solution has been implemented in several ASICs for readout of strip/pixel
detector in the particle physics experiments [144146].
A fully analog readout scheme, employing a standard ADC, is shown schematically in Fig. 3.43. Each channel is equipped with a peak detector and a Sample and Hold
(S&H) circuit. Because in X-ray applications the input pulses are statistically distributed
in time, one needs to implement a threshold discriminator in each channel to generate
a trigger signal for the S&H circuit. Analog signals from a certain number of channels
are then multiplexed into one ADC, which, in most cases, is an external device, although
one can consider integrating it in the front-end ASIC. An obvious limitation of the
maximum channel throughput is the multiplexing rate, which is less critical when we
reduce the number of channels per ADC and increase the number of ADCs in the system. Another aspect which is specific for such architecture concerns the control of the
multiplexer and the ADC operation. One can either run the multiplexer and the ADC
continuously [149] allowing for some probability of the pile-ups in the S&H circuits, or
trigger the multiplexer and the ADC upon a signal occurring in the detector [42]. The
most commonly used scheme is based on OR gate taking inputs from all the channels.
Then each signal occurring in any of the channels triggers the readout sequence. Another trend of the development is to integrate in the front-end ASICs analog memory
buffers which can serve as derandomizers and in that way increase the channel throughput (see Chapter 3.6.2).
Fig. 3.43. Analog architecture employing multiplexing of analog signals and fast ADC.
83
3.6.1. Discriminators
The discriminators used in multichannel binary and counting systems are relatively simple, however often contain blocks for offset correction. The threshold adjustment can be done using:
trimming DACs (3-bit up to 8-bit) [44, 150],
analog approach to store correction voltage on the capacitor [151].
(a)
(b)
(c)
(d)
Fig. 3.44. Possible solutions of applying threshold voltage: a) appling controlled current to resistive
structure, b) applying two differential voltages, c) changing the switching point of differential amplifier,
d) with feedback diode on simple inverter.
Threshold voltage or trim voltage can be applied in different ways (see Fig 3.44).
These are possible solutions:
controlled current is fed into the resistor (which can be based on the MOS structure) Fig. 3.44(a) [151],
a controlled current source connected to one branch of differential pair shifts its
switching point - Fig. 3.44(b) [44, 70],
84
two voltages applied differentially set an effective DC level at discriminator inputs Fig. 3.44(c) [86,152],
an extra diode with controlled current connected between inverter input and output
introduces offset voltage - Fig. 3.44(d) [153].
Let us analyze two examples of discriminator architectures used in a single photon counting system. Fig. 3.45 shows the discriminator scheme used in 64-channel
DEDIX integrated circuit (0.35 m CMOS technology) for fast readout of a silicon strip
detector for X-ray imaging applications [152]. To select the photon of given energy
there are two independent discriminators (with a common input VIN and a common reference VINREF) and a DC offset correction circuit.
(a)
(b)
Fig. 3.45. Two differential discriminators used in a single photon counting system: a) schematic, b) pulse
waveform at input, after setting the threshold and at the output [152] 2007, IEEE.
85
The correction circuit consists of transistors M20 and M21 as well as a tunable
current source ICOR (set by the internal trim DAC). The correction circuit is common for
both discriminators because the whole front-end electronics channel is DC coupled and
dominant contribution of offset spread comes from the earlier CSA and shaper stages.
The correction circuit trims a channel-to-channel DC level spread at the discriminator
inputs (VINREF voltage is set in each channel independently). The input differential stages
M22M26 and M36M40 have gain close to 1 and are used to provide differential
threshold voltages (common value for all 64 channels) for the first and the second discriminator respectively
VTHhigh = VTH 2 VTH 1
(3.124)
VTHlow = VTL 2 VTL1
(3.125)
The exemplary waveforms at discriminator input, output of M36M40 stage are

shown in the middle plots in Fig. 3.45(b). The following stages M27M35 and
M41M49 are comparators with hysteresis. Due to the differential discriminator architecture it can work with both positive and negative input pulses. In order to reduce the
effect of the comparator switching on a CSA and a shaper performance, the discriminators use a separate positive power supply Vdd.
The second example of a discriminator is shown in Fig. 3.46. This stage is used in
PX90 integrated circuit prototype (90 nm CMOS technology) for a hybrid pixel detector
[87].
Fig. 3.46. Differential discriminators used in a single photon counting system PX90 [87], 2010, IEEE.
86
This discriminator has a differential input and consists of three main parts:
two input source followers (transistors M21 and M22) with controlled currents
sources I1 and I2 to trim a channel-to-channel DC level spread,
differential stage (transistors M23M29) which add some gain and set the threshold level,
core of a discriminator (transistors M34M44).
There is an OTA at the core discriminator input (transistors M34M38) to convert
voltage signal to current signal. The discrimination is then performed by subsequent
current comparator (transistors M39-M42) [70, 154]. The last output amplifier (transistors M43 and M44) is added to drive the logic gate properly. The maximum current in
the last stage is limited to 0.7 A to reduce the current spikes (on power supply lines)
generated during comparator switching and the current consumption.
3.6.2. Peak Detector Derandomizer

Using analog-to-digital conversion (for instance with a resolution of about
10-bits) per single channel for high rate of input pulses is impractical for most large
multichannel systems. One of possible solutions is to multiplex analog signal from some
channels into one ADC, but Poisson fluctuations of the input pulse rate increase speed
requirements, both for multiplexer and the ADC. To reduce speed requirements for the
ADC, a group from Instrumentation Division, BNL, Upton, USA, has developed Peak
Detector Derandomizer (PDD) ASIC [155157]. This circuit works as a data-driven
analog first-in, first-out (FIFO) memory buffer between the preamplifiers and the ADC.
Amplitudes of signals occurring randomly in time are stored in such a buffer and read
out with the rate comparable to the average rate of input pulses.
(a)
(b)
Fig. 3.47. Simplified scheme of a two-phase peak detector: a) WRITE phase, b) READ phase (reprinted
from [155] 2002, with permission from Elsevier, http://www.sciencedirect.com/science/journal/ ).
87
The basis of the chip is a two-phase peak detector (PD) with high absolute accuracy (0.2%) and linearity (0.05%) which is shown schematically in Fig. 3.47. In the
WRITE phase PMOS transistors M1 load the hold capacitor CH up to the peak value of
the input pulse. In the READ phase it works as unity gain buffer. This PD scheme is an
offset-free configuration, because in the WRITE-READ cycle the error of amplifier
offset is cancelled.
The PDD ASIC contains 32 input channels and performs simultaneous amplitude
and time measurements, together with delivery of the channel address information. The
chip has been fabricated in 0.35 m CMOS technology. This fully self-triggered ASIC
multiplexes 32 shaped input signals into an array of eight peak detectors (which act as
a derandomizing analog memory) with associated time-to-amplitude converters (TAC) see Fig. 3.48. 32 comparators monitor the inputs for any activity. When the input pulse
arrives, the arbitration logic routes the pulse to the next available PD/TAC. The connection is maintained until the peak amplitude is found. This value is stored on the PD hold
capacitor until the external ADC is ready to convert this sample.
Fig. 3.48. Block diagram of amplitude and time measurement ASIC [157] 2003, IEEE.
In comparison with popular techniques, such as a track-and-hold and analog

memory, the PDD ASIC enables efficient pulse height measurements at 20 to 300 times
higher rates. It can operate at rates up to 300 kHz per channel with 99% efficiency.
Important aspects of multichannel IC
89
4 IMPORTANT ASPECTS OF MULTICHANNEL

LOW NOISE MIXED-MODE IC
Integrated circuits for strip/pixel detector consist of many channels. For strip detector, the chips often contain 32, 64 or 128 readout channels in a single die (see Chapter 6), while for the pixel detector, it can reach several thousands readout channels working parallelly and independently, e.g. MEDIPIX2 IC has 65536 identical front-end
channels [44]. The number of readout channels in a single integrated circuit puts constraints on the maximum available area and power dissipation per single channel. Besides, to make the system effective, the spread of analog parameters from channel to
channel must be minimized; therefore, the good matching performance as the additional
requirement should be taken into account starting from the early design stage.
Another aspect is a mixed-mode character of readout IC. In order to improve the
functionality and reliability of multichannel systems, the single chip should be equipped
with digital blocks for control and testing the chip itself and some digital data processing
90
directly on the chip. This results in extra crosstalk between sensitive analog circuits and
fast digital blocks, usually known as switching noise.
In most cases the main requirements for multichannel mixed-mode readout electronics for semiconductor detectors are:
low level of noise and high speed pulse processing,
strict limits on maximum power dissipation and area of single readout channel,
minimization of crosstalk effects in the mixed-mode integrated circuits,
good matching performance of analog parameters (gain, offsets, noise) from channelto-channel.
To the community of electronic VLSI designers, each of the above requirements
is very often a challenging task. There are number of interesting and valuable papers,
which describe each of the above aspects, but separately. In case of multichannel mixedmode integrated circuits, all of these aspects are important and they often necessitate
conflicting requirements [158].
Fig. 4.1. Relations among different aspects of multichannel mixed-mode ICs design.
The relations among different design optimization aspects are shown schematically in Fig. 4.1. For example, biasing an input stage of front-end electronics with high
current is advantageous for the noise optimization, but in multichannel system it is limited by available power dissipation in a single channel. Some elements of circuit architecture which are preferred from the point of view of crosstalk minimization (e.g. differential structure in analog blocks) increase the noise. The limitation of a single channel
area is in opposition to the low level of 1/f noise and to the reduction of mismatch effects.
Taking into account the above-mentioned aspects, we would like to concentrate
here on three problems important for such mixed-mode multichannel ASIC designs,
viz.[159]:
SPICE modeling of noise in MOS transistors and short channel effects,
crosstalk phenomena in mixed-mode integrated circuits,
mismatch modeling in the MOS transistor and circuits.
91
4.1 NOISE MODELLING IN MOS TRANSISTORS

Noise sets a lower limit to the accuracy of any measurements and to the amplitude
of signal that can be processed electronically. By understanding the noise origin and
models used by the circuit simulators, one can significantly improve noise parameters of
the circuit. As we analyze the CMOS circuits, this chapter concentrates on a brief review
of noise models for the MOS transistor, including simple models for first-hand calculation, the example of numerical model (used by HSPICE) and their limitation due to
short channel effects.
There are several noise sources in MOS transistors:
thermal noise in the drain-source channel,
flicker noise in the drain-source channel,
induced gate noise at high frequencies,
shot noise due to leakage current through the SiO2 gate,
shot noise associated with leakage current of the drain (source) reverse biased diodes,
thermal noise due to the source, drain and gate contact resistance.
In most cases only the first two items are important, so they are discussed in detail
in the next subsections. Induced gate noise becomes non-negligible at high frequencies
when the MOS transistor must be considered as an RC distributed network. The capacitive coupling to the gate is modeled as a distributed capacitance and the channel itself is
represented as a distributed resistance [160, 161]. The gate admittance has capacitive
and conductive components. The conductance has noise associated with it. To calculate
the induced noise at higher frequency one should determine the degree of correlation
between the gate and drain thermal induced noise current, since both noise currents have
the same physical origin. The leakage current through the SiO2 gate and drain (source)
reverse biased diodes are in most cases negligible, and the shot noise associated with
them can be also neglected. The source, drain and gate contact resistances contribute to
the thermal noise and their power spectral densities are provided by well-known Nyquist
equation.
4.1.1 Channel thermal noise

Every resistive element generates thermal noise which is caused by random motion of charge carriers in it. A noisy resistor can be modeled as a noiseless resistance
R with a series noise voltage generator of the power spectral density, given by
dvth2
= 4kTR
df
where k is Boltzman constant and T is an absolute temperature.
(4.1)
92
According to the Nortons theorem, the voltage noise source, as above, can be
represented as a parallel current source with the power spectral density equal to
dith2 4kT
=
df
R
(4.2)
The MOS transistor has a resistive channel between the drain and the source, and
the random thermal motion of carriers in the channel results in thermal noise. This noise
depends on bias conditions, transistor dimensions and the properties of a given technology. For the first-hand noise calculation the thermal channel noise in strong inversion in
the saturation region can be expressed as
dith2 8
= kTg m
df
3
(4.3)
where gm is gate transconductance of the MOS transistor. In the linear region, when
drain-source voltage VDS is close to zero, the power spectral density is given as
dith2
= 4kTg ds
df
(4.4)
where gds is source-drain small signal conductance of the MOS transistor.

In the weak inversion region for VDS > 5kT/q, the corresponding expression for the
thermal noise is
dith2
n
2qI DS 4kT s g m
df
2
(4.5)
where q is elementary charge, IDS is drain-source current, gm is gate transconductance of

the MOS transistor (operating in weak inversion - see eq. (3.103)) and ns is a subthreshold slope factor.
There are several channel thermal noise models used by the circuit simulators.
The HSPICE MOS transistor noise model has a NLEV parameter which is used to select
different equations for the noise calculation [162]. If the NLEV model parameter is less
than 3, then the power spectral density is given as
dith2 8
= kTg m
df
3
(4.6)
93
The above equation is used both in the saturation and the linear regions, but in the
latter case it can lead to wrong results. The model incorrectly predicts that the thermal
noise of the MOS transistor falls to zero, when VDS = 0 (because then gm equals 0). If the
NLEV model parameter is set to 3, HSPICE uses a different equation which is valid in
both the linear and saturation regions
dith2 8kT
1 + a + a2
W
=
Cox (VGS VT )
GDSNIO
3
1+ a
df
L
(4.7)
where is mobility, Cox is oxide capacitance per unit area, W, L are width and length of
MOS transistor, VGS is gate-source voltage, VT is threshold voltage, GDSNIO is HSPICE
channel thermal noise coefficient (default equals 1), a is parameter defined as
a = 1 VDS / VDSsat , VDS is drain-source voltage, VDSsat is saturation drain-source voltage.
In the linear region with VDS = 0, we have a = 1 that gives [163]
dith2
= 4kTg ds
df
(4.8)
For the HSPICE NLEV equaling 3, the noise model works reasonably well for
long channel devices, but is not adequate for short channel ones.
The other equations are used by the BSIM4 model from UC Berkeley [164].
There are also two channel thermal noise models, which can be selected by the model
flag tnoiMod. For the default tnoiMod = 0, the charge base model is used (similar to that
used in BSIM3v3.2). Power spectral density of thermal noise given by the formula
dith2
=
df
4kT
Rds (V ) +
L2eff
NTNOI
(4.9)
eff Qinv
where Rds(V) is the bias-dependent LDD (light doped drain) source/drain resistance, eff
is effective mobility, Leff is effective channel length, Qinv is total inversion channel
charge and the NTNOI parameter is introduced for more accurate fitting of short channel
devices. The inversion channel charge is computed from the charge-based capacitance
model equations [163], taking into account the effective channel width and length, the
operation point and the bulk charge effect.
For tnoiMod = 1, the holistic model is used which in the scheme gives noise voltage source partitioned to the source side and noise current source which is put in the
channel region. This model takes into account:
short-channel effects and velocity saturation,
94
the amplification of the channel thermal noise through gm and gmb, as well as the induced gate noise with partial correlation to the channel thermal noise.
4.1.2 Flicker noise

It is known that the noise of MOS transistors in the low frequency range is high
due to the flicker noise, also called the 1/f noise. Two main theories explain the physical
origin of the flicker noise. The first one is the carrier number fluctuation theory [165,
166] which assumes that the noise is caused by the random trapping and detrapping of
the mobile carriers in the channel by the oxide traps near the Si-SiO2 interface. According to that theory, the flicker noise can be modeled by the voltage noise generator in
series with the transistor gate with the voltage noise power spectral density given by the
following formula [163]
dv12/ f K f 1 1
= 2
df
Cox WL f
(4.10)
where is Kf technology dependent constant (but independent of bias condition), is

exponent constant closed to unity (varies in the narrow range of 0.7 to 1.2) and f is frequency.
In the other approach, known as the mobility fluctuation model [167], the flicker
noise is attributed to the mobility fluctuation. The electrons (holes) are scattered by phonons of lattice vibrations and the density of phonons fluctuates with a 1/f spectrum. The
result of that theory gives the equivalent voltage noise as
dv12/f K f (VGS ) 1 1
=
df
Cox WL f
(4.11)
where Kf (VGS) is a bias dependent factor and 1. The inverse proportionality with Cox
is not universally accepted [163].
The above models are generally accepted for all regions of channel inversion. In
most cases it is noticed that the PMOS transistors have significantly less noise than the
NMOS ones (by one order of magnitude or more). That is attributed to the buried channel character of the PMOS transistor, because the channel is farther from the Si-SiO2
interface and the charge carriers in the transistor channel are less affected by the interface traps. In modern technologies where the buried channel effect is no longer present,
the flicker noise for the PMOS and NMOS transistors can be similar [168].
The HSPICE MOS transistor model for the flicker noise simulation uses a current
noise source placed between the drain and the source. That enables calculation of the
95
power spectral density of the total noise as the sum of white and flicker noise components given by
din2 dith2 di12/ f

=
+
df
df
df
(4.12)
To obtain the representation of the equivalent input noise voltage source in series
with the transistor gate, the following relation should be used
dv n2
1 di 2
= 2 total
df
g m df
(4.13)
For the flicker noise, two parameters are used by the HSPICE models: flicker
noise coefficient KF and flicker noise exponent AF (default equals 1). The model equations are selected by the NLEV parameter. For the NLEV = 0, the power spectral density
of the flicker current noise is equal to
AF
di12/ f KF I DS
1
=
2
df
Cox Leff f
(4.14)
For the NLEV = 1 L2eff in the above equation is replaced by Weff Leff and then
AF
di12/f KF I DS
1
=
df
Cox Weff Leff f
(4.15)
where Weff is the effective channel width. For the NLEV equaling 2 or 3, the equation is
as follows
di12/ f KF g m2
1
=
df
Cox Weff Leff f AF
(4.16)
The BSIM4 gives two flicker noise models depending on the fnoiMod selector.
For fnoiMod = 0 the simple model similar to the equation (4.14) is used (with an additional frequency exponent close to 1). For fnoiMod = 1 a unified model is used with
a fairly complicated formula for the flicker noise calculation with three parameters:
NOIA, NOIB, NOIC. The unified model takes into account the effective channel width
96
and length as well as the effective mobility at given bias conditions and the charge bulk
effect [164]. The BSIM4 flicker noise model is smooth over all bias regions.
4.1.3 Short channel effects

The short channel devices can have significantly higher noise than the above formulae would predict. For this reason, the noise excess factor has been introduced and it
is defined as a factor by which noise power spectral density is higher than that predicted
by the long channel theory.
In case of thermal noise both, advanced models and the measurements [169, 170]
show that under a certain bias condition, the noise for the short channel transistor can
even be an order of magnitude higher than the value expected for the long channel theory. That is due to the following high-field effects:
at high electric field the velocity saturates resulting in the decrease of effective mobility;
the electric field, which is especially high in the region close to the drain, can produce
hot carriers; the hot electron effect can be modeled by an equivalent carrier temperature which is higher than the lattice temperature and that results in higher noise
[160,161];
hot electron may cause impact ionization resulting in electron-hole generation; the
generated electrons are collected by the drain, while the holes form a substrate IDB current; this current is the source of shot noise with the power spectral density of 2qIDB; at
the higher IDB value, this noise also shows an excess factor; the substrate current produces the voltage drop across the substrate resistance, and then through the substrate
transconductance gmb contributes to the drain current noise [163].
The flicker noise is also sensitive to the small dimension effects. Hot carriers can
degrade the quality of the Si-SiO2 interface and introduce additional interface traps close
to the drain region. If the transistor operates in nonsaturation region, these traps affect
the channel charge and the current, which in turn results in significant increase of the
flicker noise [171, 172].
Another effect that influences the noise performance of small area transistors is
the capture and emission of carriers at single individual traps in the Si-SiO2. Because
for a small area transistor there are only a few traps which can exchange the charge with
the channel, their individual effects become non-negligible and the discrete modulations
of the source-drain conductance become visible in the form of random telegraph signals
(RST) [173]. Variation of the drain current due to the RST effect can rise up to 0.1% or
more of the DC current value [163]. For a large gate area with a large number of charge
carriers and traps involved, neighboring traps may interact and the channel current nonuniformity is smeared out [174].
In case of applications where the noise level is critical, a dedicated experimental
study of short channel effects in given technology is often necessary. This is also the
case of HEP experiments (where the number of readout electronic channels often ex-
97
ceeds several millions) and many papers focus their experimental noise study on transistors with geometry and biasing suitable for the CSA input device.
Technology node
CMOS 130 nm
CMOS 90 nm
Table 4.1. Transistor dimensions used during the noise measurement tests [106].
Transistor length [m]
Transistor width [m]
0.13 / 0.2 / 0.35 / 0.5 / 0.7
200 / 600 / 1000
0.1 / 0.13 / 0.2 / 0.35 / 0.5 / 0.7
200 / 600
Let us briefly analyze an example of such noise measurements presented in paper

[106]. The studied NMOS and PMOS transistors were manufactured in two commercial
CMOS process 130 nm and 90 nm provided by STMicroelectronics. The dimensions of
the tested devices are summarized in Table 4.1. The transistor parameters were characterized at drain currents from 100 A to 1 mA (ranging from weak to moderate inversion). The results of measurements of flicker noise coefficient Kf (formula (4.11)) are
shown in Fig. 4.2. The conclusions are the following:
Kf is larger for transistors with channel length close to Lmin in given technology,
Kf increases with the overdrive voltage VGS VT.
The measured slope coefficient (formula (4.11)) is:
for 130 nm technology NMOS = 0.85 and PMOS = 1.19,
for 90 nm technology NMOS = 0.85 and PMOS = 1.09.
(a)
(b)
Fig. 4.2. Measurement results of 1/f coefficient Kf at VDS = 0.6 V as a function of: (a) gate length for NMOS
transistors, (b) gate overdrive voltage for PMOS transistors [106] 2007, IEEE.
In case of thermal noise there were no short channel effects in the measured operating region except for NMOS transistors with the minimum feature size in 130 nm
process. For 90 nm process the thermal noise in NMOS devices with L 130 nm were
not presented because the noise corner frequency (boundary between 1/f and white
98
noise) was located at several tens of MHz (close to the higher frequency limit of the
measured system).
The measurements of noise of technologies from the same nodes but delivered by
different vendors (different technology steps) can provide different results concerning
the short channel effects. Some designers claim [175] that using minimum transistor
length with a small current density IDS/W and a low VDS voltage (just above VDSsat) will
cause only a modest increase in noise due to short channel effects. Without dedicated
noise measurements, some designers prefer to use an input transistor with the length of
30% 100% higher than Lmin.
4.2 CROSSTALK IN MIXED-MODE CIRCUITS

With increasing integration density of VLSI circuits a trend appears to integrate
more and more functionality on a single chip. Such solutions require ASIC designs,
which contain both high performance analog circuits and advanced high speed digital
blocks on the same die. The implementation of a complex system on a single chip brings
several advantages such as reduction in size, power dissipation, package, cost and increase in the speed of operation, flexibility and reliability of the system.
A major disadvantage in such a mixed-signal system is the increased interaction
(crosstalk) between different parts of the circuit on the same die. A fast switching transient produced in the digital circuit can corrupt analog sensitive components and impair
the performance of the entire system. The problem is greatly aggravated in modern
technologies, because of higher rates of circuits operation, greater density of elements
per chip and smaller feature sizes [176, 177].
There are three main rules to minimize the crosstalk on mixed-mode chips:
reduce the amount of generated switching noise,
increase the immunity of the analog part,
introduce proper isolation between the analog and the digital part.
In order to follow these rules, one should take into account the proper system solutions at an early stage of design (differential analog section, low power digital design),
the layout solutions (floor planning, power distribution, guard rings) and the aspects of
packaging. For better understanding of these problems, let us analyze at first the mechanisms by which the switching noise is introduced and transferred in the mixed-mode
integrated circuit.
4.2.1 Generation, transmission and reception of switching noise

The working digital cells are the sources of switching noise. When digital gates
are turned on or off, brief charging or discharging of capacitors occur, which in turn
generate spikes in the circuit. The shorter switching time, the higher value of the total
99
capacitance to overload and the larger voltage swing, the higher switching noise. The
noise can be transferred to the analog blocks in two major ways: through the common
power supply lines or through the common substrate shared by the analog and the digital
circuits (see Fig. 4.3).
Fig. 4.3. Disturbance transfer from digital to analog blocks.
The crosstalk through the common supply lines is often called a supply bounce
[178]. When many gates change states, a large cumulative current spike flows through
parasitic inductance and resistance of bias lines creating power supply voltage spikes.
The main source of the series inductance in the integrated circuits is the parasitic inductance of the bond wires and package leads. The current spikes drawn from the supply
lines of inductance Lind generate the voltage drop V = Lind dI/dt, and in consequence,
these supply lines can be very noisy. Because the analog blocks always have a limited
Power Supply Rejection Ratio (PSRR), the disturbances on the supply lines can corrupt
their achievable accuracy. The main method to minimize the supply bounce is to reduce
the value of the power supply connection inductance.
Even if power supply noise is significantly reduced, there is another method of
the crosstalk due to the non-ideal isolation provided by the common substrate. Every
switching activity of the digital blocks injects current into the substrate and causes the
fluctuation of the substrate voltage. This is known as a substrate noise [179] despite the
fact that it is not a real noise. Because of the non-zero dielectric constant and the conductivity of the substrate material, the parasitic currents can reach different parts of the
chip.
There are three main mechanisms for injecting substrate noise. The first one is the
capacitive coupling from switching nodes of active and passive devices. For example, in
case of the NMOS transistor made in p-type substrate, noise is coupled to the substrate
via source/drain-to-substrate capacitance, while the vertical NPN transistor interacts
with the substrate through the collector-to-bulk junction capacitance [180].
100
The second source of substrate noise is the coupling from the clock lines and
power supply lines through the line-to-substrate capacitance. Moreover, in most cases
the digital ground is connected to the substrate in every standard digital cell, and then
the supply bounce on digital ground is directly coupled to the substrate [181].
The third mechanism responsible for the noise injection is the impact ionization in
MOS transistors. For the short channel devices working in saturation, the electrical field
strength in the drain-end of the channel can be high enough to cause impact ionization
and to generate electron-hole pairs. The holes form a drain-to-substrate current which is
always positive for both 10 and 01 transitions in the drain node. The effect of the
impact ionization is often taken into account by the SPICE transistors models provided
by the foundry. Whether or not the impact ionization is an important source of the substrate noise depends on the technology, especially on the combination of the supply
voltage and the channel length. For example, for the epi-type 0.5 m 3.3 V technology
presented in [181], the substrate current caused by impact ionization is negligible.
Transfer of the switching noise through the substrate depends strongly on its electrical properties. In most cases bulk CMOS technologies use one of two kinds of substrate: a low resistivity substrate or a high resistivity substrate shown schematically in
Fig. 4.4. In a high resistivity substrate, the bulk region of 200400 m thick is lightly
doped silicon of resistivity about = 20 cm with a thin (1 m) implant (or epi) layer
on top. In a low resistivity substrate the bulk is heavily doped and has very low resistivity of the order of 1 mcm. Above it there is an epi-type layer of the thickness
Tepi = 510 m with the resistivity in the range =1015 cm. For the p-type bulk there
is also a thin surface implant on the top (known as p-tub or channel stop) to avoid parasitic inversion of the silicon by potential of the lowest metal layers. Technology based
on the low resistivity substrate is the one mostly used for the digital CMOS design due
to its immunity to latch-up.
a)
b)
Fig. 4.4. Substrate cross-section: a) high resistivity substrate; b) low resistivity substrate.
101
Current density J flowing through the substrate can be expressed by the formula
J = ( + j Si ) E
(4.17)
where is conductivity, j is imaginary unit, is angular frequency, Si is dielectric

permittivity of silicon, E is electric field.
For both, high and low resistivity substrates with a typical material resistivity
from 1 mcm to 20 cm, the capacitance of the substrate can be neglected for the frequency range below GHz [180]. Therefore, it is adequate to treat the substrate as a distributed network of simple resistors.
After fabrication a chip is mounted on board or in package. The mounting glue
can be conductive or non-conductive, and then we are talking about conductive or nonconductive backside contact. The kind of backside contact has influence on substrate
crosstalk.
One of the methods to simulate the substrate crosstalk is to use SPICE or Spectre
models of electronic elements and a proper model of the bulk. Such simulations have to
be done for the specific layout of the circuit taking into account the positions of each
electronic block and the distribution of supply and control lines. In case of the high resistivity bulk, the substrate is modeled by a simple resistive mesh. The effective resistance between two contacts on such substrate (which can represent, for example, the
position of analog and digital blocks) increases with the distance for non-conductive
backside. For the conductive backside, some of the current flows through the backside
contact and limits the isolation for the distance comparative with the wafer thickness
[182].
The situation is different for the low resistivity bulk. The epitaxial layer is modeled as a set of vertical and horizontal resistors, while the heavily doped bulk region is
considered as a single electrical node. For two contacts placed at the distance smaller
than 4Tepi, a significant portion of the total substrate current flows in the epitaxial layer.
For the distance larger than 4Tepi, the total current flows vertically in the epitaxial layer
and then through the heavily doped bulk over the entire chip. For that reason, the isolation between two contacts ceases to be the function of distance for the separation greater
than 4Tepi [179]. The situation is slightly modified by the skin effects for the frequencies
above GHz [183].
The analog blocks pick up the switching noise directly from the power supply
lines or from the substrate by capacitive sensing or body effect. Power supply rejection
ratio coefficients (from positive and negative bias lines) decide about the influence of
the supply bounce on the analog circuit performance. The substrate noise is picked up
by the components capacitively coupled to the substrate. This concerns transistors via
the junction capacitances, passive components (polysilicon capacitance, resistors etc.),
interconnect lines and input pads. For the MOS transistors, the principal coupling
mechanism occurs through the body effect. The threshold voltage depends on the substrate potential and that makes the drain current dependent on the substrate noise.
102
The switching noise coupling degrades the performance of the analog blocks. If
the switching noise is of the order of magnitude or higher than thermal, shot or flicker
noise of electronic devices, the analog circuit can loss accuracy, dynamic range, gain
and bandwidth [180]. In addition to the above effects, one should take into account the
possibility of circuit oscillation. The total on-chip power-to-ground capacitance and the
inductance of the bond wires form a resonant LC circuit, which can oscillate at higher
frequency (for example, the total capacitance of 10 pF and the bond wires inductance of
3 nH give the resonant frequency of about 900 MHz). A remedy for the problem is to
reduce the Q-factor of such a circuit by using series resistance or the RLC parallel
branch, as it has been suggested in [184]. There is also another source of possible oscillation when the high gain amplifiers are implemented. The substrate or the power supply
lines on the chip can create a positive feedback path for the signal that leads to the loss
of circuit stability. To cut the positive feedback path, proper isolation techniques discussed in detail in section 4.2.4 should be applied.
4.2.2 Reducing the noise generation

To minimize the crosstalk one should start from reducing the noise generation in
the digital blocks. The switching noise is generated at the slopes of switching signals, so
the peak-to-peak amplitude of generated noise strongly depends on the rise and fall
times, and on the amplitude of switching signals [185]. The number of generated noise
pulses increases with the switching frequency, and with the number of switching gates.
The best solution (however impractical) would be to stop switching the voltage and the
current in a digital block. The designer can control the time when switching occurs, and
in that way can separate the critical analog function from the moment of the noise generation in digital blocks. For example, for the proper timing in analog to digital converter one should introduce a phase shift between a digital clock and an analog sampling, to avoid comparison or sampling when large digital drivers switch on and off
[183]. All switching functions, logic blocks or drivers not in use should be turned off.
The gated clock systems are preferred, while the use of synchronous logic (with a large
number of gates switching simultaneously) should be minimized.
There are several digital design styles which generate more or less switching
noise. The static CMOS, whose main potential advantage is the low power consumption,
is one of the noisiest circuit topologies: large rail-to-rail switching voltages are generated and large current spikes are drawn from the power supply. Similar situation is in
case of self-resetting logic which adds variable high frequency reset noise [186]. There
are other design styles that generate less noise. The best ones are those based on balanced current steering with the constant current consumption as ECL (Emitter-coupled
Logic), CML (Current Mode Logic) or SCL (Source-coupled Logic). Preferable solutions also include those with smaller than rail-to-rail voltage swing like LVDS (Low
Voltage Differential Standard) or low swing differential logic operated at constant current [187]. Because the low noise logic blocks have in most cases non-negligible power
103
consumption (except for [187]), they are not useful for large digital integrated circuits
and their application is limited to small blocks.
Special attention has to be paid to the nodes with large parasitic capacitance to the
substrate (large fanout) like buses, I/O drivers and clock distribution networks. The rise
and fall times for drivers of these nodes should be as large as the design constrains allow
[178]. The voltage swing on these nodes should be minimized, while the distribution of
the digital signals and clocks in complementary form reduces the net amount of coupling noise.
4.2.3 Increasing the immunity of analog part

Analog blocks should be designed to be as insensitive as possible to the injection
of noise through the supply lines and the substrate. High PSRR (Power Supply Rejection
Ratio) is necessary to minimize the coupling of supply bounce into the signal path. In
case when it is impossible to obtain sufficient PSRR, the weak path for the supply coupling must be identified in order to apply isolation rules discussed in section 4.2.4. Because the substrate noise can be treated as a common mode signal, fully differential circuits are preferred to single ended stages [185]. Such differential structures should have
a high CMRR (Common Mode Rejection Ratio), so special attention has to be paid to
the symmetry in the layout and matching of critical components. Mismatches between
circuit elements convert a fraction of common mode noise into differential signals and
significantly reduce the isolation. Sometimes other parameters of the design enforce the
single ended signal processing. In that case, the transmission of the signals to another
subcircuit or to the external world, should be made concurrently with their reference
through the dedicated path, rather than rely on the common grounds [184]. All sensitive
high-impedance nodes have to be kept inside the chip, as the chip parasitics are much
smaller than those of a package or printed circuit board. The use of the minimum required bandwidth for the signal processing in a switching noise environment is always
an important aspect of design optimization.
In case of the p-type substrate, PMOS transistors are in n-well, which is connected to a clean power supply and can be used to shield the transistors from the substrate. Therefore, PMOS transistors are preferable for the signal handling [188]. The
NMOS ones can be used as components of the DC current sources, and it is better to
refer them to the substrate rather than to the clean supply.
The new deep submicron technologies offer additionally deep n-well or t-well
which can be used as additional shielding from substrate noise, however using these
layers is very area consuming.
4.2.4 Isolation techniques

The proper isolation techniques should be used to minimize the switching noise
transfer from digital to analog blocks. The first step is to limit the supply bounce by
reducing the parasitic inductance and resistance of connections between the chip and the
104
external world [181]. These parasitics depend on the type of package, type of bonding
and the number of pads used for the power supply lines. For the bonding wire connections, the typical inductance is 2.6 nH per single wire (45 m diameter and 2.5 mm
long), while the flip-chip connection has the inductance below 0.2 nH [189]. To decrease the inductance of the bonding wire connection, multiple bonding pads and the
bonding wires for each power supply bus can be used.
Still, the application of the above steps may not reduce the noise of the power
supply lines on the chip. If this is the case, it is reasonable to separate power supply
buses, pads and bonding wires for noisy digital and sensitive analog blocks provided
there is enough space on the chip. Some designers may argue that sets of power and
ground connections should be multiplied in order to further divide circuit blocks, for
example fast output drivers [178].
The distribution of power supply on the chip is closely related to careful floor
planning (see Fig. 4.5). The analog blocks need to be categorized by the sensitivity to
the switching noise, while the digital blocks need to be classified by the amount of generated noise. The most sensitive analog circuit (i.e. high gain preamplifier) should be as
far from the noisy digital circuit (i.e. output buffers) as possible, and the least sensitive
analog blocks should be placed next to the least offensive digital circuit [190]. The
power supply lines must be sufficiently wide, especially in large chips, to avoid unwanted voltage drops across the chip, while the current loop area should be kept small.
The floor planning should enable proper signal routing and pads assignment. Digital
signals should not be routed over the analog portion of the chip or close to sensitive
lines. Sensitive and noisy pads must be kept as far away from one another as possible
due to mutual inductance of the bonding wires or package pins.
Fig. 4.5 Example of layout floorplan of 64-channel mixed-mode ASIC RX64 [159].
105
Placement and connecting substrate contacts are critical for proper isolation (see
Fig. 4.6). Here the techniques applied are different for high and low resistivity substrates, but in both cases every effort should be made to connect the substrate near the
sensitive analog region to a quiet supply [178]. The high resistivity substrate requires for
the latch-up protection that the multiply substrate contacts be tied to the ground periodically. The substrate needs to be split into quiet and noisy regions. Analog and digital
regions should have separate substrate contacts with separate bonding pads for the
ground. The backside contact to the low impedance ground is recommended, but for the
sake of effectiveness, it usually requires the wafer to be thinned [186].
Fig. 4.6. General rules for separate analog and digital power supply pads and guardrings [184] 1997,
IEEE.
For the low resistivity substrate, the best solution is the placement of substrate
contacts in the analog part of the chip with a connection to a separate substrate pad, or if
it is not possible, to the analog supply [178]. In that case, a low impedance connection
for the substrate is of great importance, because in this way the isolation can be improved further on by thinning the wafer and by adding the backside low impedance contact (with metallization) tied to the quiet ground by conductive epoxy. Most of standard
cell libraries automatically connect digital ground to the substrate, which is not recommended however because the low impedance path is formed between the quiet analog
and the noisy digital ground buses [186]. The recommended solution is to use a dedicated cell library with separate connections for bulk and source of NMOS transistors (in
the case of p-type common substrate).
Using guard rings can reduce the transfer of switching noise. There are two kinds
of these. Let us consider a p-type substrate. A guard ring may be a simply continuous
ring of substrate contacts (p+ diffusion) that surrounds the circuit providing a low impedance path to the ground for the charge carriers produced in the substrate. The guard
ring can also be formed as n-well ring and as a result the noise currents flowing near the
surface will stop. Methods of using both of them depend strongly on the kind of substrate. Because the substrate current flow is lateral and concentrated near the surface, in
high resistivity substrate, the guard rings are very effective, especially if biased via separate bonding pad. In case of p-type substrate, the p+ ring diffusion can reduce the coupling of the switching noise by almost an order of magnitude [179]. The guard rings act
as an efficient current sink, and it is better to put them close to the protected objects. The
106
best solution is to put two rings around analog and digital blocks with separate package
pins. The floating guard rings are less effective and when tied to the power supply buses
they can even have a detrimental effect. The n-well rings are also recommended, because they break the low resistivity surface implant layer and force the substrate current
to flow in the substrate underneath the well where the resistivity is significantly higher
[182].
In the low resistivity substrate, most of the current flows vertically to the low resistivity bulk and then through the heavily doped bulk, over the entire chip. The
p+ guard rings reduce the substrate crosstalk only by about 20% when placed close to
the analog circuits and biased via the dedicated pins. The p+ guard rings can be used
separately for analog and digital blocks, but then the separate bonding pads for each of
them are necessary. Connecting the p+ guard ring to the digital ground or large substrate
contact results in the increase of the observed noise [184]. The n-well guard ring in the
low resistivity bulk has nearly no effect [179].
Guard rings are not the only way of shielding. Diffusion, implant, polysilicon or
metal layers tied by the low impedance connection to the power supply noncontaminated with noise can form vertical Faraday shielding. The n-wells can protect
the device inside very effectively and for that reason PMOS transistors are recommended for signal handling. Large area sensitive devices (including input pads) and
noisy routing channels for clocks should be vertically or horizontally shielded
[191, 192].
The use of different power supply filters is also important. In most cases, it is
done by adding a large decoupling capacitance between the power supply and ground on
the chip and off the chip on the board. The capacitance on the chip can be obtained by
stacking supply rails, using the MOS or polysilicon capacitors. Simple capacitance can
be replaced by more efficient RLC filters [184]. There are other sophisticated techniques
as active supply bypass [193] or active guard ring [194] which can also be taken
into consideration.
4.2.5 Summary of crosstalk reduction techniques

The summary of crosstalk reduction discussed above is given in Table 4.2.
Table 4.2. Recommendations for cross-talk reduction in mixed-mode IC [176 - 194].
Reduce the noise generation
Increase the immunity of analog part
Isolation techniques
in digital blocks
1. Reduce the number of
1. Analog blocks should have a high
1. Limit the supply bounce by
reducing the parasitic inductance
synchronously working digi- PSRR.
tal blocks.
2. Fully differential circuits are recand resistance of connections
2. Employ design styles,
ommended with high CMRR.
between the chip and the external
which generate less distur3. PMOS transistors are preferred for
world: proper package, multiple
bances, e.g.: CML (Current
the signal handling. In case of p-type
bonding pads for power supply
Mode Logic), SCL (Sourcesubstrate, PMOS transistors are in nbus.
Coupled Logic) or LVDS
well. N-well connected to a clean
2. Use separate power supply
(Low Voltage Differential
power supply can be used to shield the buses, guard rings, pads and
Standard), especially in I/O
transistors from the substrate.
bonding wires for analog and

blocks.
3. Introduce a phase shift
between digital clock and
analog sampling.
4. Pay special attention to the
nodes with large parasitic
capacitance to the substrate
(large fanout), like buses, I/O
drivers, clock distribution
networks. Rise and fall times
for drivers of these nodes
should be as large as the
design constraints allow. The
voltage swing on these nodes
should be minimized.
4. NMOS transistors can be used as

components of the DC current and it is
better to refer them to the substrate,
than to the clean supply.
5. Use deep n-well or t-well in deep
submicron technology as additional
shielding layer,
6. Signals to another subcircuit or to
the external world should be made
concurrently with their reference
through the dedicated path, rather than
rely on the common grounds.
7. All sensitive high-impedance nodes
have to be kept inside the chip, because
the chip parasitics are much smaller
than those of package or printed circuit
board.
8. Use minimum required bandwidth
for the signal processing.
107
digital blocks.
3. Design carefully the floor
planning and the distribution of
power supply in the chip. Digital
signals should not be routed over
the analog portion of the chip or
close to the sensitive lines. Sensitive and noisy pads must be kept
as far from one another as possible due to mutual inductance of
the bonding wires or package
pins.
4. Use vertical shielding for large
area sensitive devices (including
input pads) and for noisy routing
channels, like clocks.
5. Use different decoupling techniques between power supply and
the ground: simple capacitors,
RLC filters, active supply bypass
or active guard rings.
4.3 RANDOM MATCHING AND OFFSETS

The physical circuit components (i.e. resistors, capacitors, transistors) deviate
from nominal values or design intentions due to the variety of statistical and deterministic effects [195]. The above results in variation of electrical parameters for nominally
identical devices and is a limiting factor in many precision analog circuits [196], digital
to analog converters [197], analog to digital converters [198], multichannel systems [44,
56], reference sources [199], memory sense amplifiers [200], SRAM [201, 202], etc.
One should distinguish between systematic offset and matching. Systematic offset
is the effect of asymmetry in circuit configuration, bias condition and layout. Obtaining
zero systematic offset is a matter of good engineering design. Mismatch is the process
that causes time-independent random variations of physical parameters of identically
designed devices. Mismatch as an inherent feature of the VLSI technology cannot be
omitted, but it can be understood and its influence on the performance of ICs can be
minimized (the design should be insensitive to technology imperfection).
Random errors in MOS transistors are mainly caused by random fluctuation of
[195, 202204]:
channel dopant density,
oxide thickness,
length and width of transistor,
interface states and oxide charges,
108
effective channel mobility, etc.

The impact of mismatch of MOS transistors becomes increasingly important, as the
dimensions of the devices are reduced and the available signal swing decreases. With
smaller devices the fluctuation becomes more and more important. Let us consider
a simple example of NMOS transistors of W = L = 0.25 m, shown in Fig. 4.7. Assuming a channel dopant density Na 21017 cm-3 and an average channel thickness
ydep 0.1 m, one can calculate the number of active dopants in a channel of about
1250. Poisson statistics gives the standard deviation (sd) of dopant in the channel at the
level of sd 35 (sd/mean is about 3 %). For smaller devices sd/mean of active dopant in
MOS transistor channel is even higher [205]. This level of channel dopant fluctuation
significantly influences a threshold voltage variation.
Fig. 4.7. Small area transistor in submicron technology (W = L = 0.25m) - Poisson statistics gives the
relative fluctuation of active dopant about 3% [205].
There are numerous theoretical approaches to mismatch modeling based on certain assumptions on the behavior of defects that cause mismatch [199, 204, 206209]. In
the paper by Shyu, et al. [206], the mismatch in capacitors and current sources were
analyzed in terms of the local and global variation. In 1986 Lakshmikumar, et al. [207]
started again from the possible physical causes of mismatch and described the local
variation of MOS transistors by means of threshold voltage and current factor standard
deviations. The authors [207] derived the theoretical relation between mismatch standard derivation and the inverse square root of the effective active device area. Three
years later Pelgrom, et al. [199] involved spatial Fourier transform technique to analyze
mismatch effects. The variations in the threshold voltage, the current factor and the substrate factor of the MOS transistor were measured as a function of area, distance and
orientation. In 2002 an easy-to-use mismatch model was presented by Croon, et al. [204]
and validated on submicron technology (CMOS 0.18 m). To obtain a higher accuracy,
the authors introduced fitting parameters which describe short and narrow channel effects. The Croon model is continuous from weak to strong inversion and from linear to
saturation. There are also some new models proposed in [208, 209], but they are not so
commonly used as those presented in [199, 207].
109
The model of random matching is applied to the parameters of equally designed

devices on the same chip as the result of unavoidable variation during IC fabrication.
The matched devices should be of equal nature, have the same layout, identical surrounding and be used identically (bias voltages, currents and temperature). Two kinds of
errors can be distinguished, local and global variations.
Short distance variations related to the short distance effects have the following
features [199]:
the total mismatch of the parameter P is composed of many single events of the mismatch generating process,
the effects of a single event on a parameter are so small that the contributions of many
events to the parameter can be summed,
the events have a correlation distance much smaller than the device dimensions.
The amplitude of these short distance variations has a normal distribution with
mean value around zero.
The second class of mismatch is related to the different gradients across the wafer
(for example in oxide thickness), which originates from wafer fabrication process. That
can be modeled as an additional stochastic process with a long correlation distance.
Consequently, with the above assumptions the variation of parameter P can be
expressed as [199]
AP2
(P ) =
+ S P2 D 2
WL
2
(4.18)
where AP is area proportionality constant for variation of P parameter, W and L are

width and length of rectangular devices, SP is constant of variation of P parameter with
distance and D is spacing distance.
Such definition of random matching excludes batchto-batch or wafer-to-wafer
variations.
The above equation illustrates two main rules of matching:
the devices with the larger area WL match better,
the devices matched should be placed at small spacing distance D.
Increase of the size of the devices is always a good option for better matching, but
is often in opposition to the high speed and small chip area requirements. Therefore,
matching sensitive devices should be found at first in the circuit and only then a compromise between matching and other design constraints should be considered.
4.3.1 Mismatch parameters of MOS transistors

There are three main parameters of the variations which cause the mismatch of
MOS transistors at DC and low frequencies: threshold voltage VT, body factor and
110
current factor . The threshold voltage of the NMOS transistor (with long and uniformly doping channel) built on p-type substrate can be expressed as [147]
VT = VT 0 +
( 2
+ VSB 2 F
(4.19)
with VT0 and equaling
VT 0 = MS + 2 F
4q Si F N a
Qox
+
Cox
Cox
(4.20)
2q Si N a
Cox
(4.21)
where VT0 is threshold voltage for VSB = 0, VSB is source-bulk voltage, is the body factor
of MOS transistor, F is Fermi potential in the bulk, MS is gate-semiconductor work
function difference, Na is channel doping density, Qox is fixed oxide charge density, Si
silicon permittivity, Cox is gate oxide capacitance per unit area equaling ox/tox , ox is
silicon dioxide permittivity and tox is oxide thickness.
Let us analyze the contributions of possible errors to the threshold voltage mismatch:
because MS and F have logarithmic dependence on doping in the substrate [23], they
can be considered as constants with no contribution to any mismatch,
in the well controlled process the oxide thickness tox is reproducible and its contribution to the variation of VT can be ignored,
the density of fixed oxide charges Qox in the modern VLSI MOS processing is much
smaller than the depletion charge density equal to
4q SiF N a (see the third and
fourth term in equation (4.20)), and it can be said that the variation of channel doping
level Na is a dominant source of mismatch,
the variation of body factor (caused mainly by the variation of the doping level Na
and oxide thickness tox) is important only for the transistors bias with non-zero VSB voltage.
In case of the PMOS transistors, additional term equal to qDI /Cox should be added
in equation (4.20), where DI is the threshold adjust implant dose [207]. The main factors
causing mismatch of the threshold voltage and the bulk factor satisfy the assumptions
(in the first order approximation) of the above model of random matching. According to
equation (4.18) the variance of VT0 and can be written as
2 (VT 0 ) =
( ) =
2
2
AVT
2
2
0
+ SVT
0D
WL
A2
WL
+ S2 D 2
111
(4.22)
(4.23)
where W and L are width and length of MOS transistor, AVT0 is area proportionality constant of variation of threshold voltage VT0 , SVT0 is constant of variation of threshold voltage VT0 with distance, A is area proportionality constant of variation of body factor
and S is constant of variation of body factor with distance.
The current factor is given by
= Cox
W
L
(4.24)
The mobility , oxide capacitance per unit area Cox and the dimensions W and L of the
MOS transistor are all independent. For example, the definition of width W and length L
is determined by different steps in different conditions during IC processing, so they
may be treated independently. With that assumption in mind the variance of current
factor can be expressed as
2 ( ) 2 ( ) 2 (Cox ) 2 (W ) 2 (L )
=
+
+
+
Cox2
W2
L2
2
2
(4.25)
Physical effects responsible for the variation in the mobility and oxide capacitance can be treated according to equation (4.18), while the variation in transistor dimensions requires some additional comments. Variations of the width and length originate from the variations in photolithographic process. From one dimensional analysis of
random error due to the edge roughness it can be inferred that 2(L)1/W and
2(W)1/L. The equation (4.25) can be rewritten as
2
AW2
AL2
2 ( ) A ACox
=
+
+
+
+ S 2 D 2
2
2
2
WL WL W L WL
(4.26)
where A, ACox, AW, AL are technology dependent constants and S is constant of variation
of current factor with distance.
The paper [199] suggests that for W and L large enough, the above equation can
be approximated as
112
2 ( ) A
+ S 2 D 2
2
WL
(4.27)
where A is area proportionality constant of variation of current factor .

Some other authors [207, 210] come to the conclusion that the relative variation
of current factor should be scaled with 1/(W2+L2) rather than with 1/(WL). Moreover, the
experimental results [211] show that even for equal area transistors, shorter channel
lengths and wider channel widths result in poorer matching than longer channel lengths
and narrower channel widths.
The variation of gate oxide capacitance is a common factor in VT and , so one
could expect the correlation in the mismatches in VT and . However, both the theoretical and experimental values of the correlation coefficient are close to zero [207], so for
the first approximation it can be assumed that the variations of VT and are almost independent.
4.3.2 Transistor matching in various processes

Looking into the specifications of different processes, the most common approach
is that the vendors specify only threshold voltage variation AVT0 and current variation A,
without providing the distance dependent factors (SVT0 and S) or matching parameters
for body factor (A and S ). Instead, AVT0 and A are sometimes specified for different
VSB values and different spacing between MOS transistors.
The general tendencies which are common for many n-well CMOS processes are
the following [203]:
matching of VT and is often better in case of NMOS transistors compared to the
(compensated n-well) PMOS ones,
practical benchmark for AVT0 is 1 mVm per 1 nm of oxide thickness (except for deep
submicron technologies),
rule of thumb for A is about 2 %m,
the relative effect of the increased distance between the matched devices is significant
only for large area devices with a considerable spacing.
The examples of threshold voltage matching for NMOS transistors in 180 nm CMOS
process is shown in Fig. 4.8 [204].
By scaling the technology down we not only change the minimum dimensions of
the transistor but also reduce the oxide thickness. Let us consider the VT matching for
NMOS transistors (for VSB = 0). Mismatch of VT is dominated by the variation in channel
doping level Na and can be expressed as [212]:
(VT ) const
tox 4 N a
WL
(4.28)
113
Improvement of matching due to the thinner oxide layer is slowed down by the increase
of the doping level under the oxide. The more detailed analysis requires a more accurate
model of statistical dopant fluctuation of MOS transistors given by Stolk, et al. [213].
Fig. 4.8. Threshold voltage matching for NMOS transistors in 180 nm CMOS process. The W/L [m/m]
ratio of the devices has been included. Errors bars represent 99% confidence interval [204] 2002, IEEE.
For the PMOS transistors the situation in VT matching is more complicated and
strongly depends on the technology used. Table 4.3 presents some data for the different
CMOS technologies.
Technology /
oxide thickness
0.8 m/15 nm
0.6 m/12 nm
0.25 m/4.4 nm
0.18 m/3.2 nm
0.15 m/3.3 nm
0.12 m/
0.1 m/
90 nm/
65 nm/
Table 4.3 Matching of VT for NMOS and PMOS for different technologies.
AVT for NMOS
AVT for PMOS
Reference
[mV m]
[mV m]
[168]
10.7
18
[168]
11.0
8.5
[200]
3.6
[201]
3.0
[201]
3.6
[205, 203]
3
[201]
2.5
[202]
~3.8
[214,
215]
3.3
Statistical dopant fluctuation is a serious limitation for minimum size devices in

deep submicron process. However, the dopant fluctuation alone can not explain the observation why 1 mVm per 1 nm of oxide thickness benchmark can not be maintained
in these technologies. There are new effects which appear and must be taken into account, namely [201, 202, 203, 205, 216]:
polysilicon gate morphology in thin oxides becomes important,
smallest devices (near the lithography limits) suffer from significant litho spread,
114
pockets or halo implants cause high impurity concentration in the space charge region
and strongly influence the matching in short channel devices, etc.
It should be stressed that even if technologies belong to the same technology node, some
of them provide acceptable matching, while others are much worse. The matching depends on process steps and, as it is shown in [201, 216] by careful process optimization,
it can be significantly improved (e.g. for 180 nm CMOS process the threshold voltage
coefficient was reduced from around 8 mVm to 3 mVm [201]).
By scaling the technology down, the improvements in variation are very slow,
i.e. for NMOS transistors scaled down to the oxide thickness from 50 nm to 12 nm the
A parameter is still around 2 %m [203]. For submicron technologies for a well engineered and controlled process, the A seems to hover around 1 to 2 %m [205].
4.3.3 Current matching in MOS transistors

In the analog circuits, the transistors operate mostly in the saturation region in
strong inversion where the drain current is given by
I DS =
(VGS VT )2
(4.29)
As the correlation coefficient between mismatch in VT and almost equals zero, the
relative source-drain current IDS mismatch may be expressed as
2 ( I DS )
2
I DS
=4
2 (VT )
(VGS VT )2
2 ( )
2
(4.30)
At a low value of (VGSVT ), the dominant factor in the mismatch comes from the variance of VT, while for the higher (VGSVT ), the variance of current factor dominates.
Better matching is obtained at the higher difference (VGSVT), which means the higher
current. At the low value of VGS , the mismatch does not go to infinity [203,217], because transistors enter the weak inversion region where square law model (see equation
(4.29)) is no longer valid and ID depends exponentially on VGS
I DS = I D 0
q(V VT )
W
exp GS
L
ns kT
(4.31)
where ID0 is a process dependent parameter. Calculating the relative source-drain current
IDS mismatch in weak inversion one obtains
( I DS )
I DS
115
(VT )
(4.32)
ns kT q
The subthreshold slope factor ns is usually about 1.1 to 1.3. From above formula for
example for (VT) 5 mV, T = 300 K and ns 1.2 one obtains (IDS)/IDS = 16 %.
4.3.4 Random matching in circuits

One of the main requirements for practical completion of a multichannel VLSI
chip is the uniformity of analog parameters for all channels. The spread of parameters as
gain, offset, cut-off frequency, noise, etc., should be minimized to the acceptable level
specified by an application. The spread of these analog parameters depends not only on
the geometry of the layout, but also on the bias conditions. Solutions with the possibility
of tuning some of these analog parameters for each channel independently are also possible [44, 150], but they cost an extra area of silicon and some additional complications
of chip architecture.
(a)
(b)
Fig. 4.9. Mismatch in circuits: a) differential pair, b) current sources.
To illustrate the dependence of matching of analog parameters on the bias conditions, let us consider two exemplary circuits shown in Fig. 4.9, a differential pair and
a current mirror which are often used in analog circuits. For a differential pair, both the
input transistors and the load resistors suffer from mismatching such as VT, , R.
The device mismatches are incorporated as VT1 = VT, VT2 = VT VT, 1 = , 2 = ,
R1 = R, R2 = R R. When both transistors operate in strong inversion, the total random
offsets Vosr referred to the input can be expressed as [210]
116
Vosr = VT +
VGS VT
2
(4.33)
The equation (4.33) shows that random offset depends both on device mismatches
and bias conditions. The contributions of mismatches R and increase with the transistor overdrive (VGSVT ), while the threshold voltage mismatch VT is directly referred
to the input. To minimize the offset, it is desirable to use low values of (VGSVT ) by
lowering the bias current or increasing the W/L ratio. A random mismatch results not
only in a random offset but it also reduces the common-mode rejection ratio of the differential amplifier [218].
Let us analyze the mismatch of the nominally identical current sources M1 and
M2 shown in the Fig. 4.9(b). Let us assume that both transistors work in strong inversion with the same drain source voltage VDS1 = VDS2. The device mismatch is incorporated again as VT1 = VT, VT2 = VTVT, 1 = , 2 = , that results in different currents
IDS1 = IDS and IDS2 = IDS IDS. The relative variation of the output currents can be written
as [210]
I DS
2
=
VT
I DS
VGS VT
(4.34)
To minimize the random current variation the overdrive voltage (VGS VT ) should
be maximized. And that is in the opposition to the rule of minimizing the random offset
in the differential amplifier (see equation (4.33)). In practice there is also a systematic
current variation for the case of VDS1 VDS2, coming from the finite output resistance of
the current source.
4.3.5 Layout rules for good matching

Symmetry is the main rule in the layout to improve matching. Symmetry means
not only the same layout of matched devices, but also identical temperature, bias, parasitics, metal coverage and the surrounding environment.
There are several layout design rules that help maintain the symmetry.
The same bias and signal delay. Asymmetry in the circuit configuration or bias
point is the source of systematic offset. It should be realized that the parasitic components as resistance of paths or contacts and parasitic capacitance modify the electrical
scheme of the circuit. Voltage drops on parasitic resistance of the power supply lines, in
the source of a differential pair, on the voltage reference distribution lines, etc., can be
devastating. The unwanted voltage drops can be minimized by proper metal width, extra
contacts and using the star connection to maintain symmetry of current paths. In digitally controlled analog circuits particular attention should be paid to the clock and signal
117
skew due to parasitic resistance and capacitance [219]. Sometimes manual correction
must be made in electrical scheme for the proper evaluation of these effects.
Identical temperature. The current of the MOS transistor or the resistor value
depends on temperature. For the MOS transistor, the main temperature dependent parameters are the mobility and the threshold voltage VT. Near room temperature, the
temperature coefficient for the threshold voltage is in the range of 0.53 mV/C [163],
while the mobility depends on the temperature as T 1.5 [23]. So, the matched devices must operate at the same temperature, which does not pose a problem if the power
dissipated by each block on the chip is low. Otherwise, one should identify the large
power sinks on the chip and the distribution of isotherms on the chip. If possible, the
sensitive circuits should be placed at the largest possible distance from power blocks
and realigned on the same isotherms.
The same orientation. IC processes exhibit anisotropy which results from certain
processing steps or lattice orientation and has great influence on matching. For that reason, it is important how the devices are oriented on the layout relative to one another
and what the relative directions of the current flow are. Comparative measurements of
the standard deviation of current factor matching for transistor placement rotated by
90 degrees show that the matching is several times worse than in case of parallel transistor placement [199]. Because the threshold and substrate factor mismatch is identical for
the rotated and parallel placements, the local mobility variations can be a possible explanation for the rotation dependent mismatch. In case of parallel placement, the better
matching is for the transistors with the same direction of current flow. This is due to
the subtle effect called gate shadowing [220]. To avoid the channeling effect during
the drain/source ion implantation, the implant beam (or the wafer) is tilted by 79. For
that reason one obtains small asymmetry between the source and drain diffusion resulting in different capacitive coupling as well as different transconductance between the
transistors with opposite current directions.
Common centroid layout. Because of the gradients in temperature, oxide thickness and other process variations, it is difficult to ensure symmetry for large transistors.
To reduce these global errors, the common centroid layout is the most effective solution,
however, routing of interconnections is considered to be a complex process. Also, it is
important to keep the symmetry in the routing of interconnections on the layout and to
avoid differences in the parasitic resistance or capacitance [190, 221].
Unit cells. All devices to be matched should have the same area to the perimeter
ratio. In case of two devices of different dimensions, it is a good practice to base the
layout of both of them on the same unit cell, which can be a simple capacitor, resistor,
transistor or a more complicated structure such as a current cell [222]. Let us consider
the DAC using the binary weighted current source architecture. After setting the minimum dimension of the unit current source according to the required accuracy and
matching parameters of the technology [223], each binary weighted current source is
constructed by putting the appropriate amount of N unit current sources in parallel (for
example a source of weight equaling 16, is implemented as 16 unit cells together). To
minimize the effect of linear gradient, the cells which switch simultaneously in a binary
118
array are arranged in common centroid geometry [224]. Apparently, the use of only
translated copies is allowed with no rotation or mirroring. Excellent examples of the unit
cells use can be found in [196, 225].
The same surrounding. Adjacent structures have a systematic influence on the
matched devices, so symmetry must be applied not only to the devices under consideration but also to their surrounding environment. Each line of metal, diffusion, polysilicon
etc., has width variation at the IC processing. There is also a line width variation dependent on the location of adjacent structure. This is the proximity effect due to the
variable light interference in exposure and to the variations in chemical flow for photoresist, developers and etchants [226]. So, the environment should be identical outside
of matched to the distance of at least 3050 m and the matched devices should be
infinitely far away from the crystal edge. The remedy for that problem is to surround
the matched devices with dummy structures. The dummy device should be of equal
nature as the matched device, for example for matched transistors (cells) the dummy
structures are also transistors (cells). How many rings of dummy cells are required depends on the requested accuracy and technology [225]. Obviously, the course of this
solution costs an extra area of silicon. However, there is often not enough space for
dummy structures. Then a designer should consider what kind of proximity effect is
important in their design and follow the rules specified by a technology vendor. For
example, taking into account the well proximity effect [227] the recommendation are the
following:
keeping the same transistor orientation to the well edge (preferable direction is
source/drain perpendicular to the well edge),
placing matched components at the equal distance (> 3 m) from the well edge.
Metal coverage. Symmetry is also important in metal coverage. The asymmetrical metal lines over identical MOS transistors which cover one of the transistors (partially or completely) can be disastrous for matching performance. The papers [228, 229]
show that the shape and the degree of metal 1 overlap influence the relative dramatically
mismatch current. The rule is fairly straightforward: it is ideal to avoid metal lines over
matched components. Sometimes it is impossible, for example for high accuracy DAC
[225], and then it is better if the matched cells are covered by higher metal layers than
metal 1, and to obtain the best symmetry all of them should be covered with the same
metal layer.
4.3.6 Matching on multichip modules

After fabrication and cutting a wafer, the integrated circuit is glued, bounded and
packaged. Packaging introduces not only parasitic components (resistance, capacitance,
inductance), but also is the source of mechanical stress and heat non-uniformity distribution that adversely affects the matching. It is especially important for multichannel systems, where several identical chips are mounted together on the same custom design
mulitlayer board. So, the design of such a board and the process of mounting chips
should be handled with a special care in order to limit all the above effects [230].
119
The mismatch among identical components from different dies, wafers or batches
is always bigger than among components placed on the same chip. As a result, the
spread of channel parameters inside the chip is small, while the differences from chip to
chip on the module are too large to be accepted. The solution is to design on each chip
the correction DACs for tuning the gain, passband, discriminator level, etc., and implement the local address set during bonding a die on a module. Then, after the calibration
measurements, the correction DACs are loaded one by one. That protocol guarantees the
cancellation of unwanted offsets from chip to chip, and ensures proper work of the
whole module.
4.3.7 Mismatch simulation using the Monte Carlo analysis

The evaluation of the matching performance of a design can be carried out by
employing the Monte Carlo simulation [231]. In this way, one can quickly estimate
channel-to-channel matching performance, identify critical devices and, in consequence,
optimize their dimensions or bias conditions for them. It must be remembered that
matching parameters specified in usual way (for example for transistors), are valid under
certain assumptions (common centroid layout, identical surrounding, no metal crossover, etc.).
Vendors usually provide the Monte-Carlo (MC) models, but occasionally models
for all used transistors types are not complete (e.g. MC models are available for standard
VT MOS transistors, but there are no models for low or high VT MOS transistors) or MC
models are not available at all. In case of MC models unavailability, if measurement
data of matching is available, one can calculate variations of VT0 and for each transistor dimension used in the design. The variations of the threshold voltage and the current
factor can be incorporated into transistor model for each transistor independently as
parameters of the Gaussian distribution of threshold voltage and mobility. In the Monte
Carlo simulations each of these parameters is sampled independently from a given distribution. Since the equations (4.22) and (4.27) specify matching of a pair of devices, the
standard deviation for single devices used in the Monte Carlo simulation should be
smaller by factor 1/2. The Monte Carlo simulation performed for a single channel
gives an estimate of random channel-to-channel matching. However, one should remember that the method described above is only a rough estimation of a possible variation in the circuit because:
during the variation of device parameters, the correlation between device parameters
should be additionally taken into account [232],
the method does not cover long distance systematic effects, which may be important
for multichannel architectures.
Radiation damage
121
5. RADIATION DAMAGE IN SILICON

DETECTORS AND READOUT ELECTRONICS
The effects of radiation damage were observed in 1962 for the first time during
the mission of Telstar 1 telecommunication satellite. Because of the earlier series of
nuclear weapon explosions performed by both the USA and the Soviet Union, radioactivity of the van Allen Belts surrounding the Earth increased significantly.
Telstar 1 crossed these belts several times which caused significant radiation damages in
satellite electronics. Since then the era of intensive research on the radiation damage
started. The radiation damages are important not only for space systems, but also for
nuclear plants, military equipments, high energy particle experiments and other radiation
detection systems in medicine, material science, etc. Radiation damages are usually
divided into two classes. The first one covers the total dose effects, both displacement
damages and ionization damages, while the second class is connected with Single Event
Effects (SEE), caused by high energy particles. Both types of radiation damage effects
122
Radiation damage
are shortly described below taking into account the physic phenomena in silicon and
MOS structure and degradation of parameters of detector and readout electronic components.
5.1. TOTAL DOSE EFFECTS
5.1.1. Displacement damage

A high energy particle can cause displacement of crystal atoms from their lattice
positions. The minimum recoil energy required to remove a silicon atom from its lattice
position is about 25 eV [5]. The displacement damages depend on a particle type, its
mass and energy. All summed energies deposited in a crystal, which has not been used
for a fully reversible process of ionization, are called NonIonizing Energy Loss (NIEL).
The displacement damages are scaled with NIEL. Often, as a reference for a displacement damage 1 MeV neutrons are used. Fig. 5.1 presents relative displacement damages
(to 1 MeV neutrons) vs. energy for neutrons, protons, pions and electrons.
Fig. 5.1. Relative displacement damage for different particles vs. their energies [233].
The displacement damages result in additional energy levels in a silicon band gap.
Some of the displacement damages are not stable and move throughout the crystal. This
movement is strongly temperature and bias depended leading to a complex annealing
behavior.
The main effects of bulk damages in silicon detectors are:
Radiation damage
123
increase of a leakage current because the additional energy levels in a band-gap act as
generation- recombination centers,
change of the net effective impurity concentration (see Fig. 5.2) and change of a detector full depletion voltage (see eq. (2.13)),
increase of charge trapping centers which hold a part of a signal charge for a time
longer than charge collection time which reduces the signal amplitude.
Fig. 5.2. Absolute value of the effective impurity concentration Neff versus fluence up to 1015 n/cm2 [8]
1992, with permission from Elsevier, http://www.sciencedirect.com/science/journal/ ).
In case of integrated circuits the displacement damages are mainly visible in bipolar technologies, because of the lifetime reduction of minority carriers. This lifetime
reduction results in n,p decrease of a bipolar transistor. This effect depends both on total
particle fluence and on technology of the IC - see Table 5.1.
Table 5.1. Changing in DC current gain of bipolar transistors for different technologies* [234].
Technology
DMILL
AT&T
TEKTRONIX
Dose
1.6 1014 neutrons
1.6 1014 protons
1.1 1014 protons
150/30
95/55
95/40
NPN n(pre)/ n(post)
40/25
45/23
PNP p(pre)/ p (post)
*
Data was normalized for the same collector current density 2.5 A/m2
5.1.2. Ionization effects

Ionization radiation liberates charge carriers in SiO2 which finally results in positive charge trapped in oxide and an increase of interface traps at Si-SiO2 border. Let us
consider an MOS structure with p-type bulk (see Fig. 5.3). Average energy needed to
generate an e-h pair in silicon dioxide is about 18 eV. After the charge generation some
of the electron-hole pairs recombine. The mobility of holes and electrons in silicon diox-
124
Radiation damage
ide differs considerably: the mobility of holes ranges from 10-4 to 10-11 cm2/Vs and the
mobility of an electron is about 20 cm2/Vs. Most of the electrons move rapidly towards
the positive bias gate (within a few picoseconds). The remaining holes move slowly
towards Si-SiO2 interface by hopping through localized states in oxide. A fraction of the
holes which reach the interface are trapped there, forming a positive oxide trap charge.
It seems that hydrogen atoms (protons) are likely to be released as "hop" holes through
the oxide or they are trapped near Si-SiO2 interface. The hydrogen ions can also drift to
Si-SiO2 interface where they may react to form interface traps [11]. The charge of interface traps is changed by applying external bias and the interface traps can be negative,
neutral or positive. For PMOS transistors at the threshold, the interface traps are predominantly positively charged, while for NMOS transistors at the threshold the interface
traps are predominantly negatively charged. The number of positively generated charge
oxide traps and interface traps depends not only on total ionization dose (given usually
in rad(Si) or rad(SiO2)), but it also depends on bias conditions, temperature, technology
parameters (especially oxide processing) and dose rate.
Fig. 5.3. Band diagram of MOS capacitor with a positive gate bias. The main processes for radiationinduced charge generation are shown [11] 2008, IEEE.
In case of silicon detectors the ionisation damages cause the increase of detector
leakage current (surface component mainly) and of the interstrip/interpixel capacitance
and they can cause the problem with the proper interstrip isolation in case of a doublesided detector [7, 53, 55].
For the CMOS technology the ionization damages manifest in [7, 10, 170,
235237]:
threshold voltage shift,
transconductance reduction,
Radiation damage
125
increase of the leakage current,

noise increase,
reduction of the breakdown voltages,
degradation of matching parameters,
functional failure.
The degradation of the above parameters influences not only the analog block, but
also the digital circuit (maximum frequency reduction, power consumption increase)
[237].
(a)
(b)
Fig. 5.4. Changes in transfer characteristic of MOS transistors - threshold voltage shift and
transconductance reduction are shown: a) PMOS transistor, b) NMOS transistor.
The problem of ionization damage is slightly different in older CMOS technologies and in new deep submicron technologies. For the threshold voltage shift VT both
the positive charge trapped in oxide and interface traps are responsible according to the
formula
Radiation damage
126
VT =
q
q
N ot
N it
Cox
Cox
(5.1)
where Cox is gate oxide capacitance per oxide area, Not and Nit are numbers of oxide
and interface traps per gate area. In the above equation for the NMOS transistor, the sign
before the term with interface traps is positive, while for the PMOS transistors, this sign
is negative. For the PMOS transistor, the threshold voltage shift is always negative,
while for the NMOS one, the situation is more complex (see Fig. 5.4). In the beginning,
when the positive charged oxide traps dominate, the VT is negative, while later, when
the number of negative charged interface traps increases, the VT becomes more positive. As it is shown in Fig. 5.4, the increase of the interface traps also reduces the transistor transconductance, because of mobility degradation according to the formula [238]
after =
1 + N N it
(5.2)
where after is the mobility after irradiation, N is a semi-empiric fitting parameter in the
range from 0.3510-12 [239] to 5.2610-11 cm2 [240].
In submicron technologies with the oxide thickness below 12 nm the threshold
voltage shift is dramatically reduced (see Fig. 5.5). This is because of electrons which
by a tunneling effect neutralize the trapped holes by recombination.
Fig. 5.5. Threshold voltage shift after irradiation for technologies with different oxide thickness [241-243].
Legend shows the minimum gate length in m in given technology.
The negligible threshold voltage shift (thank to the thin gate oxide) is a big advantage of deep submicron technologies. However, CMOS technologies use also a thick
field oxide. The positive induced charge in this field oxide creates parasitic NMOS transistors. These parasitic NMOS transistors are the sources of additional leakage currents,
both in standard NMOS transistors and between two NMOS transistors with different
Radiation damage
127
biased sources/drains (see Fig. 5.6). To eliminate these parasitic and leaky NMOS transistors a special treatment at the layout drawing is necessary (enclose layout transistors,
additional guarding, etc. - these mitigation techniques are discussed in Chapter 5.3).
(a)
(b)
Fig. 5.6. Radiation damages create leaky parasitic NMOS transistors: a) on the edges of standard NMOS
transistor, b) between NMOS transistors.
5.2. SINGLE EVENT EFFECTS

Single event effects are caused by a high energy ionizing particle, which crossing
the integrated circuit, creates a lot of e-h pairs. The charge generated by such a particle
can results in:
soft errors like Single Event Upsets (SEU), Multiple Bit Upsets (MBU), Single Event
Transient (SET) and Single Event Function Interrupts (SEFI) all these errors are reversible and non-destructive,
128
Radiation damage
hard errors like Single Event Latchups (SEL), Single Event Snapbacks (SES), Single
Hard Errors (SHE), Single Event Gate Ruptures (SEGR) and Single Event Burt-Out
(SEBO) - these errors are non-reversible and can be destructive.
A comprehensive overview of the above-mentioned SEE can be found in [7, 70,
244]. Let us consider the SEU as an example of the most popular SEE. A particle crossing, for example SRAM memory (shown in Fig. 5.7), creates charge along its track.
Linear Energy Transfer (LET) is a measure of the energy transferred to material as an
ionizing particle travels through it. If the linear energy transfer is higher than the critical
LET, the node is vulnerable to the SEU and the memory state can be changed from 0 to
1. The critical LET is lower for modern technologies, where the power supply voltage
and capacitance of the storage node are much lower than in older technologies.
Fig. 5.7. SEU in SRAM memory cell.
The susceptibility of Silicon On Isolator (SOI) technologies to the SEU is much

lower than in CMOS technologies. The absence of the conducting path underneath MOS
transistors completely eliminates the SEL. However, after an exposure to ionizing radiation, a radiation-induced charge is trapped in buried oxide of an SOI transistor. The
trapped charge can invert the back-channel interface, creating an additional leakage
current [11].
5.3. RADIATION TOLERANT DESIGN OF READOUT

ELECTRONICS
There are two main steps in creating a radiation tolerant design:
choosing the radiation hard technology,
hardening the design by appropriate choice of circuit/system architecture and special
treatments on the layout level.
Radiation damage
129
The dedicated rad-hard technologies are relatively expensive and not so easily accessible as a commercial process. From this point of view, the natural choice is to use
deep submicron technologies where the threshold voltage shift (due to ionizing damages) is negligible. However, there are two effects which must still be considered to
make the design radiation tolerant. The first one is the accumulation of positive charge
in field oxide which creates the parasitic leaky NMOS transistors (see Fig. 5.6). The
second effect is the problem with increased sensitivity of modern technologies to single
event effects, because of small capacitances in storage nodes and small power supply
voltages (see Fig. 5.7).
One of possible solutions for the leaky parasitic NMOS transistors with thick field
oxide is drawing the layout of NMOS transistors in so-called enclosed gate geometry
and putting them inside p+ guard rings. No special treatment is required in case of
PMOS transistor. A simple layout of an inverter using enclosed layout transistor (ELT)
of NMOS type and standard layout of PMOS transistor is shown in Fig. 5.8.
Fig. 5.8. Simplified layout of inverter: NMOS enclosed gate transistor in a p+ guard ring and standard
PMOS transistor.
However, the enclosed layout NMOS transistors have some limitations, namely
[5, 237, 245]
the device should be properly modeled,
small ratio W/L below ~2 is not possible and this for example limits the possibility of
building good current sources based on NMOS transistors,
capacitances on drain and source nodes are different and this must be taken into account at the designing stage,
larger area of an ELT transistor - because of the transistor layout and necessary
p+ guard rings (for example, two series connection of NMOS transistors requires additional p+ guard rings),
130
Radiation damage
in CMOS gates - because NMOS ELTs are larger (compared to standard transistors),
and larger PMOS transistors are required for good balance - which results in larger area
and increases dynamic power consumption.
The following steps are recommended with view of the SEE [5, 237, 246248]:
eliminate completely the "forbidden" state in a state machine to omit a permanent
lockup,
increase the critical LET for the SEU by enlarging the width of transistors driving
a sensitive node, increasing capacitive load at this node, or by adding feedback resistance between cross-coupled inverters,
using correction logic (e.g. Hamming codes) or self-correcting triple redundancy cells
(see example in Fig. 5.9); however, using real redundancy is a very costly solution due
to the silicon area, and it should be used only in the most important blocks of the IC.
Fig. 5.9. D flip-flop with majority voting, self-recover system and information bit of SEU event [248]
2002, IEEE.
Examples of multichannel counting IC
131
6. EXAMPLES OF MULTICHANNEL COUNTING

IC FOR X-RAY APPLICATION
The most advanced solutions for the multichannel readout architecture of silicon
strip or pixel detectors are known from the instrumentation for particle physics experiments [24, 48, 49, 70, 74, 83, 249253]. The intensive research of groups working on
such detectors and readout electronics were the inspiration for the application of similar
solutions in X-ray imaging techniques used in solid state physics, material science,
medicine, etc. Especially attractive for these applications are multichannel systems with
a detector of high granularity and a readout electronics working in a single photon
counting mode with a large dynamic range as they are able to cope with high intensity of
X-ray radiation. The examples of this type of mulichannel electronics are presented in
this chapter.
132
6.1. REQUIREMENS FOR MULTICHANNEL COUNTING

SYSTEMS
Depending of an X-ray imaging application, there are different requirements for
the detector type and granularity, linear range of the front-end electronics and high count
rate performance per single channel.
Let us take, for example, diffractometry measurements often used in material science, where:
the energy of X-ray photons for this application is in the range of 5 keV up to 20 keV,
a detector with a strip/pixel pitch of about 50-100 m ensures sufficient position resolution,
finally a count rate up to 12 Mcps/channel is sufficiant for most diffractometry experiments.
A standard silicon detector with 300 m thickness guarantees absorption of nearly all of
the 8 keV photons, but only about 26.7 % of 20 keV X-rays.
For medical imaging, the used photon energy is higher (see Table 6.1) and the detector material with high Z is preferable. The requirement for count high rate is up to
1 Gcps/mm2 (computer tomography). Taking into account the maximum intensity of
input pulses per readout channel, single photon counting systems are still far behind
detector systems working in integration readout mode.
Table 6.1. General specification for X-ray and computed tomography [254] 2009, IEEE.
Computed
Mammography*
General X-ray
tomography***
radiography**
Count rate (photons/mm2s)
typ. 109
5107
106 to 5108
Equiv. current per pixel (nA)
0.2
0.03 - 20
2000
typ. 85
typ. 150
typ. 1000
Pixel size (m)
Detector area (m2)
0.072
0.12
0.14 (128 slices)
Highest energy (keV)
28 40
70 120
80 140
*
with 28 kVp, 144 mA and 65 cm SDD (Source-to-Detector distance)
**
70 - 120 kVp, 2 - 300 mA, and 1.5 m SDD
***
140 kVp, 400 mA, 1.04 m SDD, with filtration of 1 mm Al, 2.5 mm Be, 1 mm Oil, 1.2 mm Ti
and 2 mm Teflon
Let us concentrate on diffractometry applications and compare the requirements

for front-end electronics with tracking applications in HEP experiments. In both cases,
the silicon detectors with a similar granularity are used. There are, however, several
differences between the HEP and low energy X-ray applications. In case of HEP experiments, the charge signals from detector are about 10 times higher than in applications for low energy X-ray imaging. A minimum ionization particle produces about
23000 e-h pairs crossing 300 m thick Si detector, while the 8 keV photon generates
only about 2200 e-h pairs. Because of low amplitude of input signals (in low energy
X-ray imaging), the noise requirements and the matching performance are more de-
133
manding. Additionally, HEP experiments are synchronous thus trigger in such system is
available. In X-ray imaging, the input pulses have the stochastic character with the Poisson distribution in time.
Single photon counting systems often use a binary readout scheme in each readout channel. From the point of view of the ASIC design, the binary readout architecture
means that a multichannel integrated circuit should be able to amplify and filter small
signals from the sensor, perform amplitude discrimination and store the data in binary
form on the integrated circuit in each channel independently at the same time. Such architecture provides fully parallel signal processing including data storage from all sensor
elements. And this is suitable for the high count rate applications, since the amount of
data to be handled is already minimized in the front-end ASIC.
Although in the binary readout architecture the front-end channel is ended with
a discriminator, the signal-to-noise ratio remains one of the most critical problems to be
solved. A typical plot of a number of counts at the discriminator output as a function of
threshold voltage level is shown in Fig. 6.1. For low threshold values (in Fig. 6.1 below
30 mV), a rapid increase of counts is observed. This is due to the noise which for low
threshold level switches the comparator on and off and contributes to the total number of
counts.
Fig. 6.1. Total number of counts at the discriminator output vs. threshold level for a given acquisition time.
By differentiating the total number of counts vs. the threshold level, one obtains
what is called pulse height spectrum shown in Fig. 6.2(a). The noise and the signal
smeared by the noise are clearly visible in Fig. 6.2(a). Sufficient separation between the
noise level and the signal level is required in order to provide high detection efficiency
and limit noise count rate. For a system with white input noise and a first order bandpass filter, the noise count rate at the comparator output is given by the Rice formula
[255]
V 2
f n = f 0 exp TH 2
2 n
(6.1)
where f0 is noise count rate at zero threshold level, VTH is comparator threshold, n is
voltage noise rms at the comparator input.
134
(a)
(b)
(c)
(d)
Fig. 6.2. Pulse height spectrum for binary readout architecture for: a) reference channel, b) channels with
different gains, c) channels with different offsets, d) channel with a crosstalk problem. In these cases setting
of the common threshold voltage is impossible.
According to the Rice formula (6.1), in the counting system, we should be able to
set a threshold voltage in the discriminator at (3-5)n, where n is a voltage noise rms
at comparator input. Then, the registration of low level signals with minimizing rate of
false noise hits is possible. However, setting such a low value of the threshold for all
channels (in a multichannel ASIC) may be impossible, if we have problems with chan-
135
nel-to-channel matching of analog parameters (gain, offset), or with the switching noise.
Various possible amplitude distributions of noise and signals in the channel affected by
mismatch and crosstalk are illustrated in Fig. 6.2 (b)(d).
Another parameter crucial for various practical applications is a possible operation of the detector with high intensity of X-ray radiation. Taking into account a fully
parallel architecture of the readout system (including counters which serve as memory
buffers), the counting rate considered for the total area of a detector depends on the following:
detector segmentation,
maximum count rate of a single channel.
Detector segmentation is limited mainly by a charge sharing effect [33]. Regarding the
counting rate limit for a single readout channel, a peaking time and a pulse width must
be shortened in a shaper stage and possible effects of pulse pile-up should be eliminated
(by using pole-zero cancellation techniques, avoiding AC coupling circuits between the
stages or using base line restorers/holders). However, a very short peaking time often
means higher noise, while with the absence of AC coupling between stages
(CSAshaperdiscriminator), DC offsets propagate.
6.2. ASIC FOR STRIP DETECTORS

Many electronic laboratories run programs to develop the multichannel binary
readout architecture for low energy X-ray imaging. Some exemplary ASICs for such
applications are listed in Table 6.2. The ASICs consist of 16, 32, 64 or even 128 channels with the power consumption usually below 5 mW/channel. In most cases, when
connected to short strip silicon detector (1-2 cm long), they achieved noise below
200 e rms. The fastest ICs can process up to a few Mcps/channel. Two of these chips,
namely CASTOR [256,257] and DEDIX [152, 258], are described as examples below.
Reference ASIC name
[259]
[257] - Castor 1.0
[260]
[261] - RX32
[262]
[263]-VATAPG
[264]-Mythen
[152] - DEDIX
[150] - RG64
Table 6.2. Examples of counting IC for a strip detector used in X-ray imaging
Count
Power/
Energy
No. of
Peaking
Noise
rate/
channel
window
channels
time
[e rms]
channel
[mW]
[ns]
[Mcps]
100
200 (Cd =1-3pF)
1
no
16
850
0.1- 0.2
3.8
no
32
60+17Cd
a few 100
40 (Cd =1.3pF)
0.2
no
16
700
155 (Cd =2.5pF)
0.1
2.5
no
32
28
4.5
no
64
225+45Cd
2000
no
128
88+22Cd
240 (Cd = ~1.5pF)
1.0
no
128
160
110 (Cd =1pF)
1.0
5
yes
64
75
126 (Cd =1pF)
2
5
yes
64
136
CASTOR IC
The CASTOR chip (Counting and Amplifying SysTem fOr Radiation detection)
was one of the first multichannel mixed-mode ASIC working in a single photon counting mode for X-ray application and optimized for silicon strip detector [256, 257].
CASTOR 1.0 version contained 32 channels and was fabricated in 1.2 m CMOS technology. The single channel consisted of a charge sensitive amplifier, an RC-CR shaper,
a discriminator and a 16-bit ripple counter (see Fig. 6.3). It used a "classical" architecture with AC couplings between the CSA-shaper and shaper-discriminator stages to
avoid offsets propagation. Resistors in the CSA, shaper feedbacks and in the AC coupling at the discriminator input are realized as simple MOS transistors with controlled
gate potentials. The CSA and shaper cores are based on folded cascode topology. The
CSA input transistor is optimized for input capacitance of 5-10 pF and has dimensions
of W/L = 1000m/1.5m with a transconductance of 5.2 mS (for CSA bias current of
1 mA). The CSA feedback capacitance is 200 fF, while the effective feedback resistance
exceeds 100 M. For the peaking time of 850 ns, the noise is ENC = 60+17Cd e rms
with the maximum counting rate up to 100-200 kcps/channel. The discriminators have
a common threshold for all channels. To minimize the discriminator offsets to a few mV
input, transistors (in discriminator differential pair) have the size of
W/L = 720m/1.5m. The channel gain is 180 mV/fC with the power consumption of
3.8 mW/channel.
Fig. 6.3. Block diagram of CASTOR channel (reprinted from [257] 1997, with permission from Elsevier,
137
DEDIX IC
DEDIX IC (Dual Energy Digital Imaging of X-ray) has been developed at the
AGH UST Cracow, Poland as a fast readout ASIC for silicon strip detector [152]. The
chip comprises six basic blocks (see Fig. 6.4(a)): 64 analog front-end channels,
264 counters with RAM, an input-output block, a control command decoder, control
DACs and a calibration circuit. The ASIC is designed in 0.35 m austriamicrosystems
CMOS process and the total layout area is 3900 m 5000 m. The block diagram for
a single channel is shown in Fig. 6.4(b). Each channel consists of a charge sensitive
amplifier with a pole-zero cancellation circuit, a shaper CR-(RC)2 with a peaking time
of 160 ns, two discriminators and two independent 20-bit counters. All stages are DC
coupled.
(a)
(b)
Fig. 6.4. Block diagram of: a) DEDIX chip, b) single channel [152] 2007, IEEE.
138
The CSA is based on the folded cascode configuration (see Fig. 6.5) with
a PMOS input transistor M1 with W1/L1 = 600m/0.45m. The transconductance of M1
is gm1 = 9.45 mS for the current IDS1 = 0.9 mA and gm1 = 12.17 mS for IDS1 = 1.47 mA.
The feedback loop of the CSA is formed by the capacitor Cf of 100 fF and the channel
conductance of the array of ten PMOS transistors Mf0Mf9 with Wf/Lf = 0.4m/10m
connected in series. The pole-zero cancellation circuit consists of a capacitor Cd = 24 pF
and twenty PMOS transistors Mpz0Mpz19 of Wpz/Lpz = 0.4m/10m connected in
parallel. For negligible detector leakage current, the transistors in CSA feedback and in
PZC circuit are working in the triode region. The gates and sources of the transistors
Mf9 and Mpz0Mpz19 are connected together. This enables setting the effective CSA
feedback resistance RMf in a wide range (from tens of M to tens of G) ensuring
proper functioning of the PZC circuit even for high rates of input pulses which generate
a DC voltage shift at CSA output.
Fig. 6.5. Scheme of charge sensitive amplifier with PZC circuit [152] 2007, IEEE.
By the use of the PZC circuit, undershoots can be eliminated after the differentiating filter stage, which are the results of the long time decay of pulses at the CSA output.
However, this results in DC coupling between CSA input and discriminator inputs. The
offsets propagate from CSA input to discriminator inputs and result in a spread of the
effective discriminator threshold in an ASIC multichannel.
The PZC structure with the tracking system is followed by the second-order filter
(shaper) with a peaking time of 160 ns. The simplified scheme of the filter is shown in
Fig. 6.6. The capacitors Csh1 = 500 fF and Csh2 = 2 pF are based on poly1-poly2 structure,
while for the resistors Rsh1 = 200 k, Rsh2 = 30 k and Rsh3 = 12 k are implemented
using high resistivity poly layer. The OTA stages are based on a folded cascode amplifier with the input transistors of Wsh1/Lsh1 = 88m/0.45m and the bias current about
6.5 times smaller than in the CSA stage. The OTA gain is about 1700 V/V. The implemented buffers separate the feedback of OTAs from the next stages.
139
Fig. 6.6. Simplified scheme of a DEDIX filter [258].
The shaper signal is fed to two discriminators (described earlier in chapter 3.6.1).
The threshold voltages for two discriminators in a single channel are set independently,
but are common for all 64 channels of the ASIC. As the signal processing chain is
DC-coupled from the CSA input up to the discriminator inputs, a DAC correction
(working in each channel independently) is necessary to minimize the effects of the DC
level spread at the discriminator inputs.
The examples of the X-ray spectra measured with a 64-channel DEDIX chip with
the correction circuit ON and OFF are shown in Fig. 6.7.
(a)
(b)
Fig. 6.7. Spectra of Pu-238 radioactive source and Cu K line measured with silicon strip detector and
DEDIX IC: a) correction OFF, b) correction ON [152] 2007, IEEE.
140
The spectra have been obtained by scanning the discriminator threshold and
measuring the integral distribution of pulse amplitudes. The differences of intensity in
different channels are due to small dimensions of X-ray source (different X-ray intensity
across the strips of the detector). The effective threshold voltage spread calculated to
CSA input is below 7 e rms.
The DEDIX chip is able to work properly up to the rate of 1 Mcps per channel for
statistically distributed photons from the X-ray tube without gain, offsets and noise degradation. The exemplary results obtained using 8 keV photons from X-ray tube are
shown in Fig. 6.8. The plots show the DEDIX high count rate performance for different
settings of CSA feedback resistance RMf.
(a)
(c)
(b)
(d)
Fig. 6.8. High count rate characteristic of DEDIX chip: a) registered counts vs. input counts for different
threshold settings, b) gain, c) DC level shift, d) noise vs. average rate of input pulses [152] 2007, IEEE.
The chip uses two power supply voltages: 2.2 V (analog parts) and 3 V (discriminators and digital blocks), and consumes about 5 mW per channel. This IC is mainly
used in diffractometry measurements. The main chip parameters are summarized in
Table 6.3.
141
Table 6.3. Summarized performance of DEDIX IC [152] 2007, IEEE.

Parameter
Technology
Size
Number of channels
Supply voltage
Power dissipation per channel
Peaking time
ENC (Tp = 160 ns, Cdet = 1 pF)
Gain
Effective threshold spread calculated to the input
Number of discriminators per channel
Counters capacity
Communication:
- control
- data output
CMOS 0.35 m
3.9 mm 5 mm
64
2.2V /3 V
5 mW
160 ns
110 e rms
54 V/ e
7 e rms
2
20-bit
LVDS standard
three state 8-bit bus
6.3. SOLUTION FOR PAD DETECTORS AND SMALL

ARRAY OF PIXEL DETECTORS
Parallelly to multichannel ICs for SSDs used in X-ray imaging applications, several interesting solutions of readout electronics for pad and small array of pixel detector
have been developed [67, 133, 135, 265-271]. The power consumption per single channel in these cases is much higher than for readout electronics of pixel architecture developed for large array of pixel detector. Exemplary designs are presented below.
BNL ASIC with Multiple Energy Discrimination

The Instrumentation Division from BNL, Upton, USA designed 64-channel ASIC
for high rate photon counting with multiple energy discriminators for the use with pixelated CdZnTe sensor [135]. The IC with the area of 6.65 mm 6.65 mm was fabricated
in commercial CMOS 0.25 m 1P5M technology. The main components of single channels are (see Fig. 6.9): low-noise two stage charge amplifiers, high order shaper (9th)
with baseline stabilizer, five window-discriminators with the same number of 16-bit
counters and 16-bit memory blocks.
The CSA has PMOS input transistors with W/L = 192m/0.24m optimized for
2 pF input capacitance. The input transistor with drain current of 200 A has a transconductance of gm 3 mS and a gate capacitance of Cg 400 fF. The CSA feedback is
based on a compensated continuous reset circuit [78] with adjustable gain. The shaper
142
has one real pole and eight complex conjugate poles with four different settings for
peaking times of 40, 80, 160 and 320 ns. The overall channel gain is adjusted at 250,
500, 750 and 1000 mV/fC. A band gap referenced baseline holder stabilizes the shaper
output for process variation, offsets, temperature and high rate operation [132]. The five
window discriminators have adjustable threshold using five on-chip 10-bit DACs common to all channels. Additionally, there are five 3-bit trim DACs (with 10 mV step)
working in each channel independently.
Fig. 6.9. Block diagram of single channel [135] 2007, IEEE.
The analog output of each channel can be monitored through an on-chip multiplexer (common buffer for all channels is used). The data is read out by 16-bit output
bus with a clock up to 60 MHz resulting in the total readout time below 20 s. The
memory blocks in each channel allow simultaneous measurement as well as readout;
and in this mode dead time is reduced to 20 ns. For floating input at 40 ns peaking time
and gain 1 V/fC an ENC 140 e rms is measured. The ENC is also measured for ASIC
connected to CdZnTe arrays of 16 elements (with the size of 2.20.73 mm3) and using
uncollimated 241Am source. For peaking time of 320 ns, the measured noise is
200 e rms (with about 70 e rms contributed from ~1 nA detector leakage current) and
495 e rms effective (with ballistic deficit) for 40 ns peaking time (without ballistic deficit ENC 390 e rms). The average power consumption per channel is about 4.9 mW
(1.1 mW for CSA, 2.8 mW for shaper, 0.45 mW for comparators, 0.36 mW for trim
DACs and the rest for common chip blocks).
143
CERN_DxCTA IC
CERN_DxCTA has been designed in 0.25 m CMOS technology for the
CdZnTe/CdTe and Si sensor for applications with a high flux of ionizing radiation at
CERN [269]. The chip contains 128 channels and a front-end electronics is optimized
for detector capacitance of about 5 pF. The single channel is equipped with CSA, fast
CR-(RC)3 shaper, two discriminators with two 5-bit trim DACs and two 18-bit counters
(see Fig. 6.10). The CSA and shaper stages, as well as shaper and discriminator stages
are AC coupled. The CSA is based on cascode configuration with bias current of
Iinput = 500 A (see Fig. 6.11). The CSA feedback contains a 38 fF capacitor and PMOS
transistor working in moderate inversion, and in the saturation region. A nominal bias
current Ifeed = 1 A provides fast discharge of the CSA feedback capacitor with time
constant of about 17 ns. The shaper structure is built as two cascaded common source
amplifiers and its peaking time is equal to 21 ns.
Fig. 6.10. Simplified scheme of a single channel of a CERN_DxCTA chip [269].
144
Fig. 6.11. Scheme of the CSA and shaper (reprinted from [269] 2003, with permission from Elsevier,
The single discriminator scheme is shown in Fig. 6.12. The first differential block
converts a single shaper output to a differential signal. A VT2-VT1 threshold applied
differentially produces a DC shift at the output of the differential pair. This DC shift can
be modified in each channel independently by 5-bit trim DAC. The buffered differential
signal is applied to a two-stage comparator with a high DC gain (72dB). The total ASIC
area is 5.0 mm 8.5 mm.
Fig. 6.12. Discriminator scheme (reprinted from [269] 2003, with permission from Elsevier,
145
The measurements with a calibration pulse shows the noise of equivalent noise
charge ENC = 430+56Cd e rms and an average gain of 143.5 mV/fC, with channel-tochannel gain variation of 1.5 %. The comparator offset is 5.2 mV rms and the power
consumption is 2.1 mW/channel. The counting rate measurement has been performed
with CdZnTe detector biased up to 1200 V. The count rate of 5 Mcps has been achieved
for maximum X-ray energy of 140 keV.
CIX 0.2 IC
A new approach for a high rate X-ray imaging system has been proposed in the
CIX (Counting and Integrating X-ray) integrated circuit, which combines the advantages
of both counting and integrating in each pixel [270, 271]. Counting systems can provide
spectral information about the photon flux. For these systems the lowest measurable flux
is a single photon in a measurement interval, while the maximum flux per pixel is limited to a few Mcps (in the best systems) as a result of pile-up effects. The integral systems provide information about the total deposited energy. However, they are well
suited for large rates and signal currents. Measurement of small signals is difficult because of electronic noise. By simultaneous counting and integrating in every pixel, the
dynamic range can be extended. Additionally, average energy of the deposited photon
can be calculated in this flux range where photon counting and integrating overlap (with
increasing pile-up, the correlation between counting and integrating signals get weaker).
Fig. 6.13. Block diagram of a CIX pixel cell [271] 2007, IEEE.
146
The CIX 0.2 version IC has been implemented in AMS 0.35 m technology with
the matrix of 8 8 pixels. The pixel dimensions are 250 m 500 m and the block
diagram of the CIX pixel cell is shown in Fig. 6.13. The pixel contains both counting
and integrating channels. The key element of this solution is a configurable feedback
circuit of the CSA which provides continuous reset, leakage current compensation and
produces the input signal replica for the integrator. To reduce the problem of the substrate noise generated by the digital block, the following have been applied [187]: a low
swing differential logic for the design of the counters and a digital circuit.
The simplified scheme of the photon counting block is shown in Fig. 6.14. The
counting channel contains a charge sensitive amplifier with a feedback capacitor of
10 fF, two stage comparator with differential output and 16-bit ripple counter. A continuous feedback of the CSA is based on a differential pair working as a voltage current
source. Negative input pulse of charge causes the voltage drop on feedback capacitor
CFb. This voltage drop activates the feedback current source. The current source delivers
the IFb current to the input node and discharge the CFb capacitor. In a simple model, the
trb time necessary to return to the baseline depends on the pulse size and it is given as
t rb =
Qin
I fb
(6.2)
If the CSA output exceeds the threshold voltage VCountTh, the pulse is registered in the
counter.
Fig. 6.14. Simplified scheme of a counter block [270].
The integrator circuit is shown in Fig. 6.15. The feedback circuit is a charge pump
operating in a clock-synchronized mode. The charge pump removes the Qpkt charge
packet of the defined size from the Cint capacitor each time a predefined threshold VIntTh
is passed. Two counters record the number of charge pumps events Npkt and the time t
during which the pump events has occurred. The measured ISignal current is given as
I Signal =
N pkt Q pkt
t
147
(6.3)
The charge pump clock frequency and the size of charge packets can be tuned.
This allows setting the minimum and the maximum integrator currents.
Fig. 6.15. Simplified scheme of an integrator circuit [270].
Fig. 6.16. Simplified scheme of feedback circuit [271] 2007, IEEE.
The core of the feedback circuit consists of two differential pairs (see Fig. 6.16).
The first one provides the shaping of the signal in the counter channel and replicates the
input signal for the integrator. The second one is responsible for detector leakage current
compensation. Both differential pairs work in a similar way: two currents at the bottom
of each branch drain precisely half of the current source above. Any difference in gate
148
voltages of two transistors in differential pair shifts the current from one branch into the
other. The additional/missing current has to leave/enter the branch through the node
above the respective current drain.
With bump bonded CdZnTe sensor (3 mm thick) the obtained energy resolution
was 0.3 keV. The maximum count rate of 3.3 Mcps (at 10 keV threshold) has been
measured. However, the combined dynamic range of the counter and integrator cover
5 orders of magnitude up to approximately 22.5 Mcps [272]. The double data readout
buffer enables dead time free data acquisition with the frame rates up to 20 kHz. The
power consumption in the CIX 0.2 is about 3.2 mW per pixel and almost all of the
power (98%) is consumed by the digital circuitry.
6.4. SOLUTIONS FOR PIXEL DETECTORS

Probably one of the most demanding solutions of the readout electronics is the one
for large area pixel detectors, because of limited area and the power per single channel,
together with the requirements for good pixel-to-pixel matching and good final yield.
The era of pixel readout electronics started in the nineties of 20th century and the last
technology developments (deep submicron and 3-D technologies) seem to be the most
appropriate for this kind of readout electronics. However, it should be mentioned that
only a few designs published in literature have succeeded in building large area detectors. Some exemplary designs have been presented below.
Pixel detector with local intelligence

In 1991 F. Krummenacher proposed a readout circuit for pixel detector which
contained a charge sensitive amplifier, shaper, discriminators and an analog storage
[84]. The blocks proposed there (especially for the CSA feedback discharge) were later
used in many designs [44, 87, 273]. The scheme of the CSA is shown in Fig. 6.17. The
CSA consists of a transconductance gm amplifier, an integrating Cf capacitance and an
active feedback. The feedback differential pair is based in this case on the PMOS differential pair biased with 2Ikrum current. The input of the M1a transistor is connected to
the reference voltage (in this case ground), while the input of the M1b transistor is connected to the CSA output. The current in the right branch (drain current of the M1b) is
integrated onto the capacitor and the resulting voltage controls the gate of the NMOS
transistor M2. This structure has two feedback paths:
- resistive path of Rf 2/gm1 to discharge the Cf capacitor, where gm1 = gm1a = gm1b is
a transconductance of the M1a (M1b) transistor,
- inductive path for detector leakage current Ileak - DC leakage current flows into drain of
the M2 rather than into the Rf equivalent feedback resistance.
149
(b)
(a)
Fig. 6.17. The CSA with active feedback which automatically compensates for detector leakage current a)
simplified circuit (reprinted from [84] 1991, with permission from Elsevier,
http://www.sciencedirect.com/science/journal/ ) - the currents in the brackets were
added for small signal analysis, b) equivalent circuit diagram [273] 2001, IEEE.
Let us perform a small signal analysis of active feedback [273] and assume for the
AC- analysis an input signal iin, input voltage vin and vout = gmvinZ0 at CSA output. Small
signal currents in each branch (as indicated in brackets in Fig. 6.17(a)) can be written as
1
g m1vout
2
1
i1b = g m1vout
2
i f = (vout vin )sC f vout sC f
i1a =
i2 = g m 2
i1b
sC
(6.4)
(6.5)
(6.6)
(6.7)
Summing the current at CSA input gives
iin + i1a + i f i2 = 0
(6.8)
Using the formulae (6.4)(6.7) the above equation can be rewritten as
iin +
1
1 g m1 g m 2vout
g m1vout + vout sC f +
=0
2
2
sC
(6.9)
150
The transfer function is
vout
2 sC
= 2
iin
2 s C f C + sCg m1 + g m1 g m 2
(6.10)
The stability criterion requires adequate separation of the poles frequency. Assuming that the poles are real and widely separated, one obtains
g m2
C
g
p2 m1
2C f
p1
(6.11)
(6.12)
The stability criterion
2C f
C
>>
gm2
g m1
(6.13)
must be satisfied for the maximum value of expected detector leakage current. The
equivalent scheme of the active feedback contains both the Rf 2/gm1 equivalent feedback resistance and the Lf inductance of the value (see Fig. 6.17(b)).
Lf =
2C
g m1 g m 2
(6.14)
The detail analysis of the Krummenacher active feedback can be found in [274].
The shaper stages in single ended and differential configurations proposed by
Krummenacher are shown in Fig. 6.18. The transfer function of a single-ended stage is
given
g mi Z D
1 + g mi Z S
(6.15)
1
g mo + sC LP
(6.16)
Kv
where
ZD =
ZS =
151
1
sCHP
(6.17)
After substitution of ZD and ZS to eq. (6.15) the transfer function of the shaper is
g mi
C LP
Kv
g
g
s + mi s + mo
C HP
C LP
(6.18)
The high pass characteristics is determined by time constant HP = CHP/gmi and low pass
characteristics by time constant LP = CLP/gmo.
(a)
(b)
Fig. 6.18. Shaper amplifier: (a) single-ended and (b) differential circuit (reprinted from [84] 1991, with
permission from Elsevier, http://www.sciencedirect.com/science/journal/ ).
IC for Digital Pixel Array Detector (DPAD)

Digital Pixel Array Detector (DPAD) has been designed for static and time resolve protein crystallography [61, 275, 276]. The detector has a pixel pitch of 150 m.
Two prototype readout ASICs with pixel array of 88 and 1616 have been designed in
HP 0.5 m 3-metal layer process. The simplified scheme of a single readout pixel is
shown in Fig. 6.19. It consists of a preamplifier with a DC adjustable reset, shaper with
a peaking time controlled in the range of 50 ns 150 ns, a differential comparator and
a 3-bit prescaler. The prescaler divides the event rate by 8 and reduces bandwidth re-
152
quirements.When a pixel has accumulated 8 counts then an additional overflow bit starts
the readout logic sequence to generate the pixel address in less than 80 ns.
Fig. 6.19. Simplified scheme of a pixel readout cell [276].
The CSA is based on a cascode stage with a PMOS input transistor M1 of

W/L = 49.5m/1m and bias current of 9.8 A (see Fig. 6.20(a)). The CSA feedback
consists of a 10 fF capacitor and PMOS transistor MRST of W/L = 1.5m/10m. Drain
current in an M3 load transistor is reduced to 0.8 A by adding an M4 additional current
source. The CSA is AC coupled to the shaper with a MOS transistor MCDIFF of effective Cdiff = 0.2 pF capacitance. The shaper is also based on cascode stage with NMOS
input transistor (see Fig. 6.20(b)). A 10 fF capacitor and an MRF1 of W/L = 1.5m/10m
transistor form shaper feedback. The MRF1 is an NMOS type transistor and it is biased
in linear region by MR1 and MR2 transistors.
(a)
(b)
Fig. 6.20. Simplified scheme of: (a) integrator, (b) shaper [61] 1996, IEEE.
The circuit gain is 690 mV/fC and the measured noise is 60 e rms (@ 5.9 keV)
when a Si pixel detector (Cdet = 0.3 pF) is used. The single channel can accommodate up
to 1 Mcps, while the power consumption in analog part is 50 W/channel (VSS = 3 V).
153
The measurements of 88 chips show the shaper's output voltage spread of about
= 7 mV (from pixel to pixel).
MPEC 2.3 IC
MPEC (Multi Picture Element Counters) ICs family started with the first IC [277]
by adopting BIER&PASTIS chip architecture developed for the ATLAS pixel detector
at the LHC at CERN [146]. The latest version of the MPEC 2.3 contains an array of
32 32 pixels with a pitch of 200 m 200 m [278, 279]. Additional blocks are input
and output buffers and six 8-bit DACs to generate internal bias currents. The MPEC 2.3
IC works in a single photon counting mode with energy windowing and operates up to
1 MHz rate of input pulses per single channel. The chip was designed in AMS 0.8 m
CMOS process with only two metal layers.
Fig. 6.21. Schematic of one pixel of MPEC 2.1/2.3 chip [279] 2004, IEEE.
The main parts of a single pixel are: the CSA with a current feedback, two independent discriminators, two 18-bit counters and a dedicated window logic which allows
the counters to record only photons within a set energy region (see Fig. 6.21). The frontend and the feedback circuit are designed for positive input charges. The discriminators
are AC-coupled to the CSA to eliminate DC voltage offsets propagation. The discriminator thresholds are set globally. Additionally, a correction voltage is stored on a capacitor independently for each discriminator (see Fig. 6.22(a)). The correction voltage stored
dynamically on a capacitor must be periodically refreshed due to leakage current
(mainly into the bulk of a switch transistor). The simple circuit with additional buffer
(between store node and bulk of switch transistor) reduces the leakage current and
minimizes the necessary refresh rate (see Fig. 6.22(b)). In order to save the silicon area
the counters are realized as pseudorandom counters (properly connected feedback in the
shift register - Fig. 6.23(a)) and a single phase flip-flop contains only two inverters and
two transistors (see Fig. 6.23(b)) [280].
154
(b)
(a)
Fig. 6.22. Correction of discriminator offset: a) discriminator with threshold adjustment, b) threshold drift
compensation circuit (reprinted from [280] 2001, with permission from Elsevier,
(b)
(a)
Fig. 6.23.Simplified scheme of counter architecture: a) 18-bit linear feedback shift register counter,
b) single phase flip-flop cell of the shift counter [280].
The test of MPEC 2.3 has been performed both with Si and CdTe sensors, however in the second case, the hole trapping and low hole mobility reduce the imaging
performance. The measured ENC without sensor is 60 e rms and about 110 e rms
when connected to the sensor. The minimum threshold can be set only to 1300 e, because of digital switching noise in the chip (the design uses the process with only two
metal layers and an effective shielding poses difficulty in this case). The threshold dispersion before the correction reaches 180 e rms and after adjustment it is reduced to
10 e rms. Multichip modules with 4 single photon counting MPEC 2.3 chips bump
bonded to Si and CdTe detectors have been successfully built and operated.
MEDIPIX2 IC
The MEDIPIX family has been developed at CERN [281, 282] and the first
MEDIPIX1 chip contains the matrix of 64 64 pixels and 170 m 170 m in size.
It has been designed in the 1 m SACMOS process. The next generation of MEDIPIX2
[44] IC has been designed in the 6-metal CMOS 0.25 m process. Its readout electronics
155
consists of an array of 256 256 readout channels which gives the matrix of 65536
identical elements in total, with the same geometry as the pixel detector. Each readout
pixel with 500 transistors occupies the area of 55 m 55 m and has a static power
consumption about of 8 W. A bump bonding technique is used to connect the detector
to the 20 m wide octagonal input pads of the readout electronics. The architecture of
the single cell is shown in Fig. 6.24.
Fig. 6.24. Single readout pixel cell [44] 2002, IEEE.
A single pixel cell consists of:

charge sensitive amplifier with a differential architecture to reduce the substrate and
power supply noises,
active structure in the CSA feedback - it provides fast discharge of feedback capacitance and compensation of DC detector leakage current [84],
two discriminators with independent threshold settings and independent 3-bit correction DACs. The outputs of the discriminators can be masked in case of malfunction or
excessive noise. The subsequent logic block produces the pulse if the amplitude of the
CSA output signal falls within a defined energy window,
shift register which can operate in two modes depending on the shutter signals. In one
mode it works as a 13-bit pseudorandom counter and its contents is increased by one
with every discriminator pulse. In the other mode, an external clock is applied and it is
used to shift the data from pixel to pixel. This mode of operation applies for both loading the values of the configuration DACs in each pixel and reading out the counter contents.
The readout electronics is able to process the signals from the input carriers of
both types. The noise performance is 140 e rms, while the unadjusted threshold variation is around 360 e rms.
156
The floor plan of MEDIPIX2 chip is shown in Fig. 6.25. Its total area is
14.1 mm x 16.1 mm, and the sensitive matrix area of pixels covers 87% of the entire
chip (i.e. 1.98 cm2). The periphery area, which contains fast shift registers, DACs, I/O
control logic and LVDS drivers and receivers, is located at the bottom part of the chip.
Such a floor plan enables minimization of the dead area in multichip module.
Fig. 6.25. Schematic floor plan of MEDIPIX2 chip [44] 2007, IEEE.
When pixels are read out or their registers are loaded, the whole pixel matrix is
organized in 256 columns. The readout of the chip can be performed in a serial mode
using fast LVDS logic or in parallel via 32-bit CMOS bus. When the 100 MHz clock is
used, the first mode of the readout takes less than 9 ms, while in the second mode it is
done in 266 s. The whole chip contains about 33 million transistors.
The MEDIPIX2 is very attractive for different applications and it is used in many
scientific experiments [282]. The RELAXD project (high REsolution Large Area X-ray
Detectors) aims to develop a four-side tillable photon-counting module with minimum
dead spaces [283]. These modules will be used to build an arbitrary large-area detector.
Other projects based on MEDIPIX2 IC, which aim to add new functionality or increase
chip performance, have been developed. These include: TIMEPIX chip [284] and completely new MEDIPIX3 chip [285].
157
TIMEPIX IC
The TIMEPIX chip [284] contains an array of 256 256 pixels with the size of
55 m 55 m. Each pixel can be used independently for arrival time, as well as for
energy and/or photon counting measurements. The chip has been designed in a commercial 6 metal CMOS 0.25 m technology. The floorplan and readout architecture are the
same as the MEDIPIX2.
The scheme of a single cell is shown in Fig. 6.26. Comparing with the MEDIPIX2
cell, there is only a single threshold with 4-bits threshold adjustment; each pixel can be
configured in three different operation modes and the counting clock is synchronized
with the external Ref_Clk clock reference.
Fig. 6.26. TIMEPIX pixel cell schematic (reprinted from [284] 2007, with permission from Elsevier,
The analog part of the pixel contains a preamplifier based on the cascode differential amplifier and Krummenacher feedback [84]. The preamplifier gain for nominal bias
condition is ~16.5 mV/ke with a linear dynamic voltage range up to ~50 ke. The peaking time can be set from 90 ns to 180 ns by the Preamp DAC, while the return to zero
baseline of ~10 ke input charge can be adjusted from 500 ns to 2500 ns depending on
Ikrum DAC setting. The preamplifier is DC coupled to the discriminator. The discriminator has a differential OTA at the input, 4-bits trim DAC and its core is based on current discriminator with hysteresis.
The digital part of the pixel contains TIMEPIX Synchronization Logic (TSL), the
14-bit shift register, the overflow control logic, the Ref_Clk pixel buffer and 8-bit Pixel
Configuration Register (PCR). The TIMEPIX uses an external clock with the frequency
of up to 100 MHz as a time reference. Depending on the Shutter signal, the shift register
is used to shift the data from pixel to pixel (Shutter = 1) or works as a counter (with
a XOR tap) with a dynamic range of 11810 counts (Shutter = 0). During the data acqui-
158
sition the pixel counter is incremented by the Ref_Clk depending of the operation mode
bits (P0 and P1):
event counting mode (P0 = 0, P1 = 1) - each hit above the threshold increments the
counter by 1,
time-over-threshold (ToT) mode (P1 = 1, P1 = 0) - the counter is incremented continuously while the preamplifier output signal is over the threshold,
arrival time mode (P1 = 1, P1 = 1) - the counter is incremented from the first time the
discriminator goes high to the closing of the Shutter.
The measured pixel noise is ~100 e rms and the threshold spread after trimming
is ~35 e rms. The chip operates for both input charge polarities with the minimum detectable charge of ~650 e. In the ToT mode, the energy resolution (ToT/ToT) is better
than 5% if the input charge is 1k e above the threshold. The measured time walk is
50 ns. Using a 100 MHz clock, the chip can be read out serially (via on-chip LVDS
drivers) in less than 10 ms, or in parallel (32-bit CMOS port) in less than 300 s. The
TIMEPIX chip operates with 2.2 V power supply. Power consumption for the analog
part is ~440 mW and ~450 mW for the digital part.
MEDIPIX3 IC
The MEDIPIX3 chip [285, 286] has been designed to eliminate the spectral distortion produced by the charge diffusion in highly segmented pixel detector (see
Fig. 6.27). The effects strongly influence the measured energy spectrum as the pixel
pitch is decreased with respects to the thickness of the detector material.
(a)
(b)
Fig. 6.27. Charge diffusion effect in highly segmented detector - charge generated at the pixel border is
shared between pixels [286].
The chip has been developed in 8-metal CMOS 0.13 m process and its core contains a matrix of 256 256 pixels, which is 55 m 55 m in size. In a new architecture proposed in MEDIPIX3, the pixels communicate with one another. At the corner of
each pixel, summing circuits add the total charge deposited in each sub-group of 4 pix-
159
els. An arbiter circuit assigns the hit to the summing circuit with the highest charge. The
chip is highly configurable and can operate with a single pixel mode or charge summing
mode with the effective pixel size of 55 m 55 m or 110 m 110 m.
Any single pixel (see Fig. 6.28) contains a charge sensitive preamplifier, shaper,
two discriminators with 5-bit threshold adjustment, pixel memory (13-bits), arbitration
logic for charge allocation, control logic and configurable counter (about 1600 transistors per pixel). At the bottom of the pixel matrix there are peripheral circuits: LVDS
drivers and receivers, bandgap reference, 25 DACs (10 9-bit and 15 8-bit), 32 e-fuse
bits, EoC, 2 test pulse generators per pixel column, temperature sensor, full IO logic and
command decoder.
Fig. 6.28. Architecture of a single pixel [285] 2007, IEEE.
The charge sensitive amplifier has a feedback capacitance of 14 fF and is based

on Krummenacher architecture [84]. The CSA output signal is filtered with a first order
semi-Gaussian shaper (AC-coupled to CSA) with a time constant of about 100 nA. The
shaper can operate in Low Gain and High Gain Mode. It generates eight identical currents whose amplitudes are proportional to the charge collected on the input electrode.
The current from a cluster of four pixels are added at each pixel corner. As there are two
discriminators in each pixel, there are also two adding nodes per pixel corner. Each discriminator has a 4-bit trim DAC to reduce the effective threshold spread. Arbiter circuits
decide which discriminator wins (in each sub-group of four pixel) and the pulse from
discriminator output is fed to a proper 15-bit pseudorandom counter. Because there are
two shift registers in each pixel (on associated to each threshold), the pixel can operate
160
in Sequential Read-Write Mode or Simultaneous Read-Write Mode. The pixel is highly

configurable and several modes of MEDIPIX3 operation are possible as specified in
Table 6.4.
Table 6.4. MEDIPIX3 operation modes [285] 2007, IEEE.
Pixel Operating Modes
Number of thresholds
Single Pixel Mode
2
Charge Summing Mode
Single Cluster Mode
8
Spectroscopic Mode 110 m 110 m
Charge Summing Mode
Front-end Gain Modes
Linearity
Number of thresholds
High Gain Mode
2
~ 10 ke
Low Gain Mode
2
~ 20 k e
Pixel Counter Modes
Dynamic range
Number of counters
1-bit
1
2
4-bit
15
2
12-bit
4095
2
24-bit
1577215
1
Pixel Readout Modes
Number of active counters
Dead time
Sequential Read-Write
2
Yes
Continuous Read-Write
1
No
System Configuration
Fine Pitch Mode 55 m 55 m
Parameter
CSA gain
CSA-shaper gain
Non-linearity
Peaking time
Return to baseline
Electronic noise
Unadjusted
threshold spread
Expected minimum
threshold
Pixel power
consumption
Table 6.5. MEDIPIX3 electrical measurements [285] 2007, IEEE.

Single Pixel Mode
Charge Summing Mode
11.4 mV/ke
High Gain
34 nA/ ke
Low Gain
20 nA/ ke
High Gain
<5% up to 10 ke
Low Gain
<5% up to 20 ke
HG/LG
~ 110 ns
High Gain
<1.5 s to 12 ke
Low Gain
<2.5 s to 25 ke
High Gain
~60 e rms
~130 e rms
Low Gain
~85 e rms
~180 e rms
High Gain
~1000 e rms
~1800 e rms
Low Gain
~1900 e rms
~3200 e rms
High Gain
~900 e
~450 e
Low Gain
~650 e
~1300 e
HG/LG
8 W
8 W
The summary of measured electrical parameters of the MEDIPIX3 is presented in

Table 6.5. The total power consumption is 600 mW in Single Pixel Mode and 900 mW
in Charge Summing Mode. The Medpix3 dimensions are 14.1 mm 17.3 mm including
top and bottom WB (wire bonding) pads. In order to build a multi-chip module with
a large area detector, the chip is prepared for the TSV (Through Silicon Via). In this
option (without WB pads) the chip dimensions are 14.1 mm 14.9 mm and the active
chip area is 94.3% [286].
161
PILATUS IC
The fast readout electronics for pixel detector has been developed for the X-ray
measurements at the beamlime of the Swiss Light Source (SLS), as part of the PILATUS project (PIxeL ApparaTUs for the SLS) [46, 153, 153, 287, 288]. The goal of this
project was to build a hybrid pixel system covering approximately the area of
40 40 cm2 with 2000 2000 pixels [153]. The first generation PILATUS I chip was
designed in 2000 at the Paul Scherrer Institute (PSI), Villigen, Switzerland, using
DMILL radiation tolerant CMOS process (Atmel Temic SA, Nantes, France).
PILATUS I contains an array of 44 78 = 3432 pixels with a pixel size of
217 m 217 m. The active area spans over 10 17 mm2. Each pixel contains a low
noise CSA, a single-level comparator with a 4-bit individual threshold adjustment and
15-bit shift register counter (see Fig. 6.29). The noise of bump-bonded chip is
75 e rms. The total power consumption is 100 W per pixel. The lowest achievable
threshold of the chip is about 3 keV, which allows to measure 22Ti K radiation
(4.5 keV).
Fig. 6.29. Schematic view of the pixel unit cell [46] 2006, IUCr Journals, http://journals.iucr.org/ .
The chip operates in two modes:

counting mode in which all pixels count incoming X-rays photons,
readout mode in which the data is read out serially with the clock frequency of
10 MHz, within the readout time 6.7 ms.
These integrated circuits are used to build a PILATUS module, which is an array
of 8 2 chips bump-bonded to silicon pixel sensors. The variation of the threshold settings is an approximately linear function of the comparator voltage. After trimming on
the module, which contains about 54 thousands pixels (16 chips 3432 pixels), the
spread of the threshold voltage is about 6%, i.e. for the average threshold setting at
1680 e, the threshold dispersion is 112 e rms.
162
To improve the yield of good pixels the chip has been redesigned. The second
version of the PILATUS II chip was designed in 2004 at the PSI, using the UMC
0.25 m technology in which radiation tolerance was achieved by design [288]. The
active chip area is 10 17 mm2 and it consists of an array of 60 97 pixels. Each pixel
has the size of 172 m 172 m. A single pixel contains similar blocks as the first version, but a comparator has a 6-bit individual threshold adjustment and the counter capacity is 20 bit. The authors claim the count rate up to 1.5 MHz/pixel/s. The chips
mounted in the PILATUS module (an array of 8 2 chips) are read out parallelly within
the readout time of about 2 ms. Using PILATUS modules, PILATUS 6M detector system has been built. This system is composed of 5 12 modules with 2463 2527 pixels
and has a total active area of 424 435 mm2.
XPAD3 IC
XPAD IC family has been developed at CPPM in France [45, 289]. The latest
XPAD3 version has been realized in 0.25 m IBM technology with the pixel matrix of
80 120 elements of single pixel size of 130 m 130 m. The chip is in two versions:
XPAD3-S (S - as in Si) version works with positive input charge generated by photons
in the energy range from 4 keV to 40 keV and has a single threshold,
XPAD3-C (C - as in CdTe) version works with negative input charge generated by
photons in the energy range from 6 keV to 60 keV and has two independent thresholds.
Fig. 6.30. XPAD3-C pixel chain [45] 2007, IEEE.
The architecture of XPAD-C is shown in Fig. 6.30. The pixel contains a CSA, an
operational transconductance amplifier and two independent working current low and
high discriminators with 5-bit and 2-bit DACs trim respectively. The XPAD3-C has an
163
active OTA feedback while the XPAD-S uses in CSA feedback a single MOS device
operated in triode region. The active OTA feedback allows proper XPAD3-S operation
with negative input charge, however, it results in an increase of noise and output offset.
The summary of measured XPAD3 parameters is presented in Table 6.6. The single pixel dissipates 40 W at 2 V power supply. The ENC is 127 e rms for XPAD3-S
and after the adjustment (6-bit trim DAC) the effective threshold spread is 57 e rms.
For XPAD3-C the noise is higher (ENC =185 e rms), because of the OTA feedback
being used in the CSA stage. The XPAD3 architecture allows for the in-flight data readout every 2 ms/frame (9600 pixels with 12-bit register each) which results in up to
500 frames per second.
Version
Number of pixels
Pixel size
Expected readout time
Counting rate
On the fly readout
Power consumption
Input polarity
Gain
Selectivity mode
Non linearity
Minimum threshold
Global electronic noise
Threshold adjustment dispersion
Threshold adjustment resolution
Table 6.6. Characterization results of XPAD3 circuits [45] 2007, IEEE.

XPAD3-S
XPAD3_C
80 120 = 9600
130 m 130 m
2 ms/frame
> 106 photons/pixel/s
Yes
40 W/pixel (2V)
Holes collections
Electrons collections
89 nA/keV to 35 keV
46 nA/keV to 60 keV
Single threshold
Double threshold
< 4% over 35 keV
< 2.5% over 60 keV
< 4 keV
< 10 keV
127 e rms
185 e rms
57 e
0.2 keV rms
-
The XPAD3 chips operate with Si, CdTe and GaAs detectors. A multichip module (up to eight XPAD3) has been constructed. A PIXSCAN project aimed to build
a small animal computed tomography scanner demonstrator based on the XPAD3 chip
with an active area of 7.5 cm 12 cm [290].
EIGER - IC for high frame rate X-ray applications

The PSI-SLS detector group has also developed a new integrated circuit for high
frame rate X-ray applications called EIGER [291]. The main features of the readout chip
are presented in Table 6.7. The EIGER chip is a completely new design when compared
to the PILATUS II: the pixel size is only 75 m 75 m, the pixel matrix is 256 256,
the chip has double buffering and very high readout speed.
The pixel architecture is presented in Fig. 6.31. The low noise preamplifier is followed by shaper with tunable shaping time. The discriminator has 6-bit DAC trimming.
A maximum count rate per pixel is more than 1 MHz. During the exposure time the
comparator pulse increments the digital counter by 1. At the end of the exposure time,
164
the counter content is loaded to the temporary pixel buffer and the counter is reset. Buffering and counter reset last about 1 s after which new exposure is possible.
Table 6.7. Main features of the new chip and of its pixel (reprinted from [291] 2010, with permission
from Elsevier, http://www.sciencedirect.com/science/journal/ ).
Readout chip features
Technology
UMC 0.25 m
Power supplies
1.1V (analog), 2V (digital), 1.8V(I/O)
Radtion tolerance
Rad-tolerant design (> 44 Mrad)
Pixel array
256 256 = 65 536
Chip size
19.3 mm 20 mm
Readout speed
up to 24 k frames/s
Pixel features
Pixel size
75 m 75 m
Gain
44.6 V/ e
Peaking time
31 ns
Return to 0 at 1%
151 ns
Noise (simulation)
135 e rms
Static power
8.8 W/pixel
Transistor count
430/pixel
Pixel counter
Configurable (4, 8, 12-bit mode), binary,
double buffered for continuous readout
Threshold adjust
6-bit DAC/pixel
Other features
Overflow control, single pixel addressing
and analog out for testing
Simulations are done with "standard" settings. "Low noise" or "high speed" settings can improve performance for applications with specific needs.
Fig. 6.31. Pixel architecture of EIGER IC for high frame rate X-ray applications (reprinted from [291]
2010, with permission from Elsevier, http://www.sciencedirect.com/science/journal/ ).
The chip can be read out via 32-line parallel bus line with 100 MHz Double Data
Rate (DDR). The double data storage allows minimizing the dead time. The maximum
frame rate can be adjusted using a selectable length of the pixel counter from 4 bits to
165
12 bits. The maximum frame rates for 4, 8 and 12 bit modes are 24, 12 and
8 k frames/sec respectively. The authors are planning to build 8-chips module bumpbonded to a silicon sensor of 78 mm 39 mm with about 0.5 Mpixel in total. Several
modules (up to 18 modules) can be tiled to build a large area detector (9 Mpixel,
~550 cm2).
PX90 IC
The PX90 IC is the first implementation of the readout electronics for hybrid
pixel detector in the CMOS 90 nm technology node [87, 292]. The prototype has been
built to investigate the possibilities of new deep submicron technologies and also to
check such critical parameters for front-end readout electronics like noise, matching and
crosstalk. The aim of the project was to build a readout electronics with a pixel of relatively small area, with high count rate and a readout architecture which allowed a dead
time free operation.
Fig. 6.32. Simplified scheme of pixel cell in PX90 IC [87] 2010, IEEE.
The core of the integrated circuit is a matrix of 4032 pixels with

100 m 100 m pixel size. A simplified block diagram of a single pixel cell is shown
in Fig. 6.32. Each pixel contains two (CSA and CSA_REF) charge sensitive amplifiers
(to make the front-end as much as possibly immune to the switching noise generated by
the digital block), two AMP II second stage amplifiers with two DACs trim (7-bit and
8-bit), two DISCR independent discriminators and two independent 16-bit ripple counters. All these stages are DC coupled. During the data readout the counters from the pixel
in each column of matrix pixels form a shift register. Each pixel cell contains additional
blocks like a simple test charge injection circuit, a block for recovery of sensitive analog
references and a set of registers (to switch between different readout modes and enable
test features).
166
(a)
(b)
Fig. 6.33. Simplified scheme of PX90 pixel blocks: (a) CSA, (b) AMPII [87] 2010, IEEE.
The core of the charge sensitive amplifier is based on the folded cascode configuration (M1M4 transistors - see Fig. 6.33(a)). The CSA M1 input transistor is PMOS
one of W/L = 20m/0.2m and operates with the nominal drain current of 5.2 A. The
designers do not use at the CSA input MOS transistors with the minimum channel
length to omit the possible noise increase connected with the short channel effect and
because of the low output drain-source resistance of the transistor with the minimum
gate length. The feedback loop of the CSA consists of a capacitor Cf = 5 fF and the
Krummenacher feedback circuit [10]. For IKrum = 21.5 nA the simulated peaking time is
tp = 27 ns with pulse width of t0.01 = 365 ns, while for IKrum = 36.5 nA these parameters
are tp = 26 ns with pulse width of t0.01 = 216 ns. To reduce power consumption, the left
branch of the folded cascode operates with power supply voltage of Vddm = 0.8 V,
while the right one with Vdda = 1.2 V.
The second AMPII stage is a fully differential stage (see Fig. 6.33(b) and has
three main functions:
add some voltage gain,
reduce (by digital trimming) offset spread in the front-end electronics,
set the threshold level for the discriminator stage.
The AMPII consists of two source followers (with control bias current) at the input, a simple differential amplifier and two source followers at the output. The fully
differential architecture of this stage allows the operation both, with positive and negative pulses. The offset spread in the signal processing chain is compensated by the input
source followers of the AMPII (M21M22 transistors), because the I1 and I2 currents
can differ according to the setting of the DAC trim. In this design currents are I1 = Ibase
and I2 = Ibase+Itrim, where Ibase = 0.5 A and Itrim is controlled by the DAC trim. By applying two different voltages Vt and Vtr (see Fig. 6.33(b)), the effective threshold level,
which equals VTH =VtVtr , is set for the next discriminator stage. The differential output
167
signals from the AMPII are fed into the current discriminator (discussed in chapter
3.6.1.).
Discriminator pulses are counted by two 16-bit counters. A single counter unit is
presented in Fig. 6.34. Each unit contains a 16-bit binary counter, which can be converted into a shift register. In the counter mode, the unit input is fed with discriminator
pulses. In the shift mode, the unit reads the data from the output of the previous unit and
provides the data for the next unit. The units are grouped according to the thresholds,
e.g. the units counting low threshold discriminator pulses are connected and so are the
units counting high threshold discriminator pulses. In this way, the data for both thresholds can be read out independently. Therefore, for the same setting of the thresholds, the
integrated circuit can operate in the continuous readout mode. Additionally, there is an
8-bit latch in each unit which provides the data for the trimming DACs. The latch is
parallelly loaded from the register.
Fig. 6.34. Scheme of a single counter unit [87] 2010, IEEE.
The ASIC is designed in the 90 nm TSMC CMOS process and its total area is
4 mm 4 mm. Each pixel contains about 1800 transistors and measures 100 m by
100 m. 2/3 of the pixel area is occupied by analog blocks and 1/3 by the digital blocks
(see Fig. 6.35(a)). The cross-section of the pixel cell showing the distribution of all
metal layers is shown in Fig. 6.35(b). The metal layers M1 to M3 are used for routing
inside the pixel and distribution of control signals. The metal layers M4 to M9 are used
for the distribution of power supplies and shielding of the IC. The chip has been manufactured with the use of the Multi-Project-Wafer (MPW) run. In order to enable tests
with pixel detectors, each readout pixel is provided with a large pad of 60 m 60 m
for stud bump bonding. The large area of input pads allows the effective stud bump
bonding (and tests of a small prototype with a detector), however this results in relatively high parasitic capacitance at the input of the CSA - in this case, 230 fF.
To reduce the effects of the injecting substrate noise the following steps have
been applied:
all NMOS transistors in the analog block are shielded with a Deep N-Well (DNW)
layer and the analog ground has a separate wire-bonding pad from digital ground,
168
PMOS transistors in analog and digital blocks have separate N-Well contacts connected to appropriate positive supply lines (except for some floating N-Wells in analog
blocks),
guard rings and decoupling capacitors are implemented according the rules suggested
in [184].
(a)
(b)
Fig. 6.35. Layout of a single pixel: (a) 1 - CSA & CSAREF, 2 - second stage amplifiers, 3 - discriminators,
4 - trim DACs, 5 - reference blocks, 6 - counters (MET4-MET9 are removed for the better visibility),
(b) cross-section with metal M1-M9 layers and NW and DNW layers [87] 2010, IEEE.
For nominal bias conditions, the power consumption is 47 W per pixel. The
digital blocks, i.e. the shift register tests and read/write counters tests work without errors up to 200 MHz clock (limitation in the test set-up). The mean gain measured on
different modules is 28 V/e. The offset spread for the threshold of the IC before correction is about 35 mV (on one sigma level) and after correction it is reduced to 1.8 mV
(calculated to the input is equal to 64 e rms). For the pixel which is not connected to
the detector, the noise is ENC = 204 e rms. For the PX90 IC with a detector, the noise
is ENC = 240 e rms. According to the simulation the total detector capacitance is about
50 fF, while the parasitic capacitance of an input pad is approx. 230 fF.
Using the 200 Mbps during the data transfer via single LVDS data output results
in about 218 s readout time. A dead time free readout is possible with the PX90 IC
using the continuous readout mode, however the observed effective noise of the system
increases by about 15 %. In order to characterize the count rate performance of the
PX90 IC, certain tests were carried out with signals arriving randomly using photons
from rotating anode high power X-ray generator. The count rate of 2 Mcps/pixel was
obtained which resulted in 200 Mcps/mm2. The PX90 IC performance is summarized in
Table 6.8.
169
Table. 6.8. Summarized performance of PX90 IC [87] 2010, IEEE.

Parameter
Technology
CMOS 90 nm
Die size
4 mm 4 mm
Total number of transistors
> 2 million
Pixel dimensions
100 m 100 m
Number of pixels
1280
Supply voltage: core / LVDS
0.8V & 1.2 V / 2.5V
Power dissipation per pixel
47 W
Peaking time
27 ns
Equivalent Noise Charge (ENC)
- without detector
204 e rms
- with stud bump bonded detector
240 e rms
Gain
28 V/e
Offset spread (after correction)
1.8 mV rms
Front-end dead time: standard/fast mode
505 ns / 236 ns
Number of discriminators per channel
2
Counters capacity
216-bit
Readout dead time
- standard mode (single output)
218 s
- continuous mode
0
Communication
LVDS standard with 200 MHz clock
VIPIC IC
For a few years the Fermi National Accelerator Laboratory (FNAL) has successfully tested the possibility of using 3D-IC technology for pixel readout electronics both
for high energy physics and related fields [293]. In 2009 the Fermilab organized a Mulit-Project-Wafer using 3D-IC technology provided by Tezzaron Semiconductor. The
wafers were fabricated in a commercial 0.13 m bulk CMOS provided by Chartered
Semiconductor. This CMOS process uses 6 Cu metal layers per wafer. The 3D integration is done by Tezzaron Semiconductor using wafer with TSVs (Through Silicon Vias)
added after completion of the Front-End-Of Line (FEOL) part of the process. TSVs are
1.3 m in diameter, 6 m deep and 3.8 m minimum spacing is required. The Tezzaron
demonstrated the possibility of stacking up to five layers, however during this MPW run
only two wafers were stacking face to face.
An example of a readout chip is a VIPIC IC (Vertically Integrated Pixel Imaging
Chip) designed for X-ray Photon Correlation Spectroscopy (XPCS) experiments by
FNAL in collaboration with AGH UST [294]. A VIPIC chip is a prototype matrix with
64 64 pixels with 80 m 80 m pixel size and consists of two layers: analog and
digital. The simplified scheme of analog pixel cell is shown in Fig. 6.36.
170
Fig. 6.36. Simplified scheme of an analog pixel cell of the VIPIC chip [294].
The single pixel cell consists of two (CSA and CSA_REF) charge sensitive amplifiers, two stages of AMP I and AMPII amplifiers (they are AC coupled to cancel the
offset propagation and shaping a signal) and single DISCR current discriminator with
differential threshold setting. The CSA feedback contains an 8 fF capacitor
(MET4MET5 structure) and a simple MOS transistor working in the linear region. The
differential or single-ended operation of front-end is possible to test digital crosstalk in
the chip. There are two trim DACs: 7-bit DAC for threshold correction and 3-bit DAC
for trimming CSA feedback time constant individually in each pixel. The simulated gain
is 52 V/e and noise ENC < 150 e rms (with Cdet = 100 fF) and peaking time
tp < 250 ns. The power consumption in the analog part is 25 W/pixel.
The chip is designed to yield 10 s frame readout time at the mean occupancy of
3.8108 photons/cm2/s. The digital layer of the VIPIC IC is divided into 16 readout
groups of pixels readout in parallel via separate serial ports with nominal frequency of
100 MHz clock using the LVDS standard (see Fig. 6.37).
171
Fig. 6.37 Block diagram of a digital tier of the VIPIC chip [293] 2009, IEEE.
The readout within each group is zero-suppressed. The sparsification scheme (addresses of hit pixels only) allows a dead-time free readout. The sparsification circuitry is
similar to the idea proposed in the MEPHISTO chip [295]. Each pixel in a digital tier
additionally contains a 5-bit counter. The readout is binary and each hit is represented
by a 16-bit long word (3 bits - start signs, 5 bits - content of in pixel counter, 8 bits pixel addresses in the sparsification mode). In imaging mode the last 8-bit of pixel address is not required. The main features of the VIPIC IC are summarized in Table 6.9.
Table 6.9. Main features of the VIPIC IC [293], 2009, IEEE.
Feature
Comments
X-ray detection (8 keV) with Si pixel detector
XPCS application
6464 pixels, pixel area: 80 m 80 m
Separate analog and digital tiers
Transistor number/pixel
Chip area 6.3 mm 5.5 mm (6.3 mm 5.5 mm)
Single threshold for discriminator
Two trim DACs/pixel
Test charge injection circuitry
Front-end channel architecture
Power consumption
active area: 5120 m 5120 m

analog = 280 tran., digital=1400 tran.
larger dicing for DBI
3-bit CSA feedback and 7-bit for offset corrections
Cinj = 1.7 fF
single ended or differential configuration
25 W/analog pixel
172
ENC (peaking time)

Gain
Readout modes
- sparsified, binary readout (spar. time slicing mode)
- imaging binary readout mode (5 bit signal depth)
Output lines
Frame readout at 100 MHz serial readout clock
< 150 e rms (<250 ns)

~52 V/ e
dead-timeless and trigger-less operation in both
readout modes; sparsification: priority encoder
based sparsification circuitry
16 parallel serial LVDS (16 groups of 464
pixels)
- 160 ns / hit pixel in spar. time slicing mode
(up to 60 hit pixels / 10 s)
- 50103 frame/s in imaging mode (5-bit counter)
The project aims to build a 4-side buttable pixel detector tile (see Fig. 6.38). The
detector will be fabricated using the whole available area of a wafer and the chips will
be tailed on the detector wafer by fusion bonding.
Fig. 6.38. Cross-section of a 4-side buttable pixel detector tile [293] 2009, IEEE.
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EuCARD-BOO-2010-004

European Coordination for Accelerator Research and Development

Front-end Electronics for Multichannel

Editorial Series on ACCELERATOR SCIENCE

Institute of Electronic Systems

the part of 64-channel DEDIX integrated circuit

Front-end electronics for multichannel semiconductor detector systems

Front-end electronics for multichannel semiconductor detector systems

4.2. Cross-talk in mixed mode circuits.................................................................................98

Front-end electronics for multichannel semiconductor detector systems

Front-end electronics for multichannel semiconductor detector systems

Front-end electronics for semiconductor detector systems

Front-end electronics for multichannel semiconductor detector systems

mobility after irradiation

Front-end electronics for semiconductor detector systems

collection time for electron, holes

power spectral density of voltage noise

input voltage signal

Front-end electronics for multichannel semiconductor detector systems

ABBERIVATIONS AND ACRONYMS

Front-end electronics for semiconductor detector systems

small animal X-ray CT-scaner

The history of semiconductor detectors started in 1951 when K. McKay noticed

Fig. 1.1. Book structure.

Semiconductor Position Sensitive Detectors (PSD) have been successfully used in

2.1. MATERIALS FOR SEMICONDUCTOR DETECTORS

Table. 2.1. Important parameters of materials used for detector.

2.2. REVERSE BIAS P-N JUNCTION

where T = kT/q 26 mV (at T = 300 K) and ni is the intrinsic carrier concentration in

The potential is described by Poisson's equation

and the maximum Emax of the electric field is at x = 0

The width of a depletion layer Wdep W1 is given as:

Dh ni2 qni Wdep

2.3. CHARGE GENERATION IN DETECTOR

I BEAM ( x) = I BEAM 0 exp( att x )

Fig. 2.2. The photon cross section vs. energy in silicon.

2.4. CHARGE TRANSPORT

Emin + x0 + Si Emin exp h D t

and for electron 0 t te

Emin + x0 + Si Emin exp e D t

The velocities uh = dxh/dt and ue = dxe/dt as a function of time are

For holes the collection time is the longest if x0 = 0 and then

For electrons the collection time is the longest if x0 = d and then

Applied voltage VR [V]

temax for electrons [ns]

thmax for holes [ns]

where De is a diffusion coefficient for electrons and Dh is a diffusion coefficient for

2.5. RAMO THEORY AND SIGNAL FORMATION

The examples of generated current pulse are shown in Fig. 2.6(a).

2.6. DETECTOR GEOMETRY

Fig. 2.9. Simplified view of 2D position sensitive pad detector.

such limitations. For an X-ray imaging application a pixel area as small as

2.7. IMPORTANT DETECTOR PARAMETERS

Fig. 2.11. Simplified 3D model of DC-coupled strip detector.

Fig. 2.12. Simplified model of position sensitive detector: a) DC-coupled, b) AC-coupled.

Cin >> 2Cn > Cb

The charge Qin which flows to the readout electronics is

Architecture of front-end electronics

Architecture of front-end electronics

Fig. 3.1 Example of a front-end electronics used in a detector readout system.

Architecture of front-end electronics

3.1. TYPES OF AMPLIFIERS