19-Feb-11

Outline
Concurrent versus Sequential
Concurrent statements (chapter 5 of Pedroni)

Combinational Logic Synthesis

with VHDL

Using operators
When...else
With Select When
GENERATE
BLOCK

Sequential statements (chapter 6 of Pedroni)

If then else
Case when
Loop
Wait until

Concurrent vs Sequential Code

Combinational vs Sequential Logic

Combinational logic is that in which the output of the circuit depends solely on the
current inputs (figure 5.1(a))
in principle, the system requires no memory and can be
implemented using conventional logic gates.
Sequential logic is defined as that in which the output does depend on previous inputs
(figure 5.1(b))
storage elements are required, which are connected to the
combinational logic block through a feedback loop, such that now the stored states
3
(created by previous inputs) will also aect the output of the circuit.

VHDL code is inherently concurrent (parallel).

Only statements placed inside a PROCESS,
FUNCTION, or PROCEDURE are sequential. Still,
though within these blocks the execution is sequential,
the block, as a whole, is concurrent with any other
(external) statements.
Concurrent code is also called dataflow code.
In general we can only build combinational logic
circuits with concurrent code.
To obtain sequential logic circuits, sequential code
(chapter 6) must be employed. Indeed, with the latter we
can implement both, sequential as well as combinational
circuits.
4

Concurrent code

Concurrency

In summary, in concurrent code the

following can be used:
Operators;
The WHEN statement (WHEN/ELSE or
WITH/SELECT/WHEN);
The GENERATE statement;
The BLOCK statement.
A VHDL concurrent body

A VHDL sequential body

19-Feb-11

Combinational Logic

Concurrent statements vs Sequential statements

Combinational logic can be implemented

with concurrent and sequential
statements.
Concurrent statements are used in
dataflow and structural descriptions.
Sequential statements are used in
behavioral descriptions.

Concurrent statements :
Execute at the same time in parallel

Sequential statements :
Execute one at a time in sequence

Concurrent assignment statements

Concurrent Statements

or Concurrent Signal Assignment (CSA)

Execute in parallel.

Lie outside of a process

Signal assignment

Order independent

X <=A+B ;
Z <=C+X ;

Z <=C+X ;
X <=A+B ;

independent of the order in

which they are written.

Concurrent
Selective (with-select-when)
Conditional (when-else)
Generate
The easiest way to perceive this is to actually draw a schematic of the
operations. Schematics are used to represent hardware, and so they are
concurrent in nature.

Architecture Body Syntax

10

VHDL Program Template

Architecture name of entity_name is

Library altera;
Use altera.maxplus2.all;
Library ieee;
Use ieee.std_logic_1164.all;
Use ieee.std_logic_arith.all;

internal signal and constant declarations

Begin
Concurrent statement 1;
Concurrent statement 2;
Concurrent statement 3;
Concurrent statement 4;
End architecture name;

Entity design_name is
port(signal1,signal2,..:mode type;
signal3,signal4,..:mode type);
End entity design_name;

11

Architecture name of entity_name is

internal signal and constant
declarations
Begin
Concurrent statement 1;
Concurrent statement 2;
Concurrent statement 3;
Concurrent statement 4;
End architecture name;

12

19-Feb-11

Table 5.1 Operators.

Using Operators

13

14

Simple Concurrent Statements

Assignment Operator

Simple Concurrent Statements

Logical Operators

Assignment operator <=

Logical operators

Ex: y <= a and b; -- defines a AND gate

For simulation purposes only, you may specify a delay.

And, or, nand, nor, xor, xnor, not

Operates on std_logic or Boolean data objects
All operators (except for the not operator) require at
least two arguments

Ex: y <= a and b after 10 ns;

This is useful if you want to also use VHDL to generate a known

test waveform or vector. This is known as a test bench.
However, we will use Maxplus II to generate test vectors. Note,
you cannot specify a delay for synthesis purposes.

Test
Vector

VHDL
Test Bench

VHDL
Design

Ex: y <= a and b; -- AND gate

Output
Vector
15

Simple Concurrent Statements

Logical Operators

16

x1
x2

Library ieee;

A
B

Entity exampl1 IS
PORT (x1,x2,x3: IN std_logic;

Logical operators
Examples

Use IEEE.std_logic_1164.all;
f

x3

y <= a and not b;

: OUT std_logic;);

END example1;
ARCHITECTURE Lfun of example1 is
Signal A,B : std_logic;

Use parenthesis to define order of execution

Ex: y<= (a and b) or c;
a

BEGIN

y <= a and (b or c);

c

b
c

b
a

17

f<= A OR B;

A<= (x1 AND x2) ;

A<= (x1 AND x2) ;

A<= (x1 AND x2) ;

f<= A OR B;

B<= (NOT x2 AND x3);

B<= (NOT x2 AND x3);

B<= (NOT x2 AND x3); f<= A OR B;

END Lfun;

18

19-Feb-11

Figure 5.4
Simulation results of example 5.1.

Example 5.1: Multiplexer #1

--------------------------------------LIBRARY ieee;
USE ieee.std_logic_1164.all;
--------------------------------------ENTITY mux IS
PORT ( a, b, c, d, s0, s1: IN STD_LOGIC;
y: OUT STD_LOGIC);
END mux;
--------------------------------------ARCHITECTURE pure_logic OF mux IS
BEGIN
y <=
(a AND NOT s1 AND NOT s0) OR
(b AND NOT s1 AND s0) OR
(c AND s1 AND NOT s0) OR
(d AND s1 AND s0);
END pure_logic;
---------------------------------------19

Complex Concurrent Statements

with-select-when

20

Selected Signal Assignment :with-select-when

with EXPRESSION select
TARGET <= VALUE_1 when CHOICE_1,

with-select-when

VALUE_2 when CHOICE_2 | CHOICE_3,

Syntax is

VALUE_3 when CHOICE_4 to CHOICE_5,

with select_signal select

signal_name <= value1 when value1_of_select_sig,
value2 when value2_of_select_sig,
value3 when value3_of_select_sig,
value_default when others;

VALUE_n when others;

Choice options must not overlap;

All choice options have to be covered (single values ; value range ;
selection of values
("|" means "or") ; "when others" covers all remaining choice options );
21

entity SELECTED_ASSIGNMENT is
port (A, B, C, X : in integer range 0 to 15;
Z_CONC : out integer range 0 to 15;
end SELECTED_ASSIGNMENT;

architecture EXAMPLE of SELECTED_ASSIGNMEN

T is
begin
-- Concurrent version of selected signal assignment
with X select
Z_CONC <= A when 0,
B when 7 | 9,
C when 1 to 5,
0 when others;
end EXAMPLE;

22

w0
w3
LIBRARY ieee ;
USE ieee.std_logic_1164.all ;
ENTITY mux4to1 IS
PORT ( w0, w1, w2, w3
s
f
END mux4to1 ;

4-to-1 MUL

s0 s1
: IN
: IN
: OUT

STD_LOGIC ;
STD_LOGIC_VECTOR(1 DOWNTO 0) ;
STD_LOGIC ) ;

ARCHITECTURE Behavior OF mux4to1 IS

BEGIN
WITH s SELECT
f <=
w0 WHEN "00",
w1 WHEN "01",
w2 WHEN "10",
w3 WHEN 11 ;
END Behavior ;
23

VHDL code for a 4-to-1 multiplexer

24

19-Feb-11

Complex Concurrent Statements

With-select-when

Complex Concurrent Statements

With-select-when

Example
---- library statements (not shown)
entity my_test is
port( a3,a2,a1,a0: in std_logic_vector(3 downto 0);
s: in std_logic_vector(1 downto 0);
y: out std_logic_vector(3 downto 0));
end entity my_test;
architecture behavior of my_test is
begin
with s select
y <= a3 when 11,
a2 when 10,
a1 when 01,
a0 when others; -- default condition
end architecture behavior;

What is the logic expression for y?

yn = a0 n s1 s0 + a1n s1s0 + a2 n s1 s0 + a3n s1s0

n = 0,1, 2,3
What is this in hardware?
A 4-bit 4X1 MUX

A3

A3

A2

A2

A1

A1

A0

A0

MUX
Mux

S
25

26

27

28

A 74x138-like 3-to-8 binary decoder.

29

VHDL architecture with a maintainable

approach to active-level handling

30

19-Feb-11

when_else
The signal is assigned a value based on
a condition.
signal_name <= value_1 when condition1 else
value_2 when condition2 else
value_3 when condition3 else

value_n;

31

UNAFFECTED with With/Slect/When

Whenever WITH / SELECT / WHEN is used, all permutations
must be tested, so the keyword OTHERS is often useful. Another
important keyword is UNAFFECTED, which should be used
when no action is to take place.
Example:
---- With WITH/SELECT/WHEN ------------------WITH control SELECT
output <=
"000" WHEN reset,
"111" WHEN set,
UNAFFECTED WHEN OTHERS;
----------------------------------------------

32

Conditional Signal Assignment : when-else

TARGET <= VALUE_1 when CONDITION_1 else
VALUE_2 when CONDITION_2 else
...
VALUE_n;

Condition is a boolean expression;

Example: true table:
Input

Output

33

34

35

36

LIBRARY IEEE;

Input

USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY example is
PORT(

X,Y

: IN

Std_Logic;

: OUT

Std_Logic

);

Output

END example;
ARCHITECTURE a OF example IS
BEGIN
Z <= '0' When (X='0' and Y='0') Else
'1' When (X='0' and Y='1') Else
'1' When (X='1' and Y='0') Else
'0';
END a;

19-Feb-11

when-else implementation of MUX

entity mux is port(
a,b,c,d : in std_logic_vector(3 downto 0);
s : in std_logic_vector(1 downto 0);
x: out std_logic_vector(3 downto 0));
end mux;
architecture when_else of mux is
begin
x <= a when (s=00) else
b when (s=01) else
c when (s=10) else
d;
end when_else;

This example shows the

implementation of the same
multiplexer of example 5.1, but
with a slightly different
representation for the sel input
(figure 5.5). However, in it WHEN
was employed instead of logical
operators. Two solutions are
presented: one using WHEN/ELSE
(simple WHEN) and the other with
WITH/SELECT/WHEN (selected
WHEN).
37

MUX with WHEN/ELSE

1 ------- Solution 1: with WHEN/ELSE -------2 LIBRARY ieee;
3 USE ieee.std_logic_1164.all;
4 ------------------------------------------5 ENTITY mux IS
6 PORT ( a, b, c, d: IN STD_LOGIC;
7
sel: IN STD_LOGIC_VECTOR (1 DOWNTO 0);
8
y: OUT STD_LOGIC);
9 END mux;
10 ------------------------------------------11 ARCHITECTURE mux1 OF mux IS
12 BEGIN
13
y <=
a
WHEN sel="00" ELSE
14
b
WHEN sel="01" ELSE
15
c
WHEN sel="10" ELSE
16
d;
17 END mux1;
18 -------------------------------------------

---------------------------------------------2 LIBRARY ieee;

3 USE ieee.std_logic_1164.all;
4 ---------------------------------------------5 ENTITY mux IS
6 PORT ( a, b, c, d: IN STD_LOGIC;
7 sel: IN INTEGER RANGE 0 TO 3;
8 y: OUT STD_LOGIC);
9 END mux;
10 ---- Solution 1: with WHEN/ELSE -------11 ARCHITECTURE mux1 OF mux IS
12 BEGIN
13 y <= a WHEN sel=0 ELSE
14
b WHEN sel=1 ELSE
15
c WHEN sel=2 ELSE
16
d;
17 END mux1;

Example 5.2: Multiplexer #2

38

MUX with WITH/SELECT/WHEN

39

18 -- Solution 2: with ------ WITH/SELECT/WHEN ---19 ARCHITECTURE mux2 OF mux IS

20 BEGIN
21 WITH sel SELECT
22
y <= a WHEN 0,
23
b WHEN 1,
24
c WHEN 2,
25 d WHEN 3; -- here, 3 or
26 --- OTHERS are equivalent,
26 END mux2; -- for all options are tested
----- anyway
27 -----------------------------------------------

41

1 --- Solution 2: with WITH/SELECT/WHEN ----2 LIBRARY ieee;

3 USE ieee.std_logic_1164.all;
4 ------------------------------------------5 ENTITY mux IS
6 PORT ( a, b, c, d: IN STD_LOGIC;
7
sel: IN STD_LOGIC_VECTOR (1 DOWNTO 0);
8
y: OUT STD_LOGIC);
9 END mux;
10 ------------------------------------------11 ARCHITECTURE mux2 OF mux IS
12 BEGIN
13 WITH sel SELECT
14
y <=
a
WHEN "00", -- notice "," instead of ";"
15
b
WHEN "01",
16
c
WHEN "10",
17
d
WHEN OTHERS; -- cannot be "d WHEN "11" "
18 END mux2;
19 --------------------------------------------

40

Example 5.3: Tri-state Buffer

This is another example that illustrates the use
of WHEN. The 3-state buffer of figure 5.6
must provide output = input when ena (enable)
is low, or output = ZZZZZZZZ (high
impedance) otherwise.

42

19-Feb-11

Tri-state Buffer

Simulation results of example 5.3.

1 LIBRARY ieee;
2 USE ieee.std_logic_1164.all;
3 ---------------------------------------------4 ENTITY tri_state IS
5 PORT ( ena: IN STD_LOGIC;
6
input: IN STD_LOGIC_VECTOR (7 DOWNTO 0);
7
output: OUT STD_LOGIC_VECTOR (7 DOWNTO 0));
8 END tri_state;
9 ---------------------------------------------10 ARCHITECTURE tri_state OF tri_state IS
11 BEGIN
12
output <= input
WHEN (ena='0') ELSE
13
(OTHERS => 'Z');
14 END tri_state;
43
15 ----------------------------------------------

Encoder with WHEN/ELSE

Example 5.4: Encoder

The top-level diagram of an nby-m encoder is shown in
figure 5.8. We assume that n
is a power of two, so m =
log2n. One and only one input
bit is expected to be high at a
time, whose address must be
encoded at the output. Two
solutions are presented, one
using WHEN / ELSE, and the
other with WITH / SELECT /
WHEN.

44

45

1 ---- Solution 1: with WHEN/ELSE ------------2 LIBRARY ieee;

3 USE ieee.std_logic_1164.all;
4 --------------------------------------------5 ENTITY encoder IS
6 PORT ( x: IN STD_LOGIC_VECTOR (7 DOWNTO 0);
7
y: OUT STD_LOGIC_VECTOR (2 DOWNTO 0));
8 END encoder;
9 --------------------------------------------10 ARCHITECTURE encoder1 OF encoder IS
11 BEGIN
12
y <=
"000"
WHEN x="00000001" ELSE
13
"001"
WHEN x="00000010" ELSE
14
"010"
WHEN x="00000100" ELSE
15
"011"
WHEN x="00001000" ELSE
16
"100"
WHEN x="00010000" ELSE
17
"101"
WHEN x="00100000" ELSE
18
"110"
WHEN x="01000000" ELSE
19
"111"
WHEN x="10000000" ELSE
20
"ZZZ";
21 END encoder1;
22 ---------------------------------------------

46

Encoder with WITH/SELECT/WHEN

1 ---- Solution 2: with WITH/SELECT/WHEN -----2 LIBRARY ieee;
3 USE ieee.std_logic_1164.all;
4 --------------------------------------------5 ENTITY encoder IS
6 PORT ( x: IN STD_LOGIC_VECTOR (7 DOWNTO 0);
7
y: OUT STD_LOGIC_VECTOR (2 DOWNTO 0));
8 END encoder;
9 --------------------------------------------10 ARCHITECTURE encoder2 OF encoder IS
11 BEGIN
12 WITH x SELECT
13
y <=
"000"
WHEN "00000001",
14
"001"
WHEN "00000010",
15
"010"
WHEN "00000100",
16
"011"
WHEN "00001000",
17
"100"
WHEN "00010000",
18
"101"
WHEN "00100000",
19
"110"
WHEN "01000000",
20
"111"
WHEN "10000000",
21
"ZZZ" WHEN OTHERS;
22 END encoder2;

Simulation results of example 5.4

47

48

19-Feb-11

Operation tale of ALU

Example 5.5: ALU
An ALU (Arithmetic Logic Unit) is shown in figure 5.10. As
the name says, it is a circuit capable of executing both kinds of
operations, arithmetic as well as logical. Its operation is
described in the truth table of figure 5.10. The output
(arithmetic or logical) is selected by the MSB of sel, while the
specific operation is selected by sels other three bits.

49

1 ---------ALU---------------------------------2 LIBRARY ieee;

3 USE ieee.std_logic_1164.all;
4 USE ieee.std_logic_unsigned.all;
5 ---------------------------------------------6 ENTITY ALU IS
7 PORT (a, b: IN STD_LOGIC_VECTOR (7 DOWNTO 0);
8 sel: IN STD_LOGIC_VECTOR (3 DOWNTO 0);
9 cin: IN STD_LOGIC;
10 y: OUT STD_LOGIC_VECTOR (7 DOWNTO 0));
11 END ALU;
12 ---------------------------------------------13 ARCHITECTURE dataflow OF ALU IS
14 SIGNAL arith, logic: STD_LOGIC_VECTOR (7
DOWNTO 0);
15 BEGIN
16 ----- Arithmetic unit: -----17 WITH sel(2 DOWNTO 0) SELECT
18 arith <= a WHEN "000",
19 a+1 WHEN "001",
20 a-1 WHEN "010",
21 b WHEN "011",

23 b-1 WHEN "101",

24 a+b WHEN "110",
25 a+b+cin WHEN OTHERS;
26 ----- Logic unit: ----------27 WITH sel(2 DOWNTO 0) SELECT
28 logic <= NOT a WHEN "000",
29 NOT b WHEN "001",
30 a AND b WHEN "010",
31 a OR b WHEN "011",
32 a NAND b WHEN "100",
33 a NOR b WHEN "101",
34 a XOR b WHEN "110",
35 NOT (a XOR b) WHEN OTHERS;
36 -------- Mux: --------------37 WITH sel(3) SELECT
38 y <= arith WHEN '0',
39 logic WHEN OTHERS;
40 END dataflow;
41 ----------------------------------------------

50

Entity declaration of ALU

1 ---------------------------------------------2 LIBRARY ieee;
3 USE ieee.std_logic_1164.all;
4 USE ieee.std_logic_unsigned.all;
5 ---------------------------------------------6 ENTITY ALU IS
7 PORT (a, b: IN STD_LOGIC_VECTOR (7 DOWNTO 0);
8
sel: IN STD_LOGIC_VECTOR (3 DOWNTO 0);
9
cin: IN STD_LOGIC;
10
y: OUT STD_LOGIC_VECTOR (7 DOWNTO 0));
11 END ALU;
12 ----------------------------------------------

51

Code for Arithmetic unit

13 ARCHITECTURE dataflow OF ALU IS
14 SIGNAL arith, logic: STD_LOGIC_VECTOR (7 DOWNTO
0);
15 BEGIN
16 ----- Arithmetic unit: -----17 WITH sel(2 DOWNTO 0) SELECT
18
arith <=
a
WHEN "000",
19
a+1 WHEN "001",
20
a-1
WHEN "010",
21
b
WHEN "011",
22
b+1 WHEN "100",
23
b-1
WHEN "101",
24
a+b WHEN "110",
53
25
a+b+cin WHEN OTHERS;

52

Codes for Logit unit and Mux

26 ----- Logic unit: ----------27 WITH sel(2 DOWNTO 0) SELECT
28
logic <=
NOT a
WHEN "000",
29
NOT b
WHEN "001",
30
a AND b
WHEN "010",
31
a OR b
WHEN "011",
32
a NAND b
WHEN "100",
33
a NOR b
WHEN "101",
34
a XOR b
WHEN "110",
35
NOT (a XOR b) WHEN OTHERS;
36 -------- Mux: --------------37 WITH sel(3) SELECT
38
y <= arith WHEN '0',
39
logic WHEN OTHERS;
40 END dataflow;
41 ----------------------------------------------

54

19-Feb-11

GENERATE
GENERATE is another concurrent statement (along
with operators and WHEN). It is equivalent to the
sequential statement LOOP (chapter 6) in the sense
that it allows a section of code to be repeated a
number of times, thus creating several instances of
the same assignments. Its regular form is the FOR /
GENERATE construct, with the syntax shown below.
Notice that GENERATE must be labeled.
Syntax of FOR / GENERATE:
label: FOR identifier IN range GENERATE
(concurrent assignments)
END GENERATE;

Combinational Logic with

GENERATE

55

IF/GENERATE
An irregular form is also available, which uses
IF/GENERATE (with an IF equivalent; recall that
originally IF is a sequential statement). Here ELSE is not
allowed. In the same way that IF/GENERATE can be
nested inside FOR/GENERATE (syntax below), the
opposite can also be done.
IF / GENERATE nested inside FOR / GENERATE:
label1: FOR identifier IN range GENERATE
...
label2: IF condition GENERATE
(concurrent assignments)
END GENERATE;
...
57
END GENERATE;

We also must to be aware of multiply-driven (unresolved)

signals. For example,
OK: FOR i IN 0 TO 7 GENERATE
output(i)<='1' WHEN (a(i) AND b(i))='1' ELSE '0';
END GENERATE;
is fine. However, the compiler will complain that accum is
multiply driven (and stop compilation) in either of the
following two cases:
NotOK: FOR i IN 0 TO 7 GENERATE
accum <="11111111" WHEN (a(i) AND b(i))='1' ELSE
"00000000";
END GENERATE;
NotOK: For i IN 0 to 7 GENERATE
accum <= accum + 1 WHEN x(i)='1';
END GENERATE;
59

56

Example:
SIGNAL x: BIT_VECTOR (7 DOWNTO 0);
SIGNAL y: BIT_VECTOR (15 DOWNTO 0);
SIGNAL z: BIT_VECTOR (7 DOWNTO 0);
...
G1: FOR i IN x'RANGE GENERATE
z(i) <= x(i) AND y(i+8);
END GENERATE;
One important remark about GENERATE (and the same is true for
LOOP, which will be seen in chapter 6) is that both limits of the
range must be static. As an example, let us consider the code
below, where choice is an input (non-static) parameter. This kind
of code is generally not synthesizable.
NotOK: FOR i IN 0 TO choice GENERATE
(concurrent statements)
58
END GENERATE;

Example 5.6: Vector Shifter

This example illustrates the use of GENERATE. In it, the output
vector must be a shifted version of the input vector, with twice its
width and an amount of shift specified by another input. For
example, if the input bus has width 4, and the present value is
1111, then the output should be one of the lines of the
following matrix (the original vector is underscored):
row(0): 0 0 0 0 1 1 1 1
row(1): 0 0 0 1 1 1 1 0
row(2): 0 0 1 1 1 1 0 0
row(3): 0 1 1 1 1 0 0 0
row(4): 1 1 1 1 0 0 0 0
The first row corresponds to the input itself, with no shift and the
most significant bits filled with 0s. Each successive row is equal
60
to the previous row shifted one position to the left.

10

19-Feb-11

1 ------------------Vector Shifter-----------------------------2 LIBRARY ieee;

3 USE ieee.std_logic_1164.all;
4 -----------------------------------------------5 ENTITY shifter IS
6 PORT ( inp: IN STD_LOGIC_VECTOR (3 DOWNTO 0);
7
sel: IN INTEGER RANGE 0 TO 4;
8
outp: OUT STD_LOGIC_VECTOR (7 DOWNTO 0));
9 END shifter;
10 -----------------------------------------------11 ARCHITECTURE shifter OF shifter IS
12
SUBTYPE vector IS STD_LOGIC_VECTOR (7 DOWNTO 0);
13
TYPE matrix IS ARRAY (4 DOWNTO 0) OF vector;
14
SIGNAL row: matrix;
15 BEGIN
16
row(0) <= "0000" & inp;
17
G1:
FOR i IN 1 TO 4 GENERATE
18
row(i) <= row(i-1)(6 DOWNTO 0) & '0';
19
END GENERATE;
20
outp <= row(sel);
21 END shifter;

Simulation results of example 5.6

61

62

BLOCK
There are two kinds of BLOCK statements:
Simple and
Guarded.

BLOCK
63

Simple BLOCK
The BLOCK statement, in its simple form,
represents only a way of locally partitioning
the code. It allows a set of concurrent
statements to be clustered into a BLOCK, with
the purpose of turning the overall code more
readable and more manageable (which might
be helpful when dealing with long codes). Its
syntax is shown below.
label: BLOCK
[declarative part]
BEGIN
(concurrent statements)
65
END BLOCK label;

64

Overall aspect of a blocked code

-----------------------ARCHITECTURE example ...
BEGIN
...
block1: BLOCK
BEGIN
...
END BLOCK block1;
...
block2: BLOCK
BEGIN
...
END BLOCK block2;
...
END example;
------------------------

66

11

19-Feb-11

Nested BLOCK
Example:
b1: BLOCK
SIGNAL a: STD_LOGIC;
BEGIN
a <= input_sig WHEN ena='1' ELSE 'Z';
END BLOCK b1;

67

Guarded BLOCK
A guarded BLOCK is a special kind of BLOCK, which
includes an additional expression, called guard expression.
A guarded statement in a guarded BLOCK is executed only
when the guard expression is TRUE.
Guarded BLOCK:
label: BLOCK (guard expression)
[declarative part]
BEGIN
(concurrent guarded and unguarded statements)
END BLOCK label;
As the examples below illustrate, even though only
concurrent statements can be written within a BLOCK, with
a guarded BLOCK even sequential circuits can be
constructed. This, however, is not a usual design approach.
69

Example 5.8: DFF Implemented with a

Guarded BLOCK
Here, a positive-edge sensitive D-type flipflop, with synchronous reset, is designed. The
interpretation of the code is similar to that in
the example above. In it, clk'EVENT AND
clk='1' (line 12) is the guard expression, while
q <= GUARDED '0 WHEN rst='1' (line 14) is
a guarded statement. Therefore, q<='0' will
occur when the guard expression is true and rst
is 1.
71

A BLOCK (simple or guarded) can be nested inside

another BLOCK. The corresponding syntax is shown
below.
label1: BLOCK
[declarative part of top block]
BEGIN
[concurrent statements of top block]
label2: BLOCK
[declarative part nested block]
BEGIN
(concurrent statements of nested block)
END BLOCK label2;
[more concurrent statements of top block]
68
END BLOCK label1;

Example 5.7: Latch Implemented with

a Guarded BLOCK
The example presented below implements a transparent latch. In it, clk='1' (line
12) is the guard expression, while q<=GUARDED d (line 14) is a guarded statement.
Therefore, q<=d will only occur if clk='1'.
1 ------------------------------2 LIBRARY ieee;
3 USE ieee.std_logic_1164.all;
4 ------------------------------5 ENTITY latch IS
6 PORT (d, clk: IN STD_LOGIC;
7 q: OUT STD_LOGIC);
8 END latch;
9 ------------------------------10 ARCHITECTURE latch OF latch IS
11 BEGIN
12 b1: BLOCK (clk='1')
13 BEGIN
14 q <= GUARDED d;
15 END BLOCK b1;
70
16 END latch;
17 -------------------------------

DFF Implemented with a Guarded BLOCK

1 ------------------------------2 LIBRARY ieee;
3 USE ieee.std_logic_1164.all;
4 ------------------------------5 ENTITY dff IS
6 PORT ( d, clk, rst: IN STD_LOGIC;
7 q: OUT STD_LOGIC);
8 END dff;
9 ------------------------------10 ARCHITECTURE dff OF dff IS
11 BEGIN
12 b1: BLOCK (clk'EVENT AND clk='1')
13 BEGIN
14
q <= GUARDED '0' WHEN rst='1' ELSE d;
15 END BLOCK b1;
16 END dff;
17 ------------------------------

72

12

19-Feb-11

Sequential Code
VHDL code is inherently concurrent. PROCESSES,
FUNCTIONS, and PROCEDURES are the only sections
of code that are executed sequentially. However, as a
whole, any of these blocks is still concurrent with any
other statements placed outside it.
One important aspect of sequential code is that it is not
limited to sequential logic. Indeed, with it we can build
sequential circuits as well as combinational circuits.
Sequential code is also called behavioral code.
The statements discussed in this section are all
sequential, that is, allowed only inside PROCESSES,
FUNCTIONS, or PROCEDURES. They are: IF, WAIT,
CASE, and LOOP.

Sequential Code
73

74

Behavioral Statements

Variables

Concurrent assignment statements and

structural descriptions are sufficient to model
any hardware architecture
State machines and storage devices are hard to
model using dataflow and structural descriptions
Most algorithms are semi-sequential in nature
Behavioral descriptions greatly simplify
sequential models
VHDL provides sophisticated mechanisms for
sequential descriptions

VARIABLES are also restricted to be used in

sequential code only (that is, inside a PROCESS,
FUNCTION, or PROCEDURE). Thus, contrary to a
SIGNAL, a VARIABLE can never be global, so its
value can not be passed out directly.
We will concentrate on PROCESSES here.
FUNCTIONS and PROCEDURES are very similar,
but are intended for system-level design, being
therefore seen in Part II of this book.
75

Processes

76

Processes

processname : process(sensitivylist)is
declarations
begin
sequentialstatements
end process processname;
-- sensitivylist : list of signals triggering the process on event
-- declarations: types, variables that will be used in the process
-signal definitions are not allowed here! (behavioral code)
-- processname: identifier of the process (optional)
77

process constructs are used to describe

behavioral models
A process lives in an architecture
An architecture may include multiple processes
A process may NOT include CSA or SSAs

78

13

19-Feb-11

79

80

Processes
library ieee;
use ieee.std_logic_1164.all;
entity foo is
port(x,y : in std_logic;
z
: out std_logic);
end foo;
architecture beh of foo is
signal s : std_logic;
begin
process(x,y) is
begin
s <= x and y;
z <= not s;
end process;
end architecture beh;
81

Wait Statements

wait on sensitivitylist;
wait for time;
wait until condition;

Provides alternative mechanism to suspend a process

NOT supported by XilinX Foundation Tools!
wait on data_in; -- wait until an event on data_in occurs
wait on a,b,c; -- wait until an event on either
-- a OR b OR c occurs
wait until a>b; -- wait until condition is satisfied
wait for 100 ns; -- suspend process execution for 100ns
wait on a for 10 ns; -- wait on signal a for event, if no
-- event occurs in 10ns resume execution
wait on a until b=c; -- ...

82

Wait Statements
Each process must have a sensitivity list or at
least one wait statement
Example: Two identical definitions
architecture beh of ha is
begin
process(a,b)
begin
sum <= a xor b;
carry <= a and b;
end;
end beh;

83

architecture beh of ha is
begin
process --no sens.list
begin
sum <= a xor b;
carry <= a and b;
wait on a,b; -- wait state.
end;
end beh;

84

14

19-Feb-11

Wait Statements

Design with cocurrent code and

sequential code

Wait statements are more powerful, but also

more difficult to synthesize!
--generates clock with T=20ns
--useful in testbenches
architecture beh of clkgen is
begin
process
begin
clk <= 0;
wait for 10 ns;
clk <= 1;
wait for 10 ns;
end;
end beh;

85

Entity Declaration of gate network

LIBRARYIEEE; --Include Libraries for standard logic data types
USEIEEE.STD_LOGIC_1164.ALL;
--Entity name normally the same as file name
ENTITYgate_network IS
--Ports: Declares module inputs and
outputs
PORT(A, B, C : IN STD_LOGIC;
--Standard Logic Vector ( Array of 4 Bits )
D : IN STD_LOGIC_VECTOR( 3 DOWNTO0 );
--Output Signals
X, Y : OUT STD_LOGIC );
ENDgate_network;

86

Architecture body of gate network

--Defines internal module architecture
ARCHITECTUREbehavior OFgate_network IS
BEGIN -- Concurrent assignment statements operate in parallel
-- D(1) selects bit 1 of standard logic vector D
X <= A AND NOT( B OR C ) AND( D(1) XOR D(2));
-- Process must declare a sensitivity list,
-- In this case it is ( A, B, C, D )
-- List includes all signals that can change the outputs
PROCESS( A, B, C, D )
BEGIN -- Statements inside process execute sequentially
Y <= A AND NOT( B OR C) AND (D(1 XOR D(2));
ENDPROCESS;
ENDbehavior;

87

88

If Statements
If statements allow
conditional execution of
statements
May contain multiple
elsif branches and one
else branch
The else branch will be
active if no conditions
are satisfied
Absence of ELSE
results in implicit
memory
if statements may be
nested

ifthenend if
if condition1 then
sequentialstatements
elsif condition2 then
sequentialstatements
else
sequentialstatements
end if;

89

condition

if condition then
statements ;
end if ;

yes

no

statements

if ENABLE = 1 then
Q <= D ;

end if ;

ENABLE

90

15

19-Feb-11

ifthenend if
if condition then

No

statements A ;
else
statements B ;
end if ;

ifthenend if

Statements B

if condition_1 then
statements A ;
elsif condition_2 then
statements B;
:
end if ;

Yes

condition

Statements A

if A = B then
F <= 1 ;
else
F <= 0 ;
end if ;

yes
Condition_1

Condition_1

Statements B

no

CLK

8
Q

RESET

Binary Counter

ifthenend if
if condition_1 then
statements A ;
elsif condition_2 then
statements B ;
else
statements C ;
end if ;

yes

Condition_2

if RESET = 0 then
Q <= X 00 ;
elsif CLKevent and CLK = 1 then
Q <= Q + 1;
end if ;
91

Statements A

no

92

ifthenend if
priority

yes
Statements A

no
yes
Condition_2

if x= 1 then
F <= A ;
elsif y = 1 then
F <= B ;
else
F <= C;
end if ;

Statements B

no
Statements C

if A > B then
F <= 100 ;
elsif A < B then
F <= 010 ;
else
F <= 001 ;
end if ;

EQV

93

94

Case Statements

if-then-else
4-1 mux shown below
mux4_1: process (a, b, c, d, s)
begin
if s = 00 then x <= a ;
elsif s = 01 then x <= b ;
elsif s = 10 then x <= c ;
else x <= d ;
end if;
end process mux4_1 ;

s
2

a
b
c
d

1
2
3

4:1 MUX

Case statements allow

conditional execution of
case expression is
statements according to a
when choices1 =>
single expression
sequentialstatements1
The when others branch
will be active if no choices
when choices2 =>
are matched
sequentialstatements2
Choices must be mutually
...
exclusive!
when others =>
A choice is a list of discrete
sequentialstatements
constant values
end case;
Case statements may be
nested
96

16

19-Feb-11

Case is when
CASE signal X IS
when value_1 =>
statements A ;
when value_2 =>
statements B ;
:
when others =>
statements P ;
END CASE;
Value must Exclusive
When others cover all others value
Value may be:
only one constant (when 101 )
up to two constant (when 3 | 7 | 9 )
Interval
(when 5 to 9 )

Value_1

Case is when

yes

Statements A

NO

Value_2

yes

Statements B

case A is
when 00 => y <= 0111 ;
when 01 => y <= 1011 ;
when 10 => y <= 1101 ;
when 11 => y <= 1110 ;
when others => y <= 1111 ;
end case;

NO

Statements A

97

98

The CASE Statement: 4-1 Mux

ARCHITECTURE archdesign OF design IS
SIGNAL s: std_logic_vector(0 TO 1);
BEGIN
mux4_1: PROCESS (a,b,c,d,s)
BEGIN
CASE s IS
WHEN "00" => x <= a;
WHEN "01" => x <= b;
WHEN "10 => x <= c;
WHEN OTHERS => x <= d;
END CASE;
END PROCESS mux4_1;
END archdesign;

s
2

a
b
c
d

1
2
3

4:1 MUX

100

3-to-8 Decoder
A: in STD_LOGIC_VECTOR(2 downto 0);
Y: out STD_LOGIC_VECTOR(0 to 7);

Behavior
for i in 0 to 7 loop
if(i = conv_integer(A))
Y(i) <= 1;
A2
else
0
Y(i) <= 0;
0
end if;
0
end loop;

101

0
1
1
1
1

then
A1 A0

Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7

0
0
1
1
0
0
1
1

1
0
0
0
0
0
0
0

0
1
0
1
0
1
0
1

0
1
0
0
0
0
0
0

0
0
1
0
0
0
0
0

0
0
0
1
0
0
0
0

0
0
0
0
1
0
0
0

0
0
0
0
0
1
0
0

0 0
0 0
0 0
0 0
0 0
0 0
1 0
01021

17

19-Feb-11

library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_arith.all;
use IEEE.STD_LOGIC_unsigned.all;

3-to-8 Decoder

entity decode38 is
port(
A : in STD_LOGIC_VECTOR(2 downto 0);
Y : out STD_LOGIC_VECTOR(0 to 7)
);
end decode38;
architecture decode38 of decode38 is
begin
process(A)
variable j: integer;
begin
j := conv_integer(A);
for i in 0 to 7 loop
if(i = j) then
Y(i) <= '1';
else
Y(i) <= '0';
end if;
end loop;
end process;
end decode38;

103

104

105

106

107

108

18

19-Feb-11

109

110

111

112

Implicit memory
Signals in VHDL have a current value and may
be scheduled for a future value
If the future value of a signal cannot be
determined, a latch will be synthesized to
preserve its current value
Advantages:
Simplifies the creation of memory in logic design

Disadvantages:
113

Can generate unwanted latches, e.g., when all of the

options in a conditional sequential statement are not
specified

19

19-Feb-11

Implicit memory:
Example of incomplete specification
ARCHITECTURE archincomplete OF
incomplete IS
BEGIN
im_mem: PROCESS (a,b)
BEGIN

a
c

IF a = '1'
THEN c <= b;
END IF;
END PROCESS im_mem;
END archincomplete;

Note: the incomplete specification of the

IF...THEN... statement causes a latch to be
synthesized to store the previous state of c

The rules to avoid implicit memory

To avoid the generation of unexpected latches
always terminate an IF...THEN... statement with
an ELSE clause
cover all alternatives in a CASE statement
define every alternative individually, or
terminate the CASE statement with a WHEN
OTHERS... clause, e.g.,
CASE coin_inserted IS
WHEN quarter => total<=total+25;
WHEN dime => total<=total+10;
WHEN nickel => total<=total+5;
WHEN OTHERS => total<=total;
error<=1;
END CASE;

CASE versus WHEN

CASE and WHEN are very similar. However, while one is
concurrent (WHEN), the other is sequential (CASE). Their main
similarities and dierences are summarized in table 6.1.
Example: From a functional point of view, the two codes below
are equivalent.
---- With WHEN: ---------------WITH sel SELECT
x <= aWHEN "000",
b WHEN "001",
c WHEN "010",
UNAFFECTED WHEN OTHERS;
---- With CASE: ---------------CASE sel IS
WHEN "000" => x<=a;
WHEN "001" => x<=b;
WHEN "010" => x<=c;
WHEN OTHERS => NULL;
119
END CASE;

Implicit memory:
Example of complete specification
ARCHITECTURE archcomplete OF
complete IS
BEGIN
no_mem: PROCESS (a, b)
BEGIN
IF a = '1'
THEN c <= b;
ELSE c <= '0';
END IF;
END PROCESS no_mem;
END archcomplete;

a
b

 The conditional statement is fully specified, and this

causes the process to synthesize to a single gate

CASE versus IF
VHDL code based on IF not to dier from that based on CASE
Example: The codes below implement the same physical
multiplexer circuit.
---- With IF: -------------IF (sel="00") THEN x<=a;
ELSIF (sel="01") THEN x<=b;
ELSIF (sel="10") THEN x<=c;
ELSE x<=d;
---- With CASE: -----------CASE sel IS
WHEN "00" => x<=a;
WHEN "01" => x<=b;
WHEN "10" => x<=c;
WHEN OTHERS => x<=d;
118
END CASE;
----------------------------

Table 6.1
Comparison between WHEN and CASE.

120

20

19-Feb-11

7-Segment Display

7-Segment Display

VHDL
D(3:0)

Truth table
D
0
1
2
3
4
5
6
7

a
1
0
1
1
0
1
1
1

b
1
1
1
1
1
0
0
1

c
1
1
0
1
1
1
1
1

d
1
0
1
1
0
1
1
0

e
1
0
1
0
0
0
1
0

f
1
0
0
0
1
1
1
0

g
0
0
1
1
1
1
1
0

D
8
9
A
b
C
d
E
F

a
1
1
1
0
1
0
1
1

b
1
1
1
0
0
1
0
0

c
1
1
1
1
0
1
0
0

d
1
1
0
1
1
1
1
0

seg7dec

e
1
0
1
1
1
1
1
1

f
1
1
1
1
1
0
1
1

g
1
1
1
1
0
1
1
1

AtoG(6:0)

Behavior
(Active LOW)

a
f

b
g

b
g

c
e

d
d

digit(3:0)

seg7dec

-- seg7dec
with digit select
ssg <= "1001111"
"0010010"
"0000110"
AtoG
"1001100"
"0100100"
"0100000"
"0001111"
"0000000"
"0000100"
"0001000"
"1100000"
"0110001"
"1000010"
"0110000"
sseg(6:0)
"0111000"
"0000001"

when
when
when
when
when
when
when
when
when
when
when
when
when
when
when
when

"0001",
"0010",
"0011",
"0100",
"0101",
"0110",
"0111",
"1000",
"1001",
"1010",
"1011",
"1100",
"1101",
"1110",
"1111",
others;

121

BCD to 7-segment Code Converter

LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY BCD IS
PORT (I :IN STD_LOGIC_VECTOR(3 DOWNTO 0);
SegmentsI :OUT STD_LOGIC_VECTOR(1 TO 7)
);
END BCD;

S2
0
0
0
0
1
1
1
1

S1
0
0
1
1
0
0
1
1

S0
0
1
0
1
0
1
0
1

Pass
AND
OR
NOT
Addition
Subtraction
Increment
Decrement

ARCHITECTURE Behavioral OF BCD IS

SIGNAL Segs: STD_LOGIC_VECTOR(1 to 7);
BEGIN
PROCESS(I)
BEGIN
CASE I IS
WHEN "0000" => Segs <= "1111110"; -- 0
WHEN "0001" => Segs <= "0110000"; -- 1

END CASE;
SegmentsI <= not Segs;-- invert the 0.s and 1.s
END PROCESS;
END Behavioral;

124

Entity Declaration of simple ALU

Operation Table of Simple ALU

Operation name

122

WHEN "0010" => Segs <= "1101101"; -- 2

WHEN "0011" => Segs <= "1111001"; -- 3
WHEN "0100" => Segs <= "0110011"; -- 4
WHEN "0101" => Segs <= "1011011"; -- 5
WHEN "0110" => Segs <= "1011111"; -- 6
WHEN "0111" => Segs <= "1110000"; -- 7
WHEN "1000" => Segs <= "1111111"; -- 8
WHEN "1001" => Segs <= "1110011"; -- 9
WHEN "1010" => Segs <= "1110111"; -- A
WHEN "1011" => Segs <= "0011111"; -- b
WHEN "1100" => Segs <= "1001110"; -- C
WHEN "1101" => Segs <= "0111101"; -- d
WHEN "1110" => Segs <= "1001111"; -- E
WHEN "1111" => Segs <= "1000111"; -- F
WHEN OTHERS => Segs <= "0000000"; -- all off
123

Select lines

--1
--2
--3
--4
--5
--6
--7
--8
--9
--A
--b
--C
--d
--E
--F
--0

Operation

LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
ENTITY alu IS
PORT (S: IN STD_LOGIC_VECTOR(2 downto 0);
-- Select for operations
A, B: IN STD_LOGIC_VECTOR(3 downto 0);
-- Input operands
F: OUT STD_LOGIC_VECTOR(3 downto 0));
-- Output
END alu;

Pass A to output
A AND B
A OR B
A'
A+ B
A- B
A+ 1
A- 1
125

126

21

19-Feb-11

ARCHITECTURE Behavior OF alu IS

BEGIN
PROCESS(S, A, B)
BEGIN
CASE S IS
WHEN "000" =>
-- Pass A through
F <= A;
WHEN "001" =>
-- AND
F <= A AND B;
WHEN "010" =>
-- OR
F <= A OR B;
WHEN "011" =>
-- Not A
F <= NOT A;
WHEN "100" =>
-- Add
F <= A + B;
WHEN "101" =>
-- Subtract
F <= A - B;
WHEN "110" =>
-- Increment
F <= A + 1;
WHEN OTHERS =>
-- Decrement
F <= A - 1;
END CASE;
END PROCESS;
END Behavior;

Comparators
Architecture
Body of
Simple ALU

X
Y

A1
A2
A3

B0
B1
B2
B3

if X = Y then
Z <= '1';
else
Z <= '0';
end if;
X
0
0
1
1

Y
0
1
0
1

Z
1
0
0
1

127

128

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

4-Bit Equality Comparator

A0

Recall that an XNOR gate can

be used as an equality detector

XNOR

A0
A1
A2
A3

C0
C1

C0
B0
C1
B1
B2

C2

B3

C3

A_EQ_B

entity eqdet4 is
Port ( A : in std_logic_vector(3 downto 0);
B : in std_logic_vector(3 downto 0);
A_EQ_B : out std_logic);
end eqdet4;

A_EQ_B

C2

architecture Behavioral of eqdet4 is

signal C: std_logic_vector(3 downto 0);
begin

C3

C <= A xnor B;
A: in STD_LOGIC_VECTOR(3 downto 0);
B: in STD_LOGIC_VECTOR(3 downto 0);
A_EQ_B: out STD_LOGIC;

A_EQ_B <= C0 and C1 and C2 and C3;

129

end Behavioral;

130

-- Comparator for unsigned and signed numbers

Comparators

library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;

A_EQ_B
A(n-1:0)

A_GT_B
comp

B(n-1:0)

A_LT_B
A_UGT_B
A_ULT_B

A, B
signed
A, B
unsigned

Signed: 2's complement signed numbers

131

A(n-1:0)

comp
B(n-1:0)

A_EQ_B
A_GT_B
A_LT_B
A_UGT_B
A_ULT_B

entity comp is
generic(width:positive);
port (
A: in STD_LOGIC_VECTOR(width-1 downto 0);
B: in STD_LOGIC_VECTOR(width-1 downto 0);
A_EQ_B: out STD_LOGIC;
A_GT_B: out STD_LOGIC;
A_LT_B: out STD_LOGIC;
A_ULT_B: out STD_LOGIC;
A_UGT_B: out STD_LOGIC
);
end comp;
132

22

19-Feb-11

architecture comp_arch of comp is

begin
CMP: process(A,B)
variable AVS, BVS: signed(width-1 downto 0);
begin
for i in 0 to width-1 loop
AVS(i) := A(i);
BVS(i) := B(i);
end loop;
A_EQ_B <= '0';
A(n-1:0)
A_GT_B <= '0';
A_LT_B <= '0';
B(n-1:0)
A_ULT_B <= '0';
A_UGT_B <= '0';
if (A = B) then
A_EQ_B <= '1';
end if;
if (AVS > BVS) then
A_GT_B <= '1';
end if;
if (AVS < BVS) then
A_LT_B <= '1';
end if;
if (A > B) then
A_UGT_B <= '1';
end if;
if (A < B) then
A_ULT_B <= '1';
end if;
end process CMP;
end comp_arch;

comp

A_EQ_B
A_GT_B
A_LT_B
A_UGT_B
A_ULT_B

Note: All outputs must be

assigned some value.
The last signal assignment
in a process is the value assigned

133

Gray Code Converter

Gray Code
Definition: An ordering of 2n binary numbers such that
only one bit changes from one entry to the next.

134

Binary - Gray Code

Conversions
Gray code: G(i), i = n 1 downto 0
Binary code: B(i), i = n 1 downto 0

Binary coding {0...7}: {000, 001, 010, 011, 100, 101, 110, 111}

Binary coding {0...7}: {000, 001, 010, 011, 100, 101, 110, 111}

Gray coding {0...7}:

Gray coding {0...7}:

{000, 001, 011, 010, 110, 111, 101, 100}

{000, 001, 011, 010, 110, 111, 101, 100}

Convert Binary to Gray:

Copy the most significant bit.
For each smaller i
G(i) = B(i+1) xor B(i)

Not unique
One method for generating a Gray code sequence:
Start with all bits zero and successively flip the
right-most bit that produces a new string.

Convert Gray to Binary:

Copy the most significant bit.
For each smaller i
B(i) = B(i+1) xor G(i)
135

library IEEE;
use IEEE.STD_LOGIC_1164.all;

136

Binary to Gray Code Conversion

bin2gray.vhd

entity bin2gray is
generic(width:positive := 3);
port(
B : in STD_LOGIC_VECTOR(width-1 downto 0);
G : out STD_LOGIC_VECTOR(width-1 downto 0)
);
end bin2gray;
architecture bin2gray of bin2gray is
begin
process(B)
begin
G(width-1) <= B(width-1);
for i in width-2 downto 0 loop
G(i) <= B(i+1) xor B(i);
end loop;
end process;
end bin2gray;

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19-Feb-11

library IEEE;
use IEEE.STD_LOGIC_1164.all;

gray2bin.vhd

entity gray2bin is
generic(width:positive := 3);
port(
G : in STD_LOGIC_VECTOR(width-1 downto 0);
B : out STD_LOGIC_VECTOR(width-1 downto 0)
);
end gray2bin;
architecture gray2bin of gray2bin is
begin
process(G)
variable BV: STD_LOGIC_VECTOR(width-1 downto 0);
begin
BV(width-1) := G(width-1);
for i in width-2 downto 0 loop
BV(i) := BV(i+1) xor G(i);
end loop;
B <= BV;
end process;
end gray2bin;

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