SOFWARE DEFINED RADIO (SDR)

LIVE DEMO

Presenter: Ching Man, Snr. Applications Engineer

What we are trying to achieve/demonstrate

A rapid SDR system development prototyping and integration

A New Industrial Input Output (IIO) Kernel Subsystem for Convertors

A Stand-alone demo and techniques for a rapid validate of designs

without the immediate expensive equipment's (e.g. spectrum analyser
etc.) for visualisation, manipulation and inspection

Our offerings free (sw/drivers, HDL source codes, filter_design_wizard,

designs files, tech support) in providing a rapid systems integration.

(Supplement) New, Integrated All-in-one multi-voltage power ICs for

Demanding FPGAs.

10 minutes Opening up Demo for evaluation and Q&As

Demo Overview: A Stand-alone-System

Xilinx

Zynq ZC706

(Alternative: Xilinx Zedboard (low cost)

HDMI monitor/capture card
USB Keyboard & Mouse

AD-FMCOMMS2-EBZ

(AD9361)
SD

Card (8GB) , with ADI

image on it

Linux + IIO Scope

ADI SDR Reference Design :

Minimum Hardware/Interface
HDMI Monitor
Single RF
Transceiver chip

Loopback here

AD9361
(FMComms3
board)
Zynq ZC706

(i) SD- card.

(ii) USB (keyboard + Mouse)

AD9361 Overview
Major Blocks
RX Gain (AGC)
Amp-TIA
Low Pass filter
Half Bands
Programmable FIR
Clock generation
ADC/DAC
Digital filters
RF PLL/LO
Digital interface
Enable state machine
TX Attenuation
Aux DAC/ADC and
GPOs
Analog and Digital
Correction/Calibration

Pre-requisite : Matlab and toolboxes:

From Design, simulation, implementation to
realisation:
DESIGN

Simplified filter design using

trusted functions, or System
objects in MATLAB

Filter
Design

DSP System Toolbox Required

AD9361

OR

Custom HDL

VERIFICATION

IMPLEMENTATION

Rapid prototyping:

AD9361 coefficient generation

Custom HDL

Run on hardware for

verification
INTEGRATION

Demo #1 AD9361_filter_wizard
=>Open up AD9361_filter_wizard in Matlab

Data rate (from FPGA)

Combined
improvements

Data rate (from FPGA)

Programmable FIR
3x HB cascaded stages
Converter sampling speed
PLL/LO
Can Target directly to eval-board

Design Tools
FIR

Filter Designer

MATLAB
Signal

Processing
Toolbox
Fixed-Point Designer
DSP System Toolbox

Main
Tx

Functions

Filter Chains

settxfilter9361.m
designtxfilters9361.m

Rx

Filter Chains

setrxfilter9361.m
designrxfilters9361.m

Free AD9361_filter_design_wizard (Matlab apps) download

http://wiki.analog.com/resources/eval/user-guides/ad-fmcomms2-ebz/software/filters
Free SimRF model
http://www.mathworks.co.uk/hardware-support/analog-devices-rf-transceivers.html

IIO Subsystem Overview

APPLICATION

SYSTEM CALL INTERFACE

VIRTUAL FILE SYSTEM (VFS)

CHARACTER DEVICE
DRIVER

Kernel Area
IIO Subsystem

IIO BUFFER

IIO Device Drivers

IIO CORE

DEVICE DRIVER

BUS DRIVERS

Hardware

SYSFS

HARDWARE

IIO TRIGGER

IIO Scope Capabilities

AD9361

control

Global

settings
Tx/Rx settings
FPGA settings
Visualization
Time

domain
Constellation
Frequency domain

control menu and configuration settings

AD9361 Demo #2, 1 CW Tone

Demo parameters:
(1) Start-up
(2) DAC_buffer_output, (file)
10.txt
(3) Use Filter FIR =
fir_bpf_64_1.txt
Disable all and select each
What you see in the Zoom-in
Spectrum =>

Power-level
In-band close
phase noise

III order
intermodulation
distortion
Phase noise

LO leakage
Image

Noise floor

AD9361 Demo #3 MSK_20M

Demo parameters:
(1) Start-up
(2) DAC_buffer_output, (file)
MSK_20M (20M bit rate)
(3) Use Filter FIR =
Disable all and select each in
turn, GSM, etc
(4) Look at constellation (lines
and point mode)

Spectrum

What you see in the Zoom-in

Spectrum, and look at the
constellation/compensate

Constellation points
(View- lines)

EVM (clusters)
(View , Point)

AD9361 Demo #4 QAM16_20M

Demo parameters:
(1) Start-up
(2) DAC_buffer_output, (file)
qam16_20M
(3) Use Filter FIR = GSM, etc
Disable all and select each in
turn
What you see in the Zoom-in
Spectrum, and look at the
constellation/compensate

Some notes on control (global) settings

Calibration

modes (four modes)

Auto auto calibrate the defaults upon power-up.

Manual Manual configuration and calibrate prior running the demo.
Tx_Quad minimise Tx DC offset, gain and phase error to improve in the tx path
Rf_dc_offs Run during initialization or carrier move from previous (100MHz away)

TRX

rate Governor Available (2 modes) :

adjust ADC sampling rate (decimate/interpolation)

Nominal
- normal (default)
Highest osr - highest over-sampling rate (osr)

Filter FIR configurations (options)

FIR_BPF_64_1 > FIR bandpass filter of 64 taps

GSM
> GSM (spec)
LTE10_Mhz
> LTE 10MHz system with 40MHz ref. clock
UMTS
> UMTS (spec)

Some notes on Receive settings

RF

Port select

A_Balance/B_Balance > select differential port A, B etc

A_N/A_P
> select single port

Tracking

Quadrature tracking
RF DC (RF DC tracking)
BB DC ( Base Band tracking)

Gain Control (use depending on your signal variation/speed)

Manual / Fast_attack / Slow_attack / Hybrid

Some notes on FPGA files and settings

File/output

1M_10M_nyq.txt
o

10.txt/11.txt
o

16-QAM waveform waveform of 20Mbit rate, suggested sampling rate >= 30.72MSPS

Qpsknofilt_30M
o

Minimum Shift-keying waveform of 20Mbit rate, suggested sampling rate >= 30.72MSPS

QAM16_20M
o

Can use any sample rate for a basic IQ imbalance test waveform. The frequency that you will see
will be determined by the sample rate.

MSK_20M
o

Can use any sample rate for a 10 point sine wave, generating 1MHz tone @ 10MSPS

QPSK waveform of 30Mbit rate, suggested sampling rate >= 30.72MSPS

Sinewave_0.3
o These are Matlab files of various amplitude either for 1 or 2 channels (I&Q)

Free Simulink Model (Model Based Design)

e.g. model/Simulation/test LTE-like 5MHz OFDM Signal + CW Blocker

-10.5
Blocker

Simulink Test/Result e.g. MGC for 2 Tones

In-band noise Images

DC Offset

IP2

Fundamental

IP3

AD9361 Simulink TEST/Results pwr Spectrum:

for a LTE-like 10MHz OFDM Signal

Conclusions:

Model based design/simulation (using Matlab/Simulink)

System-level model of the Analog Devices Agile RF Transceiver

AD9361
Program and test the transceiver before going in the lab
The

model is lab-verified by the ADI and useful for most

customers
Control the gain settings, digital filters, AGC timing dynamics
Get better insight in the single chip transceiver and understand
where issues are coming from
Try different / varied channel impairments, which may be
impossible to replicate in the lab

Hardware Boards: FMComms2/3/4/5

AD9361
2

Tx, 2 Rx : Matched inputs and outputs

RF Evaluation platform : FMCOMMS2
Meets datasheet specs at 2.4GHz
Software Development Kit : FMCOMMS3
Wide tuning range 70 MHz 6 GHz (cons Slightly degraded performance)
AD9364
1

Tx, 1 Rx
Datasheet Specs and Wide Tuning range on one board:
FMCOMMS4

Summary:
ADI General Purpose SDR Boards
Wide tuning
Range
Narrow band
Discrete
Version

AD-FMCOMMS2

AD-FMCOMMS1

Discrete
1Rx, 1Tx
400 MHz 4GHz
tuning range
200+ MHz channel
bandwidth
Available Now

AD9361 Integrated
2 x Rx, 2 x Tx
2.2 GHz 2.6GHz
tuning range
200kHz - 56 MHz
channel bandwidth
Available Now

AD-FMCOMMS3

AD9361 Integrated
2 x Rx, 2 x Tx
70 MHz 6GHz
tuning range
200kHz - 56 MHz
channel bandwidth
Available Now

AD-FMCOMMS5

AD-FMCOMMS4

AD9364 Integrated
1 x Rx, 1 x Tx
70 MHz 6GHz
tuning range
200kHz - 56 MHz
channel bandwidth
Available Now

2 x AD9361 Integrated
4 x Rx, 4 x Tx
70 MHz 6GHz tuning
range
200kHz - 56 MHz
channel bandwidth
Releasing July 2014

Power, Transceiver

Power, Transceiver,
PLL, LNA

Pre_AMP

Power, Transceiver
TX_OUT

LNA

12P0V
IN

TX2A

RX2A

12P0V
IN

12P0V
IN

AD9361

12P0V
IN

TX_IN

RX_OUT

FMCOMMS2/3/4-EBZ

Primary side

RX_IN

Power, Transceiver

FMC COMMS BOOSTER

Rx LNA (ADL5521)

Tx Pre-Amp (ADL5610)

Power (ADP2370, ADP7104)

Releasing July 2014

RX1A

POWER

RX_IN

Power, Clocks, ADC,

DAC, PLL, DVGA,

TX1A

12P0V
OUT

Secondary side

32

RX_OUT

TX_IN

TX_OUT

FMComms3 : AD9361

PCB Component
frequency wide
turning range (70
6000 MHz)
(Close to
datasheet specs)

Tx

FPGA

Channel Attenuation

Rx

To re-create the demo, you need:

Xilinx

base platform

Zedboard : $395
ZC702
: $895
ZC706
: $2495

ADI

Follow instructions on wiki:

AD9361 board:

AD-FMComms2 : $750
RF Engineers evaluation system
Optimized for 2.4GHz, Meets all
datasheet specs

https://wiki.analog.com/resources/eval/user
-guides/ad-fmcomms2-ebz/quickstart/zynq

Download Schematics, Gerbers,

BOM:

https://wiki.analog.com/resources/eval/user
-guides/ad-fmcomms2-ebz/hardware

https://wiki.analog.com/resources/eval/user
-guides/ad-fmcomms3-ebz/hardware

AD-FMComms3 : $750
Software Developers Kit
Wide tuning range (close to datasheet
specs at 70 6000 MHz tuning range)

Ask questions on the EngineerZone

https://ez.analog.com/welcome

Tools to help you design with the

AD9361/AD9364
Hardware

package:

Schematics,

Layout,

Datasheet
Software:
Complete

Linux and noOS drivers

HDL
Generic

Verilog, verified
on Xilinx

Design
FIR

Tools

Filter designer
(MATLAB)
System level simulation
(MATLAB/Simulink)

Summary
With MATLAB AD9361 Filter Wizard you can
Design
Easily

AD9361 filters with minimum trial and error

create custom filters

Examine
Quickly

filter performance

generate coefficients for implementation

Links and references

1.

Download the Filter Design wizard

http://www.mathworks.com/matlabcentral/fileexchange/45843-ad9361-filter-design-wizard

2.

Instructions are at the ADI wiki

http://wiki.analog.com/resources/eval/user-guides/ad-fmcomms2-ebz/software/filters

3.

Request a MATLAB trial license from Mathworks website

http://www.mathworks.com/products/dsp-system/

4.

Refer to webinar: Digital Filter Design Made Easy

http://www.mathworks.com/videos/digital-filter-design-made-easy-81883.html

Power regulators (Multi-Voltage) ICs

More

38

Moore more Power

For FPGA that demands more and more power

Multi-Voltage Power regulator ICs

Recent Release, All-in-one Multi-voltage
regulator for FPGAs (Xilinx/Altera)

39

ADP505x LFCSP package (7mm x 7mm)

(Where x = 0,1,2,3)
Real-Estate design area < 29mm x 22mm

ALREADY INCORPORATED INTO THE

DILIGENT ZYBO ZYNQ DEVELOPMENT BOARD

40

SAMPLING : ADP5054

RELEASING SEPT. 2014: 50% MORE POWER THAN

THE ADP5050

Real-Estate Area

41mm

20mm
7mm x 7mm

41

ADP5054 POWERING XILINX VIRTEX-7

Combine
arrangement
Doubling up to 12A!

42

Other Features: Scaling

ADP5054 Quad Buck (6A, 6A, 2.5A, 2.5A)
ADP5054
VIN
4.5V to 15V

6A* Buck Reg

0.8V to 0.85*Vin @ 6A

6A* Buck Reg

0.8V to 0.85*Vin @ 6A

2.5A Buck Reg

0.8V to 0.85*Vin @ 2.5A

2.5A Buck Reg

0.8V to 0.85*Vin@ 2.5A

PWGRD

43

*Resistor Programmable Current Limit (6A, 4A, 2A)

Thank You

10

minutes Opening Demo floor for evaluation

Q&As