Memory Data Book

MEMORY
DATABOOK
1986
MEMORY
DATABOOK
1986
IC MEMORY UNE-UP AND

TYPICAL CHARACTERISTICS
PACKAGING
RELIABILITY INFORMATION
MOSMEMORY
HANDLING PRECAUTIONS
EPROM WRITING
AND ERASURE
II
MASK ROM CUSTOMER

PROGRAM SPECIFICATIONS
MASK ROM
DEVELOPMENT FLOWCHART
TERMINOLOGY
AND SYMBOLS
DATA SHEET
CROSS REFERENCE LIST
[[!]
APPLICATIONS
DI
CONTENTS
o
IC MEMORY LINE-UP AND TYPICAL CHARACTERISTICS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DYNAMIC RAMS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SIP/SIMM MODULE. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
NMOS STATIC RAMS ............................................................
6
7
CMOS STATIC RAMS ............................................................
MASK ROMS ....................................................................
EPROMS .. ....... ... ......... ... .... ........... ...... ....... .... ..... .... ... ....
E2PROMS .........................................................,.............
PACKAGING .......................................................................... 13
16 PIN PLASTIC ................................................................. 15
16 PIN STACK PLASTIC. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
18 PIN PLCC .................................................................... 16
16
18 PIN PLASTiC ................................................................. 17
18 PIN SIDE-BRAZED ............................................................ 17
22 PIN PLCC .................................................................... 18
22 PIN PLASTIC ................................................................. 18
24 PIN PLASTIC ................................................................. 19
24 PIN CERDIP .................................................................. 19
24 PIN PLASTIC FLAT ............................................................ 20
26 PIN SOJ ...................................................................... 20
28 PIN PLASTIC ................................................................. 21
28 PIN CERDIP .................................................................. 21
32 PIN PLCC .................................................................... 22

40 PIN SIDE-BRAZED ............................................................ 22
. . RELIABILITY INFORMATION .......................................................... 25
1. INTRODUCTION ................................................................. 25
2. QUALITY ASSURANCE SYSTEM AND UNDERLYING CONCEPTS ......... ,........ 25
3. EXAMPLE OF RELIABILITY TEST RESULTS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 27
4. SEMICONDUCTOR MEMORY FAILURES ................................. , . . . . . . .. 31

MOS MEMORY HANDLING PRECAUTIONS ................................... ,........ 35
1. STATIC ELECTRICITY COUNTERMEASURES ............................ ,.. . . . ... 35
2. POWER SUPPLY AND INPUT SIGNAL NOISE ............................. , . . . . . . .. 35
3. CMOS MEMORY OPERATING PRECAUTIONS ........................... ,........ 35
IDI
EPROM WRITING AND ERASURE ...................................................... 39

1. EPROM WRITING ERASURE ..................................................... 39
2. EPROM HANDLING .............................................................. 40
III
MASK ROM CUSTOMER PROGRAM SPECIFICATIONS ................................

1. USABLE MEDIA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
2. MAGNETIC TAPE SPECiFiCATIONS....................... .. ........... .... . . ....
3. EPROM SPECiFiCATiONS ........................................................
MASK ROM DEVELOPMENT FLOWCHART........................ ........... .... . . ....
11.1
43
43
43
44
47
TERMINOLOGY AND SYMBOLS ....................................................... 51

1. PIN TERMINOLOGY ............................................................. 51
2. ABSOLUTE MAXIMUM RATINGS ................................................. 52
3. RECOMMENDED OPERATION CONDITIONS.. .. . . . . . . .. .. . . .... . . . . .. . . . .. . .. . . .. 53
4. DC CHARACTERISTICS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 54
5. AC CHARACTERISTICS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 55
DATASHEET
MOS DYNAMIC RAMS

32,768-Word x 1-Bit RAM (NMOS) . . . . . . . . . . . . . . . . . . . . . . . . . .. 60
MSM 3732AS/RS
MSM3764AS/RS
65,536-Word x 1-Bit RAM (NMOS) . . . . . . . . . . . . . . . . . . . . . . . . . .. 76
MSM3764AASIARS 65,536-Word x 1-Bit RAM (NMOS) . . . . . . . . . . . . . . . . . . . . . . . . . .. 92

MSM41256AS/RS
262,144-Word x 1-Bit RAM (NMOS) < Page Mode> .......... 108
MSM41256JS
262,144-Word x 1-Bit RAM (NMOS) < Page Mode> .......... 122
MSM41256AAS/RS 262,144-Word x 1-Bit RAM (NMOS) < Page Mode> .......... 132
MSM41257AAS/RS 262,144-Word x 1-Bit RAM (NMOS) <Nibble Mode> ......... 147
MSM41464RS
65,536-Word x 4-Bit RAM (NMOS) ........................... 163
MSM414256RS
262,144-Word x 4-Bit RAM (NMOS) ......................... 178
MSM411000RS
1,048,576-Word x 1-Bit RAM (NMOS) ....................... 191
MSM411 001 RS
1,048,576-Word x 1-Bit RAM (NMOS) <Nibble Mode> ....... 204
MSM511000RS
1,048,576-Word x 1-Bit RAM (NMOS) <Fast Page> ......... 217
MSM511 001 RS
1,048,576-Word x 1-Bit RAM (NMOS) <Static Column> ...... 218
MSM514256RS
262,144-Word x 4-Bit RAM (CMOS) <Fast Page> ........... 219
MSM514257RS
262,144-Word x 4-Bit RAM (CMOS) <Static Column> ....... 220
MSM37S64ARS/37S64RS 131,072-Word x 4-Bit RAM (NMOS) .................. 221

MSC2301 YS9/KS9 65,536-Word x 9-Bit RAM (NMOS) ........................... 234
MSC2304 YS8/KS8 262,144-Word x 8-Bit RAM (NMOS) ......................... 245
MSC2304 YS9/KS9 262,144-Word x 9-Bit RAM (NMOS) ........................ 256
MOSSTATICRAMS
MSM5114RS
4,096-Word x 4-Bit RAM (CMOS) ............................ 268
x 8-Bit RAM
MSM2128RS
2,048-Word
MSM5128RS
MSM5128-20GSK
(NMOS) ............................ 273
MSM5126RS
MSM5165RS/JS
MSM5165LRS/JS
MSM5188US
16,384-Word x 4-Bit RAM (CMOS) ........................... 307
MSM5127RSJJS
MSM51257LRS/JS 32,768-Word x 8-Bit RAM (CMOS) ........................... 318
ii
MOS MASK ROMS

MSM3864RS
8, 192-Word x 8-Bit MASK ROM (NMOS) ..................... 326
x 8-Bit MASK ROM (NMOS) .................... 330
MSM38128ARS
16,384-Word
MSM38256RS
32,768-Word x 8-Bit MASK ROM (NMOS) .................... 334
MSM38256ARS
MSM38512RS
MSM28101AAS
1 M Bit MASK ROM (NMOS) .................................. 346
MSM28201 AAS
MSM53256RS
32,768-Word
MSK531000RS
131,072-Word
8-Bit MASK ROM (CMOS) .................... 356

X
8-Bit MASK ROM (CMOS) .................. 360
MOSEPROMS
MSM2764AS
8,192-Word X 8-Bit EPROM (NMOS) ......................... 366
MSM27128AS
16,384-Word X 8-Bit EPROM (NMOS) ........................ 372
MSM27256AS
32,768-Word
8-Bit EPROM (NMOS) ........................ 378
MSM27512AS
65,536-Word
8-Bit EPROM (NMOS) ........................ 384
MSM271000AS
131,072-Word X 8-Bit EPROM (NMOS) ...................... 389
MSM271024AS
65,536-Word
MSM27C64AS
8,192-Word
16-Bit EPROM (NMOS) ...................... 395
8-Bit EPROM (CMOS) ......................... 401
MSM27C128AS
16,384-Word X 8-Bit EPROM (CMOS) ........................ 407
MSM27C1024AS
65,536-Word
16-Bit EPROM (CMOS) ...................... 413
MOS E2 PROMS
MSM2816ARS
2,048-Word X 8-Bit E2 PROM ................................ 420
II!] CROSS REFERENCE LIST

1. DYNAMIC RAM ................................... ; .............................. 431
2. STATIC RAM .................................................................... 436
3. MASK ROM ...................................................................... 438
4. EPROM ......................................................................... 439
5. E2P ROM ........................................................................ 441
APPLICATIONS
64KBIT DYNAMIC RAM APPLICATIONS NOTES ........................................ 445
1. MEMORY DRIVER ............................................................... 445
2. DECOUPLING CAPACITORS ..................................................... 446
3. PRINTED CIRCUIT BOARD ....................................................... 446
4. PERIPHERAL CONTROL CiRCUiT ................................................ 447
5. NOTES ON MOUNTING 1 MB MEMORY ON A BOARD .............................. 448
6. MEMORY SYSTEM RELIABILITY ................................................. 449
7. MEMORY COMPARISON STANDARD ............................................. 451
CMOS RAM BATTERY BACK-UP ........................................................ 454
1. SYSTEM POWER AND BATTERY SWITCHING CIRCUIT ........................... 454
2. SWITCHING CIRCUIT MODIFiCATIONS ........................................... 454
3. DATA RETENTION MODE ........................................................ 456
4. INTERFACING ................................................................... 457
5. MISCELLANEOUS ............................................................... 457
MASK ROM KANJI GENERATION MEMORY DESCRIPTION .............................. 457
1. KANJI GENERATION MEMORIES ................................................. 458
2. MSM38256 SERIES ............................................................... 459
iii
IC MEMORY LINE-UP AND TYPICAL CHARACTERISTICS. . . . . . . . . . . . . . . . . . . . . . . . .

DYNAMIC RAMS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . .
SIP/SIMM MODULE. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
NMOS STATIC RAMS.......................................................
CMOS STATIC RAMS.......................................................
MASK ROMS ...............................................................
EPROMS .......... ...................................... .............. .....

PPROMS .... ............ ......................... ........................
3
5
6
7
7
8
9
9
IC MEMORY LINE-UP AND TYPICAL

CHARACTERISTICS
* Under development
.IC MEMORY LINE-UP AND TYPICAL CHARACTERISTICS
.1--------
* Under development
- - - - - - - - - . I C MEMORY LINE-UP AND TYPICAL CHARACTERISTICS.
DYNAMIC RAMS
Model Name
Mem
ory
Circuit Function
Capac
ity
MSM3732H15
32k
MSM3732H20
MSM3732L15
32k
MSM3732L20
Num
ber of
Access
Memory
Pins
Configura per
Time
tion
MAX
Pack
(ns)
age
16 Pin Dynamic
A7 (Column)=H
32,768x1
16 Pin Dynamic
A7 (Column)=L
32,768x1
16 Pin Dynamic
65,536x1
150
270
248/28
200
330
248/28
150
270
248/28
200
330
248/28
150
270
248/28
16
200
330
248/28
MSM3764A12
120
230
330/28
64k
16 Pin Dynamic
65,536x1
16
150
260
330/28
200
330
330/28
150
260
385/28
200
330
385/28
100
200
385/28
120
220
385/28
MSM41256A15
150
260
385/28
MSM41257A10
100
200
385/28
MSM4125615
256k
16 Pin Dynamic
262,144x1
16
MSM4125620
MSM41256A10
MSM41256A12 250k
MSM41257A12 256k
16 Pin Dynamic
16 Pin Dynamic
262,144x1
262,144x1
16
16
MSM41257A15
MSM4146410
MSM4146412
256k
18 Pin Dynamic
65,536x4
18
MSM4146415
MSM41425610
256k
20 Pin Dynamic
262,144x4
MSM41100010
1M
18 Pin Dynamic
1,048,576x1
MSM41100110
1M
18 Pin Dynamic
1,048,576x1
MSM51100010
18 Pin Dynamic
1,048,576x1
MSM51100110
18 Pin Dynamic
1,048,576x1
MSM51425610
MSM51425612
20 Pin Dynamic
262,144x4
385/28
100
200
385/28
120
230
385/28
150
260
385/28
100
200
413/28
120
230
385/28
TMS416420
+5
100
200
413/28
120
230
385/28
100
200
413/28
120
230
385/28
100
190
385/11
120
220
330/11
100
190
385/11
120
220
330/11
100
190
413/11
120
220
385/11
+5
+5
+5
+5
+5
+5
+5
+5
18
MSM51100112
1M
385/28
260
18
MSM51100012
1M
220
150
18
MSM41100112
1M
120
18
MSM41100012
TMS416415
+5
20
MSM41425612
Device
+5
16
MSM3764A20
Equivalent
+5
MSM376420
MSM3764A15
Power
Supply
Voltage
(V)
+5
16
MSM376415
64k
Cycle
Time
MIN
(ns)
Power
Consump
tion
MAX
(mw)
Operating/
Standby
+5
20
.IC MEMORY LINE-UP AND TYPICAL CHARACTERISTICS - - - - - - - -
Model Name
Memory
Capacity
Circuit Function
Number of
Access
Memory
Pins
ConfiguraTime
per
tion
MAX
Pack(ns)
age
1M
20 Pin Dynamic
262.144x4
MSM514257-10
MSM37S64-15
131,072xl
413/11
120
220
385111
150
270
360/55
200
330
360/55
Equivalent
Device
+5
+5
SIP/SIMM MODULE
Model Name
MSC230112YS9/KS9
MSC230115YS9/KS9
Memory
Capacity
576k
MSC230412YS8/KS8
MSC230415YS8/KS8
2M
MSC230412YS9/KS9
MSC230415YS9/KS9
190
16
MSM37S64-20
100
20
MSM514257-12
128k 16 Pin Dynamic
Cycle
Time
MIN
(ns)
Power
Consumption
Power
MAX
Supply
(mw)
Voltage
(V)
Operatingl
Standby
2M
Circuit Function
Number of Access
Pins
Time
Memory
Configura- per
MAX
(ns)
Packtion
age
30 Pin Socket
Insertable Module
65536x9
30 Pin Socket
Insertable Module
262144x8
30 Pin Socket
Insertable Module
262144x9
Cycle
Time
MIN
(ns)
120
120
150
150
120
120
150
150
120
120
30
30
30
150
150
Power
Consumption
Power
MAX
Supply
(nw)
Voltage
(V)
Operatingl
Standby
+5
+5
+5
Equivalent
Device
- - - - - - - - - I . I C MEMORY LINE-UP AND TYPICAL CHARACTERISTICS.

NMOS STATIC RAMS
Model Name
Memory
Capacity
Circuit Function
Number of
Access
Memory
Pins
Time
Configura- per
tion
Pack- MAX
(ns)
age
MSM2128-12
MSM2185,15
16k
MSM2128-20
Static, Common I/O

2048x8
with Power Down
Mode
24
Cycle
Time
MIN
(ns)
Power
Consumption
Power
MAX
Supply
(mw)
Voltage
Operating/
(V)
Standby
120
120
660/110
150
150
550/110
200
200
550/110
+5
Equivalent
Device
TMM2016
M58725
CMOS STATIC RAMS
Model Name
MemCircuit Function
ory
Capacity
Number of
Memory
Pins Access
Configura- per
Time
tion
Pack- MAX
(ns)
age
MSM5114-2
Cycle
Time
MIN
(ns)
Power
Consumption
Power
MAX
Supply
(mw)
Voltage
(V)
Operating/
Standby
200
200
192/0.04
300
300
192/0.04
MSM5114
450
450
192/0.04
MSM5128-12
120
120
330/0.275
150
150
300/0.275
200
200
275/0.275
MSM5114-3
MSM5128-15
4k
16k
Fully Static,
Common I/O
Fully Static,
Common I/O
1024x4
2048x8
18
24
MSM5128-20
MSM5126-20
150
150
385/0.165
200
200
385/0.165
120
120
248/5.5
150
150
248/5.5
MSM5165-20
200
200
248/5.5
MSM5165L-12
120
120
248/0.55
MSM5126-25
16k
Fully Static
Common I/O
64k
Fully Static
Common I/O
2048x8
24
MSM5165-12
MSM5165-15
MSM5165L-15
64k
Fully Static
Common 110
8192x8
8192x8
28
28
MSM5165L-20
MSM5188-45
MSM5188-55
64k
Fully Static
Common I/O
16384x4
22
150
150
248/0.55
200
200
248/0.55
45
45
605/11
55
55
605/11
70
70
605/11
MSM51257-85
85
85
385/5.5
100
100
385/5.5
120
120
385/5.5
85
85
100
100
385/0.55
120
120
385/0.55
Fully Static
Common I/O
32768x8
28
MSM51257-120
MSM51257L-85
MSM51257L-l00 256k
MSM51257L-120
Fully Static
Common I/O
32768x8
28
+5
TC5514
!,PD444
HM6116
).IPD446
TC5517
+5
MSM5188-70
MSM51257-100 256k
+5
Equivalent
Device
+5
+5
+5
+5
385/0.55
+5
.IC MEMORY LINE-UP AND TYPICAL CHARACTERISTICS ...- - - - - - - -
MASK ROMS
Model Name
Mem
ory
Capac
ity
Circuit Function
Num
berof Access
Memory
Pins Time
Configura
per
MAX
tion
(ns)
Pack
age
Cycle
Time
MIN
(ns)
Power
Consump
Power
tion
Supply
MAX
Voltage
(mw)
(V)
Operating/
Standby
MSM3864
64k
Fully Static
8192x8
28
250
250
550/165
+5
MSM38128A
128k
Fully Static
16384x8 .
28
250
250
550/165
+5
MSM38256
256k
Fully Static
32768x8
28
250
250
660/165
+5
MSM38256A
256k
Fully Static
32768x8
28
150
150
330/33
+5
MSM38512
512k
Fully Static
65536x8
28
200
200
+5
JISChinese
character
coding systern 0-7,
16-47
MSM28101
1M
40 Pin MASK RAM

18x16 Chinesecha- 3760x16
racter font output
x 18
MSM28201
MSM53256
MSM531000
Equivalent
Device.
40
10j.ls
22j.1s
893
+5
JISChinesecharacter
coding sys
tern 48-87
.
256k
Fully Static
32768x8
28
150
150
83/0.6
+5
1M
Fully Static
131072x8
28
250
250
83/0.6
+5
- - - - - - - - - - _ I C MEMORY LINE-UP AND TYPICAL CHARACTERISTICS _

EPROMS
Model Name
Mem
ory
Capac
ity
Cycle
Time
MIN
(ns)
Power
Consump
tion
MAX
(mw)
Operating/
Standby
Power
Supply
Voltage
(V)
Equivalent
Device
MSM2764
64k
28 Pin EPROM
8192x8
28
200
200
790/185
+5
2764
MSM27128
128k
28 Pin EPROM
16,384x8
28
250
250
788/184
+5
27128
MSM27256
256k
28 Pin EPROM
32,768x8
28
150
150
525/184
+5
27256
MSM27512
512k
28 Pin EPROM
65,536x8
28
150
150
525/184
+5
27512
MSM271000
1M
32 Pin EPROM
131,072x8
32
120
120
525/184
+5
271000
MSM271024
1M
40 Pin EPROM
65,536x16
40
120
120
525/184
+5
271024
MSM27C64
64k
28 Pin EPROM
8,192x8
28
200
200
165/0.55
+5
27C64
MSM27C128
128k
28 Pin EPROM
16,384x8
28
200
200
165/0.55
+5
27C128
1M
40 Pin EPROM
65,536x16
40
100
100
175/0.55
+5
27Cl024
Circuit Function
Num
ber of Access
Memory
Pins
Time
Configura per
MAX
(ns)
tion
Pack
age
Cycle
Time
MIN
(ns)
Power
Consump
tion
MAX
(nw)
Operating/
Standby
Power
Supply
Voltage
(V)
Equivalent
Device
MSM27Cl024
Circuit Function
Num
ber of
Memory
Pins Access
Configura per
Time
tion
Pack MAX
(ns)
age
PP ROMS
Model Name
Mem
ory
Capac
ity
MSM2816A25
MSM2816A30
16k
MSM2816A35
24 Pin
E'P ROM
2048x8
250
250
300
300
350
350
450
450
24
+5
+5
MSM2816A45
PACKAGING ..................................................................... 13
16 PIN PLASTIC ............................................................ 15
16 PIN STACK PLASTIC. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
18 PIN PLCC ............................................................... 16
18 PIN PLASTIC ............................................................ 17
16
18 PIN SIDE-BRAZED ....................................................... 17
22 PIN PLCC ............................................................... 18
22 PIN PLASTIC ............................................................ 18
24 PIN PLASTIC ............................................................ 19
24 PIN CERDIP ............................................................. 19
24 PIN PLASTIC FLAT... .. . .. ........ . .. ..... . . . ... . . ......... .. . ........... 20
26 PIN SOJ ...................... .' .......................................... 20
28 PIN PLASTIC ............................................................ 21
28 PIN CERDIP ............................................................. 21
32 PIN PLCC ............................................................... 22
40 PIN SIDE-BRAZED ....................................................... 22
PACKAGING
Name
M8M3732
3764
3764A
37864
37S64A
41256
41256A
41257A
41464
411000
411001
414256
511000
511001
514256
514257
2128
5114
5126
5128
5165
5165L
5188
51257
51257L
3864
38128A
38256
38256A
28101A
28201A
38512
531000
53256
2764
No.
of
Pins
RS
PLASTIC
DIP
16
16
16
16
16
16
18
16
18
16
18
22
18
26
18
26
20
26
18
26
18
26
20
26
20
26
24
18
24
24
28
32
28
32
22
28
32
28
32
28
28
28
28
40
40
28
28
28
28
GS
PLASTIC
FLAT
JS
PLASTIC
LCC
PACKAGES
US
PLASTIC
SKINNY
YS
MODULE
KS
MODULE
AS
SIDEBRAZED
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
6
0
0
0
0
0
0
0
0
0
0
0
0
0
0
13
fI
.PACKAGING -----------------------------------------------PACKAGES
Name
27128
27256
27512
271000
271024
27C64
27C128
27C1024
2816A
2301
2304
14
No.
of
Pins
28
28
28
32
40
28
28
40
24
30
30
RS
GS
JS
US
PLASTIC
DIP
PLASTIC
FLAT
PLASTIC
LCC
PLASTIC
SKINNY
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MODULE
KS
AS
MODULE
SIDE
BRAZED
0
0
0
0
0
0
0
0
0
0
------------------------------------------------.PACKAGING
16 PIN PLASTIC
20.0MAX
INDEX MARK
7.620.30
,-______________________ 2
WffVm~f
I
2.540.25
0.65MAX
Seating Plane
16 PIN PLASTIC
20.0 MAX
\'
'I
~b::;;;;lq~~;;::::;;;;;:::;~!
\INDEX MARK
762 030
2
,-------------,~ -~
I!l
z
::;
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0.65 MAX
;:i;
2.540.25
~raa~~ng
0.6 MAX
If
-I15' MAX
-----
Note: All dimensions in millimeters.
15
.PACKAGING --------------------------------__------------__
16 PIN STACK PLASTIC
20.0 MAX
INDEX MARK
0.65 MAX 2.540.25
18 PIN PLCC
1.521=;4:
2.41
'0.38 MIN
064MIN-+-tt
033
t+O: l~~
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10719
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12.370
12.522 13.208
13.588
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7.290
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f- 8.508:}-
16
APEX REF
APEX OF LEAOS TO BE
&lACIQ38]
:=IO.l:]
----------------------------------------------.PACKAGING
18 PIN PLASTIC
24.5MAX
2.54O.25
O.S5MAX
18 PIN SIDE-BRAZED
232MAX
)
0
lL
"\INDEX MARK
Zx
~ --~
7.S2O.30
~~f~5MJ
..
2.54O.52
O.SMAX
Seating
Plane
17
.PACKAGING.I--------------------------------------------- 22 PIN PLCC

PIN 1
'INDEX
MARK
~45oL_-
1.22
o
0.50TYP
3 PLACES
I,
J:
~~~ -+-r~ ~:~~ ~. ~FLEAD.S
r--
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TO BE
~I!I-W::C ro:38]
12.370 13.208
12.~22
~IQJol
13.588
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r
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6.261
6. 604
6.794
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f--:~~: IT~
22 PIN PLASTIC
27.6 MAX
o
INDEX MARK
7.620.30
rn~r
Ir~~~
I
Seating Plane
0.65 MAX
18
150 MAX
' 0 . 6 MAX f---~~c-I
2.54 0.25
9.5 MAX
--------------------------------------------------.PACKAGING
24 PIN PLASTIC
:::;
o
X I
15.24+0.30
-~w~v~~~'ji~
~~~
Jill
----rI-
2.540.25
150MAX
0.65MAX
Seating
Plane
.24 PIN CERDIP
:::;
,...
M
15.240.30
~~AI.I
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0.6MAX
2.540.25
z
i ..
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-1-+
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Plane
0.6M~
15 MAX
19
.PACKAGING ------------------------------------------______
24 PIN PLASTIC FLAT
fJ
16.5 MAX
L0.45 MAX
1.270.13
13.0 MAX
~.
~2
fB.60.3
~ 2~==t1:::=7i)LL~r
10 MAX
26 PIN SOJ
r--
17,145O.15
f.M.~
~I
<0
.J
1P INDEX
C1.14
BASE PLANE
SEATING PLANE
1=1
20
O~
------------------.PACKAGING
28 PIN PLASTIC
38MAX
15.240.30
~x
----..gil~. ~
...
:E
~-----
"L~u U:,OMA~
0.65 MAX
:EN
Seati n9 15 MAX
28 PIN CERDIP
38.0 MAX
"I
[~~~Q~~~]]
I
15.24 0.30
[I
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15MAX
'"
21
PACKAGING.I----------------------------------------------- 32 PIN PLCC
APEX OF LEADS TO BE
~$IAIB-Cl
Q38J
.40 PIN SIDE-BRAZED
51.5 MAX
1-
"I
Ii
Zx
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0.35 MAX
2.54 0.25
0.6 MAX
vlfl
Seat; ng Plane
22
III
RELIABILITY INFORMATION ..................................................... 25

1. INTRODUCTION ............................................................ 25
2. QUALITY ASSURANCE SYSTEM AND UNDERLYING CONCEPTS ............. 25
3. EXAMPLE OF RELIABILITY TEST RESULTS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 27
4. SEMICONDUCTOR MEMORY FAILURES. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 31
RELIABILITY INFORMATION
1. INTRODUCTION
Semiconductor memories play a leading role in the
explosive progress of semiconductor technology. They
use some of the most advanced design and manufacturing technology developed to date. With greater
integration, diversity and reliability, their applications
have expanded enormously. Their use in large scale
computers, control equipment, calculators, electronic
games and in many other fields has increased at a fast
rate.
A failure in electronic banking or telephone switching
equipment, for example, could have far reaching effects
and can cause incalculable losses. So, the demand, for
stable high qual ity memory devices is strong.
We, at Oki Electric is fully aware of this demand. So
we have adopted a comprehensive quality assurance
system based on the concept of consistency in development, manufacturing and sales.
With the increasing demand for improvement in function, capability and reliability, we will expand our
efforts in the future. Our quality assurance system and
the underlying concepts are outlined briefy below.
2. QUALITY ASSURANCE SYSTEM

AND UNDERLYING CONCEPTS
The quality assurance system employed by Oki Electric
can be divided into 4 major stages: device planning,
developmental prototype, production prototype, and
mass production. This system is outlined in the following block diagram (Fig. 1-1).
1 t Device plann ing stage
To manufacture devices that meet the market demands
and satisfy customer needs, we carefully consider
functional and failure rate requirements, utilization
form, environment and other conditions. Once we
determine the proper type, material and structure,
we check the design and manufacturing techniques and
the line processing capacity. Then we prepare the
development planning and time schedule.
2) Developmental prototype stage
We determine circuits, pattern design, process settings,
assembly techniques and structural requirements during
this stage. At the same time, we carry out actual prototype reliability testing.
Since device quality is largely determined during the
designing stage, Oki Electric pays careful attention to
quality confirmation during this stage.
This is how we do it:

(1) After completion of circuit design (or pattern
design), personnel from the design, process technology, production technology, installation' technology and reliability departments get together for
a thorough review to ensure design quality and to
anticipate problems that may occur during mass
production. Past experience and know-how guide
these discussions.
(2) Since many semiconductor memories involve new
concepts and employ high level manufacturing
technology, the TEG evaluation test is often used
during this stage.
Note: TEG (Test Element Group) refers to the
device group designed for stability evaluation of MaS transistors, diodes, resistors,
capacitors and other circuit component
element used in LSI memories.
(3) Prototypes are subjected to repeated reliability and
other special evaluation tests. In addition, the
stabil ity and capacity of the manufactu ring process
are checked.
3) Production prototype stage
During this stage, various tests check the reliability and
other special features of the production prototype at
the mass production factory level. After confirming
the quality of device, we prepare the various standards
required for mass production, and then start production.
Although reliability and other special tests performed
on the production prototype are much the same as
those performed on the developmental prototype, the
personnel, facilities and production site differ for the
two prototypes, necessitating repeated confirmation
tests.
4) Mass production
During the mass production stage. careful management
of purchased materials, parts and facilities used during
the manufacturing process, measuring equipment,
manufacturing conditions and environment is necessary
to ensure device qual ity first stipulated during the
designing stages. The manufacturing process (including
inspection of the completed device) is followed by a lot
guarantee inspection to check that the specified quality
is maintained under conditions identical to those under
which a customer would actually use the device. This
lot guarantee inspection is performed in 3 different
forms as shown below.
25
~
I\J
Ol
~rt-
Process
ment
Acceptance
of order
Desig"
Sales
Marketing & Product Planning
...
Development
Design
--r1
-l
Production Engineer
Engineer
...
Quality
Objectives
Technical
& Quality
I Standards
Transportation
Storage
Maintenance
Service
::u
Customer
m
r
:;
i=
UJ
ILayout Program I
r~
Production
Inspectio~
Production
Design Review and Tnal Product Review
Purchasing
(Vendors)
Production
Control
Operahon
Standard
Production
Process
Setup
~I Productton
Plannmg
:::j
I I Process
Control
-<
r
I
."
::u
~~
.1 Process
Production ~
Control
3:
~l
t~ H
)10
-f
is
~ Accept~nce
Inspection
Purchasing
GUidelines
."
~.
In-Process
Inspection
Inspection
I~H
Quality
Testing
-'-
I.H
Product
Inspection
..
Storage
Control
I
Shipment
Delivery
<
.
.
!;
~paCkag,"g
:I
-Y
Transportation
Control
I
I
..
Service
I
1
Quality Assurance
& Quality Control
Staff Activities
Reliability
Englneenng
Quality Management and Education
Quality Control Program + Reliability Program
v
Quality Assurance
I.auallty and Reliability

Information Analysis
- Quality Evaluation
-Failure AnalYSIS
Failure
Report
AnalysIs
Service
r-
r-
- - - - - - - - - - - - - - - - - - - . RELIABILITY INFORMATION.
Fig. 2
Defect Processing Flowchart
Failure report processing
Request for
technical
improvement
r-------I
Report on
I
I
Failure
Customer
Engineering
Department
results of
investigation
& improvement
Failure report
delivery
Quality
Assurance
Department
Report on
results of
investigation
L _ ~ ~~r~v.:~e~t
Manufacturing
Department
Request for
manufacturing
improvement
11)
Group A tests:
(2)
Group B tests:
(3)
Group C tests:
appearance. labels. dimensions

and electrical characteristics inspection
check of durability under thermal
and mechanical environmental
stresses, and operating I ife characteristics
performed periodically to check
operational life etc on long term
basis.
Note: Like the reliability tests. the group B tests con

form to the following standards.
MILSTD-883B, JIS C 7022, EIAJ-IC-121
Devices which pass these lot guarantee inspections are

stored in a warehouse awaiting shipment to customers.
Standards are also set up for handling, storage and
transportation during this period, thereby ensuring
qual ity prior to delivery.

5) At Oki Electric, all devices are subjected to thorough
quality checks. If, by chance, a failure does occur after
delivery to the customer, defective devices are processed
and the problem rectified immediately to minimize the
inconvenience to the customer in accordance with the
following flowchart.
3. EXAMPLE OF RELIABILITY TEST

RESULTS
We have outlined the quality assurance system and
the underlying concepts employed by Oki Electric.
Now, we will give a few examples of the reliability tests
performed during the developmental and production
prototype stages. All reliability tests performed by Oki
Electric conform with the following standards.
MIL-STD-883B, JIS C 7022, EIAJ-IC-121
Since these reliability tests must determine performance
under actual working conditions in a short period of
time, they are performed under severe test conditions.
For example, the 125"C high temperature continuous
operation test performed for 1000 hours is equivalent

to testing device life from 2 to 300 years of use at
Ta~40C.
By repeating these accelerated reliability tests, device

quality is checked and defects analyzed. The resulting
information is extremely useful in improving the manufacturing processes. Some of the more common defects
in memory LSI elements and their analysis are described
below.
27
RELIABILITY INFORMATION - - - - - - - - - - - - - - - - - OKI MEMORY LSI LIFE TEST RESULTS
Device name
MSM41256-XXRS
MSM3764A-XXRS
MSM5165-XXRS
Function
262144 x 1 bit
DYNAMIC RAM
65536 x 1 bit
DYNAMIC RAM
8192 x 8 bit
STATIC RAM
Structure
Si gate N-MOS
16P plastic package
Si gate N-MOS
16P plastic package
Si gate C-MOS
28P plastic package
Sample
size
Test
hours
Failures
Sample
Size
Test
hours
Failures
Ta = 125C
Vcc = 5.5V
300
2000
300
2000
Ta = 150 V
Vcc = 5.5V
40
6000
50
140C 85%
Vcc = 5.5V
100
100
85C 85%
Vcc = 5.5V
100
2000
Pressure
cooker test
121C 100%
No bias
100
Low temperature life test
Ta = _10C
Vcc = 7.0V
Temperature
cycling test
_55C 150C
Test item
Operating
life test
Temperature
humidity test
Test item
Operating
life test
Temperature
humidity test
Test condition
Sample
size
Test
hours
Failures
88
2000
2000
50
2000
100
100
22
100
150
2000
100
2000
500
100
500
50
300
22
2000
22
2000
22
2000
100
500
cycles
100
500
cycles
100
500
cycles
Device name
MSM27256-AS
MSM38256-XXRS
MSM531000-XXRS
Function
32768 x 8 bit
UV erasable EP ROM
32768 x 8 bit
Mask ROM
MSM531000-XXRS
Mask ROM
Structure
Si gate N-MOS
28P cerdip
Si gate N-MOS
28P plastic package
Si gate C-MOS
28P plastic package
Test condition
Sample
size
Test
hours
Failures
Ta = 125C
Vcc = 5.5V
88
2000
Ta = 150C
Vcc = 5.5V
40
2000
Sample
Size
55
Test
hours
2000
Failures
140C 85%
Vcc = 5.5V
Sample
size
Test
hours
Failures
88
2000
22
100
85C 85%
Vcc = 5.5V
50
1000
50
2000
25
2000
Pressure
cooker test
121C 100%
No bias
22
48
22
500
50
200
Low temperatu re Iife test
Ta = _10C
Vcc = 7.0V
22
2000
22
2000
Temperature
cycling test
_55C 150C
100
500
cycles
50
300
28
50
300
cycles
OKI MEMORY LSI ENVIRONMENTAL TEST RESULTS
~
Soldering
heat
Thermal
environmental
test
Mechanical
environmental
test
Electrical
Environmental
test
Thermal
shock
MSM41256-XXRS MSM3764A-XXRS MSM5165-XXRS

Sample
size
Failures
Sample
size
Failures
Sample
size
Failures
260C
10 sec
0C-100C
5 min
10 cycles
5 min
Temperature
cycling
Variable
frequency
vibration
100Hz-2000Hz
4 min per cycle
4 times in X, Y, Z
Shock
1500G, 0.5 ms,

5 times in each
X,Y,Z
Constant
acceleration
10000G or 20000G
1 min in each X, Y, Z
ESD
200pF, on, 5 times

200V
Device name
Test condition
Soldering
heat
260C
10 sec
Thermal
shock
0C-100 G C
5 min
5 min
10 cycles
Thermal
environmental
test
Electrical
environmental
test
Test condition
-55C-RT-150C
30 min
30min
20 cycles
Mechanical
environmental
test
Device name
Temperature
cycling
-55C-RT-150C
30 min
30 min
20 cycles
Variable
frequency
vibration
100Hz-2000Hz
4 min per cycle
4 times in X, Y, Z
Shock
1500G, 0.5 ms,

5 times in each
X,Y,Z
Constant
acceleration
10000G or 20000G
1 min in each X, Y, Z
ESD
200pF, on, 5 times

200V
22
22
22
22
22
22
10
10
10
MSM2725-AS
MSM38256-XXRS MSM531000-XXRS
Sample
size
Failures
Sample
size
Failures
Sample
size
Failures
22
22
22
22
22
22
10
10
10
29
RELIABILITY INFORMATION - - - - - - - - - - - - - - - - - -
HIGH TEMPERATURE OPERATING LIFE TEST

ITa
SAMPLE SIZE
= 125C, Vee = 5.5V, teyele = 31's)
= 300 pes.
MSM41256-12RS
mA
ICCl
mA
ICC2
OH
168H
500H
1000H
MAX.
63.54
64.58
64.70
64.86
64.98
MIN.
57.92
57.94
57.86
57.90
57.96
MEAN
60.740
60.700
60.710
60.620
60.700
S.D.
1.339.
1.370
1.376
1.389
1.394
DEL.
0.00
1.04
1.16
1.32
1.44
MAX.
3.50
3.74
3.62
3.66
3.68
MIN.
2.92
2.94
2.92
2.94
2.94
MEAN
3.083
3.097
3.068
3.084
3.084
S.D.
ns
TRAC
.113
.119
0.00
0.68
0.20
0.26
MAX.
112
112
112
112
113
109
109
109
109
110
MEAN
110.9
110.9
111.1
110.9
111.0
.8
.7
.8
.7
.7
-1
-1
MAX.
52
52
52
52
53
MIN.
49
49
49
49
49
MEAN
50.8
50.6
51.0
50.6
.7
.6
.7
.6
S.D.
DEL.
-1
ns
120
60
115
55
1--- f---f---f--- i
.7
-1
50
I---i---f---f----i
45
105
OH
168H
500H
1000H
2000H
ICCl
mA
OH
l68H
70
65
3.5
I---f---l---}---I
1000H
2000H
ICC2
mA
I----I---l-l--I
2.5
55
OH
30
50.6
TCAC
ns
60
-1
-1
TRAC
110
.120
.119
0.24
MIN.
DEL.
ns
.144
DEL.
S.D.
TCAC
2000H
l68H
500H
1000H
2000H
OH
l68H
500H
1000H
2000H
4. SEMICONDUCTOR MEMORY
FAILURES
.....
AQ
)'~'
The lifespan characteristics of semiconductor elements

in general (not only semiconduc'or Ie devices) is
described by the curve shown in the diagram below.
Although semiconductor memory failures are similar to
those of ordinary integrated circuits, the degree of
integration (miniaturization), manufacturing complexity
and other circuit element factors influence their
incidence.
< Semiconductor
2l
OJ
a:
Element Failure Rate Curve>
Initial SHIPPING
Wear-out
fa:.ic.1u=-r"'e'--.'-I----'Random _ _ _ _...,...:f;::ailure
failure
\
m> 1
AluminurT:
wire
Input section
~l'1'f7t7R~
r
Poly Si
Destruction
position
2) Oxide Film Insulation Destruction (Pin Holes)

Unlike surge destruction, this kind of failure is caused
by manufacturing defects. Local weakened sections are
ruptured when subjected to external electrical stress.
Although this problem is accentuated by the miniaturization of circuit elements, it can be resolved by maintaining an ultra-clean manufacturing environment and
through 100% burn-in screening.
\
\
,>.
devices
___ ~:,1__
m<1.
J_//
'----v-----'
Debuggi ng by bu rn-i n
screening
General
electronic
Semiconductor
elements
--+Time
1) Surge Destruction
This is destruction of the input/output stage circuits by
external surge currents or static electricity.
The
accompanying photograph shows a point of contact
between aluminum and poly-silicon that has been
dissolved by a surge current. A hole has formed in the
substrate silicon, leading to a short circuit. This kind of
failure is traceable in about 30% of defective devices
returned to the manufacturer. Despite miniaturization
of semiconductor memory component elements (wh ich
means the elements themselves are less resistant), these
failures usually occur during assembly and other handling operations.
At Oki Electric, all devices are subjected to static
electricity intensity tests (under simulated operational
conditions) in the development stage to reduce this type
of failure. In addition to checking endurance against
surge currents, special protective circuits are incorporated
in the input and output sections.
3) Surface Deterioration due to Ionic Impurities
Under some temperature and electric field conditions,

charged ionic impurities moving within the oxide film
previously resulted in occasional deterioration of silicon
surfaces. This problem has been eliminated by new
surface stabilization techniques.
4) Photolithographic Defects
Integrated circuits are formed by repeated photographic
etching processes.
Dust and scratches on the mask
(which corresponds to a photographic negative) can
At preseht, component
cause catastrophic defects.
elements have been reduced in size to the order of 10.....
cm through miniaturization. However, the size of dust
and scratches stays the same. At Oki Electric, a high
degree of automation, minimizing human intervention
in th& process, and unparalleled cleanliness solves this
problem.
Photolithographic Defect
Example of surge destruction
31
RELIABILITY INFORMATION . ' - - - - - - - - - - - - - - - - - - -
51 Aluminum Corrosion
Aluminum corrosion is due to electro/ytic reactions
caused by the presence of water and minute impurities.
When aluminum dissolves, lines break. This problem is
unique to the plastic capsules now used widely to reduce costs. Oki Electric has carefully studied the possible cause and effect relationship between structure
and manufacturing conditions on the one hand, and
the generation of aluminum corrosion on the other.
Refinements incorporated in Oki LSls permit superior
endurance to even the most severe high humidity
conditions.
61 Alpha-Particle Soft Failure
This problem occurs when devices are highly miniaturized, such as in 64-kilobit RAMs. The inversion of
memory cell data by alpha-particle generated by radioactive elements like uranium and thorium (present in
minute quantities, measured in ppb) in the ceramic
package material causes defects. Since failure is only
temporary and normal operation restored quickly, this
is referred to as a "soft" failure. At Oki Electric we
have eliminated the problem by coating the chip surface
of 64-kilobit RAMs with a resin which effectively
screens out these alpha-particle.
Package ceramic
71 Degradation in Performance Characteristics Due to

Hot Electrons
With increased miniaturization of circuit elements,
internal electric field strength in the channels increases
since the applied voltage remains the same at 5 V. As
a result, electrons flowing in the channels, as shown in
the accompanying diagram, tend to enter into the oxide
film near the drain, leading to degradation of performance. Although previous low-temperature operation
tests have indicated an increase of this failure, we have
confirmed by our low-temperature acceleration tests,
including checks on test element groups, that no such
problem exists in Oki LSls.
Drain
VD
G~ ~ :
+VG
Source
Hot electron
Drain
Substrate silicon
Characteristic deterioration caused by hot electron

S iii co n ox i de
..:,-::,,:,-.,=::..:..:.:..:.;o..:...=rF:':"':"--'--"-'-'j-"=-'-'-'- fi I m
p
-'-"-----'7"'"""-''-:---'-'--:+--'---:--O''''-'=C-:CC-:-
Substrate silicon
/
a-particle
Ionization along
the a-particle path
32
With further progress in the miniaturization of circuit

components, failures related to pin hole oxide film
destruction and photolithography have increased. To
eliminate these defects during manufacturing, we at
Oki Electric have been continually improving our production processes based on reliability tests and information gained from the field. And we subject all devices
to high-temperature burn-in screening for 48 to 96
hours to ensure even greater reliability.
.c
MOS MEMORY HANDLING PRECAUTIONS ....................................... 35

1. STATIC ELECTRICITY COUNTERMEASURES................................ 35
2. POWER SUPPLY AND INPUT SIGNAL NOISE. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 35
3. CMOS MEMORY OPERATING PRECAUTIONS ............................... 35
MOS MEMORY HANDLING PRECAUTIONS

1. STATIC ELECTRICITY COUNTER
MEASURES
Since voltage is generally controlled by means of the
transistor gate oxide film in MOS memories, the input
impedance is high and the insulation tends to be destroyed more readily by static electricity.
Although Oki MOS memories incorporate built-in
protector circuits to protect all input terminals from
such destruction, it is not considered possible to give
complete protection against heat destruction due to
overcurrents and insulation film destruction due to
irregular high voltages. It is, therefore, necessary to
observe the following precautionary measures.
1) Under no circumstances must voltages or currents
in excess of the specified ratings be applied to any
input terminal.
2) Always use an electrically conductive mat or shipping tubes for storage and transporting purposes.
3) Avoid wearing apparel made of synthetic fiber
during operations. The wearing of cottons which do
not readily generate static electricity is desirable.
Also avoid handling devices with bare hands. If
handling with bare hands cannot be avoided, make
sure that the body is grounded, and that a 1MO
resistor is always connected between the body and
ground in order to prevent the generation of static
electricity.
4) Maintaining the relative humidity in the operation
room at 50% helps to prevent static electricity.
This should be remembered especially during dry
(1) Avoid excessive undershooting when using an

address common bus for memory board RAMs and
ROMs.
(2) Si nce noise can be generated very easily when using
direct drive for applying memory board RAM
addresses from other driver boards, it is highly
recommended that these addresses be first received
by buffer.
(3) Methods available for eliminating undershooting
generated in the address line include
a) Clamping of the undershooting by including a
diode.
b) Connect 10-200 in series with driver outputs.
c) Smooth the rising edge and fall ing edge waveforms.
3. CMOS MEMORY OPERATING

PRECAUTIONS
3.1
Latch-Up
If the CMOS memory input signal level exceeds the

Vcc power line voltage by +0.3 V, or drops below the
ground potential by -0.3 V, the latch-up mechanism
may be activated. And once this latchup mode has
been activated, the memory power has to be switched
off before normal operating mode can be restored.
Destruction of the memory element is also possible if
the power is not switched off.
Although Oki CMOS memories have been designed
to counter these tendencies, it is still recommended that
input signal overshooting and undershooting by avoided.
seasons.
5) When using a soldering iron, the iron should be
grounded from the tip. And as far as possible, use
low power soldering irons (12 V or 24 V irons!.
2; POWER SUPPLY AND INPUT SIGNAL

NOISE
2.1
Power supply noise absorption
In dynamic memories, the flow of power supply

current differs greatly between accessing and standby
modes.
Although very little power is consumed by CMOS
memories during standby mode, considerable current
is drawn for charging and discharging (instantaneous
current requirements) during access mode. In order to
absorb the "spike noise" generated by these current
requirements, the use of relatively large capacitance
capacitors (about one lO",F capacitor for every 8 to
10 RAMs) is recommended along with good high fre
quency response capacitors of about O.l",F for each
memory element. Power line wiring with as little line
impedance as possible is also desirable.
2.2
Input signal noise absorption
Overshooting and undershooting of the input signal

should be kept to a bare minimum. Undershooting in
particular can result in loss of cell data stability within
the memory. For this reason,
3.2
Battery Back-Up
Take special note of the following 4 pOints when

designing battery back-up systems.
(1) Do not permit the input signal H level to exceed
Vee +0.3 V when the memory Vcc power is dropped.
To achieve this, it is recommended that a CMOS
driver using a Vcc power common with the CMOS
memory, or an open collector buffer or open drain
buffer pulled-up by a Vcc power common with the
CMOS memory be used for driving purposes.
(2) Set the chip select input signal CE to the same H
level as the CMOS memory Vcc power line. And in
order to minimize memory power consumption, set
the write enable input WE level, the address input
arid the data input to either ground level or to the
same H level as the CMOS memory Vcc power line.
(3) Make sure that the CMOS memory Vcc power line is
increased without "ringing" or temporary breaks
when restoring the battery back-up mode.
(4) When using synchronous type CMOS memories
(MSM5115, MSM51 04), make sure that accessing
occurs after elapse of the chip enable off time (t cc )
prescribed in the catalog after the Vcc power line
has reached the guaranteed operating voltage range.
For further details, refer to "CMOS Memory Battery
Backup" at the end of this manual.
35
EPROM WRITING AND ERASURE ................................................. 39
1. EPROM WRITING ERASURE ................................................ 39

2. EPROM HANDLING ......................................................... 40
EPROM WRITING AND ERASURE

1.2
1. EPROM WRITING ERASURE

1.1
EPROM MSM2764 writing
Writing in the MSM2764RS involves setting the drain

and gate voltages of the floating gate stage to a high
voltage. When the cjrain voltage exceeds 15 V and the
gate voltage 20 V, the channel charge (electrons) be
comes highly energized and flow over the oxide film
barrier into the floating gate. And since the high gate
voltage is positive polarity, electrons will flow into the
floating gate very easily. When electron, build up in
the floating gate, the memory element "threshold
voltage" is changed, and subsequently stored as memory
data. Once the charge has been built up, the surrounding
oxide film (high insulation) prevents escape of electrons.
The data is thus stored as "nonvolatile" data.
Drain
PROM programmer
Oki Electric employs a system whereby the various

programmer available on the market are examined, and
agreements reached with different programmer manufacturers. The purpose of this system is to check
compatibility between programmer manufacturers and
Oki Electric devices, and making modifications whenever required. Users are thus ensured trouble-free use.
In the event of EPROM trouble with Oki devices and
approved programmer, problems will be handled by
both Oki and driver manufacturer except where such
problems have been caused purposely.
1.3 Erasure
Erasure of data written in the MSM2764RS can
be effected by ultra-violet radiation of the memory
element. In this case, the charge is discharged into the
substrate or electrode by the ultra-violet energy, but
note that the following erasure conditions must be met.
If a memory which has not been properly erased is used,
writing problems and operating failures are likely to
arise. Also note that excessively long erasure times (of
several hours duration) can also result in failure.
Gate
0-----11 V
!
Floating Gate
Charging
,..- Threshold
--~~
'----When the MSM2764RS is shipped from the factory,
the floating gate is left in discharged status (all bits "1"),
i.e. "blank" status. During writing processes, +25 V is
applied to the Vpp terminal and VIH to the OE input.
The data to be programmed is applied in parallel to the
outputs (0. -7). After the address and data have been
set up, application of VIH level for 50ms to the CE
input will enable writing of data. Since the +25 V
applied to Vpp is fairly close to the element's with
standing voltage, make sure that the voltage setting is
maintained strictly within the 25 V 1 V range. Applica
tion of voltages in excess of the rated VOltage, and
oversh"oting, to the Vpp terminal can result in permanent damage to the element.
Although MSM2764RS rewriting should be checked
about 100 times by sample testing, in actual practice 5
to 10 times is usually the limit. This will not likely
result in any problem.
Exposure time
Lengthy exposure to direct sunlight can also result

in loss of bits. Direct exposure of MSM2764 to
the strong summer sun for a single day can result in bit
changes.
Although normal fluorescent lights have
practically no effect, light rays beamed onto elements
can cause special changes. I t is therefore recommended
that the glass face be covered with a screening label.
39
EPROM WRITING AND ERASURE - - - - - - - - - - - - - - - -
2. EPROM HANDLING
2.1 Defects caused by static electricity
The generation of static electricity on the EPROM
glass face can result in changes in the memory con
tents. This, however, can be restored by brief exposure
(several seconds) to ultraviolet radiation. But this
exposure must be kept short. Exposure for 30 seconds
or more can cause changes in the normal bits.
2.2
Handling precautions
(1) Avoid carpets and clothes etc where static electricity

is generated.
(2) Make sure the programmer and mounting system are
securely grounded.
40
(3) Also make sure that any soldering iron employed is

properly grounded.
.
(4) Always carry in an electrically conductive plasti.c
mat.
(5) Written ROMs are also to be kept in an electrically
conductive plastic mat.
(6) Do not touch the glass seal by hand since th is can
result in deterioration of the ultraviolet permeability
required for erasure, and subsequently lead to poor
erasure.
2.3 System debugging precautions
During system debugging, check operations with a
voltage of 5%' (oscillating).
IfI
MASK ROM CUSTOMER PROGRAM SPECIFICATIONS ........................... 43

1. USABLE MEDIA.. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . ..
43
2. MAGNETIC TAPE SPECiFiCATIONS ......................................... 43

3. EPROM SPECiFiCATIONS ................................................... 44
MASK ROM CUSTOMER PROGRAM

SPECIFICATIONS
The mask ROM custom program code
programming method is outlined below.
1. USABLE MEDIA
(1) Magnetic tape
(2) EPROM
Magnetic tape and EPROM are used as standard.
2. MAGNETIC TAPE SPECiFICATIONS

2.1 Use the following types of magnetic tape in mag
netic tape units compatible with IBM magnetic tape
units.
(1) Length:
2400 feet, 1200 feet or 600 feet
(2) No label
(3) Width:
1/2 feet
(4) Channels: 9 channels
(5) Bit density:800BPI standard, although 1600BPI
can also be employed.
(6) Block size: I nteger multiples of 256 bytes
possible with 256 bytes as standard.
1 block, 1 record is standard.
2.2
Magnetic tape format

The data for a single chip should not extend into
several tapes. Data for several chips are allowed to be
included in a single magnetic tape, mUltiple file format
being permitted. In this case, include the data of a
single chip in one file.
(2) Use tape marks for file partitions when employing
multiple file formats.
(3) Denote the completion of a magnetic tape file by
two successive tape marks.
(1)
2.3 Magnetic tape data format

(1) The data contained in a single file on magnetic tape
must be inserted from the head address (OOOO)hex of
the device up to the final address in succession for a
single chip.
(2) I n this case, the LSB of the data should correspond
to Do, and the MSB to 0,.
(3) "1" bits in the data denote high device output,
while "0" denotes low output.
2.4
Magnetic tape examples
Multifile format (m chips)
1chip data file 1
File 2
(- H
-- -
/
I
R
Block 1
I
R
Block 2
I
R
Block 3
tape mark
1+1
File m
*:
- -
(~
-- ---
1~ 1
Block n1
Block n
43
MASK ROM CUSTOMER PROGRAM SPECIFICATIONS - - - - - - - - -
3. EPROM SPECIFICATIONS
(1) MSM2764, Intel 2764 or 27128 equivalent device
may be used,
(2) Prepare 2 EPROMs containing identical data,
44
MASK ROM DEVELOPMENT FLOWCHART.. .. . . ... . . . . . . . .... .... . .. . . .... . .. .... 47
MASK ROM DEVELOPMENT FLOWCHART
Mask ROM
automatic
designing program
User's
ROM data
ROM data
check list
No
Examination
~y~
Approval
J
Mask ROM
manufacture
Test
safTIpling
IExamination
No
Engineering
sample
shipment TAT'
~y.
..
Approval
Mass
production
I
I
Shipment
Production I
I
shipment
I
TAT"
User
Oki Electric
"TURN-AROUND-TIME
47
TERMINOLOGY AND SYMBOLS .................................................. 51

1. PIN TERMINOLOGY ........................................................ 51
2. ABSOLUTE MAXIMUM RATINGS ............................................ 52
3. RECOMMENDED OPERATION CONDITIONS. . . . ... . . . . .. . . ..... . .... . . ... ... 53
4. DC CHARACTERISTICS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 54
5. AC CHARACTERISTICS ..................................................... 55
TERMINOLOGY AND SYMBOLS

1. PIN TERMINOLOGY
Term
Power Supply Voltage Pin
ROM
EPROM
VDD.Vee
Vee
Static RAM
Vec
Dynamic RAM
VDD. VCC
VGG,VBB
Address Input Pin
Ao ,.....
Al2
Ao ..... All
Data Input Pin
Data Output Pin
O. - 0,
Do . . . .
Data Input/Output Pin
DIS
Ao ,. . .,
All
A. - A,
01
DIN
DO
D OUT
I/O, - I/O,
Chip Enable Pin
CE
CE
CE
Output Enable Pin
OE
OE
OE
AE
Address Enable Pin
Chip Select Pin
CS
CS
Write Enable Pin
WE
WE
WE
Row Address Strobe Pin
RAS
Column Address Strobe Pin
CAS
Program Input Pin
Program, Vpp
Data Valid Pin
DV
Clock Input Pin
<t>T
Ground Pin
VSS
VSS
Vacant Terminal
NC
NC
VSS
VSS
51
.TERMINOLOGYANDSyMBOLS.--------------------------------___
2. ABSOLUTE MAXIMUM RATINGS
Term
EPROM
Voo. Vee
Power supply voltage
ROM
Static RAM
Dynamic RAM
Vee
Vee
Voo. Vee
VSS
VSS
VSS
VT
VT
VGG.VBB
VSS
Terminal voltage
VT
Input voltage
VI
VI
VI
VI
Output voltage
Va
Va
Va
Va
Input current
Output cu rrent
10
Output short circuit current
lOS
Load capacitance
52
Power dissipation
Po
Po
Po
Po
Operating temperature
Topr
Topr
Topr
Topr
Storage temperature
Tstg
Tstg
Tstg
Tstg
- - - - - - - - - - - - - - - - - ' . T E R M I N O L O G Y AND SYMBOLS.

3. RECOMMENDED OPERATION CONDITIONS
EPROM
Term
VDD. VCC
Power Supply Voltage
ROM
Static RAM
VCC
VCC
VDD. VCC
VSS
VSS
VSS
VGG. VBB
VSS
Dynamic RAM
VBB
"H" Clock Input Voltage
VIHC
"H" Input Voltage
VIH
VIH
VIH
VIH
"L" Input Voltage
VIL
VIL
VIL
VIL
Data Pretention Voltage
VCCH
Load Capacitance
CL
CL
Fanout
Operating Temperature
Topr
Topr
Topr
Topr
53
TERMINOLOGY AND SYMBOLS ...- - - - - - - - - - - - - - - - 4. DC CHARACTERISTICS

Term
EPROM
ROM
Static RAM
Dynamic RAM
"H" output voltage
VOH
VOH
VOH
VOH
"L" output voltage
VOL
VOL
VOL
VOL
"H" output current
10H
"L" output current

Input leakage current
III
III
III
III
Output leakage current
ILO
ILO
ILO
ILO
I/O leak cu rrent

Program terminal current
ILO
IpPl. lpP2
Peak power on current
Power supply current
100. ICC
IBB.ICCl
ICC2
54
IpO
IPO.ISBP
ICC.ICCS
ICCA
ICC.ICCA
ICC1. ICC2
1001. ICC1. IBBl

1002. ICC2. IBB2
ICCS.ICCSl
IOD3. ICC3. IBB3
ISB
1004. ICC4. IBB4
-----------------1. TERMINOLOGY AND SYMBOLS.

5. AC CHARACTERISTICS
(1) Read cycle
Term
EPROM
Read cycle time
ROM
Static RAM
tC. tRe. tCYC
tRC
Address access time
tAce
tAA. tACC
tAo tACo
tACC. tAA
Chip select access time
tco
tcs
tCO. tACS1.
tACS2
Chip enable access time
tCE
tACE
tAC
Output enable access time
tOE
tco
tOE
tLZ
tex. tLZ
Output setting time

Output valid time
tOH
tOH
tOH. tOHA
Output disable time
tOF
tHZ
tOTO. tHZ.
tOFF
Address set-up time
tAS
tAS
Address hold time
tAH
tAH
Chip enable off time
tcc
Chip enable pulse width
tCE
Power-up time
tpu
tpu
Power-down time
tpo
tpo
Address enable pulse width
tAE
Oata valid access time
tVA
Oata valid delay time
tvo
Clock delay time
tVH
Clock pule width
tH
Clock delay time
tL
Output delay time
too
Output access time
tOA
Output hold time
tOH
Address enable set-up time
tAES
Oynamic RAM
tRC
tOFF
55
_TERMINOLOGY AND SYMBOLS _ . _ - - - - - - - - - - - - - - - (2) Write Cycle

Term
EPROM
Write cycle time
ROM
Static RAM
twc
Address set-up time
tAS
tAS. tAW
Write pulse width
tpw
tWo twp
Write recovery time
Dynamic RAM
tRC
twp
tWR
Data set-up time
tos
tOS. tow
tos
Data hold time
tOH
tOH
tOH
Output off'time
tOF
tOTW.twZ
tOFF
Chip select set-up time
tcss
tew
Address hold time
tAH
tAH. tWR
Chip enable off time
tcc
Chip enable pulse width
tew. tCE
Write enable set-up time
tws
Write enable read time
tWCL
Write enable hold time
twH
Address/write enable setting time
tAW
Write enable output activation
tow
Output enable set-up time
tOES
Output enable hold time
tOEH
Program read delay time
tOPR
Output enable delay ti me
tOE
Chip enable data valid time
tov
Program pulse rising edge time
tPRT
Program pulse falling edge time
tpFT
VPP restoration time
tVR
Chip enable hold time
tCH
56
III
DATA SHEET
MOS DYNAMIC RAMS

32,768-Word x l-Bit RAM (NMOS) . . . . . . . . . . . . . . . . . . . . . . . . . .. 60
MSM 3732AS/RS
MSM3764AS/RS
65,536-Word X l-Bit RAM (NMOS) . . . . . . . . . . . . . . . . . . . . . . . . . .. 76
MSM3764AASI ARS 65,536-Word X l-Bit RAM (NMOS) . . . . . . . . . . . . . . . . . . . . . . . . . .. 92
MSM41256AS/RS
262,144-Word
l-Bit RAM (NMOS) <Page Mode> .......... 108
MSM41256JS
262,144-Word
MSM41256AAS/RS 262,144-Word
l-Bit RAM (NMOS) < Page Mode> .......... 122

l-Bit RAM (NMOS) <Page Mode> .......... 132
MSM41257AAS/RS 262,144-Word x l-Bit RAM (NMOS) <Nibble Mode> ......... 147

MSM41464RS
MSM414256RS
MSM411000RS
MSM411 001 RS
MSM511000RS
65,536-Word x 4-Bit RAM (NMOS) ........................... 163

262,144-Word x 4-Bit RAM (NMOS) ......................... 178
1,048,576-Word x l-Bit RAM (NMOS) ....................... 191
1,048,576-Word x l-Bit RAM (NMOS) <Nibble Mode> ....... 204
1,048,576-Word x l-Bit RAM (NMOS) <Fast Page> ......... 217
MSM511 001 RS
1,048,576-Word x l-Bit RAM (NMOS) <Static Column> ...... 218
MSM514256RS
262,144-Word x 4-Bit RAM (CMOS) <Fast Page> ........... 219
MSM514257RS
262,144-Word x 4-Bit RAM (CMOS) <Static Column> ....... 220
MSM37S64ARS/37S64RS 131,072-Word x 4-Bit RAM (NMOS) .................. 221
MSC2301 YS9/KS9 65,536-Word x 9-Bit RAM (NMOS) ........................... 234
MSC2304YS8/KS8 262,144-Word x 8-Bit RAM (NMOS) ......................... 245
MSC2304YS9/KS9 262,144-Word x 9-Bit RAM (NMOS) ......................... 256
MOS STATIC RAMS
MSM5114RS
MSM2128RS
2,048-Word x 8-Bit RAM (NMOS) ............................ 273
MSM5128RS
MSM5128-20GSK 2,048-Word x 8-Bit RAM (CMOS) ............................ 283
MSM5126RS
MSM5165RS/JS
MSM5165LRS/JS
MSM5188US
MSM5127RS/JS
MSM51257LRS/JS 32,768-Word x 8-Bit RAM (CMOS) ........................... 318
MOS MASK ROMS
MSM3864RS
8,192-Word x 8-Bit MASK ROM (NMOS) ................... ,.326
MSM38128ARS
MSM38256RS
MSM38256ARS
MSM38512RS
MSM28101AAS
MSM28201 AAS

MSM53256RS
32,768-Word x 8-Bit MASK ROM (CMOS) .................... 356

131,072-Word x 8-Bit MASK ROM (CMOS) .................. 360
MSK531000RS
MOSEPROMS
MSM2764AS
8,192-Word x 8-Bit EPROM (NMOS) ......................... 366
MSM27128AS
16,384-Word x 8-Bit EPROM (NMOS) ........................ 372
MSM27256AS
MSM27512AS

MSM271000AS
131,072-Word x 8-Bit EPROM (NMOS) ...................... 389

65,536-Word x 16-Bit EPROM (NMOS) ...................... 395
MSM271024AS
MSM27C64AS
MSM27C128AS
8,192-Word x 8-Bit EPROM (CMOS) ......................... 401
MSM27Cl024AS
65,536-Word x 16-Bit EPROM (CMOS) ...................... 41 3
MOS E2 PROMS
MSM2816ARS
16,384-Word x 8-Bit EPROM (CMOS) ........................ 407
2,048-Word x 8-Bit E2 PROM ................................ 420
MOS
DYNAMIC
RAMS
OKI
semiconductor
MSM3732 AS/RS
32,768-BIT DYNAMIC RANDOM ACCESS MEMORY
GENERAL DESCRIPTION
The Oki MSM3732H/L is a fully decoded, dynamic NMOS random access memory organized as 32,768 one-bit words.
The design is optimized for high-speed, high performance applications such as mainframe memory, buffer memory,
peripheral storage and environments where low power dissipation and compact layc;>ut is required.
Multiplexed row and column address inputs permit the MSM3732 'to be housed in a standard 16 pin DIP.
The MSM3732 is fabricated using silicon gate NMOS and Oki's advanced Double-Layer Polysilicon process. This
process, coupled with single-transistor memory storage cells, permits maximum circuit density and minimum chip
size. Dynamic circuitry is employed in the design, including the sense amplifiers.
Clock timing requirements are noncritical, and power supply tolerance is very wide. All inputs and output are TTL
compatible.
FEATURES
.32,768 x 1 RAM, 16 pin package
Silicon-gate, Double Poly NMOS, single transistor cell
Row access time,
150 ns max (MSM3732H/L-15)
200 ns max (MSM3732H/L-20)
Three-state TTL compatible output

"Gated"C"AS
128 refresh cycles/2 ms
Common 1[0 capability using "Early Write"
operation
Cycle time,
270 ns min (MSM3732H/L-15)
330 ns min (MSM3732H/L-20)
Low power: 248 mW active,
28 mW max standby
Single +5V Supply, 10% tolerance
All inputs TTL compatible, low capacitive load
Output unlatched at cycle end allows extended page

bou ndary and two-d imensional ch ip select
Read-Modify-Write, RAS-only refresh, and PageMode capability
On-chip latches for Addresses and Data-in
On-chip substrate bias generator for high
performance
PIN CONFIGURATION
NC
Vss
WE
Dout
A o.....,A 7
RAS
Row Address Strobe
A,'
CAS
Column Address Strobe
Wf
Write Enable
Din
Data Input
Oout
Data Output
Pin Names
60
A.'
A'
A,'
A,'
A,'
A'
Vee
A,
Function
Address Inputs
VCC
Power Supply (+5V)
VSS
Ground (OV)
Refresh Address
- - - - - - - - - - - - - - - -... DYNAMIC RAM MSM3732AS/RS

FuNcTIONAL BLOCK DIAGRAM
I----WE
Buffers
Ao-A,
Oout
Row
Address
Buffers
Word
Memory
Cells
Driv-
ers
Vee
VSS-
I-----Oin
On chip VBB
ABSOLUTE MAXIMUM RATINGS
(See Notel
Rating
Voltage on any pin relative to VSS
Symbol
Value
Uriit
VIN, VOUT
-1 to +7
V
V
Voltage on Vee supply relative to VSS
Vee
-1 to +7
Topr
o to 70
Storage temperatu re
T stg
-55 to +150
PD
1.0
50
rnA
Power dissipation
Short circuit output current
Note: Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. Functional operation should be restricted to the conditions as detailed in the operational sections of this data sheet. Exposure
to absolute maximum rating conditions for extended periods may affect device reliability.
RECOMMENDED OPERATING CONDITIONS

(Referenced to VSSI
Parameter
Supply Voltage
Symbol
Min.
Typ.
Max.
Unit
Vee
VSS
4.5
0
5.0
0
5.5
0
V
V
Input High Voltage, all inputs
VIH
2.4
6.5
Input Low Voltage, all inputs
VIL
-1.0
0.8
Operating
Temperature
ooe to +70oe
61
DYNAMIC RAM . MSM3732AS/RS - - - - - - - - - - - - - - - -
DC CHARACTERISTICS
(Recommended operating conditions unless otherwise noted.)
Parameter
Symbol
Operating Current"
Average power supply current
(RAS, CAS cycling; tRC = min.)
Standby Current
(RAS = CAS = VIH)
Refresh Current"
(RAS cycling, CAS = VIH; tRC
= min.)
Page Mode Current"

(RAS = VI l, CAS cycling; tpc
= min.)
Min.
Max.
Unit
ICCl
45
mA
ICC2
5.0
mA
ICC3
35
mA
ICC4
42
mA
Input Leakage Current

I nput leakage current, any input
(OV:;:; VIN :;:; 5.5V, all other pins not
under test = OV)
III
-10
10
IJ.A
Output leakage Current

(Data out is disabled,
OV :;:; VOUT :;:; 5.5V)
IlO
-10
10
IJ.A
Output levels
Output high voltage (tOH = -5 mAl
Output low voltage (tOl = 4.2 mAl
2.4
VOH
VOL
0.4
Notes
V
V
Note*: ICC is dependent on output loading and cycle rates. Specified values are obtained with the output open.
CAPACITANCE
ITa = 25C, f = 1 MHz)

Parameter
Symbol
Typ.
Max.
Unit
Input Capacitance (Ao - A" DIN)
CINl
4.5
pF
Input Capacitance (RAS, CAS, WE)
CIN2
10
pF
Output Capacitance (DOUT)
COUT
pF
Capacitance measured with Boonton Meter.
62
- - - - - - - - - - - - - - - -.... DYNAMIC RAM . MSM3732AS/RS
AC CHARACTERISTICS
Parameter
Units
MSM3732-15
MSM3732-20
Min.
Min.
Max.
Refresh period
tREF
ms
Random read or write cycle time
tRC
ns
270
330
330
Note
Max.
2
Read-write cycle time
tRWC
ns
270
Page mode cycle time
tpc
ns
170
Access time from RAS
tRAC
ns
150
200
4,6
Access time from CAS
tCAC
ns
100
135
5,6
Output buffer turn-off delay
tOFF
ns
Transition time
tT
RAS precharge time
tRP
RAS pulse width
tRAS
ns
150
RAS hold time
tRSH
ns
100
CAS precharge time
tcp
ns
60
100
CAS pulse width
Symbol
Note 1,2,3
40
ns
35
ns
100
tCAS
ns
CAS hold time
tCSH
ns
150
RAS to
tRCD
ns
25
~to RAS precharge time
tCRP
ns
Row Address set-up time
CAS delay time
225
50
50
120
10,000
200
80
10,000
135
10,000
200
50
30
65
tASR
ns
Row Address hold time
tRAH
ns
15
20
Column Address set-up time
tASC
ns
Column Address hold time
tCAH
ns
45
55

referenced to R AS
tAR
ns
95
120
Read command set-up time
tRCS
ns
Read command hold time
tRCH
ns
Write command set-up time
twcs
ns
-10
-10
Write command hold time
twCH
ns
45
55

referenced to RAS
tWCR
ns
95
120
Write command pulse width
twp
ns
45
55
45
55
45
55
tRWL
ns
Write command to CAS lead time
tCWL
ns
Data-in set-up time
tDS
ns
Data-in hold time
tDH
ns
45
55
Data-in hold time referenced

to RAS
tDHR
ns
95
120
Write command to RAS lead time
10,000
135
CAS to WE delay
tCWD
ns
60
80
RAS to WE delay
tRWD
ns
110
145

referenced to R AS
tRRH
ns
20
25
63
DYNAMIC RAM MSM3732AS/RS

NOTES:
.11-----------------
1) An initial pause of 1001's is required after power-up followed by any 8 RAS cycles (Examples;
only) before proper device operation is achieved.
2) AC measurements assume tT = 5 ns.
RAS
3) VIH (Min.) and VIL (Max.) are reference levels for measuring timing of input signals. Also, transition
times are measured between VI H and VI L.

< tRCD (max.).
If tRCD is greater than the maximum recommended value shown in this table, tRAC will increase by
4) Assumes that tRCD
the amount that tRCDexceeds the value shown.

5) Assumes that tRCD < tRCo (max.)
6) Measured with a load circuit equivalent to 2 TTL loads and 100pF.
7) Operation within the tRCD (max.) limit insures that tRAC (max.! can be met. tRCD (max.) is specified as a reference point only; if tRCD is greater than the specified tRCD (max.! limit, then access
time is controlled exclusively by tCAC.
8) twcs, tCWD and tRWD are not restrictive operating parameters. They are included in the data sheet
as electrical characteristics only; if twcs ~ twcs (min.), the cycle is an early write cycle and the data
out pin will remain open circuit (high impedance) throughout the entire cycle; if tCWD ~ tCWD
(min.! and tRWD > tRWD (min.) the cycle is read-write cycle and the data out will contain data read
from the selected cell; if neither of the above sets of conditions is satisfied the condition of the data
out (at access time) is indeterminate.
READ CYCLE TIMING
~-------------------tRC------------------~~
~------------tRAS------------~
RAS
VIH VIL -
CAS
VIH VIL -
Addresses
WE
------,I ~-------tAR------~.~1
-------'-''--------u.---.. 1-~-t-tCAS----~., r-'-+------,.
VIHVIL -
VIHVIL -
I----tCAC
~----------tRAC----------~
DOUT
~------~
VOH-
OPEN
tOFF
Valid Data
VOL~ "H", "L" = Don't Care
64
- - - - - - - - - - - - - - - -.... DYNAMIC RAM MSM3732AS/RS

WRITE CYCLE TIMING
(EARLY WRITE)
Addresses V I H - ~
VIL - /,,ij
V IH -
rTTJ'17T,'777:7777mb77?\
-r__~__~~~~~~~~~~~~~~~~
VIL-~~~~~~~__
VIH-I
V I L - ,,"".i.U.l.Cf.I.I..~""'I'4UJ...<..i.i.<,",
DOUT
VOH- _ _ _ _ _ _ _--i
VOL-
READ-WRITE/READ-MODIFY-WRITE CYCLE
~------------tRWC-----------~~
-'-I-t-R-A-S~-tC-t~-~--H-----------------------""--Il1t~~
--,-_+----..
'-
--.:...---------d-----.
Addresses VV I H - ,
IL -
~ "H", "L" = Don't Care
65
.1-----------------
DYNAMIC RAM' MSM3732AS/RS
RAS ONLY REFRESH TIMING

(CAS: VIH,W" & DIN: Don't care)
-RAS
VIHVIL-
~:~ _~
~RAH~
tASR
Addresses
DOUT
VOH -
Row Address
___________~
VOL -
OPEN
"H", "L" ~ Don't Care
PAGE MODE READ CYCLE
~---------tRAS-----------'""
VIHAdresses V I L -
DOUTVOH--------I
tOFF
I
~~~~------~~------~irj----~~--tR-~-H~~~~
~ .. H","L"=Don't CarE
66
- - - - - - - - - - - - - - - -__ DYNAMIC RAM MSM3732AS/RS _
PAGE MODE WRITE CYCLE
~-----------------tRAS------------------~
Addresses ~ IH-
'/!>tIRD!\IV;;VC
IL-~1~~~'uF~~~~~~~l~~'~~~~
~"H",
"L" = Don't Care
PAGE MODE, READ-MODIFY-WRITE CYCLE
RAS
VIH
VIL
CAS
VIH
VIL
Addresses VIH
VIL
WE
VIH
VIL
DIN
VIH
VIL
DOUT VOH
VOL
~~,
1;/0
~tCAC--j ~F-l--tcAch
OPEN~~
~
"H" , "L"
Don't Care
67
DYNAMIC RAM MSM3732AS/RS - - - - - - - - - - - - - - - HIDDEN REFRI;SH
RAS
VIH
VIL
CAS
VIH
VIL
VIH
Addresses VIL
WE
VIH
VIL
DOUT
~----_----~f'j1!7~.~
5Valid Data
DESCRIPTION
Address Inputs:
A total of fifteen binary input address bits are required
to decode any 1 of 32,768 storage cell locations within
the MSM3732. Eight row-address bits are established on
the input pins (Ao -A,) and latched with the Row
Address Strobe (RAS)' The seven column-address bits
(Ao through A.) are established on the input pins and
latched with the Column Address Strobe (CAS). All
input addresses mU!l.t be stable on or before the falling
edge of RAS. CAS is internally inhibited (or "gated")
by RAS to permit triggering of CAS as soon as the Row
Address Hold Time ItRAH) specification has been
satisfied and the address inputs have been changed from
row-addresses to column-addresses.
One Column Address (A,) has to be fixed at logic "0"
(low level) for MSM3732L, and at logic "1" (high level)
for MSM3732H.
Write Enable:
The read mode or write mode is selected with the WE
input. A logic high (1) on WE dictates read mode;
logic low (0) dictates write mode. Data input is dis
abled when read mode is selected.
Data Input:
Data is written into the MSM3732 during a write or
read-write cycle. The last falling edge of WE or CAS is
a strobe for the Data In (DIN) register. In a write
cycle, if WE is brought low (write mode) before CAS,
DIN is strobed by CAS, and the set-up and hold times
are referenced to CAS. I n a read-write cycle, WE will
be delayed until CAS has made its negative transistion.
Thus DIN is strobed by WE, and set-up and hold times
are referenced to WE.
Data Output:
The output buffer is three-state TTL compatible with
68
a fan-out of two standard TTL loads. Data-out is the

same polarity as data-in. The output is in a high impedance state until CAS is brought low. In a read cycle,
or read-write cycle, the output is valid after tRAC from
transition of RAS when tRCD (max.) is satisfied, or
after tCAC from transition of (!AS when the transition
occurs after tRCD (max.). Data remain valid until CAS
is returned to a high level. In a write cycle the identical
sequence occurs, but data is not valid.
Page Mode:
Page-mode operation permits strobing the rowaddress
into the MSM3732 while maintaining RAS at a logic
low (0) throughout all successive memory operations in
which the row-address doesn't change. Thus the power
dissipated by the negative going edge of RAS is saved.
Further, access and cycle times are decreased because
the time normally required to strobe a new row-address
is eliminated.
Refresh:
Refresh of the dynamic memory cells is accomplished
by performing a memory cycle at each of the 128 rowaddresses (Ao -A.) at least every two milliseconds.
During refresh, either VIL or VIH is permitted for A,.
RAS only refresh avoids any output during refresh
because the output buffer is in the high impedance
state unless CAS is brought low. Strobing each of 128
row-addresses with RAS will cause all bits in each rwo
to be refreshed. Further RAS-only refresh results in a
substantial reduction in power dissipation.
Hidden Refresh:
RAS ONLY REFRESH CYCLE may take place while
maintaining valid output data. This feature is referred
to as Hidden Refresh.
Hidden Refresh is performed by holding CAS as VIL
from a previous memory read cycle.
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _... DYNAMIC RAM . MSM3732AS/RS
(Relative value) v.s. Vee
>"0
Ta
"uu
"-
Iti
1.1
>
U
<{ 1.0
a::
25C
'",
>
C
a
.;::;
.t:
11
ICCl (tRAS: Constant)

v.s. Vee
50,----r----.---or---,
Ta = 25C
I
tRAS = 140 ns
401----+-----1-
0.9
..
Ii;
!'-
c.
U 201---~~--~~~----~
loo0ns
<{
~
4.0
5.0
4.5
5.5
6.0
4.0
4.5
VeelV]

(Relative value) v.s. Ta
Vee = 5.0V
III
N
".
1.1
I-
U 1.0
<{
a::
.t:
m
IU
5.0
5.5
6.0
Vee IV]
V
./
<{

v.s. Cycle rate
50,----r----r----r----,
Ta = 25C
I
tRAS = 140 ns
Voo = 5.5V
5.0V
4.5V
co
.;::;
~
c.
"
0.9
U
9
<{
25
50
75
Cycle Rate (l/tRc) [MHz]


v.s. Ta
50
>"0
Iti
1.1
u
u
.;::;
~
1.0
"c.
.t:
">
U
u
40
>
u<{
VeeI = 5.5VI
tRAS = 140 ns
30
0.9
<{
20
....!B..c;,. = 2qO
ns
------ r--
330 ns
500 ns
1000 ns
!:?
4.0
75
Vee IV]
69
DYNAMIC RAM MSM3732AS/RS . - - - - - - - - - - - - - - - - -
ICCl (tRP: Constant)

v.s. Vee
50,----,----.----,---,
Ta = 25C
tRP = 100 ns
~
40~--~----~--~
ICC2 v.s. Vee
VIH: max.
5.0
%4.0
--
-6
c:
co
!1
:fa = aOC
25C
C
3.0
2.0
4.0
5.0
4.5
4.0
6.0
5.5
4.5

v.s. Cycle rate
5.5
5.0
6.0
I f::C2 v.s. Ta
50
Ta= 25 C
I
tRP = 100 ns
5.0
5.0V
~
E
4.5V
>.0
0
.~
veb = 5.5\1.
VIH: max.
4.0
-6
c:
co
"
!1
3.0
...............
!:?
!:?
Cycle Rate (lltRc) [MHzI

v.s. Ta
50.-,----,----.----,-.
Vee = 5.5V
tRP = 100'ns
40~+--_+----+---~~
70
:;:::;;:;-
Vee [VI
Vee [V]
75C
75
2.0
~ r---....
...... r--.
25
50
75
ICC3 hRAS: Constant)

v.s Vee
ICC3 hRP: Constant)

v.s. Vee
40~---r----r----r--~
<"E
0;
40~---r----r----r----'
Ta = 25C
tRP = 100 ns
Ta = 25C
tRAS = 140 ns
301----+-----+-
30
>
Xl
"
000 ns
1; 10 L..._-l---*'==I=====I
ou
U
U
5.0
4.5
4.0
4.5
4.0
6.0
5.5
ICC3 hRAS: Constant)

v.s. Cyel e rate
ICC3 (tRP: Constant)

v.s. Cycle rate
40~---r----r----r----'
<"E
6.0
5.5
5.0
Vee [V]
Vcc [V]
Ta = 25C
tRAS = 140 ns
40
Ta = 25"C
tRP = 100 ns
<"E
301---~----+--~+-~~
0;
30
5.0V
4.5V
>
u
-5i
!5'"
M
10
!:?
2
0;
30
>
u
-5i
~
a:'"
M
u
u
20
10
ICC3 (tRAS: Constant)

v.s. Ta
ICC3 hRP: Constant)

v.s. Ta
40
ve1 = 5.5VI
tRAS = 140 ns
Cycle rate (l/tpC) [MHz]
40
<"E
Cycle rate (lItRC) [MHz]
~ f---.:.~o ns
0;
I-..
330 ;-
I-
u
-5i
500 ns
Vee
tRP
<"E
1000 ns
30
!5'"
M
5.5VI
100 ns
1 - - ~tRc
20
10
~ 240 Os
>
I---
.:-g~
:-!2! ~
~
!:?
75
--1
25
50
75
Ta rOC]
71
DYNAMIC RAM MSM3732AS/RS . - - - - - - - - - - - - - - - - -
ICC4 (tCAS: Constant)

v.s. Vee
Ta ~ 25C
tCAS ~ 100 ns
<{
ICC4 (tcp: Constant!

v.s. Vee
<{
40~--~----+---~~.
E
Q;
>
'"
If'"
4.0
5.0
4.5
6.0
5.5
4.0
4.5
5.0
Vee [V]
Ta ~ 25C
tcp ~ 50 ns
~
E 40
Ta~25C
~
100 ns
Vee
Q;
>
5.5V
5.0V
4.5V
30
2l,
'"
f!o
'<t
u 20
Q;
U
u>
30
'"'"
f!o'"
'<t
u 20
Cyele rate (l/tpC) [MHz]
ICC4 (tcp: Constant)

v.s. Ta
Q;
Q;
1j
>
'<t
5.5V/
50 ns
>
'"'"
f!o'"
'<t
20
u
u
25
50
Ta [DC]
72
~
~
1j
30
'"'"
'"
f!o
u
Vee
tcp
E 40
E 40
Cyele rate (l!tpc! [MHz]

V.s. Ta
6.0
ICC4 (tCP: Consta nt)

v.s. Cycle rate

v.s. Cycle rate
tCAS
~
E 40
5.5
Vee [V]
75
20
25
50
Ta rOC]
75
Address Input
v.s Vee
Address Input
v.s. Ta
II
Ta = 25C
Vee = 5.0V
VIHmin
>"
2.0
-_~"
1. 5
VIH min
VIL max
::>
C.
c:
1.0
4.0
4.5
5.0
5.5
6.0
25
Vee [V]
50
75
Ta rOC]
Data Input
v.s. Vee
Data Input
v.s. Ta
Ta = 25C
J.
Vee = 5.0V
>"
2.0
>"
Oi
~
2.0
VIH min
1.5
::>
VI~ max
C.
c:
1.0
o
Vee [V]
J.
Vee = 5.0V
>"
Oi
2.0
VIHmin
Oi
75
Clock Input
v.s. Ta
Ta=25C
2.0
50
Ta rOC]
Clock Input
v.s. Vee
>"
25
1.5
::>
::>
C.
C.
.E
.E
VIL max
1.0
o
Vee [V]
25
50
75
Ta rOc]
73
DYNAMIC RAM MSM3732AS/RS . - - - - - - - - - - - - - - - RAS/CAS CYCLE LONG RAS/CAS CYCLE RAS ONLY CYCLE PAGE MODE CYCLE
'- -f..l
r- r-r-
I\. _1 ""\
\~ .....
80
I
60
ft
ICC
[mAl 40
20
74
(\.1 \J
lJ ~ r\
\J rv
~~
'"
i\
J rv 1"- 1\
50 ns/dlv
11\ I
'1/
J" 1\V'
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ DYNAMIC RAM MSM3732AS/RS

MSM3732 Bit MAP (Physical-Decimal)
MSM3732L BIT MAP
[A7column="L"j
MSM3732H BIT MAP

[A7 column - "H"j
~~g
129 128
255 255
,......
192 193
255 255
254 255
255 255
191 190
127 127
129 128
127 127 r<>-1
63 62
255 255
1
0
255 255
re-
64 65
255 255
~;~ 255
127
63 62
127 127
1
0
127 127
126 127
254 254
63 62
126126
1
0
126 126
191
255
OPIN16
r-- .--192 193
~~
64
,-e-
254 255
127 127
126 127
127 127
65
64 ~
.... r!E
126 126
126 127
126 126
192 193
126 126
254 255
126 126
192 193
254 255
125 125
63 62
254 254
1
0
254 254
f--e-
64 65
254 254
191 190
254 254
129 128
254 254
192 193
254 254
254 255
254 254
191 190
126126
129 128
126 126
l<><
191 190
253 253
129 128
253 253
192 193
253 253
254 255
253 253
191 190
125125
129 128
125 125
63 62
253 253
1
0
253 253
64 65
253 253
126 127
253 253
63 62
125125
1
0
125 125
fe-
63 62
252 252
1
0
252 252
64 65
252 252
126 127
252 252
63 62
124124
0
1
124 124
f-e-
191 190
252 252
129 128
252 252
192 193
252 252
254 255
252 252
191 190
124124
129 128
124 124
I<><
191 190
251 251
129 128
251 251
192 193
251 251
254 255
251 251
191 190
123 123
129 128
123 123
~
~
64
126 127
125 125
65
~
~
64 65
126 127
124 124
~
~
192 193
124 124
254 255
124 124
192 193
123 123
254 255
123 123
I
i90
4
i90
191 190
132 132
129 128
132 132
192 193
132 132
254 255
13 2 132
191
191 190
131 131
129 128
131 131
B2 193
131 131
254 255
13 1 131
191
3
64 65
131 131
126 127
13 1 131
63
3
62
64 65
130 130
1 26 127
13 0130
63
62
63 62
f--
-<>-
22!. 22!.
~ !22.
-rn -- B CD
129 128
4
4
129 128
3
3
/&<
1
3
0
3
1
2
0
2
63 62
130 130
0
1
130 130
191 190
130 130
129 128
130 130
192 193
130 130
254255
13 0130
191
2
i90
129 128
2
2
191 190
129 128
129 129
192 193
129 129
2 54 255
129 129
191
i90
129 128
1
1
--<>--
64 65
129 129
1 26 127
129129
64 65
128 128
126 127
128128
192 193
128 128
2 54 255
128128
~~
63 62
129 129
-B-
1
0
129 129
- 1- 0
63 62
128 128
128 128
rn
i28
128 128
191 190
128 128
rni~1l
~e"esh Add,e
Ref,esh Add,ess?
,
163- 01
6,
{Positive)
D,
D,
"-D,
Sub Amp IC
:=
Column Address (Decimal)
0
1
62
o ....9.
1
0
0
0
191 190
o 0
f-192 193
254 25 5
4
4
~~
254 25 5
3
3
192 193
3
3
~ -65
3
126 12
2
126 12 7
2
2
254 255
2
2
192 193
1
1
254 25 5
1
1
~ 65
,... 1m i93
)G<
-e-
,...
129 128
0
0
f;2s -12
64 65
f-1
~ -65
126 12 7
o
0
~~
254 255
0 o
192 193
0
0
OJ rnBCD
ill
~ ~efcesh
Add,ess.
Ref,esh Add,es7,
163 ~ 01
A = Row Address (Decimal)
Cell
1
1
63
164 ~ 1271
1lI
I
Din
(Positive)
(Negative)
D,n
0
Pin 8
-1
63 62
1
164 -127
I
Din
IColumnl
04
_
0
"3
04
Din
(Negative)
IRowl
Word Driver
Sense Amp
~ Numbe' of Bus L,nel
75
OKI
semiconductor
MSM3764 AS/RS
65,536-BIT DYNAMIC RANDOM ACCESS MEMORY
GENERAL DESCRIPTION
The Oki MSM3764 is a fully decoded, dynamic NMOS random access memory organized as 65536 one-bit words.
peripheral storage and environments where low power dissipation and compact layout is required.
Multiplexed row and column address inputs permit the MSM3764 tb be housed in a standard 16 pin DIP. Pin-outs
conform to the JEDEC approved pin out.
process, coupled with single-transistor memory storage cells, permits maximum circuit density and minimum chip
compatible.
FEATURES
.Silicon-gate, Double Poly NMOS, single transistor cell
Row access time,
150 ns max (MSM3764-15)
200 ns max (MSM3764-20)
Cycle time,
270 ns min (MSM3764-15)
330 ns min (MSM3764-20)
Low power: 248 mWactive,
28 mW max standby

"Gated" "CAS
Common I/O capability using "Early Write"
operation
boundary and two-dimensional chip select
Read-Modify-Write, RAS-only refresh, and PageMode capability
performance
PIN CONFIGURATION
IJ
76
NC
v"
Din
CAS
WE
Dout
Ao,.....,A?
RAS
Row Address Strobe
RAS
A,'
CAS
Column Address StrObe
A,
A,'
WE
Din
Write Enable
A,'
A,'
Dout
Data Output
VCC,
Power Supply (+5V)
A,'
A,'
VSS
Ground (OV)
Vee
A,
Refresh Address
Pin Names
Function
Address Inputs
Data" Input
--------------------11. DYNAMIC RAM MSM3764AS/RS

FUNCTIONAL BLOCK DIAGRAM
RAS
eAS--~=;~~~~~~L-)------lL-------T-~
1-------- WE
Dout
1-------- Din
ABSOLUTE MAXiMUM RATINGS
(See Note)
Rating
Symbol
Value
Unit
VIN, VOUT
-1 to +7
Vee
-1 to +7
Topr
o to 70
Storage temperature
T stg
-55 to +150
PD
1.0
50
mA
Voltage on any pin relative to
vss
Power dissipation

(Referenced to Vss)
Parameter
Supply Voltage
Symbol
Vee
VSS
Min.
Typ.
Max.
Unit
4.5
0
5.0
0
5.5
0
V
V
VIH
2.4
6.5
VIL
-1.0
0.8
Operating
T emperatu re
oOe to +70o e
77
.1-----------------
DC CHARACTERISTICS
(Recommended operating conditions unless otherwise noted.1
Parameter
Symbol
Min.
Max.
Unit
45
mA
Notes
Operating Current*

(RAS, CAS cycling; tRC = min.1
ICCl
Standby Current
(RAS = CAS = VIHI
ICC2
Refresh Current"
(RAS cycling, CAS = VIH; tRC = min.!
ICC3
35
mA
Page Mode Current"

(RAS = Vll, CAS cycling; tpc = min.1
ICc4
42
mA
Input leakage Current

Input leakage current, any input
(OV ::; VIN ::; 5.5V, all other pins not
under test = OVI
III
-10
10
jJ.A
Output leakage Current

OV ::; VOUT::; 5.5VI
IlO
-10
10
jJ.A
Output levels
5.0
2.4
VOH
VOL
0.4
mA
V
V
Note*: ICC is dependent on output loading and cycle rates. Specified values are obtained with the output open.
CAPACITANCE
(T a = 25 C, f = 1 MHzl
Parameter
Symbol
Typ.
Max.
Unit
Input Capacitance (Ao - A 7 , DINI
CINl
4.5
pF
Input Capacitance (RAS, CAS, WEI
CIN2
10
pF
Output Capacitance (DOUTI
COUT
pF
78
- - - - - - - - - - - - - - - -... DYNAMIC RAM . MSM3764AS/RS
AC CHARACTERISTICS
Note 1,2,3
Parameter
Symbol
Units
MSM3764-15
MSM3764-20
Min.
Min.
Max.
Note
Max.
Refresh period
tREF
ms
tRC
ns
270
330
tRWC
ns
270
330
tpc
ns
170
tRAC
ns
150
200
4,6
Ac~ess
time from CAS
tCAC
ns
100
135
5,6
tOFF
ns
Transition time
tT
RAS precharge time
tRP
RAS pulse width
40
ns
35
ns
100
tRAS
ns
150
tRSH
ns
100
CAS precharge time
tcp
ns
60
100
tCAS
ns
CAS hold time
tCSH
ns
150
~ to CAS delay time
CAS pulse width
225
RAS hold time
50
50
120
10,000
200
10,000
135
80
10,000
135
10,000
200
tRCD
ns
25
CAS" to RAS precharge time
tCRP
ns
50
tASR
ns
0
20
30
tRAH
ns
15
tASC
ns
tCAH
ns
45
55

referenced to R AS
tAR
ns
95
120
Read command setup time
tRCS
ns
tRCH
ns
twcs
ns
-10
-10
tWCH
ns
45
55

referenced to RAS
tWCR
ns
95
120
twp
ns
45
55
tRWL
ns
45
55
tCWL
ns
45
55
Datain set-up time
tDS
ns
Datain hold time
tDH
ns
45
55

to RAS
tDHR
ns
95
120
CAS to WE delay
65
tCWD
ns
60
80
RAS to WE delay
tRWD
ns
110
145

referenced to R AS
tRRH
ns
20
25
79
DYNAMIC RAM MSM3764AS/RS . - - - - - - - - - - - - - - - - NOTES: 1) An initial pause of 100ILs is required after power-up followed by any 8 RAS cycles (Examples; RAS
3) VIH (Min.) and VI L (Max.) are reference levels for measuring timing of input signals. Also, transition
times are measured between VIH and VIL.
4) Assumes that tRCD < tRCD (max.).
the amount that tRCD exceeds the value shown.
5) Assumes that tRCD < tRCD (max.)
7) Operation within the tRCD (max.) limit insures that tRAC (max.) can be met. tRCD (max.) is specified as a reference point only; if tRCD is greater than the specified tRCD (max.) limit, then access
as electrical characteristics only; if twcs ~ twcs (min.), the cycle is an early write cycle and the aata
(min.) and tRWD > tRWD (min.) the cycle is read-write cycle and the data out will contain data read
READ CYCLE TIMING
tRC
RAS
VIHVIL -
CAS
VIH VIL-
Addresses
11
WE
tAR
VIHVIL -
VIHVIL-
I---tCAC
tRAC
DOUT
VOHVOL-
OPEN
tOFF
Valid Data
~"H", "L"
80
= Don't Care
- - - - - - - - - - - - - - - -__
WRITE CYCLE TIMING

(EARLY WRITE)
RAS
vIHVILtRSH
CAS
VIH -VIL-
_ _ _---l.~=~~:::::T~-tCAS---
r---lr--=.:..::....--'-_____
Addresses Vv i H - 1)
IL -1,'l
V IH -
7T17",",",",",",""",,""
VIL-,~~""""~~~-~-7_-~~""""""~~~""""~~~""~~
VIH-;::
VI L - '-I.I..t.~~~"4'""~~
DOUT
VOH- _ _ _ _ _ _ _---i
VOL-
Addresses VV IH IL -
VIH-~""""~~"*-------------~
VI L - "-'-'-1..I.I.I.'fL'-""lU.4
DOUT
tCAC
~~~ :::
OPEN
,I-DIN
~-----
r-------<r----VV;;ialicidjjDD;art"ta;;-----...
-tRAC-----1
~~tDH
VIH-~_Valid
VIL
_'//~
Data
~ "H", "L"
= Don't Care
81
- - - - - - - - - - - - - - - - - - - t l . DYNAMIC RAM MSM3764AS/RS
~------------------tRAS------------------~
Addresses vV I H -
IL-
'/l>.1Hooi'V/',v'C
~~~~~~~~r~~~~4~~
~"H", "L"
= Don't Care
Addresses V I H
VIL
~==.'
!--tCAC--j
DOUT VOH
VOL
----OPEN-----<
P1F-
WWA%%WAW
f--tcACI.,.---...
OPEN~~
~"H", "L" = Don't Care
83
DYNAMIC RAM . MSM3764AS/RS
.1----------------
HIDDEN REFRESH
RAS
VIH
VIL
CAS
VIH
VIL
Addresses
WE
VIH
VIL
_ - - - -____~av~~/,0
DOUT
Valid Data
5-
DESCRIPTION
Address Inputs:
A total of sixteen binary input address bits are required
to decode any 1 of 65536 storage cell locations within
the MSM3764. Eight row-address bits are established on
the input pins (Ao -A 7 ) and latched with the Row
Address Strobe (FiAS). The eight column-address
bits are establ ished on the input pins and latched with
the Column Address Strobe (CASI. All input addresses
must be stable on or before the falling edge of RAS.
CAS is internally inhibited (or "gated") by RAS to
permit triggering of CAS as soon as the Row Address
Hold Time (tRAH) specification has been satisfied and
the address inputs have been changed from row-addresses
to column-addresses.
Write Enable:
logic low (0) dictates write mode. Data input is disabled when read mode is selected.
Data Input:
01 N is strobed by CAS, and the set-up and hold times
are referenced to CAS. In a read-write cycle, WE will
Data Output:
84
after tCAC from transition of ~ when the transition
occurs after tRCD (max.1. Data remain valid until CAS
Page Mode:
Page-mode operation permits strobing the row-address
low (0) throughout ..all successive memory operations in
is eliminated.
Refresh:
During refresh, either VIL or VIH is permitted for A 7
Hidden Refresh:
Hidden Refresh is performed bV holding CAS as VIL
------------------11. DYNAMIC RAM MSM3764AS/RS

ICCI hRAS: Constant!
v.s. Vee

(Relative value! v.s. Vee
>
o
Ta
"-
tti
" 1.1
II
>
u~
.g:
11
>
25C
'",
1.0
co
..
.;:
0.9
I'--
looo ns
!f
4.0
5.0
4.5
5.5
4.0
6.0
4.5
Vee[V]
5.0
Vee [V]
5.5
6.0
ICCI (tRAS: Constant!

v.s. Cycle rate

(Relative value! v.s. Ta
50r----r----~--~----,
It)
N
"..
l,-
1.1
U 1.0
~
a:
.t:
co
~
Ta = 25C
I
tRAS = 140 ns
Vee' = 5.0"
V
V
Voo = 5.5V
5.0V
4.5V
co
.~
Co
U
tJ
0.9
g:
25
50
75
Cycle Rate (l/tRcI [MHz]
Access tlme from CAS

ICCI hRAS: Constant}

v.s. Ta
50
;;
0
tti
<"E
1.1
u
u
>
U
.~
.,Co
1.0
.t:
40
tJ
11
VeeI = 5.5VI
tRAS = 140 ns
30
U 20
0.9
tJ
~
--
=2qG ns
~~
."
30 ns f.-
500 ns
I-
4.0
tRr-
1000 ns
25
50
75
Vee [V]
85
DYNAMIC RAM MSM3764AS/RS - - - - - - - - - - - - - - - -

v.s. Vee
50r----r----r----r---,
Ta = 25C
tRP = ioo ns
~ 401----+-,.-+_
ICC2 v.s. Vee

VIH: max.
:;{
E
5.0
--I-.
%4.0
-6
c:
co
~ 3.0
N
U
U
4.0
4.5
4.0
6.0
5.5
5.0
4.5
2.0
:fa = OC
25C
--

v.s. Cycle rate
50r----r----r----r----,
ICC2 v.s. Ta
5.0
:;{
E
:;{
E
co
>.c
4.5V
-6c:
"c.
3.0
co
'5
Cycle Rate (litRe) [MHz]
ICCl (tRp: Constant)

v.s. Ta
50r-~--~----,---~--,
Vee = 5.5V
tRP = 100'ns
40I-F-......=--
co
.':::
~
"c.
S
U
u
86
..
:;{
E
Vee = 5.5\l
VIH: max.
4.0
.~
25
50
6.0
5.5
5.0
Vee [V]
Vee [V]
7'5 C ~
75
2.0
........
i'...... .........
25
50
Ta [OC]
............
75
- - - - - - - - - - - - - - - - - . DYNAMIC RAM MSM3764AS/RS

v.s Vee
ICC3 (tRp: Constant)

v.s. Vee
40r----r----,----r--~
Ta = 25C
tRAS = 140 ns
E
30f----+-----h
';i'
40~--~----~----~--~
';i'
E
Q;
Ta = 25C
tRP = 100 ns
301----1------1-
Q;
u>
>
~
Q)
.::
Q)
000 ns
10~--~--~~~~==~
::;
4.0
4.5
5.0
4.0
6.0
5.5
4.5
';i'
E
6.0
5.5
5.0
Vee [V]
Vee [V]

v.s. Cycle rate
40,----r----,----.----,
Ta = 25C
tRAS = 140 ns
30~--_+----1---~~~~
ICC3 (tRp: Constant)

v.s. Cycle rate
40
';i'
Q;
U
Ta = 25C
tRP = 100 ns
30
5.0V
4.5V
>
~
Q)
!S
M
10
::;
2
Cycle rate (lltRd [MHz]

v.s. Ta
40
';i'
E
Q;
30
;;;;
20
Q)
!S
M
10
Vee = 5.5V!
tRP = 100 ns
:t
Q;
'--
330 ns
500 ns
---.;.;.
1000 ns
!S
t--

v.s. Ta
;:-- ~Ons
I-
40
Ve~ = 5.5VI
tRAS = 140 ns
U
>
Cycle rate (1/tpC) [MHz]
20
Q)
U
U
30
U
>
10
---
---
~~ns
"-
1'-3~
500 ns
100~
.....
--
::;
25
50
75
25
50
75
87
DYNAMIC RAM MSM3764AS/RS - - - - - - - - - - - - - - - -

v.s. Vee
"<E
ICC4 Itcp: Constantl

v.s. Vee
Ta = 25C
tCAS = 100 ns
"<E
40r---~---+----~
4.0
4.5
5.0
6.0
5.5
Ta = 25C
tcp = 50 ns
40r---~--~----~
4.0
4.5
5.0
Vee [V]

v.s. Cycle rate
"<E
ICC4 ItCP: Constantl

v.s. Cycle rate
Ta = 25C
tCAS = 100 ns
40r---~--~----+---~
.,~
!!,
tS
u
"<E
Ta = 25C
tcp = 50 ns
40r----r----r---~--~
a;
a;
6.0
5.5
Vee [V]
30r----+--~~~~E=~~
>-
30 I----t----,.""":....."I-:~~
~
201--::.1--+--+---1
201---"--+-----+--+-----1
tS
Cycle rate (l/tpC) [MHz]
Cycle rate (l/tpC) [M Hz]

v.s. Ta

v.s. Ta
Vee = 5.5V/
"<E
"<E
a;
u
>u 30
a;
u
>u
.,
~
!!,
.,
tS
CI)
01
!!,
tS
20
= 50 ns
40r-;---~----+----1~
201-~----~---F
25
50
Ta rOC]
88
tcp
75
25
50
Ta rOC]
75
Address Input
v.s. Ta
Address Input
v.s Vee
Vl=5.0J
5'
2.0
VIH min
1.5
VIL max
OJ
!
;
0.
.:
4.0
5.0
4.5
5.5
1.0
6.0
Vee [V]
75
Ta rOC]
Data Input
Data Input
v.s. Vee
v.s. Ta
v~e = 5.0'V
Ta = 25C
50
25
2.0
5'
OJ
2.0
OJ
>
.2!
~
VIH min
1.5
::l
::l
0.
VIL max
0.
.:
.:
1.0
o
Vee [V]
25
50
75
Ta rOC]
Clock Input
Clock Input
v.s. Vee
v.s. Ta
v~e =5.dv
5'
5'
OJ
2.0
VIHmin
OJ
1.5
::l
::l
.:
.:
0.
0.
4.0
4.5
5.0
5.5
6.0
VIL max
1.0
25
50
75
Vee [V]
89
DYNAMIC RAM MSM3764AS/RS - - - - - - - - - - - - -_ _ __

RAS/CAS CYCLE LONG RAS/CAS CYCLE RAS ONLY CYCLE PAGE MODE CYCLE
- ..J
'-
\:- :- r-1
I\. _1 ""\ I- -
\1- .....
80
.I
60
ICC
[mAl 40
20
"'"
90
~I V ~ ~\
\j IV
~~
i\
\
1\
~\
lJ rv '" ~
50 ns/dlv
11\
II 'I
~
\.
Ui\.. 'V
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _--11. DYNAMIC RAM MSM3764AS/RS
MSM3764 Bit MAP (Physical-Decimal)
[A7 column = "H"]
[A7 column
= "L"]
191 190
255 255
129 128
255 255 ~
192 193
255 255
254 255
255 255
191 190
127 127
129 128
127 127
r-
63 62
255 255
1
0
255 255
r&-
64 65
255 255
~;~
127
255
63 62
127 127
1
0
127 127
r<>
63 62
254 254
1
0
254 254
......
64 65
254 254
126 127
254 254
63 62
126126
1
0
126 126
f...
191 190
254 254
129 128
254 254
192 193
254 254
254 255
254 254
191 190
126 126
129 128
126 126
191 190
253 253
129 128
253 253
192 193
253 253
254 255
253 253
191 190
125125
129 128
125 125
63 62
253 253
1
0
253 253
f-<>-
64 65
253 253
126 127
253 253
63 62
125125
1
0
125 125
64 65
252 252
126 127
252 252
63 62
124124
0
1
124 124
f-e
252 252
254 255
252 252
191 190
124124
129 128
124 124
192 193
251 251
254 255
251 251
191 190
123 123
129 128
123 123
63 62
252 252
1
0
252 252
-&-
191 190
252 252
129 128
252 252
l-<><
191 190
251 251
129 128
251 251
l-<><
~ t;gj
OPIN 16
~
~
64 65
126 127
127 127
~
~
64 65
126 127
126 126
~
~
192 193
254 255
126 126
~~
193
254 255
125 125
192
~~
64
254 255
127 127
192 193
65
126 127
125 125
~
~
64
65
126 127
124 124
~~
192 193
124 124
254 255
124 124
192 193
123 123
254 255
123 123
191 190
132132
129 128
132 132
191 190
131 131
129128
131 131
63 62
131 131
192 193
~~
131 131
r-;-r--o
254255
132 132
1~2
193
131 131
254 255
131 131
64 65
131 131
126 127
131 131
126 127
130130
191190
192 193
129 128
~~
191 190
63
62
6~ 6~
f.&-
-2-2
--
130130
191 190
130130
129 128
130130
192193
130130
254 255
130130
2~
129 128
2
2
191 190
129129
129128
129 129
192193
129 129
254 255
129 129
19~ 19~
12~ 12~
63 62
129129
1
0
129129
64 65
129 129
126 127
129129
63 62
126128
1
0
~~
-e-
64 65
128128
126 127
128128
~~~ :~g
g~ g~
192 193
128 128
254 255
128128
q:LJ=l~ll'1f
163-0}
o.!
IPos"~'ve} 0,
63'62
~~
126 127
6~ 6~
12~ 12~
'i92 i9:i
254 255
19~ 19~
25i 25~
>-9-
64 65
--2.--2.
i;2s"i27
1
0
0
-e-
~~
1
0
12~ 12g
19~ 199
65
~,......:
63'62
64
254 255
64
65
~~
126 127
0
0
19~ 19~
25
6256
\wm EO ill Hrn ill

.Refresh
,\
O'D 0,
164-127}
0,
/,
ill
I
Din
INe~~~ve}
~ : ~~I~:ndC;;~~Sr!~et~::ail~al)
Addres0l~ \;"Befresh Address
163-0}
~-'-
Pin 8
Cell
191 190
254 255
192193
3
3
129 128
64 65
130 130
63 62
130130
IColumn}
(Positive)
0,
164-127}
,'\
"---
0,
04
_
Din
(Negative)
IRow}
Word Driver
--e--
Sense Amp
Sub Amp IC = Number of Bus Line}
91
OKI
semiconductor
MSM3764 AAS/RS
65,536-BIT DYNAMIC RANDOM ACCESS MEMORY (E3-S-004-321
GENERAL DESCRIPTION
The Oki MSM3764A is a fully decoded, dynamic NMOS random access memory organized as 65536 one-bit words.
The design is optimized for highspeed, high performance applications such as mainframe memory, buffer memory,
Multiplexed row and column address inputs permit the MSM3764A to be housed in a standard 16 pin DIP. Pin-outs
The MSM3764A is fabricated using silicon gate NMOS and Oki's advanced DoubleLayer Polysilicon process. This
process, coupled with singletransistor memory storage cells, permits maximum circuit density and minimum chip
compatible.
FEATURES
Silicongate, Double Poly NMOS, single transistor cell
Row access time,
120 ns max (MSM3764A12)
150 ns max (MSM3764A15)
200 ns max (MSM3764A20)
Cycle time,
230 ns min (MSM3764A12)
260 ns min (MSM3764A15)
330 ns min (MSM3764A20)
Low power: 330 mWactive,
28 mW max standby
.Single +5V Supply, 10% tolerance

"Gated" CAS
operation
ReadModifyWrite, RASonly refresh, and Page
Mode capability
On-chip latches for Addresses and Datain
performance
PIN CONFIGURATION
NC
Pin Names
WE
92
Function
Address Inputs
Dout
Ao .......A,
RAS
Row Address Strobe
A,'
CAS
.~
Write Enable
Ao'
A,'
A,'
A,
A,'
A,'
Vee
A,
Refresh Address
Din
Data Input
Oout
Data Output
Vcc
Power Supply (+5V)
VSS
Ground (OV)
- - - - - - - - - - - - - - -____ DYNAMIC RAM MSM3764AAS/RS _

I----WE
Buffers
Ao-A,
Dout
Row
Address
Buffers
Word
Memory
Cells
Driv-
ers
Vee
VSS-
I-----Din
On chip VBB
(See Note)
Rating
Symbol
Value
Unit
VIN, VOUT
-1 to +7
Voltage on Vee supply relative to Vss
Vee
-1 to +7
Topr
o to 70
Storage temperature
T stg
-55 to +150
PD
1.0
50
mA
Power dissipation

(Referenced to VSS)
Parameter
Supply Voltage
Symbol
Vee
VSS
Min.
Typ.
Max.
Unit
4.5
0
5.0
0
5.5
0
V
V
VIH
2.4
6.5
VIL
-1.0
0.8
Operating
Temperature
oOe to +70 0 e
93
DYNAMIC RAM MSM3764AAS/RS - - - - - - - - - - - - - - - -
DC CHARACTERISTICS
I Recommended operating conditions unless otherwise noted.)
Symbol
Parameter
Operating Current"
IRAS, CAS cycling; tRC = min,)
ICCl
Standby Current
IRAS = CAS = VIH)
ICC2
Refresh Current"
IRAS cycling, CAS = VIH; tRC
Min.
Max.
Unit
60
mA
5.0
Notes
mA
ICC3
40
mA
ICC4
60
mA
= min.)
Page Mode Current"

IRAS = VI L, CAS cycling; tpc
= min.)

(OV S; VIN S; 5.5V, all other pins not
under test = OV)
III
-10
10
/lA
ILO
-10
10
/lA
Output Leakage Current

OV S; VOUT S; 5.5V)
Output Levels
Output high voltage IIOH = -5 mAl
Output low voltage IIOL = 4.2 mAl
2.4
VOH
VOL
0.4
V
V
Note": ICC is dependent on output loading and cycle rates. Specified values are obtained with the output open.
CAPACITANCE
ITa= 25C, f= 1 MHz)
Unit
Symbol
Typ.
CINl
pF
I nput Capacitance IRAS, CAS, WE)
CIN2
pF
COUT
pF
Output Capacitance IDOUT)

94
Max.
Parameter
Input Capacitance lAo - A" DIN)
- - - - - - - - - - - - - - - -.... DYNAMIC RAM MSM3764AAS/RS
AC CHARACTERISTICS
(Recommended operating conditions unless otherwise noted. I
Parameter
Symbol
Note 1,2,3
MSM3764A-12
MSM3764A-15
MSM3764A-20
Min.
Min.
Min.
Units
Note
Max.
Max.
Max.
Refresh period
tREF
ms
tRC
ns
220
260
330
tRWC
ns
245
280
345
tpc
ns
120
145
Access time from R AS
tRAC
ns
120
150
200
4,6
tCAC
ns
60
75
100
5,6
tOFF
ns
Transition time
35
35
tT
ns
RAS precharge time
tRP
ns
90
RAS pulse width
120
40
35
100
tRAS
ns
tRSH
ns
60
75
CAS precharge time (Page cyclel
tcP
ns
50
60
CAS pulse width
tCAS
ns
60
CAS hold time
tCSH
ns
120
RAS to CAS delay time
tRCD
ns
25
CAS to RAS precharge time
tCRP
ns
190
RAS hold time
10,000
10,000
150
75
25
0
50
50
120
10,000
200
10,000
100
80
10,000
150
60
100
10,000
200
75
30
100
tASR
ns
tRAH
ns
15
15
20
tASC
ns
tCAH
ns
20
20
25

referenced to R AS
tAR
ns
80
95
125
tRCS
ns
tRCH
ns
a
a
twcs
ns
-10
-10
-10
tWCH
ns
40
45
55

referenced to RAS
tWCR
ns
100
120
155
twp
ns
40
45
55
tRWL
ns
40
45
55
tCWL
ns
40
45
55
Data-in set-up time
tDS
ns
Data-in hold time
tDH
ns
40
45
55

to RAs
tDHR
ns
100
120
155
CAS to WE delay
tCWD
ns
40
45
55
RAS to WE delay
tRWD
ns
100
120
155

referenced to RAS
tRRH
ns
CAS precharge time
tCPN
ns
30
35
45
95
DYNAMIC RAM MSM3764AAS/RS - - - - - - - - - - - - - - - NOTES: 1) An initial pause of 100jts is required after power-up followed by any 8 RAS cycles (Examples; RA!l
4) Assumes that tRCD < tRCD (max.).
the amount that tRCD exceeds the value shown.
5) Assumes that tRCD < tRCD (max.)
7) Operation within the tRCD (max.) limit insures that tRAC (max.) can be met. tRCD (max.) is specified as a reference point only; if tRCD is greater than the specified tRCD (max.) limit, then access
as electrical characteristics only; if twcs ~ twcs (min.), the cycle is an early write cycle and the oata
READ CYCLE TIMING
~-----------------tRC------------------~
-I
~------------tRAS----------~~
RAS
VIHVIL -
- - - - -....1
!-.......----tAR
Ir----.j
'----
~----r--tRSH------~
CAS
Addresses
WE
VIH VIL-
----'-'-----v--....I----+-tCAS-------!
VIHVIL -
VIHVIL-
I-----tCAC
~----------tRAC----------~
DOUT
;'--+------,1
VOHVOL-
----I
.r-----i
OPEN
tOFF
Valid Data
~"H", "L" = Don't Care.
96
- - - - - - - - - - - - - - - -..... DYNAMIC RAM MSM3764AAS/RS
WRITE CYCLE TIMING

(EARLY WRITE)
RAS
VIHVIL -
tRC
tRAS
tAR
tRSH
tCAS
CAS
VIH -VIL -
WE
VIHVIL -
DIN
DOUT
VOHVOL -
OPEN
READWRITE/READMODIFYWRITE CYCLE
RAS
CAS
V'"--t;
VIL -
~I
'A'
'RWC
tRAS
~,,~}-
tRSH
tCAS
tRCD
VIHVIL -
VIH- /
Addresses V
IL -
WE
VIHVIL tOFF
LtCAC
DOUT VOH VOL-
DIN
OPEN
Valid Data
~~~~
~:~=~valisa;wa
97
DYNAMIC RAM MSM3764AAS/RS - - - - - - - - - - - - - - - RAS ONLY REFRESH TIMING

(CAS: VIH,WE & DIN: Don't care)
~:~ _~
~RAH~
tASR
Addresses
Row Address
VOH DOUT
OPEN
VOL
~ "H", "L"
= Don't Care
~~~~~~--~~-tRAS~~~~~~~~~~~
CAS
VIHAdres,es V I L -
DOUT VOH- _ _ __
m=~~~--~~~--~s)r--~~-t-R~-H-~~==
~ .. H .. ,"L .. =Don't Care
98
~----------tRAS----------~
Addresses vVIH-
IL-
,/N11O/v"W"-T1
~~~~~~~~r~~~~4~~
V I H - ,7777
Im'77"J':mIll
WE
VIL-~~~~~~~~""~~~I'"'rn>~~~~~~~~~""~~~~""~
PAGE MODE, READMODIFYWRITE CYCLE
Addresses V IH
VIL
---OPEN---<I
~ "H" , "L" = Don't Care
99
HIDDEN REFRESH
Addresses
v::
W~.RA~~______---T'I@'I(,'lIA
DOUT V O L - - - OPEN
Valid Data
5-
~ "H", "L"
DESCRIPTION
Address Inputs:
A total of sixteen binary input address bits are required
to decode any 1 of 65536 storage cell locations within
the MSM3764A. Eight rowaddress bits are establ ished
on the input pins (AD ~A,) and latched with the Row
Address Strobe (FiASl. The eight column-address
bits are established on the input pins and latched with
the Column Address Strobe (CAS). All input addresses
must be stable on or before the falling edge of RAS.
CAS is internally inhibited (or "gated") by RAS to
permit triggering of CAS as soon as the Row Address
Hold Time (tRAH) specification has been satisfied and
the address inputs have been changed from row-addresses
Write Enable:
Data Input:
Data is written into the MSM3764A during a write or
Data Output:
100
= Don't Care
after tCAC from transition of CAS when the transition
occurs after tRCD (max.l. Data remain valid until CAS
Page Mode:
into the MSM3764A while maintaining RAS at a logic
is eliminated.
Refresh:
Refresh of the dynamic memory cells is accompl ished
Hidden Refresh:
Hidden Refresh is performed by holding CAS as V I L
:>
o
lri
1.4
II
t5
1.2
c3
1.0
>
u

(Relative value) v.s. VCC
"-
~ 0.8
u
1.4
U1
N
II
t::.'"
u
a:
4.5
..
t::.
u
a:
0.8
......
Cii
Access fime from RAS

(Relative value) v.s. Ta
VCC; 5.0V
tRCO: min
V"
6.0

v.s. Cycle rate
O
5 r--~-.--.--,
Ta; 25C
u
u
75
345
Cycle Rate (l/tRC) [MHz]
50
JS
u
u 1.2
40

v.s. Ta
0
''::;
a: 1.0
......
Ta; 50C
Ta; 25C
Ta ; OC
..
5.0
5.5
VCC[V]
./
II
a:
4.5
E 40r---+----r---.~r

(Relative value) v.s. VCC
1.4
tRCO: max
lri
>
40r---+---~~~~~
4.0
6.0
:>
0
~--~~.----r---.
""'r-.....
5.0
5.5
VCC [V]
1.2
1.0
JS
L __L __~~~~~tR~C ; 1000 ns
4.0
50
Ta; 25C
tRCO: min

V.s. VCC
0.8
VCC - 5.5V ;1
tRAS; 120 ns
tR C; 220 flS
I
tR C; 260 ns
'1
30
tR C; 330 ns
u 20
u
tR C; 500 ns
E
Q)
a.
tR C; 1000 ns
4.0
4.5
5.0
5.5
VCC [V]
6.0
75
101
DYNAMIC RAM MSM3764AAS/RS . - - - - - - - - - - - - - - - -
50 ICCl (tRP: Constant) v.s. VCC

Ta = 25C
~
tRC = 220 ns
.... 40 ~--+---~~~~ tRCI = 260 ns
.;:::;
8.
S?
tRC = 330 ns
I
30~-"='_b"",..'9'---:::;a,.-tRC = 500 ns
I
tRC = 1000 ns
U 20~~. .~=r--~--~
4.5
5.0
5.5
VCC [V]
Ta = 25C
tRP = 90 ns
V9 C = 5.5V
6.0
<'
.... 4.0
--"" ..........
............... ~
50lCCl (tRP: Constant) v.s. Ta
40
"2
0
.;:::;
30
Co
20
..
---
--
RC
, = 220 ns
r-t RC = 260 ns
I
t RC = 330 ns
I
.. t RC = 500 ns
t RC = 1000 ns
VCC = 5.5V
tRP = 90 ns
102
5.0
5.5
VCC [V]
ICC2 v.s. Ta
VCC = 5.5V
VIH: max
D 2.0
Sd
4.5
~
~
S?
U
u
4.0
c:
'"Co
-6 3.0
S?
.... Ta=
-:Ta =
Ta Ta
--
3.0
5.0
.;:::;
'"
-g
6.0
.... 40 I--'~""""'---+---"""~V CC = 5.0V

"2
V'CC=4.5V
0
>:
.0

v.s. Cycle rate
50
VIH:'max
.... 4.0
S:?
4.0
<'E
<'
D 2.0
ICC2 v.s. Vce
5.0
1
75
25
50
Ta rC]
75
_______________--11. DYNAMIC RAM MSM3764AAS/RS
oS
a.>
40
40
30
tRC = 330 ns
tRG = 500 ns
tR = 1000 ns
>
20
20
.<:
CJ!!'
10
a: 10
...-'"~
a.>
U
U
0
4.0
4.5
5.0
5.5
VCC[V]

v.s. Cycle rate
~
E
~=260ns
13
.<:
U
U
tRC = 220 ns
a; 30
>
'"
...-a.>~
Ta = 25C
oS
13
ICC3 (tRP: Constant) v.s. VCC
ICC3 (tRAS: Constant) v.s. VCC
VCC = 5.5V
!--'-'.:...=.-t---..,----bO'''-::ooVCC = 5.0V
I
VCC = 4.5V
4.5
5.0
5.5
VCC [V]
6.0

v.s. Cycle rate
40~--~--~--~--~
40r---,----r---.--~
0
4.0
a.>
Ta = 25C
tRP = 90 ns
VCC = 5.5V
30 I--'-'-'--T---+--c:::II"""""-:::VCC = 5.0V
VCC = 4.5V
~ 20~~~~~~--+---~
'"
~
't
a:
10 I---+----t-----/----i
o~--~--~----~--~
U
U
O~
2
3
4
5
Cycle Rate (1/tRC) [MHz]
Cycle Rate (1/tRC) [MHz]
ICC3 (tRAS: Constant) v.s. Ta

VCC - 5.5V
tRAS= 120ns
E
tRIC = 220 ns
a; 30
I
13
tR C = 260 ns
>
E..
-s; 20
.<:
20
a:
10
40
...-a.>~
a:
10
tR C = 330 ns
I
t~ C = 500 ns
tR C = 1000 ns
'1
o
75
__~__~____~__~
~
a.>
40
30
13
>
....a.>~
ICC3 (tRP: Constant) V.5. Ta

VCC - 5.5V
tRP = 90 ns
!~
-'--
C = 220 ns
tFiC = 260 ns
C = 330 ns
C = 500 ns
tR C = 1000 ns
!R
!R
U
U
25
50
Ta rC]
75
103
DYNAMIC RAM MSM3764AAS/RS . - - - - - - - - - - - - - - - - -

v.s. VCC
50
Ta = 25C
tCAS = 60 ns
:?
E
'">
40
ICC4 (tcp: Constant) v.s. VCC

50
tpc = 120 ns
tpc = 145 ns
t3
()
'"Cl
e:.'"
<:t
30
tpc = 230 ns
I
tp = 400 ns
20
t3
>
()
'"
e:.'"'"
<:t
30
20
!:?
()
4.0
4.5
5.0
5.5
VCC[V]
4.0
6.0

v.s. Cycle rate
50r---~--T---~--~
:?
E
~
Ta = 25C
tcp = 50 ns
401--~--+-~-~
'"
>
30 1----J..-__""""4--""""-~
()
30 ~--+-~4...q _
(l)
Cl
'"
a..
rf.
<:t
<:t
()
()
()
()
4
10
8
6
Cycle Rate (1/tPC) [MHzJ
ICC4 (tCAS: Constant) v .5. Ta
4
6
8
10
Cycle Rate (1/tPC) [MHz]
ICC4 (tcp: Constant) v.s. Ta
50
50
:?
:?
~ 40~~~~~~--~~
'"
tpc
() 30 I------''''--=,---l--~I--==~tpc
rf.
tpc
I
tpc
20
=
=
=
=
120 ns
145 ns
230 ns
400 ns
'"
t3
>
c;
75
30
r-....;;;:::---+--=T-I
Cl
rf.
<:t
()
()
()
104
6.0
t3
t3
()
5.0
5.5
VCC[V]
50r---.---.----.--~
Qj'
<:t
4.5

v.s. Cycle rate
Ta = 25C
E 40 tCAS = 60 ns
>
()
40
Qj'
()
()
:?
Ta = 25C
:?
tpc = 230 ns
20 f.--+---l--=~~--I.-tPc = 400 ns
75
- - - - - - - - - - - - - - - -...... DYNAMIC RAM MSM3764AAS/RS
Address Input v.s. Vcc
Address Input v.s. Ta

vdc= 5.bv
:> 2.0
2:
>
....
>
....
VIL max
Co
Co
c:
1.0
4.0
4.5
5.0
5.5
VCC[V]
6.0
Data Input v.s. VCC
:>
:>
2.0
~
~ 1.5 f---::;;oo'l!5~-t--+---I
....
VJc= 5.bv
2.0
VIH
4.0
>
....
VIL max
1.5
4.5
5.0
5.5
VCC[V]
c:
1.0
6.0
Clock Input v.s. VCC
.....
Ta = 25C
2.0
:>
1.5
'"
>
....
Co
6.0
~IH mi~
t
1.5
5.0
5.5
VCC [V]
75
vbc = 5.6v
2.0
VIL max
Co
c:
1.0
4.0
25
50
Ta rOC]
Clock Input v.s. Ta
.=
mi~
OJ
Co
Co
c: 1.0 f - - - t - - - t - - + - - - i
Q;
>
75
25
50
Ta [0C]
Data Input v.s. Ta
2:
mi~
1.5
.=
VIH
Q;
Q;
1.0
25
50
Ta rOC]
75
105
..
VCC = 5.5V
Ta = 25C
50 ns/div
RAS/CAS CYCLE LONG RAS/CAS CYCLE RASONL Y CYCLE PAGE MODE CYCLE
RAS ~
CAS
-~ ~iJ
-~
~-
I\-~ ~
,-f\ 'ri"\..
~IJ
iJ
140
ICC
[rnA]
120
100
80
60
11
'I
20
0
106
\I
40
\I
-~ ~
II'
'"
- - - - - - - - - - - - - - -______ DYNAMIC RAM MSM3764AAS/RS _

MSM3764A Bit MAP (PhysicalDecimal)
[A7 column - "H"]
0
255 255
I
63 62
255 255
191 190
255 255
129 128
255 255
63 62
254 254
1 0
254 254
r<>-
126 127
255 255
254 255
25! 255
~
191 ~
190
f-e-
64 65
254 254
126 127
254 254
126 126
r-<>--
129 128
254 254
193
254
~
~
63 62
r"
1
0
126 126
r-
64 65
126 126
126 127
126 126
192 193
126 126
254
126
126
125
r<>
64 65
252 252
126 127
252 252
63 62
124 124
0
1
124 124
192 193
252 252
254 255
252 252
191 190
124 124
129 128
124 124
64 65
251 251
126 127
251 251
63 62
1 0
123 123
f-e-
192 193
253 253
63 62
252 252
0
1
252 252
f-e-
191 190
252 252
129 128
252 252
63 62
251 251
I
0
251 251
254
254
126
253
65
253
255
254
127
253
~~
r--<>-
254 255
253 253
192
254
64
253
65
126 127
127 127
129 128
127 127
128
126
0
125
64
OPIN 16
1 0
127 127
129
126
1
125
129 128
125 125
0
253 253
129 128
253 253
63 62
191 190
126 126
63 62
125 125
191 190
125 125
62
253
191 190
253 253
191
254
63
253
190
254
[A7 column - "L"]
64 65
255 255
192 193
255 255
~
~
192 193
127 127
64
65
125
~
192 i93
~
~
64 65
~~
193
192
124 124
64 65
123 123
254 255
127 127
255
126
127
125
254 255
125 125
126 127
124 124
254 255
124 124
126 127
123 123
(Column)
254 255
132132
1 0
131 131
192193
132132
64 65
131 131
129128
131 131
192 1!i3
131 131
254 255
131 131
130130
0
1
130130
64 65
130130
126 127
130130
191 190
130130
129128
130130
192193
130130
254 255
130130
63 62
1 0
129 129
64 65
129 129
126 127
129 129
129129
129128
129129
192 193
129129
254255
129129
1~ 1~~
12~
64 65
128128
126 127
128128
192 193
254
191 190
132 132
129 128
132 132
63 62
~~
~~
63 62
~~
191 190
f;g;"700
12g
129 128
f-e-
me
OJ ll,1J IUefreSh
Refresh Address?
(63~O)
D
In
02
01
0 01
Cell
: :
129128
~~
63 62
~~
191 190
~~
63 62
~2
191'190
~~
1
3
129128
3
3
1
2
o
2
129 128
192193
254 255
64
3
65
3
126 127
3
3
192193
3
3
254 255
64
65
126 127
192193
64
65
Addrcss_
(64-127)
L-.L
02
Din
(Negative)
Pin 8
11\
(Poso!lve)
126127
131 131
1-+191190
~~~~~~~Sr!~(~:-jl~al)
(Row)
Word Driver
Sense Amp
Sub Amp (C = Number of 8us Line)
107
OKI
semiconductor
MSM41256AS/RS
262144-BIT DYNAMIC RANDOM ACCESS MEMORY
< Page Mode Type>
GENERAL DESCRIPTION
The Oki MSM41256 is a fully decoded, dynamic NMOS random access memory organizad as 262144 one-bit words.
Multiplexad row and column address inputs permit the MSM41256 to be housed in a standard 16-pin DIP, Pin-outs
process, coupled with single-transistor memory storage cells, permits maximum circuit density and minimal chip
size. Dynamic circuitry is employad in the design, including the sense amplifiers.
compatible.
FEATURES
.262144 x 1 RAM, 16-pin package.
Silicongate, Double Poly NMOS, single transistor cell
Row access time,
120 ns max. (MSM41256-12AS/RS)
Cycle time,
230 ns min. (MSM41256-12AS/RS)
Low power:
385 mW active (MSM41256-12AS/RS)
360 mWactive (MSM41256-15AS/RS)
305 mWactive (MSM41256-20AS/RS)
28 mW max. standby

"Gated" 'CAS
4 ms/256 refresh cycles
operatiori
Output unlatchad at cycle and allows extendad page
Read-Modify-Write, RAS-only refresh, and Page
Mode capability
On-<:hip latches for Addresses and Data-in
On-<:hip substrate bias generator for high
performance
PIN CONFIGURATION
A,
Pin Names
WE
Ao -All
Address Inputs
RAS
A,-
CAS
Row Addr Strobe

Write Enable
Data Input
Data Output
Power (+!iV)
Ground (OV)
WE'
A.
A,'
A,'
A,'
Dout
A,
VCC
VSS
A,'
Refresh Addres.
Va:
108
Function
Oout
Din
- - - - - - - - - - - - - - -_____ DYNAMIC RAM MSM41256AS/RS _
WE
Column
Address
Buffers
Ao .... A,
Dout
Row
Address
Buffers
Word
Drivers
VCC
VSS-
Memory
Cells
Din
On chip VBB
(See Note)
Rating
Symbol
Value
Unit
VIN, VOUT
-1 to +7
Voltage on VCC supply relative to VSS
Vee
-1 to +7
Topr
o to 70
Storage temperature
T stg
-55 to +150
Po
1.0
50
mA
Power dissipation

(Respect to VSS)
Parameter
Supply Voltage
Symbol
Vr:r:
VSS
Min.
Typ.
Max.
Unit
4.5
0
5.0
0
5.5
0
V
V
VIH
2.4
6.5
VIL
-1.0
0.8
Operating
Temperature
oOe to +70 o e
109
DYNAMIC RAM MSM41256AS/RS - - - - - - - - - - - - - - - DC CHARACTERISTICS

Symbol
Parameter
OPERATING CURRENT"
MSM4125612
MSM4125615
MSM4125620
ICCl
STANDBY CURRENT
(RAS = CAS = VIH)
REFRESH CURRENT
PAGE MODE CURRENT"
(RAS = VIL, CAS cycling; tpc
Min.
Max.
Unit
70
65
60
mA
5.0
ICC2
mA
ICC3
60
55
50
mA
= min.)
MSM4125612
MSM4125615
MSM4125620
ICC4
60
55
50
mA
= min.)
MSM4125612
MSM4125615
MSM4125620
INPUT LEAKAGE CURRENT

(OV ~ VIN ~ 5.5V, all other pins not
under test = OV)
III
-10
10
J.<A
OUTPUT LEAKAGE CURRENT

(OV ~ VOUT ~ 5.5V)
ILO
-10
10
J.<A
OUTPUT LEVELS
Output high voltage (lOH = -5 mAl
Output low voltage (IOL = 4.2 mAl
Note*: ICC
IS
V
V
2.4
VOH
VOL
0.4
..
dependent on output loading and cycle rates. Specified values are obtained with the output open .
CAPACITANCE
(Ta = 25C, f = 1 MHz)
Parameter
Note: Capacitance measured with Boonton Meter.
110
Symbol
Max.
Unit
CINl
pF
CIN2
pF
COUT
pF
..
- - - - - - - - - - - - - - . . . : . - -..... DYNAMIC RAM MSM41256AS/RS

AC CHARACTERISTICS
Notes 1, 2, 3
Under Recommended
Operating conditions
MSM41256-12
Parameter
Symbol
Units
Min.
Refresh period
Max.
MSM41256-15
MSM41 256-20
Min.
Min.
Max.
Note
4
tREF
ms
tRC
ns
230
260
330
tRWC
ns
255
325
410
tpc
ns
130
145
tRAC
ns

tCAC
ns
150
200
4,6
60
75
100
5,6
tOFF
ns
40
tT
ns
50
RAS precharge time
tRP
ns
100
RAS pulse width
tRAS
ns
120
RAS hold time
tRSH
ns
60
CAS precharge time
tcp
ns
60
tCAS
ns
60
tCSH
ns
120
CAS hold time
190
120
Transition time
CAS pulse width
40
50
100
10,000
150
10,000
50
200
80
10,000
150
100
ns
25
tCRP
ns
tASR
ns
20
20
25
60
25
0
10,000
200
tRCD
time
10,000
100
60
75
50
120
75
10,000
~to RAS precharge time
RAS to CAS delay
Max.
75
30
100
tRAH
ns
tASC
ns
45
55
155
tCAH
ns
35

referenced to R AS
tAR
ns
95
120
tRCS
ns
tRCH
ns
twcs
ns
Wrote command hold time
tWCH
ns
40
45
55

referenced to RAS
twCR
ns
100
120
155
twp
ns
40
45
55
80
80
tRWL
ns
40
60
tCWL
ns
40
60
Data-in set-up time
tDS
ns
Data-in hold time
tDH
ns
40
45
55

to'RAS
tDHR
ns
100
120
155
CAS to WE delay
tCWD
ns
40
75
100
8
8
RAS to WE delay
tRWD
ns
100
150
200

referenced to RAS
tRRH
ns
20
20
25
111
DYNAMIC RAM MSM41256AS/RS . - - - - - - - - - - - - - - - RAS cycles (Examples; RAS

AC measurements assume tT = 5 ns.
VIH (Min.) and VIL (Max.) are reference levels for measuring timing of input signals. Also, transition
Assumes that tRCD < tRCD (max.).
the amount that tRCD exceeds the values shown.
Assumes that tReD < tRCD (max.)
Measured with a load circuit equ ivalent to 2 TTL loads and 100 pF.
Operation within the tRCD (max.) limit insures that tRAC (max.) can be met. tRCD (max.) is specified as a reference point only; if tRCD is greater than the specified tRCD (max.) limit, then access
twcs, tCWD and tRWD are not restrictive operating parameters. They are included in the data sheet
as electrical characteristics only; if twcs ~ twcs (min.), the cycle is an early write cycle and the aata
1) An initial pause of 100 J.LS is required after power-up followed by any 8
NOTES:
2)
3)
4)
5)
6)
7)
8)
READ CYCLE TIMING
~-------------------tRC--------------------~
.1
~-------------tRAS------------~~
VIH _ - - - , I f-o------tAR
Ir--------i
VIL -
Addresses
VIHVIL -
I
WE
DOUT
tRcsH
VIH-~
VIL-
VOHVOL-
!---tCAC
1-
tRAC
OPEN
tOFF
Valid Data
~"H", "L"
112
= Don't Care
- - - - - - - - - - - - - - - -...... DYNAMIC RAM MSM41256AS/RS
WRITE CYCLE TIMING

(EARLY WRITE)
RAS
vlH VIL -
CAS
VIH VIL -
Addresses
VIH VIL -
tRSH
______~~==~~==~--r---tCAS----~k_~----~~
WE
VIH - /j
VIL -
DIN
VIH VIL -
DOUT
VOHVOL-
~------tDHR------~
OPEN
~
"H", "L" = Don't Care
READWRITE/READMODIFYWRITE CYCLE
113
DYNAMIC RAM MSM41256AS/RS
.1----------------

(CAS: VIH,WE' & DIN: Don't care)
-RAS
VIHVIL-
~:~ _~
~RAH~
tASR
Addresses
RowAddress
VOH DOUT
OPEN
VOL -
~---------tRAS-----------..,
VIHAdresses V I L -
~"H","L"=Don't Care
114
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ DYNAMIC RAM MSM41256AS/RS _
RAS
VIH VIL -
CAS
Addresses
WE
vlH VIL -
DIN
VIH VIL ~ "H", "L" = Don't Care
CAS
VIH - --+-4----.1-.
VIL -
Addresses
DIN VIH-
V I L - """"~;":"':''''""''''J.f
115
DYNAMIC RAM MSM41256AS/RS . - - - - - - - - - - - - - - - -
HIDDEN REFRESH
Addresses
VIH-///,
vlL -""//.<.t..!..I./''7'-''r..t..Lt.lJ
~tCAC
i---tRAC_
V OH~----------______
V_a_lid_D_a_ta_ _ _ __
DOUT VOL _ - - - OPEN
DESCRIPTION
Address Inputs:
A total of eighteen bi nary input address bits is required to decode any 1 of 262144 storage cell locations
within the MSM41256 Nine row-address bits are established on the Input pins (Ao - A.) and latched with
the Row Address Strobe (RAS). The Nine columnaddress bits are established on the input pins and
input addresses must be stable on or before the falling
edge of RAS, CAS is internally inhibited (or "gated")
Address Hold Time (tRAH) specification has been
satisfied and the address inputs have been changed
from row-addresses to column-addresses.
Write Enable:
The reed mode or write mode is selected with the WE
input. A logic high (1) on Wt dictates read mode;
Data Input:
reed-write cycle. The last falling edge of WE or CAS is
DIN is strobed by CAS, and the setup and hold times
are referenced to CAS. In a reedwrite cycle, WE will
be delayed until CAS has made its negative transition.
Data Output:
116
same polarity as data-in. The output is in a high impedance state until CAS is brought low. I n a read cycle,
after tCAC from transition of ~ when the transition
Page Mode:
into the MSM41256 while maintaining RAg at a logic
dissipated by the negative gOing edge of RAS is saved.
is eliminated.
Refresh:
by performing a memory cycle at each of the 256 rowaddresses (Ao - A7) at least every four milliseconds.
During refresh, either VIL or VIH is permitted for A B
RAg only refresh avoids any' output during refresh
row-addresses with RAS will cause all bits in each row
Hidden Refresh:
RAg ONLY REFRESH CYCLE may take place while
- - - - - - - - - - - - - - - -..... DYNAMIC RAM MSM41256AS/RS

(Relative value) vs. VCC
Ta
>

(Relative value) vs. Ta
= 25C
VCC
1.4
G
'in
N
1.2
1.2
t:'"
1 .1
L!)
II
= 5.0V
2:
IE
'"
1.0
2:
u
!F
0.8
0.6
4.0
4.5
5.0
r---
5.5
1.0
t.
!F
0.9
0.8
6.0
,,/
./
70
VCC [V]

(Relative value) vs. VCC
Ta
>
L!)
II

(Relative value) vs. Ta
VCC = 5.0V
tRCD; max.
25C
tRCD; max.
1.4
u
u
2:
u
1.2
1.0
~
u
t-...
2:
'"
i:?
4.5
1.2
t:'"
1.1
/"
'-...
5.0
r---
5.5
cc
1.0
t:
u
i:?
0.9
0.8
6.0
~V
0
rOc]
ICCl vs. Cycle rate

60
';{
';{
E
.,
70
50
Ta
ICCl vs. VCC
1/
25
VCC [V]
c:0
0.8
0.6
4.0
G
'in
N
Ta = 25C
tRAS = 160 nS
VCC
50
.s
c:0
.,
40
= 5.5V
I
= 5.0V
= 4.5V
40
:;;'"
Q)
c.
c.
.s
.s
!:l
30
!:l
10
4.5
5.0
VCC [V]
5.5
6.0
117
DYNAMIC RAM MSM41256AS/RS . - - - - - - - - - - - - - - - ICCl vs. Ta

60
:t
S
c:o
VCC = 5.5V
tRC = 260 nS
Ta = 25C
VIH; max.
:t
55
......
.;;
.,e!
ICC2 vs. VCC

4.0
50
r-- r--
3.5
>:
-9
"0
c:
Co
.tl
..
3.0
!:?
45
40
2.5
---
2.0
4.0
70
/'
4.5
5.0
5.5
6.0
VCC [V]
ICC2 vs. Ta
4.0
:t
S
>:
c:
co
~
3.0
E
N
:t
3.5
-9
"0
ICC3 vs. VCC

60
VCC = 5.5V
VIH; max
50
./
0;
'" ~
........
2.5
2.0
Ta = 25C
tRC = 260 nS
~ .......
U
>
u
40
-&
~
~
30
... /
!:?
70
20
4.0
4.5
5.0
5.5
6.0
VCC [V]
ICC4 vs. VCC
ICC3 vs. Ta
50
:t
S
60
VCC = 5.5V
tRC = 260 nS
45
0;
>
u
-&
40
r- r--
35
---
50
0;
U
>
u
40
S
:--
.,
'"co
2-
30
/
...,. /
,/"
I--"""
<T
!:?
!:?
30
:t
Ta = 25C
tpc = 145 nS
70
20
4.0
4.5
5.0
VCC [V]
118
5.5
6.0
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ DYNAMIC RAM MSM41256AS/RS _

ICC4 vs. Ta
50
.s
45
I"-..
(i;
>-
"en
<1>
VCC = 5.5V
tpc = 145 nS
40
..............
'"
Eo
".
!:?
r-- t-
35
30
25
50
70
Ta lOC]
Address, Data Input vs. Ta
Address, Data Input vs. Ta

2.5
2.5
VCC
VCC = 5.5V
= 4.5V
2.0
2.0
VIH min.
~
>
<1>
--'
VIH min.
a;
T""""
a;
>
1.5
<1>
1.5
--'
:;
:J
C.
VIL max.
c.
VIL max.
1.0
1.0
0.5
0.5
0
50
25
70
25
Clock I ntJut vs. Ta
70
Clock Input vs. Ta
2.5
2.5
VCC
VCC = 5.5V
= 4.5V
2.0
2.0
VIH min.
~
a;
a;
VIH min.
>
<1>
1.5
--'
>
<1>
--' 1.5
:;
:;
c.
c.
VIL1max.- f-
1.0
0.5
50
Ta lOC]
Ta lOC]
25
Ta lOC]
50
70
VIL max.
1.0
0.5
25
50
70
Ta lOC]
119
DYNAMIC RAM MSM41256AS/RS . - . . . . : . - - - - - - - - - - -_ _ __

Address, Data Input vs. Vcc
2.5
Clock Input vs. VCC

2.5.---.......
--..,--....:...0--...,
I
Ta = 25C
2.0
2.01---+--+----1---1
G
a;
>
Q)
1.5
oJ
...::>
10-
--
VIHm~
a;
1.5 I--:::;.,..jo~~+----I---I
VIL max .
c.
.:
1.0
1.0F---+--
4.0
5.0
4.5
5.5
6.0
4.0
5.0
4.5
5.5
VCC [V]
VCC [V]
TYPICAL CURRENT WAVEFORMS

RAS/CAS CYCLE
RAS
CAS
l-
LONG RAS/CAS CYCLE
... ....
VCC =5.5V
Ta = 25C
RAS ONLY CYCLE
\1-
PAGE MODE CYCLE
.....
\1-
.s
lr
200
150
100
50
0
~
~I--
j,- ~
6.0
... IA
1
Iv I-- In: 1-1" l"-I-' u-
1\
.....
1&
r\. t-
...... 1---1 I\... l - \. P
I-
I - 1-1
tor ~ r---
\~
100 nS/Div
120
_ _ _ _ _ _ _ _--:..__________ DYNAMIC RAM MSM41256AS/RS _

MSM41256 Bit Map (Physical-Decimal)
[A8 column "L"I
255
255
511
255
254
255
510
255
511 510
254 254
255 254
254 254
255
253
511
253
254
253
510
253
511 51Ci
252 252
255 254
252 252
255 254
251 251
'129Ua
1
0
255 255
258 257
~~
~
258 ~
255 255
385 384
255
254 254
~~
254 254
129 128
253 253
t-;2e
rm
~~
384
253
252 252
129 128
~
~
129 128
251 251
~0 ~1
254 254
1
0
253 253
/
254
511
'129i2a
510
511
385 384
511 511
511 510
510 510
385 384
510 510
255 254
510 510
129 128
510 510
126 127
255 256
382 383
255 255
255
511
511
511
382 383
254 254
126 127
254 254
Pin 16
[A8 column' "H"I
255 254
511 511
126
253
382
253
127
253
509 509
129 129
508 509
258 257
253 253
383
253
511 510
509 509
385 384
509 509
258 257
252 252
1
0
252 252
1
0
251 251
382 383
252 252
126 127
252 252
126 127
251 251
511 510
508 508
385
508
129
509
129
507
2s5 2s4
~~
255 254
~ 2!!Z
1
0
511 611
258 257
511 511
Us 1"127
~
~
382 383
258 257
510 510
1
0
510 510
382 383
510 510
511 511
126 127
~
509 509
0
1
509 509
258 257
509 509
258 257
508 508
0
1
508 509
384
508
128
508
128
507
382 383
~
382 ~
508
126
508
126
507
0
1
507 507
508
127
508
127
507
(Column)
t-;2e
rm
1
4
126 127
4
4
255 254
260 260
0
3
1
3
126 127
3
3
255 254
259 259
258 257
3
3
382 383
3
3
382 383
2
2
126 127
2
2
126 127
1
1
511 510
259 259
511 510
258 258
258 257
2
2
0
1
2
2
o 1
1
1
511 510
385384
256 257
382 383
51~
o 0
~~
2~0 25~0
38~0 38~0
255 254
255 254
3
3
511 510
3
3
511 510
2
2
255 254
2
2
255 254
1
1
51:
I;2e ~
3
~~
r2-r2385 384
r--2
~
129 128
2
t-;2e ~
1
~r---.!!.
255 254
129 128
0000
nlTIJ
-~
Address
(255-1281;/'
,\
126 127
0
1
259 259
126 127
259 259
385 384
259 259
258 257
259 259
382 383
259 259
385
258
129
258
258 257
258 258
0
1
258 258
1
0
257 257
382 383
258 258
126 127
258 258
258 257
257 257
382 383
257 257
258 257
258 256
0
1
258 256
382
256
126
258
384
258
128
258
129 128
257 257
511 510
257 257
385 384
257 257
511
258
255
258
385
256
129
258
510
258
254
258
012
Refresh Addres:
(O~ 1271
r5rn
(Negative)
I'
384
256
128
258
Refresh Address - ;
260 260
126 127
257 257
Din
(Positive)
(O~
D.
383
258
127
258
r:::=:J
Refresh Addre..
(255-1281
~:
1
0
260 260
I I I [IT LD 4} I I I
"'-
012
~~
0
1
126 127
0000
---J /
Din
(Positive)
255 254
258 258
255 254
129
260
128
259
129
260
129
259
0;;
1271
rnn
(Negative)
Sense Amp.
: Sub Amp.
121
OKI
semiconductor
MSM41256JS
< Page
Mode Type>
GENERAL DESCRIPTION
The Oki MSM41256 is a fully decoded, dynamic NMOS random access memory organized as 262144 one-bit words.
Multiplexed row and column address inputs permit the MSM41256 to be housed in a standard 18pin PLCC, Pinouts
process, coupled with singletransistor memory storage cells, permits maximum circuit density and minimal chip
compatible.
FEATURES
.262144 x 1 RAM, 18-pin PLCCpackage
Silicon-gate, Double Poly NMOS, single transistor cell
Row access time,

120 nsmax. (MSM41256-12JS)
150 ns max. (MSM41256-15JS)
Cycle time,
230 ns min. (MSM41256-12JS)
260 ns min. (MSM4125615JS)
Low power: 385 mW/360 mW active
28 mW max. standby

"Gated" CAS
4 ms/256 refresh cycles
Common 110 capabil ity using "Early Write"
operatio,;
Output unlatched at cycle and allows extended page
Read-Modify-Write, RAS-only refresh, and Page
Mode capability
performance
PIN CONFIGURATION
Din A, VSS CAS
2
1 1817
Pin Names
Dout
WE
WE"
Write Enable
A~
Din
A:
Dout
VCC
VSS
Data Input
Data Output
Power (+5V)
Ground (OV)
NC
No Connection
NC
1Vee
122
NC
Row Addr.s. Strobe

Column Addres. Strobe
A~
A* A*
7
Function
Address Inputs
RAS
CAS
RAS
A*
Ao - A"
Refresh Addr.ss
- - - - - - - - - - - - - - - - -_____ DYNAMIC RAM MSM41256JS _
WE
eolumn
Address
Buffers
Ao -A,
Dout
Row
Address
Butiers
Vee
VSS-
Word
Driv
ers
Memory
Cells
Din
On chip VBB
(See Notel
Symbol
Value
VIN. VOUT
-1 to +7
Vee
-1 to +7
Rating
Unit
T opr
o to 70
Storage temperatu re
T stg
-55 to +150
Po
1.0
50
mA
Power dissipation
Note: Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. Functional opera
tion should be restricted to the conditions as detailed in the operational sections of this data sloeet. Exposure

(Respect to VSSI
Parameter
Supply Voltage
Symbol
Vee
VSS
Min.
Typ.
Max.
Unit
4.5
0
5.0
0
5.5
0
V
V
Input High Voltage. all inputs
VIH
2.4
6.5
VIL
-1.0
0.8
Operating
Temperatu re
ooe to +70oe
123
DYNAMIC RAMMSM41256JS - - - - - - - - - - - - - - - - DC CHARACTERISTICS

Parameter
OPERATING CURRENT"
Symbol
MSM41256-12
PAGE MODE CURRENT"

(RAS = VIL, CAS cycling; tpc
Max.
Unit
70
ICC1
MSM41256-15
STANDBY CURRENT
(RAS = CAS = VIH)
REFRESH CURRENT
Min.
65
mA
5.0
ICC2
MSM41256-12
mA
60
mA
ICC3
= min.!
MSM41256-15
55
MSM41256-12
60
mA
ICC4
= min.)
MSM41256-15
55
INPUT lEAKAGE CURRENT

(OV ~ V IN ~ 5.5V, all other pins not
under test = OV)
III
-10
10
jlA
OUTPUT lEAKAGECURRENT
(OV ~ VOUT ~ 5.5V)
ILO
-10
10
jlA
OUTPUT LEVELS
VOH
VOL
2.4
V
V
0.4
Note": ICC is dependent on output loading and cycle rates. Specified values are obtained with the output open.
CAPACITANCE
(T a
= 25 C, f = 1 MHz)
Parameter
Input Capacitance (Ao - AI' DIN)
Note: Capacitance measured with Boonton Meter.
124
Symbol
Max.
Unit
CIN1
pF
CIN2
pF
COUT
pF
- - - - - - - - - - - - - - - - -_____ DYNAMIC RAM MSM41256JS _
AC CHARACTERISTICS
Notes 1, 2, 3
Under Recommended
Operating conditions
MSM41256-12
Parameter
Symbol
Note
Min.
Refresh period
tREF
MSM41256-15
Units
Max.
Min.
ms
Max.
4
tRC
ns
230
tRWC
ns
255
tpc
ns
130
tRAC
ns
120
150
4,6
tCAC
ns
60
75
5,6
tOFF
ns
Transition time
tT
RAS precharge time
tRP
RAS pulse width
tRAS
-
ns
120
RAS hold time
tRSH
ns
60
tcp
ns
60
60
260
325
145
40
ns
50
ns
100
40
50
100
10,000
150
10,000
~~
-~
CAS precharge time
CAS pulse width
f---=---tCAS
ns
CAS hold time
tCSH
ns
120
tRCD
ns
25
tCRP
ns
CAS to
RAS precharge time
75
60
10,000
75
60
25
75
tASR
ns
tRAH
ns
20
20
tASC
ns
0
45
10,000
150
tCAH
ns
35

referenced to R AS
tAR
ns
95
120
tRCS
ns
tRCH
ns
twcs
ns
Write command hold tIme
tWCH
ns
40
45

referenced to RAS
tWCR
ns
100
120
twp
ns
40
45
tRWL
ns
40
60
tCWL
ns
40
60
Data-in set-up time
tDS
ns
Data-in hold time
tDH
ns
40
45

to RAS
tDHR
ns
100
120
CAS to WE delay
tCWD
ns
40
75
RAS to WE delay
tRWD
ns
100
150

referenced to R AS
tRRH
ns
20
20
125
_ DYNAMIC RAM MSM41256JS _ . . . . _ - - - - - - - - - - - - - - - - NOTES:
11
21
31
41
51
61
71
81
An initial pause of 1001's is required after power-up followed by any 8 RAS" cycles (Examples; RAS
only I before proper device operation is achieved_
AC measurements assume tT = 5 ns.
VIH (Min-l and VIL (Max.1 are reference levels for measuring timing of input signals. Also, transition
Assumes that tRCD < tRCD (max.1.
the amount that tRCD exceads the values shown.
Assumes that tRCD < tRCD (max-l
Measured with a load circuit equivalent to 2 TTL loads and 100pF.
Operation within the tRCD (max-l limit insures that tRAC (max-l can be met. tRCD (max-l is specified as a reference point only; if tRCD is greater than the specified tRCD (max-l limit, then access
twcs, tCWD and tRWD are not restrictive operating parameters. They are included in the data sheet
as electrical characteristics only; if twcs ~ twcs (min-l, the cycle is an early write cycle and the oata
out pin will remain open circuit (high impedance I throughout the entire cycle; if tCWD ~ tCWD
(min-l and tRWD > tRWD (min-l the cycle is read-write cycle and the data out will contain data read
out (at access timel is indeterminate.
READ CYCLE TIMING
tRC
tRAS--
AAS
tAR
VIHVIL -
"\
tRSH
CAS
tCAS
VIH VIL -
tCSHVIHAddresses VI L -
tRCS~
VIH-~
VIL -
VOHDOUT
VOL-
!---tCAC
1~~---------tRAC--~------~
OPEN
tOFF
r-V-a-lid-D-a-ta-i>------
~"H", "L"
126
= Don't Care
- - - - - - - - - - - - - - - - -__ DYNAMIC RAM 'MSM41256JS _
WRITE CYCLE TIMING

(EARLY WRITE)
RAS
VIH VIL tRSH
CAS
VIH VIL -
Addresses
VIH VIL -
WE
VIH VIL -
DIN
VIH VIL -
DOUT
VOHVOL-
_ _ _--4-1==~~f=~-I-tCAS------i
-+--+_ _-'-__.
:0
r------tDHR------~
OPEN
READWRITE/READMODIFY-WRITE CYCLE
127
DYNAMIC RAM MSM41256JS
.I-------------~---

(CAS: VIH,VlE" & DIN: Don't care)
--
RAS
VIH
VIL-
~:~ _~
t~AH~
tASR
Addresses
RowAddress
VOH DOUT
OPEN
VOL -
~-----------tRAS-----------~
~"H","L"= Don't Care
128
- - - - - - - - - - - - - - - - - - - - - DYNAMIC RAM, MSM41256JS _
RAS
VIHVIL -
CAS
VIH - --H---.<i..
VIL -
Addresses
129
DYNAMIC RAM MSM41256JS - - - - - - - - - - - - - - - - - HIDDEN REFRESH
Addresses
DOUT
DESCRIPTION
Address Inputs:
A total of eighteen binary input address bits are required to decode any 1 of 262144 storage cell locations
with in the MSM41256 Nine row-address bits are established on the input pins (Ao - A,) and latched with
the Row Address Strobe (RAS). The Nine columnaddress bits are established on the input pins and
input addresses must be stable on or before the falling
edge of RAS, CAS is internally inhibited (or "gated")
Address Hold Time (tRAH) specification has been
satisfied and the address inputs have been changed
from row-addresses to column-addresses.
Write Enable:
Data Input:
be delayed until CAS has made its negative transition.
Data Output:
130
same polarity as data-in. T/1e output is in a high impedance state until CAS is brought low. In a read cycle,
Or read-write cycle, the output is valid after tRAC from
after tCAC from transition of CAS when the transition
Page Mode:
dissipated by the negative gOing edge of RAS is saved.
is eliminated.
Refresh:
Refresh of the dynamic memory cells is accompl ished
by performing a memory cycle at each of the 256 rowaddresses (Ao - A,) at least every four milliseconds.
FfAS only refresh avoids any' output during refresh
row-addresses with FfAS will cause all bits in each row
to be refreshed. Further RASonly refresh results in a
Hidden Refresh:
FfAS ONLY REFRESH CYCLE may take place while
------------------11. DYNAMIC RAM MSM41256JS

/
255 254
255 255
129 128
255 255
511 510
255 255
385 384
255 255
511 510
254 254
385 384
254 254
255 254
254 254
129 128
254 254
255 254
253 253
129 128
253 253
[A8 column' "L")
1
0
511 511
126 127
511 511
385 384
511 511
256 257
511 511
382 383
511 511
385 384
510 510
256 257
510 510
382 383
510 510
255 254
510 510
129 128
510 510
1
0
510 510
126 127
510 510
255 254
509 509
129 128
509 509
1
0
509 509
126 127
509 509
0
1
255 255
126 127
255 255
255 254
511 511
256 257
382 383
255 255
511 510
511 511
382 383
254 254
511 510
510 510
254 254
126 127
254 254
0
1
253 253
126 127
253 253
~~
~0 ~1
~ 257
[AB column - "Hill
129 128
211. ~
511 510
253 253
129 128
253 253
253 253
382 383
253 253
511 510
509 509
385 384
509 509
256 257
509 509
382 383
509 509
511 510
252 252
385 384
252 252
256 257
252 252
382 383
252 252
511 510
508 508
385 384
508 508
382 383
508 508
255 254
252 252
129 128
252 252
1
0
252 252
126 127
252 252
255 254
508 508
129 128
508 508
256 257
508 508
1
0
508 508
255 254
251 251
129 128
251 251
1
0
251 251
126 127
251 251
255 254
129 128
507 507
1
0
507 507
126 127
507 507
~~
126 127
508 508
(Column)
255 254
4
4
255 254
3
3
511 510
3
3
129 128
4
4
129 ~
3
385 384
511 510
2
2
~2 3842
.2.
0
4
1
4
126 127
4
4
255 254
260 260
129 128
260 260
I
0
260 260
126 127
260 260
0
3
1
3
126 127
3
3
255 254
259 259
129 128
259 259
1
0
259 259
126 127
259 259
256 257
3
3
382 383
3
3
511 510
259 259
385 384
259 259
256 257
259 259
382 383
259 259
256 257
2
2
382 383
2
2
511 510
258 258
385 384
258 258
256 257
258 258
382 383
258 258
255 254
2
2
129 128
2
2
0
2
1
2
126 127
2
2
255 254
258 258
129 128
258 258
1
0
258 258
126 127
258 258
255 254
1
1
129 128
I
1
0
1
1
1
126 127
1
1
255 254
257 257
129 128
257 257
1
0
257 257
126 127
257 257
511 510
1
1
385 384
1
1
256 257
1
1
382 383
1
1
511 510
257 257
385 384
257 257
256 257
257 257
382 383
257 257
511 510
0
0
385 384
0
0
256 257
0
0
382 383
0
0
511 510
256 256
385 384
256 256
256 257
256 256
382 383
256 256
255 254
0
0
129 128
0
0
126 127
0
0
255 254
256 256
129 128
256 256
0
1
256 256
1. 1!!
q;IP-=J4}\\
1255~
0
0
Din
(Positive)
A
B
Cell
Sub Amp.
D"
012
A '" Row Address (Decimal)

B '" Column Address (Decimal)
126 127
I I I L::J
I I I o::::rilJ --0- ~
Refresh Addres:
1281
10-1271
-Din
(Negative)
Refresh Address
1255~
Refresh Address
(0-1271
1281
Din
(Positive)
~:
D"
-0
34
'[)I'i1
(Negative)
Sense Amp.
131
OKI
semiconductor
MSM41 256AAS/RS
262,144-BIT DYNAMIC RANDOM ACCESS MEMORY <Page Mode Type>
GENERAL DESCRIPTION
The Oki MSM41256A is a fully decoded, dynamic NMOS random access memory organized as
262144 one-bit words. The design is optimized for high-speed, high performance applications such
as mainframe memory, buffer memory, peripheral storage and environments where low power.dissipation and compact layout is required.
Multiplexed row and column address inputs permit the MSM41256A to be housed in a standard
16 pin DIP. Pin-outs conform to the JEDEC approved pin out. Additionally, the MSM41256A offers
new functional enhancements that make it more versatile than previous dynamic RAMs.
"CAS-before-RAS" refresh provides an on-Chip refresh capability.
The MSM41256A is fabricated using silicon gate NMOS and Oki's advanced VLSI Polysilicon
process. This process, coupled with single-transistor memory storage cells, permits maximum circuit
density and minimum chip size. Dynamic circuitry is employed in the design, including the sense
amplifiers.
Clock timing requirements are noncritical, and power supply tolerance is very wide. All inputs and
output are TTL compatible.
FEATURES
262,144 x 1 RAM, 16 pin package

Silicon-gate, Double Poly NMOS, single
transistor cell
Row access time:
100 ns max (MSM41256A-1 OASIRS)
120 ns max (MSM41256A-12AS/RS)
150 ns max (MSM41256A-15AS/RS)
Cycle time:
200 ns min (MSM41256A-1 OAS/RS)
220 ns min (MSM41256A-12AS/RS)
260 ns min (MSM41256A-15AS/RS)
Low power:
385 mW active, 28 mW max standby

"Gated" CAS
operation
Output unlatched at cycle end allows
extended page boundary and
two-dimensional chip select
Read-Modify-Write, RAS-only refresh,
capability
On-Chip substrate bias generator for high
performance
CAS-before-RAS refresh capability
"Page Mode" capability
PIN CONFIGURATION (TOP VIEW)
As
DIN
WE
VSS
Pin Names
CAS
AD-A.
Address Inputs
RAS
Row Address Strobe
CAS
Col umn Address Strobe
WE
Write Enable
DIN
Data Input
DOUT
Data Output
Dour
RAS
A,'
Ao'
A,'
A,'
A,'
A,'
A,'
Function
Vec
PowerSupply (+5V)
VSS
Ground (OV)
, Refresh Address
132
- - - - - - - - - - - - - - - - . DYNAMIC RAM MSM41256AAS/RS

Ao-As
~:~ -------------~~~~
1 ____________-"
L.
OnchipVSB
ELECTRICAL CHARACTERISTICS
ABSOLUTE MAXIMUM RATINGS (See Note)
Rating
Symbol
Value
Unit
VIN. VOUT
-1 to +7
Vee
-1 to +7
Topr
Oto 70
Storage temperature
Tstg
-55 to +150
PD
1.0
50
mA
Power dissipation
Note: Parmanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded.
Functional operation should be restricted to the conditions as detailed in the operational sections of this data sheet. Exposure to absolute maximum rating conditions for extended periods
may affect device reliability.
133
DYNAMIC RAM MSM41256AAS/RS . - - - - - - - - - - - - - - - RECOMMENDED OPERATING CONDITIONS

(Referenced to VSS)
Min.
Typ.
Max.
Unit
Vce
4.5
5.0
5.5
VSS
VIH
2.4
6.5
VIL
-1.0
0.8
Parameter
Symbol
Supply Voltage
Operating
Temperature
OC to +70C
DC CHARACTERISTICS
Parameter
Symbol
Min.
Max.
Unit
OPERATING CURRENT
ICC1
70
rnA
STANDBY CURRENT
(RAS =CAS =VIH)
ICC2
5.0
rnA
REFRESH CURRENT 1
(RAS cycling, CAS = VIH; tRC = min.)
ICC3
60
rnA
PAGE MODE CURRENT

(RAS = VIL, CAS cycling; tpc = min.)
ICC4
40
rnA
REFRESH CURRENT 2
(CAS before RAS; tRC = min.)
ICC5
65
rnA

(OV :0:::: VIN :0:::: 5.5V, all other pins not
under test = OV)
(Data out is disabled, OV :0:::: VOUT
:0::::
OUTPUT LEVELS
Output high voltage UOH = -5 rnA)
Output low voltage UOL = 4.2 rnA)
5.5V)
III
-10
10
,..A
ILO
-10
10
,..A
VOH
VOL
2.4
0.4
V
V
Notes
Note*: ICC is dependent on output loading and cycle rates. Specified values are obtained with the
output open.
134
_ _ _ _ _ _ _ _---..:.._ _ _ _ _ _ _1. DYNAMIC RAM MSM41256AAS/RS

CAPACITANCE
(Ta = 25C, f = 1 MHz)
Symbol
Typ.
Max.
Unit
Input capacitance (Ao - As, DIN)
CIN1
pF
Input capacitance (RAS, CAS, WE)
CIN2
10
pF
Output capacitance (DOUT)
COUT
pF
Parameter
135
DYNAMIC RAM MSM41256AAS/RS . - - - - - - - - - - - - - - AC CHARACTERISTICS

Parameter
Symbol
Unit
Note 1,2,3
MSM41256A- MSM41256A- MSM41256A10

12
15
Min.
Max.
Min.
Max.
Min.
Notes
Max.
Refresh period
tREF
ms
Random read or write

cycle time
tRC
ns
200
220
260
tRWC
ns
200
220
260
tRAC
ns
100
120
150
4,6
tCAC
ns
50
60
75
5,6
Output buffer turn-off

delay
tOFF
ns
Transition time
tT
ns
RAS precharge time
tRP
ns
85
RAS pulse width
tRAS
ns
105
RAS hold time
tRSH
ns
55
CAS pulse width
tCAS
ns
55
CAS hold time
tCSH
ns
105
tRCD
ns
25
CAS to RAS set-up time
tCRS
ns
20
20
20
Row address set-up

time
tASR
ns
Row address hold time
tRAH
ns
15
15
15
Column address set-up

time
tASC
ns
Column address hold

time
tCAH
ns
20
20
25
Read command set-up

time
tRCS
ns
Read command hold

time referenced to CAS
tRCH
ns
Read command hold

time referenced to RAS
tRRH
ns
20
20
20
Write command set-up

time
twcs
ns
136
30
50
30
3
50
120
1OILS
60
1 OILS
60
25
30
3
50
150
1 OILS
75
1OILS
120
50
100
90
1 OILS
75
1OILS
150
60
25
75
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ DYNAMIC RAM MSM41256AAS/RS

AC CHARACTERISTICS (Continued)
Parameter
Symbol
Unit
MSM41256A- MSM41256A- MSM41256A10

12
15
Min.
Max.
Min.
Max.
Min.
Notes
Max.
Write command pulse

width
twp
ns
15
20
25
Write command hold

time
tWCH
ns
15
20
25
Write command to
RAS lead time
tRWL
ns
35
40
45
Write command to
CAS lead time
tCWL
ns
35
40
45
Data-in set-up time
tos
ns
Data-in hold time
tOH
ns
20
20
25
CAS to WE delay time
tcwo
ns
15
20
25
Refresh set-up time for

CAS referenced to RAS
tFCS
ns
20
25
30
Refresh hold time for

tFCH
ns
20
25
30
CAS precharge time

(C before R cycle)
tCPR
ns
20
25
30
RAS precharge to
CAS active time
tRPC
ns
20
20
20
Page mode cycle

time
tpc
ns
100
120
150
Page mode read

write cycle time
tPRWC
ns
100
120
150
Page mode CAS

precharge time
tcp
ns
40
50
65
Refresh counter test

cycle time
tRTC
ns
340
375
430
10

RAS pulse width
tTRAS
ns
230

CAS precharge time
tCPT
ns
50
1OILS
265
60
1OIL
320
70
1OILS
10
10
137
DYNAMIC RAM MSM41256AAS/RS . - - - - - - - - - - - - - - Notes:
An initial pause of 100 JJ.s is required after power-up followed by any 8 RAS cycles
(Example: RAS only) before proper device operation is achieved.
2 The AC measurements assume tT = 5 ns

3 VIH (Min.) and VIL (Max.) are reference levels for measuring of input signals. Also transition times are measured between VIH and VIL.
4 Assumes that tRCD ~ tRCD (Max.). If tRCD is greater than the maximum recommended
value shown in this table, tRAC will increase by the amount that tRCD exceeds the value
shown.
5 Assumes that tRCD ~ tRCD (Max.).
6 Measured with a load circuit equivalent to 2TTL loads and 100 pF.
7 Operation within the tRCD (Max.) limit insures that tRAC (Max.) can be met. tRCD (Max.)
is specified as a reference point only; if tRCD is greater than the specified tRCD (Max.)
limit, then access time is controlled exclusively by tCAC.
8 twcs and tCWD are not restrictive operating parameters. They are included in the data
sheet as electrical charcteristics only; if twcs ~ twcs (min.), the cycle is an early write
cycle and the data out pin will remain open circuit (high impedance) throughout the
entire cycle; if tCWD ~ tCWD (min.), the cycle is read-write cycle and the data out will
contain data read from the selected cell; if neither of the above sets of conditions is
satisfied the condition of the data out (at access time) is indeterminate.
9 Page mode cycle.
10 CAS before RAS Refresh Counter Test Cycle only.
138
- - - - - - - - - - - - - - - . DYNAMIC RAM MSM41256AAS/RS
READ CYCLE
RAS
VIHVIL-
CAS
VIHVIL-
Addresses
WE
vIHVIL-
VIHVIL-
VOHDOUT
VOL-
~ Don't Care
WRITE CYCLE (EARLY WRITE)
RAS
CAS
Addresses
VIHvIL-
VIHVIL-
VIHVIL-
WE
VIHVIL-
DIN
vIHVIL-
DOUT
VOHVOL-
OPEN
I
~
Don'tCare
139
DYNAMIC RAM MSM41256AAS/RS
.1---------------
READ/WRITE/READ-MODIFY -WRITE CYCLE
~---------------------tRWC--------------------~
Don'tears
~-----------------tRAS--------------------~
VIHAdresses VI L - ,///~"1.",~ .. It\{/4I'"
~"H"."L"~Dont CarE
140
~----------------tRAS----------------~
RAS
VIHVIL -
Addresses Vv I H - 'lAJ'ROiv'U;',\J
IL'~~~'~~"Ul~~~~~~~~
~"H", "L"
= Don't Care

tRAS--------------~--~11~
RAS
VIH_
VIL_
CAS
VIH_
VIL_
'RSH=J
L""1 '--
.,..,..,.,'7t"n777'l""""'' '
V I HVIL_ """'"'"'-f"-'-"'-'-'-'-'-'-'-'-'
DOUT VOH- _____

VOL-
~ "H" , "L" = Don't Care
141
DYNAMIC RAM MSM41256AAS/RS . , - - - - - - - - - - - - - - -
RAS ONLY REFRESH CYCLE
NOTE: CAS
VOH- _ _ _ _ _ _ _ _ _ _ _-11
DOUT
= VIH, WE, DIN = Don't care
OPEN
VOL-
~ Don't Care
CAS-BEFORE-RAS REFRESH CYCLE
NOTE: Address, WE, DIN
RAS
VIH VIL -
CAS
VIHVIL-
VOH-
DOUT
VOL-
f~"
~--------~I
OPEN
----------
~I
142
= Don't care
Don'tCare
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ DYNAMIC RAM MSM41256AAS/RS
HIDDEN REFRESH CYCLE
VIH _
----..L I - - - - t . , " " - - - _ J..---.,J
,..>---- t"Ae'------l
VIL -
V IH -
='777'm......-!-i---'II""\.
VIL -
Addresses
WE (Read)
DOUT
WE
VOH- __________
VOL-
V IH-
(Read-Write) VIL -
4-~----~--------~~~~---------1~----
7T>777,..,..,.,,.,..,.,....,,.,777do-------..!
......""''"'''"''''''''~
~ Don't Care
CAS-BEFORE-RAS REFRESH COUNTER TEST CYCLE
tRTe
RAS
VIHVIL -
CAS
VIHVIL-
Addresses
VIHVIL-
vIH-
WE (Read) VIL-
VOHDOUT
WE (Write)
DIN
vOL-
VIHVILVIHVIL -
~ Don't Care
143
DYNAMIC RAM MSM41256AAS/RS
.1---------------
FUNCTIONAL DESCRIPTION
Simple Timing Requirements:
The MSM41256A has the circuit considerations for easy operational timing requirements
for high speed access time operations. The
MSM41256A can operate under the condition of
tRCD (max) = tCAC which provides an optimal
time space for address multiplexing. In addition,
the MSM41 256A has the minimal hold time of
Address (tCAH), WE (tWCH) and DIN (tDH). And
the MSM41256A can commit better memory
system through-put during operations in an inter~
leaved system. Furthermore, Oki has made
timing requirements referenced to RAS nonrestrictive and deleted from the data sheet,
which includes tAR, tWCR, tDHR and tRWD
Therefore, the hold times of the Column Address
DIN and WE as well as tCWD (CAS to WE Delay)
are not restricted by tRCD.
Fast Read- While-Write Cycle:
The MSM41 256A has the fast read while
write cycle which is achieved by excellent control of the three-state output buffer in addition
to the simplified timings described in the previous section. The output buffer is controlled
~the state of WE when CAS goes low. When
WE is low during CAS transition to low, the
MSM41256A goes to early write mode where
the output becomes floating and common liD
bus can be used on the system level. Whereas,
when WE goes low after tCWD following CAS
transition to low, the MSM41256A goes to
delayed write mode where the Gutput contains
the data from the cell selected and the data from
DIN is written into the cell selected. Therefore,
very fast read write cycle becomes available.
Address Inputs:
A total of eighteen binary input address bits
are required to decode any 1 of 262,144 storage
cell location within the MSM41256A. Nine rowaddress bits are established on the input pins
(Ao through AS> and latched with the Row Address Strobe (RAS). Then nine column address
bits are established on the input pins and
latched with the Column Address Strobe (CAS).
All input addresses must be stable on or before
the falling edge of RAS. CAS is internally inhibited (or "gated") by RAS to permit triggering of
CAS as soon as the Row Address Hold Time
(tRAH) specification has been satisfied and the
address inputs have been changed from rowaddresses to column-addresses.
144
Write Enable:
The read or write mode is selected with the
WE input. A logic "high" oli WE dictates read
mode, logiC "low" dictates write mode. Data input
is disabled when read mode is selected.
Data Input:
Data is written into the MSM41256A during a
write or read-write cycle. The last falling edge of
WE or CAS is a strobe for the Data in (DIN)
register. In a write cycle, if WE is brought "low"
(write mode) before CAS, DIN is strobed by CAS,
and the set-up and hold times are referenced to
CAS.~ read-write cycle, WE will be delayed
until CAS has made its negative transition. Thus
DIN is strobed by WE, and set-up and hold times
Data Output:
The output buffer is three-state TTL compatible with a fan-out of two standard TTL loads.
Data out is the same polarity as data in. The
output is in a high impedance state until CAS is
brought "low". In a read cycle, or a read-write
cycle, the output is valid after tRAC from transition of RAS when tRCD (max) is satisfied, or after
tCAC from transition of CAS when the transition
occurs after tRCD (max). Data remain valid until
CAS is returned to "high". In a write cycle, the
identical sequence occurs, but data is not valid.
Page Mode:
Page-mode operation permits strobing the
row-address while maintaining RAS at a logic
low (0) throughout all successive memory operations in which the row-address doesn't change.
Thus the power dissipated by the negative going
edge of RAS is saved. Further, access and cycle
times are decreased because the time normally
required to strobe a new row-address is eliminated.

RAS Only Refresh:
Refresh of the dynamic memory cells is accomplished by performing a memory cycle at
each of the 256 row-addresses (Ao to A 7) at least
every 4 milliseconds. RAS only refresh avoids
any output during refresh because the output
buffer is in the high impedance state unless CAS
is brought low. Strobing each of the 256 rowaddresses (Ao to A7) with RAS will cause all bits
in each row to be refreshed. Further RAS only refresh results in a substantial reduction in power
dissipation.
CAS Before RAS Refresh:
CAS before RAS refreshing available on the
MSM41256A offers an alternate refresh method.
If CAS is held on low for the specified period
(tFCS) before RAS goes to low, on chip refresh
control clock generators and the refresh address
counter are enabled, and an internal refresh operation takes place. After the refresh operation is
performed, the refresh address counter is automatically incremented in preparation for the next
CAS before RAS refresh operation.
Hidden Refresh:
Hidden refresh cycle may take place while
maintaining latest valid data at the output by extending CAS active time from the previous
memory read cycle. In MSM41 256A hidden refresh means CAS before RAS refresh and the internal refresh addresses from the counter are
used to refresh addresses, because CAS is
always low when RAS goes to low in this mode.
CAS Before RAS Refresh Counter Test Cycle:

A special timing sequence using CAS before
RAS counter test cycle provides a convenient
method of verifying the functionality of CAS
before RAS refresh activated circuitry. As shown
in CAS before RAS Counter Test Cycle, if CAS
goes to high and goes to low again while RAS is
held low, the read and write operation are
enabled. A memory cell address, consisting of a
row address (9 bits) and a column address (9
bits), to be acceded can be defined as follows:
A ROW ADDRESS
- Bits Aothrough A7 are defined by the refresh
counter. The other bit As is set "high"
internally.
A COLUMN ADDRESS
All the bits Ao through As are defined by
latching levels on Ao through As at the
second falling edge of CAS.
Suggested CAS before RAS Counter Test
Procedure:
The timing, as shown in CAS before RAS
Counter Test Cycle, is used for all the operations
described as follows:
(1) Initialize the internal refresh counter. For
this operaton, 8 cycles are required.
(2) Write a test pattern of lows into memory
cells at a single column address and 256
row addresses.
(3) By using read-modify-write cycle, read the
low written at the last operation (Step (2))
and write a new high in the same cycle. This
cycle is repeated 256 times, and highs are
written into the 256 memory cells.
(4) Read the high written at the last operation
(Step (3)).
(5) Complement the test pattern and repeat the
steps (2), (3) and (4).
145
DYNAMIC RAM MSM41256AAS/RS . - - - - - - - - - - - - - - MSM41256A Bit Map (Physical-Decimal)

OPin16
r--
252
253
254
255
256
257
258
259
511
510
509
252
253
254
255
256
257
258
259
511
510
509
508
256
256
256
256
256
256
256
256
256
256
256
256
256
256
256
256
252
253
254
255
256
257
258
259
511
510
509
508
252
253
254
255
257
257
257
257
257
257
257
257
508
256
257
258
259
511
510
509
508
257
257
257
257
257
257
257
257
508
II:
Cl
()
Cl
~
~
..J
256
257
258
259
511
510
509
126
126
126
126
126
126
126
126
126
126
126
126
126
126
126
126
252
253
254
255
256
257
258
259
511
510
509
508
382
382
382
382
382
382
382
382
382
382
382
382
382
382
382
382
252
253
254
255
256
257
258
259
511
510
509
508
127
127
127
127
127
127
127
127
127
127
127
127
127
127
127
127
252
253
254
255
256
257
258
259
511
510
509
508
383
383
383
383
383
383
383
383
383
383
383
383
383
383
383
383
508
252
253
254
255
()
ROW DECODER
ROW DECODER
252
253
254
255
256
257
258
259
511
510
509
511
511
511
511
511
511
511
511
511
511
511
511
511
511
511
511
252
253
254
255
256
257
258
259
511
510
509
508
255
255
255
255
255
255
255
255
255
255
255
255
255
255
255
255
252
253
254
255
256
257
258
259
511
510
509
508
510
510
510
510
510
510
510
510
252
253
254
255
254
254
254
254
254
254
254
254
510
510
510
510
510
510
510
510
II:
256
257
258
259
511
510
509
508
Cl
254
254- 254
254
254
254
254
254
0
w
()
Cl
256
257
258
259
511
510
509
508
()
385
385
385
385
385
385
385
385
256
257
258
259
511
510
509
508
129
129
129
129
129
129
129
129
129
129
256
257
258
259
511
510
509
508
384
384
384
384
384
384
384
384
384
384
384
384
256
257
258
259
511
510
509
508
128
128
128
128
128
128
128
128
128
128
128
128
253
254
255
385
385
385
385
385
385
385
385
252
253
254
255
129
129
129
129
129
129
252
253
254
255
384
384
384
384
252
253
254 -255
128
128
128
128
..J
252
A8 ROW ="L"
REFRESH ADDRESS
(0-255)
(0-255)
o
Pin8
A = ROW ADDRESS (DECIMAL)
CELL
146
A8ROW="H"
REFRESH ADDRESS
B =COLUMNADDRESS (DECIMAL)
OKI
semiconductor
MSM41 257 AAS/RS

262, 144-BIT DYNAMIC RANDOM ACCESS MEMORY < Nibble Mode Type>
GENERAL DESCRIPTION
The Oki MSM41257A is a fully decoded, dynamic NMOS random access memory organized as
262144 one-bit words. The design is optimized for high-speed, high performance applications such
as mainframe memory, buffer memory, peripheral storage and environments where low power dissipation and compact layout is required.
Multiplexed row and column address inputs permit the MSM41257A to be housed in a standard
16 pin DIP. Pin-outs conform to the JEDEC approved pin out. Additionally, the MSM41257 A offers
new functional enhancements that make it more versatile than previous dynamic RAMs. "CASbefore-RAS" refresh provides an on-chip refresh capability, also features "nibble mode" which allows
high speed serial access to up to 4 bits of data.
The MSM41257 A is fabricated using silicon gate NMOS and Oki's advanced VLSI Polysilicon
density and minimum chip size. DynamiC circuitry is employed in the design, including the sense
amplifiers.
FEATURES
transistor cell
Row access time:
100 ns max (MSM41257 A-1 OAS/RS)
120 ns max (MSM41257 A-12AS/RS)
150 ns max (MSM41257 A-15AS/RS)
Cycle time:
200 ns min (MSM41257A-1 OAS/RS)
220 ns min (MSM41257 A-12AS/RS)
260 ns min (MSM41257 A-15AS/RS)
Low power:
Single +5V Supply, 1 0% tolerance

"Gated"CAS
Common 1/0 capability using "Early Write"
operation
capability
performance
"Nibble Mode" capability

VSS
Pin Names
DIN
CAS
AD-A.
Address Inputs
WE
DOUT
RAS
Row Address Strobe
CAS
WE
Write Enable
DIN
Data Input
DOUT
Data Output
VCC
Power Supply (+5V)
VSS
Ground (OV)
A.
RAS
A,'
Ao'
A,'
A,'
A ..
A,'
A,'
vCC
A,'
Function
* Refresh Address
147
.DYNAMICRAMMSM41257AAS/RS.-----------------------------FUNCTIONAL BLOCK DIAGRAM
I-----WE
Ao-As
1-----
~~~ -----~r>----<L--J
DIN
L.
I _ _ _ _ _ _...J
OnchipVSB
Rating
Symbol
Value
Unit
VIN. VOUT
-1 to +7
Vee
-1 to +7
Topr
Ot070
Storage temperature
Tstg
-55 to +150
PD
1.0
50
rnA
Power dissipation
148
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ DYNAMIC RAM MSM41257AAS/RS

(Referenced to VSS)
Min.
Typ.
Max.
Unit
VCC
4.5
5.0
5.5
VSS
VIH
2.4
6.5
VIL
-1.0
0.8
Symbol
Parameter
Supply Voltage
Operating
Temperature
OC to +70C
DC CHARACTERISTICS
Symbol
Parameter
Min.
Max.
Unit
OPERATING CURRENT
ICC1
70
mA
STANDBY CURRENT
(RAS = CAS = VIH)
ICC2
5.0
mA
REFRESH CURRENT 1
ICC3
60
mA
NIBBLE MODE CURRENT

(RAS = VIL, CAS cycling; tNC = min:)
ICC4
30
mA
REFRESH CURRENT 2
ICC5
65
mA

(OV VIN 5.5V, all other pins not
under test = OV)
III
-10
10
/l-A

(Data out is disabled, OV VOUT
ILO
-10
10
/l-A
VOH
VOL
2.4
0.4
V
V
:s
:s
:s
:s 5.5V)
OUTPUT LEVELS
Output low voltage (lOL = 4.2 mAl
Notes
output open.
149
DYNAMIC RAM MSM41257 AAS/RS . - - - - - - - - - - - - - - - CAPACITANCE

(Ta = 25C, f = 1 MHz)
Parameter
Input capacitance (Ao - As, DIN)
Input capacitance (RAS, CAS, WE)
150
Symbol
Typ.
CIN1
Max.
Unit
pF
CIN2
10
pF
COUT
pF

AC CHARACTERISTICS
Parameter
Symbol
Unit
Note 1,2,3
MSM41257A- MSM41257A- MSM41257A12

10
15
Min.
Max.
Min.
Max.
Min.
Notes
Max.
Refresh period
tREF
ms

cycle time
tRC
ns
200
220
260
tRWC
ns
200
220
260
tRAC
ns
100
120
150
4,6
tCAC
ns
50
60
75
5,6

delay
tOFF
ns
Transition time
tT
ns
RAS precharge time
tRP
ns
85
RAS pulse width
tRAS
ns
105
RAS hold time
tRSH
ns
55
CAS pulse width
tCAS
ns
55
CAS hold time
tCSH
ns
105
tRCD
ns
25
tCRS
ns
20
20
20
Row address set-up

time
tASR
ns
tRAH
ns
15
15
15

time
tASC
ns
Column address hold

time
tCAH
ns
20
20
25
Read command set-up

time
tRCS
ns
Read command hold

time referenced to CAS
tRCH
ns
Read command hold

tRRH
ns
20
20
20

time
twcs
ns
30
50
30
3
50
90
1OILS
120
60
1 OILS
25
30
3
50
150
1OILS
75
1 OILS
75
1OILS
150
120
50
100
60
1 OILS
60
25
75
151
DYNAMIC RAM MSM41257AAS/RS . - - - - - - - - - - - - - - - AC CHARACTERISTICS (Continued)

Parameter
Symbol
Unit
MSM41257A10
Min.
Max.
MSM41257A12
Min.
Max.
MSM41257A15
Min.
Notes
Max.
Write command pulse

width
twp
ns
15
20
25
Write command hold

time
tWCH
ns
15
20
25
Write command to
RAS lead time
tRWL
ns
35
40
45
Write command to
CAS lead time
tCWL
ns
35
40
45
Data-in set-up time
tDS
ns
Data-in hold time
tDH
ns
20
20
25
tCWD
ns
15
20
25
Refresh set-up time for

tFCS
ns
20
25
30
Refresh hold time for

tFCH
ns
20
25
30
CAS precharge time

(C before R cycle)
tCPR
ns
20
25
30
RAS precharge to
CAS active time
tRPC
ns
20
20
20
Nibble mode read/write

cycle time
tNC
ns
55
60
70
Nibble mode read-write

cycle time
tNRWC
ns
55
60
70
Nibble mode access

time
tNCAC
ns
Nibble mode CAS

pulse width
tNCAS
ns
25
30
35
Nibble mode CAS

precharge time
tNCP
ns
20
25
30
Nibble mode read

RAS hold time
tNRRS~
ns
25
30
40
Nibble mode write

RAS hold time
tNWRSH
ns
45
50
60
tRNH
ns
20
20
20
Nibble mode CAS hold

152
30
25
35

Parameter
Symbol
Unit
MSM41257A- MSM41257A- MSM41257A10

12
15
Min.

cycle time
tRTC
ns
340

RAS pulse width
tTRAS
ns
230

CAS precharge time
tCPT
ns
50
Notes:
Max.
Min.
Max.
375
10fLS
265
60
Min.
430
10fLS
320
70
Notes
Max.
10
10fLS
10
10
An initial pause of 100 fLs is required after power-up followed by any 8 RAS cycles
2
3
The AC characteristics assume at tT
Assumes that tRCD ~ tRCD (Max.). If tRCD is greater than the maximum recommended
value shown in this table, tRAC will increase by the amount that tRCD exceeds the value
shown.
5 ns
VIH (Min.) and VIL (Max.) are reference levels for measuring of input signals. Also transition times are measured between VIH and VIL.
5 Assumes that tRCD ~ tRCD (Max.).

7 Operation within the tRCD (Max.) limit insures that tRAC (Max.) can be met. tRCD (Max.)
twcs and tCWD are not restrictive operating parameters. They are included in the data
sheet as electrical charcteristics only; if twcs ~ twcs (min.), the cycle is an early write
cycle and the data out pin will remain open circuit (high impedance) throughout the
entire cycle; if tCWD ~ tCWD (min.), the cycle is read-write cycle and the data out will
contain data read from the selected cell; if neither of the above sets of conditions is
satisfied the condition of the data out (at access time) is indeterminate.
Nibble mode cycle.
10 CAS before RAS Refresh Counter Test Cycle only.
153
DYNAMIC RAM MSM41257 AAS/RS . - - - - - - - - - - - - - - - -
READ CYCLE
tRC
tRAS
RAS
VIHVILtRSH
CAS
VIHVIL-
Addresses
VIHVIL-
WE
VIHVIL -
tCAS
~tRCH~RRH
I..
VOHDOUT
VOL-
~tCAC
tRAC
I OPEN
:1
~
vJ f'O"
Oata
Don't Care
RAS
11
CAS
Addresses
VIHvIL-
VIHVIL-
VIHVIL-
WE
VIHVIL-
DIN
VIHVIL-
DOUT
VOHVOL-
154
OPEN
I
~
Don'tCare
READ-WRITE/READ-MODIFY -WRITE CYCLE
~----------------------tRWC----------------------~
V I H-
----4.....-:-::-----.1--..
VIL -
VIHAddresses V I L - '(;d~~!!!:'.;)
DOUT
NIBBLE MODE READ CYCLE
tRP
RAS
VIHVIL -
CAS
Addresses
111
~IHIL -
WE
VIHVIL-
DOUT
VOHVOL-
Don't Care
155
NIBBLE MODE WRITE CYCLE
tRP
RAS
CAS
Addresses
WE
DIN
DOUT
VIHVIL-
VIHVIL -
VIHVIL-
VIHVIL-
VIHVIL VOHVOL-
Open
Don't Care
NIBBLE MODE READ-WRITE CYCLE
RAS
VIHVIL -
CAS
Addresses
WE
DOUT
DIN
vIHVIL -
VIHVIL -
VIHVIL -
VOHVOL-
VIHVIL -
156
Don't Care
FfAS ONLY REFRESH
CYCLE
NOTE: CAS
= VIH, WE,
DIN
= Don't
care
VOH- _ _ _ _ _ _ _ _ _ _ _ _1 OPEN
DOUT
VOL-
~ Don't Care
RAS
CAS
Don't care
VIH VIL -
VIHVIL -
VOH-
DOUT
VOL-
----------~I
OPEN
Don'tCare
157
RAS
VIHVIL -
CAS
VIH VIL -
Addresses
VIH VIL -
WE (Read)
DOUT
WE
VOHVOL -
v1H-
(Read-Write) V IL-
~ Don't Care
RAS
VIHVIL -
CAS
VIHVIL -
Addresses
VIHVIL -
VIH-
WE (R ead) V I L _ .,"",,",,,,,,",,""",,,",",,,,,,",,""",,,",",,~
DOUT
VIH- ~~7n~~~7n~~~7n~~~
V IL -
158
.:..:.;."""=""""'"""""""="""=""""'""'"'~ lI'--_ _ _ _Jr
"'''"'''''"'''"''=''"''="
~ Don't Care
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ DYNAMIC RAM MSM41257AAS/RS
Simple Timing Requirements:
The MSM41257 A has the circuit considerations for easy operational timing requirements
for high speed access time operations. The
MSM41257 A can operate under the condition of
tRCD (max) = tCAC which provides an optimal
time space for address multiplexing. In addition,
the MSM41257A has the minimal hold time of
Address (tCAH), WE (tWCH) and DIN (tDH). And
the MSM41257 A can commit better memory
system through-put during operations in an interleaved system. Furthermore, Oki has made
timing requirements referenced to RAS nonrestrictive and deleted from the data sheet,
which includes tAR, tWCR, tDHR and tRWD
Therefore, the hold times of the Column Address
DIN and WE as well as tCWD (CAS to WE Delay)
are not restricted by tRCD.
Fast Read- While-Write Cycle:
The MSM41 257 A has the fast read while
write cycle which is achieved by excellent control of the three-state output buffer in addition
to the Simplified timings described in the previous section. The output buffer is controlled
by the state of WE when CAS goes low. When
WE is low during CAS transition to low, the
MSM41257 A goes to early write mode where
the output becomes floating and common liD
bus can be used on the system level. Whereas,
when WE goes low after tCWD following CAS
transition to low, the MSM41257 A goes to
delayed write mode where the output contains
the data from the cell selected and the data from
DIN is written into the cell selected. Therefore,
very fast read write cycle .becomes available.
Address Inputs:
are required to decode any 1 of 262,144 storage
cell location within the MSM41257 A. Nine rowaddress bits are established on the input pins
(Ao through ABJ and latched with the Row Address Strobe (RAS). Then nine column address
bits are established on the input pins and
latched with the Column Address Strobe (CAS).
All input addresses must be stable on or before
the falling edge of RAS. CAS is internally inhibited (or "gated") by RAS to permit triggering of
CAS as soon as the Row Address Hold Time
(tRAH) specification has been satisfied and the
address inputs have been changed from rowaddresses to column-addresses.
Write Enable:
The read or write mode is selected with the
WE input. A logic "high" on WE dictates read
mode, logic "low" dictates write mode. Data input
is disabled when read mode is selected.
Data Input:
Data is written into the MSM41 257 A during a
WE or CAS is a strobe for the Data in (DIN)
register. In a write cycle, if WE is brought "low"
CAS. In a read-write cycle, WE will be delayed
Data Output:
Data out is the same polarity as data in. The
brought "low". In a read cycle, or a read-write
cycle, the output is valid after tRAC from transition of RAS when tRCD (max) is satisfied, or after
tCAC from transition of CAS when the transition
occurs after tRCD (max). Data remain valid until
CAS is returned to "high". In a write cycle, the
identical sequence occurs, but data is not valid.
Nibble Mode:
Nibble mode allows high speed serial read,
write or read-modify-write access of 2, 3 or 4
bits of data. The bits of data that may be accessed during nibble mode are determined by
the 8 row addresses and the 8 column addresses. The 2 bits of addresses (CJ\a RAa) are used
to select 1 of the 4 nibble bits for initial access.
After the first bit is accessed by normal mode,
the remaining nibble bits may be accessed by
CAS "high" then "low" while RAS remains "low".
Toggling CAS causes RAa and CAa to be incremented internally while all other address bits are
held constant and makes the next nibble bit
available for access. (See Table 1)
If more than 4 bits are accessed during
nibble mode, the address sequence will begin to
repeat. If any bit is written during nibble mode,
the new data will be read on any subsequent
access. If the write operation may be executed
again on subsequent access, the new data will
be written into the selected cell location.
In nibble mode, the three-state control of
DOUT Pin is determined by the first normal access cycle.
The data output is controlled by only WE
state referenced at CAS negative transition of
the normal cycle (first Nibble bit). That is, when
twcs > twcs (min) is met, the data output will
remain open circuit throughout the succeeding
Nibble cycle regardless of WE state. Whereas,
when tCWD > tCWD (min) is met, the data
output will contain data from the cell selected
during the succeeding nibble cycle regardless of
WE state. The write operation is done during the
period where WE and CAS clocks are low.
Therefore, write operation can be done bit by bit
during each nibble operation at any timing conditions of WE (twcs and tCWD) at the normal
159
cycle (first Nibble bit).
DYNAMIC RAM MSM41257AAS/RS . - - - - - - - - - - - - - - - Table 1
SEQUENCE
NIBBLE MODE ADDRESS SEQUENCE EXAMPLE
NIBBLE
BIT RAa
RAS/CAS (normal mode)

toggle CAS (nibble mode)
3
4

ROW
ADDRESS CAa
COLUMN
ADDRESS
0
1
10101010 0
10101010
10101010 0
10101010
10101010
10101010
10101010 1
10101010
10101010 0
10101010
RAS Only Refresh:

each of the 256 row-addresses (AD to A 7) at least
is brought low. Strobing each of the 256 rowaddresses (AD to A7) with RAS will cause all bits
in each row to be refreshed. Further RAS only refresh results in a substantial reduction in power
dissipation.
CAS before RAS refreshing available on the
MSM41 257 A offers an alternate refresh method.
If CAS is held on low for the specified period
(tFCS) before RAS goes to low, on chip refresh
control clock generators and the refresh address
counter are enabled, and an internal refresh operation takes place. After the refresh operation is
performed, the refresh address counter is automatically incremented in preparation for the next
CAS before RAS refresh operation.
Hidden Refresh:
maintaining latest valid data at the output by extending CAS active time from the previous
memory read cycle. In MSM41257 A hidden refresh means CAS before RAS refresh and the internal refresh addresses from the counter are
used to refresh addresses, because CAS is
always low when RAS goes to low in this mode.
160
... input addresses
generated internally sequence

repeats

enabled. A memory cell address, consisting of a
row address (9 bits) and a column address (9
bits), to be acceded can be defined as follows:
A ROW ADDRESS
- Bits AD through A7 are defined by the refresh
counter. The other bit Aa is set "high"
internally.
A COLUMN ADDRESS
- All the bits Ao through Aa are defined by
latching levels on Ao through Aa at the
Procedure:
row addresses.
(Step (3)).
steps (2), (3) and (4).
NIBBLE MODE
1) The case of first nibble cycle is Early write
~~
__________________________
~r--
----~~---------~-------
DOUT
:==)>-_____________
Hi9h-Z _ _ _ _ _ _ _ _ _ _ _ _ _ __
~EarlY Write~NO ope.~.~I. .--Write~~Write~

(Add Increment)
~: Valid Data
2) The case of first nibble cycle is delyed write IRead-Write)
RAS
r-\~.----------------------------~I
\~---------'/
\\.--_--1,
------~~-------~----DOUT
I----
Read-Write
. I.
Read-Write~ Read------t.- Read-write--I

~:
Valid Data
161
DYNAMIC RAM MSM41257AAS/RS . - - - - - - - - - - - - - - - MSM41257A Bit Map (Physical-Decimal)

,-----
o Pin 16
252
253
254
255
256
257
258
259
511
510
509
252
253
254
255
256
257
258
259
511
510
509
508
508
256
256
256
256
256
256
256
256
256
256
256
256
256
256
256
256
252
253
254
255
256
257
258
259
511
510
509
508
252
253
254
255
257
257
257
257
257
257
257
257
256
257
258
259
511
510
509
508
257
257
257
257
257
257
257
257
508
0:
Cl
(J
Cl
::!:
:::J
252
254
256
257
258
259
511
510
509
126
126
126
126
126
126
126
126
126
126
126
126
126
126
126
252
253
254
255
256
257
258
259
511
510
509
508
382
382
382
382
382
382
382
382
382
382
382
382
382
382
382
382
252
253
254
255
256
257
258
259
511
510
509
508
127
127
127
127
127
127
127
127
127
127
127
127
127
127
127
127
252
253
254
255
256
257
258
259
511
510
509
508
383
383
383
383
383
383
383
383
383
383
383
383
383
383
383
383
508
255
..J
126
253
(J
L--
ROW DECODER
ROW DECODER
r---
252
253
254
255
256
257
258
259
511
510
509
511
511
511
511
511
511
511
511
511
511
511
511
511
511
511
511
252
253
254
255
256
257
258
259
511
510
509
508
255
255
255
255
255
255
255
255
255
255
255
255
255
255
255
255
252
253
254
255
256
257
258
259
511
510
509
508
510
510
510
510
510
510
510
510
252
253
254
255
254
254
254
254
254
254
254
254
510
510
510
510
510
510
510
510
0:
256
257
258
259
511
510
509
508
Cl
254
254
254
254
254
254
254
254
w
0
(J
Cl
::!:
252
253
254
255
:::J
385
385
385
385
385
385
385
385
(J
252
253
254
255
256
257
258
259
511
510
509
129
129
129
129
129
129
129
129
129
129
129
129
129
129
129
129
252
253
254
255
256
257
258
259
511
510
509
508
384
384
384
384
384
384
384
384
384
384
384
384
384
384
384
384
252
253
254
255
256
257
258
259
511
510
509
508
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
256
257
258
259
511
510
509
508
385
385
385
385
385
385
385
385
508
..J
A8ROW="L"
REFRESH ADDRESS
(0-255)
(0-255)
o
Pin8
A =ROW ADDRESS (DECIMAL)
CELL
B =COLUMN ADDRESS (DECIMAL)
162
A8ROW="H"
REFRESH ADDRESS
OKI
semiconductor
MSM41464RS
65,536-WORD x 4-BITS DYNAMIC RANDOM ACCESS MEMORY
GENERAL DESCRIPTION
The Oki MSM41464 is a fully decoded, dynamic NMOS random access memory organized as
65,536 words by 4 bits. The design is optimized for high-speed, high performance applications such
as mainframe memory, buffer memory, peripheral storage and environments where low power dissipation and compact layout is required.
Multiplexed row and column address inputs permit the MSM41464 to be housed in a standard 18
pin DIP. Pin-outs conform to the JEDEC approved pin out. Additionally, the MSM41464 offers new
functional enhancements that make it more versatile than previous dynamic RAMs. "CASbefore-RAS" refresh provides an on-chip refresh capability.
The MSM41464 is fabricated using silicon gate NMOS and Oki's advanced VLSI Polysilicon
density and minimum chip size. Dynamic circuitry is employed in the design, including the sense
amplifiers.
FEATURES

transistor cell
Row access time:
100 ns max (MSM41464-1 DRS)
120 ns max (MSM41464-12RS)
150 ns max (MSM41464-15RS)
Cycle time:
200 ns min (MSM41464-1 DRS)
230 ns min (MSM41464-12RS)
260 ns min (MSM41464-15RS)
Low power:

"Gated" CAS
Output impedance controllable through early
write and OE operations
capability
performance
"Page Mode" capability

OE
VSS
DQ1
DO,
DO,
WE
RAS
A,
VCC
FUnction
Address Inputs
CAS
RAS
Row Address Strobe
D03
CAS
Ao
DO,-DO,
Data In/Data Out
OE
WE
Output Enable
A,
A5
Pin Names
Ao-A,
A,
A3
A-
Write Enable
VCC
Power Supply (+5V)
VSS
Ground (DV)
163
DYNAMIC RAM MSM41464RS - - - - - - - - - - - - - - - - - FUNCTIONAL BLOCK DIAGRAM
~~~ -----~r.--L--J
I'-_ _ _ _ _ _...J
OnchipV SB
Symbol
Value
Unit
VIN. VOUT
-1 to +7
Vee
-1 to +7
Topr
o to 70
Storage temperature
Tstg
-55 to +150
PD
1.0
50
mA
Rating
Power disSipation
164
- - - - - - - - - - - - - - - - - - . DYNAMIC RAM MSM41464RS

(Referenced to VSS)
Min.
Typ.
Max.
Unit
VCC
4.5
5.0
5.5
VSS
VIH
2.4
6.5
VIL
-1.0
0.8
Parameter
Supply Voltage
Symbol
Operating
Temperature
OC to +70C
DC CHARACTERISTICS
Parameter
Symbol
Min.
Max.
Unit
OPERATING CURRENT'
ICC1
70
mA
STANDBY CURRENT'
(RAS = CAS = VIH)
ICC2
5.0
mA
REFRESH CURRENT l '

ICC3
55
mA
PAGE MODE CURRENT'

(RAS = VIL, CAS cycling; tpc = min.)
ICC4
60
mA
REFRESH CURRENT 2'

ICC5
60
mA

(OV ::; VIN ::; 5.5V, all other pins not
under test = OV)
III
-10
10
J1-A

(Data out is disabled, OV ::; VOUT ::; 5.5V)
ILO
-10
10
J1-A
OUTPUT LEVELS
Output low voltage (lOL = 4.2 mAl
VOH
VOL
2.4
0.4
V
V
Notes
Note": ICC is dependent on output loading and cycle rates. Specified values are obtained with the
output open.
165
DYNAMIC RAM MSM41464RS ...- - - - - - - - - - - - - - - - - CAPACITANCE

(Ta = 25C, f = 1 MHz)
Parameter
Symbol
Typ.
Input capacitance (AD - A7)
CIN1
pF
Input capacitance (RAS, CAS, WE, OE)
CIN2
10
pF
CD
pF
Data 1/0 capacitance (DO 1 - 004)

166
Max.
Unit
------------------1. DYNAMIC RAM MSM41464RS

AC CHARACTERISTICS
Parameter
Symbol
Unit
Note 1,2,3
MSM4146410
MSM4146412
MSM4146415
Min.
Min.
Min.
Max.
Max.
Notes
Max.
Refresh period
tREF
ms

cycle time
tRC
ns
200
230
260
tRWC
ns
275
320
360
tpc
ns
100
120
145
tRAC
ns
100
120
150
4,6
tCAC
ns
50
60
75
5,6

delay
tOFF
ns
30
35
40
Transition time
tT
ns
50
50
50
RAS precharge time
tRP
ns
90
RAS pulse width
tRAS
ns
100
RAS hold time
tRSH
ns
50
60
75
CAS precharge time

(Page mode cycle only)
tcp
ns
40
50
60
CAS pulse width
tCAS
ns
50
CAS hold time
tCSH
ns
100
tRCD
ns
22
tCRS
ns
20
25
30
Row address set-up

time
tASR
ns
tRAH
ns
12
12
15

time
tASC
ns
Column address hold

time
tCAH
ns
15
15
20
Read command set-up

time
tRCS
ns
Read command hold

time
tRCH
ns

time
twcs
ns
-5
-5
-5
100
10J.Ls
10J.Ls
120
60
100
10J.Ls
10J.Ls
120
50
22
150
75
10J.Ls
10J.Ls
150
60
25
75
7,8
10
9
167
DYNAMIC RAM MSM41464RS . - - - - - - - - - - - - - - - - - AC CHARACTERISTICS (Continued)

Parameter
Symbol
Unit
MSM4146410
MSM4145412
MSM4146415
Min.
Min.
Min.
Max.
Max.
Notes
Max.
Write command pulse

width
twp
ns
20
25
30
Write command hold

time
tWCH
ns
20
25
30
Write command to
RAS lead time
tRWL
ns
35
45
50
Write command to
CAS lead time
tCWL
ns
35
45
50
Data-in set-up time
tDS
ns
Data-in hold time
tDH
ns
20
25
30
CAS to WE delay
tCWD
ns
85
100
120
RAS to WE delay
tRWD
ns
135
160
195
Read command hold

time reference to RAS
tRRH
ns
20
20
25
Access time from OE
tOEA
ns
OE data delay time
tOED
ns
30
35
40
OE hold time
tOEH
ns
Turn-off delay time

from OE
tOEZ
ns
RAS to CAS set-up time

(CAS before RAS)
tFCS
ns
20
25
30
RAS to CAS hold time

(CAS before RAS)
tFCH
ns
20
25
30
CAS active delay from

RAS precharge
tRPC
ns
20
20
20
CAS precharge time

(CAS before RAS)
tCPR
ns
20
25
30
Read/write cycle
(Refresh counter test)
tRTC
ns
385
450
515
RAS pulse width

tTRAS
ns
285
CAS precharge time

tCPT
ns
50
60
70
Read/write cycle time

(Page mode)
tpRWC
ns
175
210
245
168
25
30
1 OILS
40
30
340
35
1 OILs
10
405
40
11
1 OILS
11
11
- - - - - - - - - - - - - - - - - - . DYNAMIC RAM . MSM41464RS

Notes:
An initial pause of 100 JJ.s is required after power-up followed by any 8 RAS cycles
2
3
The AC characteristics assume at tT
5 ns
VIH (Min.) and VIL (Max.) are reference levels for measuring of input signals. Also transition times are measured between VIH and VIL.
Assumes that tRCD ~ tRCD (Max.) If tRCD
- tRCD (Max.)}.
> tRCD (Max.), tRAC will increase by {tRCD
Assumes that tRCD ;;;, tRCD (Max.).
Measured with a load circuit equivalent to 2TTL loads and 100 pF.
Operation within the tRCD (Max.) limit insures that tRAC (Max.) can be met. tRCD (Max.)
8
9
Assumes that tRCD (Min.) = tRAH (Min.)
+ 2tT + tASC (Min.)
twcs, tCWD and tRWD are not restrictive operating parameters. They are included in
the data sheet as electrical charcteristics only; if twcs > twcs (Min.), the cycle is an
early write cycle and the data in/data out pin will remain open circuit (high impedance)
throughout the entire cycle; if tCWD ;;;, tCWD (Min.) and tRWD ;;;, tRWD (Min.) the cycle
is read-write cycle and the data in/data out will contain data read from the selected cell;
if neither of the above sets of conditions is satisfied the condition of the data out (at
access time) is indeterminate.
10 Either tRRH or tRCH must be satisfied for a read cycle.

11
CAS before RAS refresh counter test cycle only.
READ CYCLE
tRC
RAS V I H
tRAS
=-----i. 1 - - - - - - - - - - - - ' - " - " - " . - - - - - - - - - 1 x.-------,L
VIL-
tcs
_ _J - - - - - tRsH------~
---~~---_,r___ ~-------tCAs-----~
CAS V IH VIL-
Addresses V I H
VlL
VIH
77TT.n7TTTT.r.n777T---~-----------~-~~77TTTTTTT
tCAC _____-I
I------'
I L ...LL..L.LLLI.".J..L.L.L.L..l4T
~------tRAC ------~
DATA VOH _ _ _ _ _ __
V OL -
OPEN
Valid Data
V IH
VIL
LLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLL~_ _-ZZLLLLLLLLLLLLLLLLLL
169
DYNAMIC RAM MSM41464RS - - - - - - - - - - - - - - - - - -
- - V 1H RAS V 1L -
------J
OE WRITE CYCLE
IRC
t RAS
RAS
V 1H V 1L tRSH
tCSH
CAS
V 1H V 1L -
WE
V 1H
V 1H
t CAS
170
- - - - - - - - - - - - - - - - - . DYNAMIC RAM MSM41464RS
READ/WRITE AND READ MODIFY WRITE CYCLE
Y'/OHDATAy
/
___
VOL-
OPEN
r---
IRAe
~ "H", "L"=Don'ICare
~----------------------IRAS
[:}
1 ' - - - - - - - - - - - - - - - f f - - -I-RS
=;-----=
IRP
ICRS
Addresses Y, H
olumn
address
Y IL
DATA Y OH
-=---
VOL -
WE
OE
~!
OPEN
~CS
ICA
!oF"F
I f-ICAC-=W
JJ~~~S
!oFF
f- IC~RE!OFF
LLdrI
------
~:~=!IlIi}~.
I~~ I ~OEA~
'L 1Wf&
-~.-~ ~ ~ -ib~
(I
~: ~
1Il/llIIlllll1/J
ECZiI
"W', "L" = Don'l Care
171
.OVNAMICRAMMSM41464RS.----------------------------------PAGE MODE WRITE CYCLE
tRAS
RAS
V IH -
V IL -
(I
CAS V IH V IL -
Address VIH
VlL
WE
V IH
VlL
DATA
V IH
VlL
Cl"E
PAGE MODE OE WRITE CYCLE
tRSH _ _ _-1
1 - - - - - - - - tpc - - - - - - - 1
_____ tCAS _ _ _ _
RC~-l-r---t CAS - - - - - I
~
CAS VI H _=-+f====tt- tCSH

V lL - 1'---------1
Address
WE
VI
H -ZTTTTT7"7TTT7-+-------<
1'---4----J
VI L
DATA VIH/VOH
2LnTTT77Trn-,,~n7Tn7T,~.r--~n7T,r,~,,7T,~n77n7nLk--_,L/7rn77TTT
VIL/VOL~~LW~~~~~LULW~t~~-~~~~LL~L6~UL~~~~CJ'~~LLLL
tOED
OE
0:: W////////$!1111!//k'J
tOEH
IOED
b/#!I////$$!/#xJ
~
172
- - - - - - - - - - - - - - - - - - . DYNAMIC RAM . MSM41464RS
PAGE MODE READ/WRITE CYCLE
r-__________t'PRWL-________
RSH
----------i
teA S ______-I
Address
WE
V I H ~77771rcrn7Tm--+---------=\
VIL~~~WU~~
DATA V1H/VOH
~~~~
____- J
~n7~~~~~~jb.~~\~~~~_in77TTTrr,77~,b~--\A,~~~_Jrv77TTTTT
VIL/VOL~~4L~~~~~
OE' V I H = - - - - - - .
VlL - ~
"H", "L" =Don't Care
Note: CAS = VIH, WE and OE not dependent on the high or low level.
Address
DATA VOH - - - - - - - - - - - - - - VOL
OPEN
173
DYNAMIC RAM MSM41464RS
.1------------------
CAS BEFORE RAS REFRESH CYCLE
Note: WE and OE not dependent on the high or low level.
CAS VIHVIL -
1-----tCPR
DATA VOH ---=-------------VOL ---
OPEN
Il
RAS
V IH V IL -
CAS
V IH V IL -
Address
WE
V IH
VIL
Iw~'
~::W#/~~
f---IRAC
DATA
V OH
--=---
VOL-
OPEN
tOEA
OE
V IH -
V IL -
174
-----------------------------------.OYNAMICRAMMSM41464RS.
CAS BEFORE RAS REFRESH COUNTER TEST CYCLE
1--_ _ _ _ _ _ _ _ _ _
tRTC
_ _~r---------tTRAS
tcp
---------~~r_---~I
1_ _ _ _ tRSH ---~
I-k--------{f------ tCAS -----lc------,.
III~
I
1'W//,0/0
tRCH-j
I
toFF
DATAYOL
__
Valid Data
YOH::::~---------------------~~::1===~~~~~c}.~----------
YIH
M~~
YIL
=TT:'777TrT7Tr;'7TTTO'T7-rr-;-r"T""rrr?;"""'"
==:.LL.LL.L.LL.LL.L.LL.LLL.L...L..'-L.I..L.L1LLLLLl.c:t.L4-_ _ _ _ _ _..,.-__---!...-tp0'..LLLLt.'..LL:.LLLLt.CLL
YIH
WE (Write) =7=;<'TT}'77TTTTTTJ'7777TTTTT'-\:---'-------,t-l---
YIL
z%LW~.LL.L...L..~'-L.I..L.L.L.L.LLLT
Il~----~LU.LL.'-L.I..L.L.LL.L...L..~
~ "H", "L"
Address Inputs:
16 bits of binary address input are required
to decode anyone of the 65,536 words by 4 bit
storage cell locations,
8 row-address bits are set up on address
input pins Ao through A7 and latched onto the
chip by the row address strobe (RAS). Then 8
column-address bits are set up on pins Ao
through A7 and latched onto the chip by the
column address strobe (CAS).
All addresses must be stable on or before the
falling edges of RAS. CAS is internally inhibited
(gated) by the RAS to permit triggering of CAS as
soon as the Row Address Hold Time (tRAH) specification has been satisfied and the address
inputs have been changed from row-addresses
Therefore specifications permit column addresses to be input immediately after the row address hold time (tRAH).
= Don't Care
Write Enable:
The read mode or write mode is selected with
the WE input. The logic high of the WE input
selects the read mode and a logic low selects
the write mode. The data input is disabled when
the read mode is selected. Data-out will remain
in the high-impedance state allowing a write
cycle with WE grounded.
Data Input:
Data is written during a write or read-modify
write cycle. Depending on the mode of operation,
the falling edge of CAS or WE strobes data into
the on-chip data latches. In an early-write cycle,
WE is brought low prior to CAS and the data is
strobed in by CAS with setup and hold times
referenced to this signal. In a delayed write or
read-modify-write cycle, CAS will already be low,
thus the data will be strobed in by WE with setup
and hold times referenced to this signal. In
delayed or read-modify-write, OE must be high
to bring the output buffers to high impedance
prior to impressing data on the I/O lines.
175
DYNAMIC RAM' MSM41464RS . - - - - - - - - - - - - - - - - - Data Output:

The three-state output buffer provides direct
TTL compatibility with a fan-out of two standard
TTL loads. Data-out is the same polarity as datain. The output is in the high-impedance (floating)
state until CAS is brought low. In a read cycle the
output goes active after the access time interval
tCAC that begins with the negative transition of
CAS as long as tRAC and tOEA are satisfied.
The output becomes valid after the access time
has elapsed and remains valid while CAS or OE
are low. CAS or OE going high returns it to a high
impedance state. In an early-write cycle, the
output is always in the high impedance state. In
a delayed-write or read-modify-write cycle, the
output must be put in the high impedance state
prior to applying data to the DO input. This is accomplished by bringing OE high prior to applying
data, thus satisfy tOED.
Output Enable:
The OE controls the impedance of the output
buffers. When OE is high, the buffers will remain
in the high impedance state. Bringing OE low
during a normal cycle will activate the output buffers putting them in the low impedance state. It is
necessary for both RAS and CAS to be brought
low for the output buffers to go into the low impedance state. Once in the low impedance state,
they will remain in the low impedance state until
OE or CAS is brought high.
Page Mode:
low (0) throughout all successive memory operations in which the row-address doesn't change.
Thus the power dissipated by the negative going
edge of RAS is saved. Further, access and cycle
times are decreased because the time normally
required to strobe a new row-address is eliminated.
RAS Only Refresh:
each of the 256 row-addresses (Ao to A 7) at least
every four milliseconds. RAS only refresh avoids
is brought low. Strobing each of 256 (Ao to A7)
row-addresses with RAS will cause all bits in
each row to be refreshed. Further RAS-only refresh results in a substantial reduction in power
dissipation.
CAS before RAS refreshing offers an alternate refresh method. If CAS is held on low for the
176
specified period (tFCS) before RAS goes to low,

on chip refresh control clock generators and the
refresh address counter are enabled, and an internal refresh operation takes place. After the refresh operation is performed, the refresh address
counter is automatically incremented in preparation for the next CAS before RAS refresh
operation.
Hidden Refresh:
maintaining latest valid data at the output by extending CAS active time. Hidden refresh means
CAS before RAS refresh and the internal refresh
addresses from the counter are used to refresh
addresses, because CAS is always low when
RAS goes to low in this mode.
enabled. This is shown in the CAS before RAS
counter test cycle. A memory cell address, consisting of a row address (8 bits) and a column address (8 bits), to be acceded can be defined as
follows:
A ROW ADDRESS
- Bits Ao through A 7 are defined by the refresh
counter.
A COLUMN ADDRESS
All the bits Ao through A7 are defined by
latching levels on Ao through A 7 at the
Procedure:
row addresses.
(Step (3)).
steps (2), (3) and (4).
- - - - - - - - _ - - - - - - - - - 1 . DYNAMIC RAM MSM41464RS

DQ1 DQ2
252
0
252
0
252
1
252
1
252
2
252
2
253
0
253
0
253
1
253
1
253
2
253
2
254
0
254
0
254
1
254
1
254
2
254
2
255
0
255
0
255
1
255
1
255
2
255
2
3
0
3
0
3
1
2
0
2
0
2
1
2
1
2
2
2
2
3
1
3
2
3
2
1
0
1
0
1
1
1
1
1
2
1
2
0
0
0
0
0
1
0
1
0
2
0
2
o Pin 18
DQ3 DQ4
0
0
0
0
0
1
0
1
0
2
0
2
1
0
1
0
1
1
1
1
1
2
1
2
2
0
2
0
2
1
2
1
2
2
2
2
3
0
3
0
3
1
3
1
3
2
3
2
255
0
255
0
255
1
255
1
255
2
255
2
0
125
0
125
0
126
0
126
0
127
0
127
1
125
1
125
1
126
1
126
1
127
1
127
2
125
2
125
2
126
2
126
2
127
2
127
3
125
3
125
255
125
255
125
255
126
255
126
255
127
.255
127
1
255
1
255
1
254
1
254
1
253
1
253
2
255
2
255
2
254
2
254
2
253
2
253
3
255
1
130
1
130
1
129
1
129
1
128
1
128
2
130
2
130
2
129
2
3
130
1- k
}
1-
gk
a:
254
254
1
254
1
254
2
254
2
253
0
253
0
253
1
253
1
253
2
253
2
252
0
252
0
252
1
252
1
252
2
252
2
254
125
254
125
254
126
254
126
254
127
254
127
253
125
253
125
253
126
253
126
253
127
253
127
252
125
252
125
252
126
252
126
252
127
252
127
255
255
255
255
255
254
255
254
255
253
255
253
254
255
254
255
254
254
254
254
254
253
254
253
253
255
253
255
253
254
253
254
253
253
253
253
252
255
252
255
252
254
252
254
252
253
252
253
255
130
255
130
255
129
255
129
255
128
255
128
254
130
254
130
254
129
254
129
254
128
254
128
253
130
253
130
253
129
253
129
253
128
253
128
252
130
252
130
252
129
252
129
252
128
252
128
a
254
'"
:J
252
125
252
125
252
126
252
126
252
127
252
127
253
125
253
125
253
126
253
126
253
127
253
127
254
125
254
125
254
126
254
126
254
127
254
127
253
255
253
255
253
254
253
254
253
253
253
253
254
255
254
255
254
254
254
254
254
253
254
253
3
125
3
125
3
126
3
126
3
127
3
127
2
125
2
125
2
126
2
126
2
127
2
127
1
125
1
125
1
126
1
126
1
127
1
127
2
255
2
255
2
254
2
254
2
253
2
253
1
255
1
255
1
254
1
254
1
253
1
253
0
125
0
125
255
255
255
255
255
254
255
254
255
253
255
253
3
255
3
255
3
254
3
254
3
253
3
253
<5
<)
~
0
126
0
126
0
127
0
127
1- k
ROW DECODER
I
252
255
252
255
252
254
252
254
252
253
252
253
255
125
255
125
255
126
255
126
255
127
255
127
I
0
255
0
255
0
254
0
254
0
253
0
253
ROW DECODER
1- H
7- h
ffi
0
<)
0
255
0
255
0
254
0
254
0
253
0
253
3
126
3
126
3
127
3
127
3
255
3
254
3
254
3
253
3
253
w
0
252
130
252
130
252
129
252
129
252
128
252
128
253
130
253
130
253
129
253
129
253
128
253
128
254
130
254
130
254
129
254
129
254
128
254
128
255
130
255
130
255
129
255
129
255
128
255
128
3
130
3
130
3
129
3
129
3
128
3
128
2
130
2
130
2
129
2
129
2
128
2
128
REFRESH ADDRESS
1
130
1
130
1
129
1
129
1
128
1
128
0
130
'"
:J
~ 8~
0
130
0
129
0
129
0
128
0
128
0
130
0
130
0
129
0
129
0
128
0
128
Ping
12~
3
129
3
129
2
128
2
128
3
128
3
128
REFRESH ADDRESS
(0- 255)
3
130
(0-255)
CELL
A = ROW ADDRESS (DECIMAL)

8
= COLUMN ADDRESS (DECIMAL)

177
.---=D=-._K
__I__s_._rn-'----l_c_onc:I
__U_c_.or
______~_~
MSM414256RS
262,144WORD x 4BITS DYNAMIC RAM
GENERAL DESCRIPTION
The MSM414256RS is a new generation dynamic RAM organized as 262,144 words by 4 bits.
The technology used to fabricate the MSM414256RS is OKI's N channel silicon gate MOS process
technology. The device operates at a single +5V power supply. Its I/O pins are TTL compatible.
FEATURES
Standard 20-pin plastic DIP
Family organization
Silicon gate, tripple polysilicon NMOS,

1-transistor memory cell
262,144 words by 4 bits
Power Dissipation
Family
Access Time
(MAX)
Cycle Time
(MIN)
MSM414256-10RS
100 ns
200 ns
413mW
MSM414256-1 2RS
120 ns
230 ns
385mW
Single +5V supply, 10% tolerance

Input: TTL compatible, address input, data
input latch
Output: TTL compatible, tristate, non latch
Refresh: 512 cycles/8 ms
Operating
(MAX)
Stand By
(MAX)
28mW
Page mode, read modify write capability

CAS before RAS refresh, CAS before RAS
hidden refresh, RAS only refresh capability
"Gated"CAS
Built-in VBB generator circuit
D03
D04
WE
DOl
CAS
NC
OE
"AO
AS"
"Al
A7"
"A2
"A3
"Refresh Address
178
Pin Names
Function
AOtoA8
Address Input
RAS
Row Address Strobe
c;;;g
001 to 004
Data In/Data Out
DE
Output Enable
WE
Write Enable
VCC
Power Supply (+5V)
VSS
Ground (OV)
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ DYNAMIC RAM MSM414256RS _
1 - - - - - WE
A.-A.
DO ,-DO,
Word
Drivers
Memory
Cells
----Y--,______- '
V
VCC S S -
OnchipV BB
Rating
Symbol
Conditions
Value
VT
Ta = 25C
los
Ta =25C
50
rnA
Power dissipation
PD
Ta =25C
Topr
Storage temperature
Tstg
Unit
-1.0 to +7.0
o to +70
-55 to +150

(Ta = 0 to +70)
Parameter
MIN
TYP
MAX
Unit
4.5
5.0
5.5
VSS
Input high voltage
VIH
2.4
6.5
I nput low voltage
VIL
-1.0
0.8
Supply Voltage
Symbol
Conditions
VCC
179
DYNAMIC RAM MSM414256RS . - - - - - - - - - - - - - - - - DC CHARACTERISTICS

(VCC = 5V 10%, Ta = 0 to +70C)
Parameter
Symbol
MSM
MSM
414256-10 414256-12
Conditions
MIN
Output high voltage
VOH
10H =-5.0 mA
Output low voltage
VOL
10L =4.2 mA
MAX MIN
Unit
MAX
2.4
2.4
-0.4
0.4
III
OV ;;;; VI ;;;; 6.5V;

all other pins not
under test = OV
-10
10
-10
10
JJ.A
ILO
00UT disable
OV;;;; VO ;;;;5.5V
-10
10
-10
10
JJ.A
Average power supply

current" (Operating)
ICC1
75
70
mA
Power supply current"

(Standby)
ICC2
RAS =VIH
CAS=VIH
mA

current"
(RAS only refresh)
ICC3
RAS cycling,
CAS=VIH
tRC = min
65
60
mA

current"
(Page mode)
ICC4
RAS=VIL,
CAS cycling
tpc =min
70
65
mA

current"
(CAS before RAS refresh)
ICC5
RAScycling,
CAS before RAS
70
65
mA
RAS, CAS cycling,

tRC =min
Note
*Note: ICC is dependent on output loading and cycle rates. Specified values are obtained with the
output open.
CAPACITANCE
(Ta = 25C, f = 1 MHz)
Symbol
Conditions
TYP
MAX
Unit
Input capacitance (AO to A8)
CIN1
pF
Input capacitance
(RAS, CAS, WE, DE)
CIN2
10
pF
pF
Parameter
1/0 capacitance (001 to 004)
180
- - - - - - - - - - - - - - - - -__ DYNAMIC RAM MSM414256RS _

AC CHARACTERISTICS
Note 1,2,3 (VCC = 5V 1 0%, Ta
0 to +70C)
MSM414256-10 MSM414256-12
Parameter
Symbol
Unit
MIN
MAX
MIN
Note
MAX
Refresh period
tREF
Random read/write cycle time
tRC
200
230
ns
tRWC
275
305
ns
tpc
100
120
ns
tRAC
100
120
ns
4,6
tCAC
50
60
ns
5,6
tOFF
25
25
ns
Transition time
tT
50
50
ns
RAS precharge time
tRP
ns
RAS pulse width
90
100
tRAS
100
10000
120
RAS hold time
tRSH
50
CAS precharge time

tcp
40
CAS pulse width
tCAS
50
CAS hold time
tCSH
100
tRCD
25
CAS and RAS set-up time
tCRS
15
Row address set-up time
tASR
tRAH
Column address set-up time
ms
10000
ns
60
ns
50
ns
60
10000
ns
ns
25
60
ns
20
ns
ns
15
15
ns
tASC
ns
Column address hold time
tCAH
20
20
ns
Column address hold time from RAS,
tAR
70
80
ns
tRCS
ns
tRCH
ns
95
ns
10000
120
50
Write command hold time from RAS
tWCR
80
twcs
ns
tWCH
30
35
ns
7,8
10
181
DYNAMIC RAM MSM414256RS . - - - - - - - - - - - - - - - - AC CHARACTERISTICS (CONT.)

MSM414256-10 MSM41 4256-12
Parameter
Symbolr-----.-----+------r----~
MIN
MAX
MIN
Unit
30
35
ns
40
40
ns
40
40
ns
ns
Data-in hold time
30
35
ns
Data-in hold time from RAS
80
95
ns
twp

Write command to CAS lead time,
tCWL
Data-in set-up time
tDS
Note
MAX
CAS to WE delay
tCWD
80
90
ns
RAS to WE delay
tRWD
130
150
ns

reference to RAS
tRRH
20
20
ns
10
Access time from OE
tOEA
OE data delay time
tOED
25
25
ns
OE hold time
tOEH
tOEZ
o
o
ns
Turn-off delay time from OE
o
o
OE set-up time
tOES
30
30
ns

(CAS before RAS)
tFCS
20
25
ns
tFCH
30
30
ns
precharge
tRPC
20
20
ns
CAS precharge time

(CAS before RAS)
tCPR
20
25
ns
385
435
ns
11
10000
ns
11
ns
11
(CAS before RAS)

CAS active delay from RAS
Read/write cycle
30
RAS pulse width

tTRAS
CAS precharge time

tCPT
50
tpRWC
175
Read/write cycle time (Page mode)
182
285
25
10000
30
325
60
195
25
ns
11
ns
ns
- - - - - - - - - - - - - - - - - - 1 1 . DYNAMIC RAM MSM414256RS

Notes:
An initial pause of 100 JLs is required after power-up followed by any 8 RAS cycles
2
3
The AC characteristics assume at tT = 5 ns
Assumes that tRCD ;S tRCD (Max.). If tRCD

- tRCD (Max.)l
5
6
7
Assumes that tRCD :;;; tRCD (Max.).

Measured with a load circuit equivalent to 2TTL
the data sheet as electrical charcteristics only; if twcs ~ twcs (Min.), the cycle is an
early write cycle and the data out pin will remain open circuit (high impedance)
throughout the entire cycle; if tCWD ~ tCWD (Min.) and tRWD ~ tRWD (Min.) the cycle
is read-write cycle and the data out will contain data read from the selected cell; if
neither of the above sets of conditions is satisfied the condition of the data out (at
10
11
VIH (Min.) and VIL (Max.) are reference levels for measuring of input signals. Also,
transition times are measured between VIH and VIL

+ 100 pF.
is specified as a reference pOint only; if tRCD is greater than the specified tRCD (Max.)
+ 2tT + tASC (Min.).
Either tRRH or tRCH must be satisfied for a read cycle.

183
DYNAMIC RAM 'MSM414256RS . - - - - - - - - - - - - - - - - -
READ CYCLE
tRC
RAS V IH VIL-
tRAS
tAR
0'
tcs
CAS VIHVIL -
tRSH
tCAS
Address VIH
VJL
WE
V IH
VIL
i-------:--tCAC
-----j
f - - - - - - - tRAC - - - - - - - l
DATA
DE
VOH VOL
OPEN
V IH
VJL
~ Don'tCare

tRC
tRAS
tAR
tCSH
- - V IH -
CAS V IL -
184
tRS
tCA
RAS
Y rH -
Y rL
CAS
Yr/ OH DATAy /
____
VOL -
OPEN
r--------
t RAe
~ Don'tCare
r--------------
tAR---j
tRAS
~----~I-------------(f-----tR-S
tRP
tCRS
II
Address
y IH
YJL
Don'tCare
185
DYNAMIC RAM . MSM414256RS
.1-----------------
tRAS
RAS
CAS
Address V IH
V IL
V IH
VIL
WE
V
DATA V IH
IL
DE
~ Don'tCare
~-~---__tpRw~----~
~__lo.r_-o___-t CAS - - - - 1
R S H -----1
teA S - - - - - 1
Address
WE
DATA
VIH~n7ih~7Tnf--1_--------~
V IL
-z:lC/J..,'f-L.J..t..,f..!...!!
Vla/VOH~7nJ;~~~~~~~~,~~~--_i-/T.r,7777TTF,~\1__~,~~~~_Jd7.r.n7777T
V
[L/V 0 L
-::Z:;<.LL.l...L.U-':.LL.LL"--,-,UU
OE V I H
=----------,
V IL ~
186
Don'tCare
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ DYNAMIC RAM MSM414256RS -
'Note: CAS
DATA V 1H - - - - - - - - - - V/L
= VIH, WE and OE not dependent on the high or low level.
OPEN
EZZJ
Don'tCare
Note: WE and OE not dependent on the high or low level.
DATA V 1H
V/L
-----------
OPEN
~ Don'tCare
187
DYNAMIC RAM . MSM414256RS
.1-----------------

tRC
RAS
tAR----1
V IH V IL -
1
tRSH
CAS
1----tFCH
V IH V IL -
---I
~---
Address
VIff1M"!II//#I$///#/IIII4
WE
OPEN
V IH
Valid Data
=-----,
V IL -
~ Don'tCare

tRTC
tTRAS
.1
RAS
tCPT
CAS
/,
Address
WE (Read)
I.
~I
IjjITIIV/ II//!1/I/ITI/1/./
Ir
tCAC
DATA
OE(Read)
WE (Write)
DATA
OE (Write)
7ff!ll!I/!]-LLllf!7.lJ..IZ1Z17Z1fZl;i
10m
~toEH
V///////fl/!11//////2
~ Don'tCarc
188
- - - - - - - - - - - - - - - - -.... DYNAMIC RAM MSM414256RS
Address Inputs:
to decode anyone of the 262,144 words by 4
bits storage cell locations.
input pins AO through A8 and latched onto the
column-address bits are set up on pins AO
(gated) by the RAS to permit triggering of CAS as
soon as the Row Address Hold Time (tRAH)
specification has been satisfied and the address
Therefore specifications permit column
addresses to be input immediately after the row
address hold time (tRAH).
Write Enable:
the read mode is selected. Data-out will remain
in the high-impedance state allowing a write
cycle with WE grounded.
Data Input:
referenced to this Signal. In a delayed write or
and hold times referenced to this Signal. In
delayed or read-modify-write, OE must be high
to bring the output buffers to high impedance
prior to impressing data on the I/O lines.
Data Output:
TTL loads. Data-out is the same polarity as datain. The output is in the high-impedance (floating)
state until CAS is brought low. In a read cycle the
output goes active after the access time interval
tCAC that begins with the negative transition of
CAS as long as tRAC and tOEA are satisfied.
has elapsed and remains valid while CAS and
OE is low. CAS or OE going high returns it to a
high impedance state. In an early-write cycle,
the output is always in the high impedance state.
In a delayed-write or read-modify-write cycle,
the output must be put in the high impedance

state prior to applying data to the DQ input. This
is accomplished by bringing OE high prior to applying data, thus satisfy tOED,
Output Enable:
The OE controls the impedance of the output
buffers. When OE is high, the buffers will remain
in the high impedance state. Bringing OE low
during a normal cycle will activate the output buffers putting them in the low impedance state. It is
necessary for both RAS and CAS to be brought
low for the output buffers to go into the low impedance state. Once in the low impedance state,
they will remain in the low impedance state until
CAS or OE is brought high.
Page Mode:
low (0) throughout all successive memory
operations in which the row-address doesn't
change. Thus the power dissipated by the
negative going edge of RAS is saved. Further,
access and cycle times are decreased because
the time normally required to strobe a new
row-address is eliminated.
RAS Only Refresh:
Refresh of the dynamic memory cells is
accomplished by performing a memory cycle at
each of the 51 2 row-addresses (Ao to As) at least
every eight milliseconds. RAS only refresh
avoids any output during refresh because the
output buffer is in the high impedance state
unless CAS is brought low. Strobing each of 512
(Ao to As) row-addresses with RAS will cause all
bits in each row to be refreshed. Further
RAS-only refresh results in a substantial
reduction in power dissipation.
CAS before liAS" refreshing offers an
alternate refresh method. If CAS is held on low
for the specified period (tFCS) before RAS goes
to low, on chip refresh control clock generators
and the refresh address counter are enabled,
and an internal refresh operation takes place.
After the refresh operation is performed, the
refresh address counter is automatically
incremented in preparation for the next CAS
before RAS refr~sh operation.
Hidden Refresh:
maintaining latest valid data at the output by
extending CAS active time. Hidden refresh
means CAS before RAS refresh and the internal
refresh addresses from the counter are used to
refresh addresses, because CAS is always low
when RAS goes to low in this mode.
189
DYNAMIC RAM MSM414256RS - - - - - - - - - - - - - - - - CAS Before RAS Refresh Counter Test Cycle:

method of verifying the functionality of CAS"
in CAS before "RAS Counter Test Cycle, if CAS
goes to high and goes to low again while 'RAS is
counter test cycle. A memory cell address,
consisting of a row address (9 bits) and a
column address (9 bits), to be acceded can be
defined as follows:
A ROW ADDRESS
- Bits AD through As are defined by the
refresh counter.
A COLUMN ADDRESS
All the bits AD through As are defined by
latching levels on AD through As at the
second falling edge of CAS".
190

Procedure:

row addresses.
(Step (3.
steps (2), (3) and (4).
OKI
setnlconductor
.,.~
~-------------------------------------------~~~
MSM411000RS
1,048,576-WORD
x 1-BITS DYNAMIC RAM
GENERAL DESCRIPTION
The MSM411 OOORS is a new generation dynamic RAM organized as 1,048,576 words by 1 bit.
The technology used to fabricate the MSM411 OOORS is OKI's N channel silicon gate MOS process
technology. The device operates at a single +5V power supply. Its I/O pins are TTL compatible.
FEATURES
Silicon gate, tripple polysilicon NMOS,

1-transistor memory cell
1,048,576 words by 1 bit
Standard 1 8-pin plastic DIP

Family organization
Power Dissipation
Family
Access Time
(MAX)
Cycle Time
(MIN)
MSM411 000-1 ORS
100 ns
200 ns
413mW
MSM411 000-1 2RS
120 ns
230 ns
385mW
Single +5V supply, 1 0% tolerance

input latch
Output: TTL compatible, tristate, nonlatch
operation
Operating
(MAX)
Stand By
(MAX)
28mW
Page mode, read modify write capability

"Gated" CAS
Pin Names
AOtoA9
Function
Address Inpul
RAS
Row Address Strobe
CAS
DIN
Data Input
DOUT
Data Output
WE
Write Enable
VCC
Power Supply (+5V)
VSS
Ground (OV)
Refresh Address
191
_ DYNAMIC RAM MSM411 OOORS ___- - - - - - - - - - - - - - - -
i-----WE
Ao-A.
DOUT
Word
DrIvers
Memory
Cells
t-----DIN
----y--,______-'
VssVCC
OnchipVBB
Rating
Symbol
Conditions
Value
VT
Ta = 25C
los
Ta = 25C
50
Power disSipation
Po
Ta =25C
Unit
-1.0 to +7.0
V
mA
W
Topr
o to +70
DC
Storage temperature
Tstg
-55 to +150

(Ta = 0 to +70)
Parameter
MIN
TYP
MAX
Unit
4.5
5.0
5.5
VSS
Input high voltage
VIH
2.4
6.5
Input low voltage
VIL
-1.0
0.8
Supply Voltage
192
Symbol
Conditions
VCC
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ ___._ DYNAMIC RAM MSM411 OOORS _

DC CHARACTERISTICS
(VCC = 5V 1 0%, Ta = 0 to +70C)
Parameter
Symbol
MSM
MSM
411000-10 411000-12
Conditions
Output high voltage
VOH
IOH =-5.0 mA
Output low voltage
VOL
IOL=4.2 mA
Unit
MIN
MAX
MIN
MAX
2.4
2.4
0.4
0.4
III
OV ~ VI ~ 6.5V;
all other pins not
under test = OV
-10
10
-10
10
~A
ILO
DOUT disable
OV ~VO ~5.5V
-10
10
-10
10
~A

current" (Operating)
ICC1
RAS, CAS cycling,

tRC =min
75
70
mA
Power supply current"

(Standby)
ICC2
RAS=VIH
CAS=VIH
mA

current"
(RAS only refresh)
ICC3
RAS cycling,
CAS =VIH
tRC =min
65
60
mA

current"
(Page mode)
ICC4
RAS=VIL,
CAS cycling
tpc =min
70
65
mA

current"
(CAS before RAS refresh)
ICC5
RAScycling,
CAS before RAS
70
65
mA
Note
"Note: ICC is dependent on output loading and cycle rates. Specified values are obtained with the
output open.
CAPACITANCE
(Ta = 25C, f = 1 MHz)
Symbol
Conditions
TYP
Input capacitance (AO to A9, DIN)
CIN1
pF
Input capacitance
(RAS, CAS, WE)
CIN2
10
pF
COUT
pF
Parameter
MAX
Unit
193
DYNAMIC RAM MSM411 OOORS - - - - - - - - - - - - - - - - AC CHARACTERISTICS

Note 1,2,3 (VCC = 5V 1 0%, Ta
0 to +70C)
MSM411000-10 MSM411000-12
Parameter
Symbol
Unit
MIN
MAX
MIN
Note
MAX
Refresh period
tREF
Random read/write cycle time
tRC
200
230
ns
tRWC
235
255
ns
tpc
100
120
ns
tRAC
100
120
ns
4,6
tCAC
50
60
ns
5,6
tOFF
25
25
ns
Transition time
tT
50
50
ns
100
ns
--
RAS precharge time
--
RAS pulse width
tRP
90
ms
tRAS
100
10000
120
10000
ns
RAS hold time
tRSH
50
60
ns
CAS precharge time

tcp
40
50
ns
CAS pulse width
tCAS
50
CAS hold time
tCSH
100
tRCD
25
CAS and RAS set-up time
tCRS
15
tASR
tRAH
--
10000
60
10000
ns
ns
25
60
ns
20
ns
ns
15
15
ns
tASC
ns
tCAH
20
20
ns
Column address hold time from RAS,
tAR
70
80
ns
tRCS
ns
ns
120
50
I
tRCH
tWCR
80
95
ns
twcs
ns
tWCH
30
35
ns
194
7,8
10
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _........ DYNAMIC RAM MSM411000RS

AC CHARACTERISTICS (CONT.)
MSM411000-10 MSM411000-12
Parameter
Symbol
Unit
MIN
MAX
MIN
MAX
Note
twp
30
35
ns
tRWL
40
40
ns
tCWL
40
40
ns
Data-in set-up time
tDS
ns
Data-in hold time
tOH
30
35
ns
Data-in hold time from RAS
tOHR
80
95
ns
CAS to WE delay
tcwo
40
40
ns
RAS to WE delay
tRWD
90
100
ns

reference to RAS
tRRH
20
20
ns
10

(CAS before RAS)
tFCS
20
25
ns

(CAS before RAS)
tFCH
30
30
ns
CAS active delay from RAS

precharge
tRPC
20
20
ns
CAS precharge time

(CAS before RAS)
tCPR
20
25
ns
Read/write cycle
tRTC
355
385
ns
11
RAS pulse width

tTRAS
255
275
10000
ns
11
CAS precharge time

tCPT
11
Read/write cycle time (Page mode)
tpRWC
10000
50
60
ns
135
145
ns
195
DYNAMIC RAM MSM411 OOORS - - - - - - - - - - - - - - - - Notes:
An initial pause of 100 iJ-s is required after power-up followed by any 8 RAS cycles
2
3
The AC characteristics assume at tT = 5 ns
Assumes that tRCD ;:S tRCD (Max.). If tRCD

- tRCD (Max.)}.
5
6
7
Assumes that tRCD ~ tRCD (Max.).

Measured with a load circuit equivalent to 2TTL
VIH (Min.) and VIL (Max.) are reference levels for measuring of input signals. Also,
+ 100 pF.
+ 2tT + tASC (Min.).
9 twcs, tCWD and tRWD are not restrictive operating parameters. They are included in
196
10
the data sheet as electrical charcteristics only; if twcs ~ twcs (Min.), the cycle is an
early write cycle and the data out pin will remain open circuit (high impedance)
throughout the entire cycle; if tCWD ~ tCWD (Min.) and tRWD ~ tRWD (Min.) the cycle
is read-write cycle and the data out will contain data read from the selected cell; if
neither of the above sets of conditions is satisfied the condition of the data out (at
Either tRRH or tRCH must be satisfied for a read cycle.
11
- - - - - - - - - - - - - - - -___ DYNAMIC RAM MSM411 OOORS _
READ CYCLE
RAS V IH V IL -
CAS V IH VIL-
Address
WE
DOUT
V IH
V 1L
VIH
VIL
f------,;:-'''' ~ ___
V OH -
VOL - - - - - - -
------1
OPEN
Valid Data
~ Don't Care

tRC
_ _ _ _--.,j,
-
VIH-
RAS V I L _
t RAS
~-----------~I~~--------~
,Je------{.
~---tAR--~-~
tCSH
tRCD
VOH_
DOUT VOL
-------------------
OPEN
Don't Care
197
DYNAMIC RAM MSM411 OOORS ...- - - - - ' - - - - - - - - - - - -
V I H- --1r-~----.r-""
VIL-
DOUT
Oon'tCare
1 - - - - - - - - - - - tRAS
tAR---j
l'-----'--------rf----t-RSa::::=:.j----'
teA
tRP
tCRS
Address V IH
V 1L
'f
198
Don'teare
- - - - - - - - - - - ' - - - - - - - - . DYNAMIC RAM MSM411 OOORS
RAS V IR V IL -
Address VIR
VIL
WE
VIR
V IL
DIN
VIR
V IL
Don't Care

RAS VIR
tRAS
~~t_____
----'tA~R~---_~I----------~~~---------------------~~-~
V IL -
I------'I'--_ _-'t P RW"-----------i
tRS" _ _ _-I
teA S ------I
Address
WE
VIR~nT.~n77T,~-+-------~
V IL --=:..u...L.LJ..L:J
~ Don'tCare
199
DYNAMIC RAM MSM411 OOORS - - - - - - - - - - - - - - - - -
Note: CAS = VIH' WE and DIN not dependent on the high or low level.
Address
OPEN
~ Don'tCare
Note: Address WE and DIN not dependent on the high or low level.
DOUT
VOH VOL - - - - - - - - - - - -
OPEN
~ Don'tCare
200
-----------------11. DYNAMIC RAM MSM411 OOORS

RAS
VIH VIL -
CAS
VIH VIL -
Addresses
VIH VIL -
WE (Read)
VIH VIL-
DOUT
VOHvOL-
vIHWE
(Read-Write) V I L -
~ Don't Care
RAS
VIHVIL -
CAS
VIHVIL -
Addresses
vIHVIL-
---
VIH-
WE (Read) VIL _
~~~~~~~~~~~~~~--------------~~---i~~~
::.:::.:::."'""''"'"'""''"''"'="'''"'
DOUT
VIH- ~""~~~~~~~~~~~~ ~----------~,~~~~~~"
V IL -
~~~~~"''"'"''"'"'""''"'"'~ 1I-________-.JI
~ Don't Care
201
DYNAMIC RAM MSM411 OOORS - - - - - - - - - - - - - - - - -
Address Inputs:
to decode anyone of the 1,048,576 words by 1
bit storage cell locations.
input pins AO through A9 and latched onto the
column-address bits are set up on pins AO
. (gated) by the RAS to permit triggering of CAS as
soon as the Row Address Hold Time (tRAH)
specification has been satisfied and the address
Therefore specifications permit column
addresses to be input immediately after the row
address hold time (tRAH).
Write Enable:
the read mode is selected.
Data Input:
referenced to this signal. In a delayed write or
and hold times referenced to this signal.
Data Output:
TTL loads. Data-out is the same polarity as
data-in. The output is in the high-impedance
(floating) state until CAS is brought low. In a read
cycle the output goes active after the access
time interval tCAC that begins with the negative
transition of CAS as long as tRAC is satisfied.
has elapsed and remains valid while CAS is low.
CAS going high returns it to a high impedance
state. In an early-write cycle, the output is
always in the high impedance state.
Page Mode:
low (0) throughout all successive memory
202
operations in which the row-address doesn't

change. Thus the power dissipated by the
negative going edge of RAS is saved. Further,
access and cycle times are decreased because
the time normally required to strobe a new
row-address is eliminated.
RAS Only Refresh:
each of the 51 2 row-addresses (Ao to As) at least
is brought low. Strobing each of 512 (Ao to As)
each row to be refreshed. Further RAS-only refresh results in a substantial reduction in .power
dissipation.
CAS before RAS refreshing offers an
alternate refresh method. If CAS is held on low
for the specified period (tFCS) before RAS goes
to low, on chip refresh control clock generators
and the refresh address counter are enabled,
and an internal refresh operation takes place.
After the refresh operation is performed, the
refresh address counter is automatically
incremented in preparation for the next CAS
before RAS refresh operation.
Hidden Refresh:
maintaining latest valid data at the output by
extending CAS active time. Hidden refresh
means CAS before RAS refresh and the internal
refresh addresses from the counter are used to
refresh addresses, because CAS is always low
when RAS goes to low in this mode.
special timing sequence using CAS before
counter test cycle. A memory cell address,
consisting of a row address (9 bits) and a
column address (10 bits), to be acceded can be
defined as follows:
A ROW ADDRESS
- Bits Ao through As are defined by the
refresh counter.
A COLUMN ADDRESS
All the bits Ao through A9 are defined by
latching levels on Ao through A9 at the

Procedure:
row addresses.
(3)
(4)
(5)
By using read-modify-write cycle, read the

low written at the last operation (Step (2
written into the 51 2 memory cells.
Read the high written at the last operation
(Step (3.
Complement the test pattern and repeat the
steps (2), (3) and (4).
203
OKI
semiconductor
MSM411 001 RS
< Nibble Mode Type>
GENERAL DESCRIPTION
The Oki MSM411 001 is a fully decoded, dynamic NMOS random access memory organized as 1048576 one-bit words.
Multiplexed row and column address inputs permit the MSM411 001 to be housed in a standard 18 pin DIP. Pin-outs
conform to the JEDEC approved pin out. Additionally, the MSM411001 offers new functional enhancements that
make it more versatile than previous dynamic RAMs. "CAS-before-RAS" refresh provides an on-chip refresh capability, also features "nibble mode" which allows high speed serial access to up to 4 bits of data.
The MSM411001 is fabricated using sil icon gate NMOS and Oki's advanced VLSI Polysilicon process. This process,
coupled with single-transistor memory storage cells, permits maximum circuit density and minimal chip size. Dynamic
circuitry is employed in the design, including the sense amplifiers.
compatible.
FEATURES
.1048576 x 1 RAM, 18 pin package
Silicon-gate, Tripple Poly NMOS, single transistor cell
Row access time

100 ns max (MSM411001-10RS)
120 nsmax (MSM411001-12RS)
Cycle time
200 ns min (MSM411001-10RS)
230 ns min (MSM411001-12RS)
Low power: 411001-12RS
413 mW/28 mW (MSM411001-10RS)
385 mW/28 mW (MSM411001-12RS)
Single+5V Supply, 10% tolerance
Gated CAS
8ms/512 refresh cycles
operation
Read-Modify-Write, RAS-only refresh, capability
On-<:hip latches for Addresses and Data-in
On-<:hip substrate bias generator for high
performance
CAS-beforeRAS refresh capability
"Nibble Mode" capability
PIN CONFIGURATION
D,N
v"
WE
DOUT
RAS
CAS
NC
A,.
A,
A,
A,
vcc
204
A,
A,
A,
Pin Names
Function
Ao -At}
Address Inputs
RAS
CAS
WE
Write Enable
Row Address Strobe
DIN
Data Input
A,
DOUT
VCC
VSS
Data Output
Power (+5VI
Ground (OV)
A,
Refresh Address
- - - - - - - - - - - - - - - - - . DYNAMIC RAM MSM411 001 RS
BLOCK DIAGRAM
I----WE
OUT
Word
Drivers
VCC------~y~
VSS-
I _________
On chip VSS
ABSOLUTE MAXiMUM RATINGS
Memory
Cells
I - - - - - O IN
(See Note)
Rating
Symbol
Value
Unit
VIN, VOUT
-1 to +7
Vee
-1 to +7
Topr
o to 70
Storage temperature
T stg
-55 to +150
Power dissipation
Po
1.0
lOS
50
mA

(Referenced to VSS)
Parameter
Supply Voltage
Symbol
Vee
VSS
Min.
Typ.
Max.
Unit
4.5
0
5.0
0
5.5
0
V
V
VIH
2.4
6.5
VIL
-1.0
0.8
.V
Operating
Temperature
oOe to +70 o e
205
DYNAMIC RAM MSM411 001 RS . - - - - - - - - - - - - - - - - -
DC CHARACTERISTICS
Parameter
Symbol
MSM411001-10 MSM411001-12
Min
Max
Min
Max
Unit
OPERATING CURRENT"
ICC1
75
70
mA
STANDBY CURRENT*
Power su pply cu rrent
(RAS = CAS = VIH)
ICC2
mA
REFRESH CURRENT 1 *
(RAS cycling, CAS = VIH; tRC= min.)
ICC3
65
60
mA
Nibble MODE CURRENT*

(RAS = VIL, CAS cycling; tNC = min.)
ICC4
70
65
mA
REFRESH CURRENT 2*
ICC5
70
65
mA

(OV ::: V IN::: 5.5V, all other pins not
under test = OV)
III
-10
10
-10
10
/lA

OV ~ VOUT ~ 5.5V)
ILO
-10
10
-10
10
/lA
VOH
VOL
2.4
-
0.4
2.4
-
0.4
V
V
OUTPUT LEVELS
Output high voltage UOH = -5 mAl
Output low voltage UOL = 4.2 mAl
Notes
Not.": ICCis dependent on output loading and cycle rates. Specified values are obtained with the output open.
CAPACITANCE
(Ta
= 25C, f = 1 MHz)
Parameter
CIN1
CIN2
COUT
206
Symbol
Typ.
Max.
Unit
pF
10
pF
pF
- - - - - - - - - - - - - - - - - - 1 1 . DYNAMIC RAM MSM411 001 RS
AC CHARACTERISTICS
(Recommended operating conditions unless otherwise noded.)
Parameter
Symbol
Unit
MSM411001
10
Min
Max
MSM411001
12
Min
Notes
Max
8
tREF
ms
tRC
ns
200
tRWC
ns
235
tRAC
ns
100
120
4,6
50
60
5,6
Refresh period
tCAC
ns
tOFF
ns
Transition time
tT
RAS precharge time

RAS pulse width
8
230
255
25
ns
50
tRP
ns
90
tRAS
ns
100
RAS hold time
tRSH
ns
50
CAS pulse width
tCAS
ns
50
25
50
100
10l's
120
10l'S
60
CAS hold time
tCSH
ns
100
tRCO
ns
25
tCRS
ns
15
tASR
ns
tRAH
ns
15
15
50
25
tASC
ns
tCAH
ns
20
20
Column address hold time from RAS
tAR
ns
70
80
tRCS
ns
Read command hold time referenced to CAS
tRCH
ns
Read command hold time referenced to RAS
tRRH
ns
20
20
tWCR
ns
80
95 1
twcs
ns
twp
ns
30
35
tWCH
ns
30
35
tRWL
ns
40
40
tCWL
ns
40
40
tos
ns
Oata-in hold time
tOH
ns
30
35
Oata-in hold time from RAS
tOHR
ns
80
95
tcwo
ns
40
40
RAS to WE delay time
tRWO
ns
90
100
Refresh set-up time for CAS referenced to RAS
tFCS
ns
20
25
Refresh hold time for CAS referenced to RA::;
tFCH
ns
30
30
CAS precharge time (C before R cycle)
tCPR
ns
20
25
RAS precharge to CAS active time
tRPC
ns
20
20
Nibble mode read/write cycle time
tNC
ns
65
70
Nibble mode read-write cycle time
tNRWC
ns
65
70
Nibble mode access time
tNCAC
ns
Nibble mode CAS pulse width
tNCAS
ns

Oata-in set-up time
30
30
60
20
10 I'S
120
10l's
60
9
9
35
35
9
9
207
DYNAMIC RAM MSM411001 RS - - - - - - - - - - - - - - - -
Parameter
Nibble mode CAS precharge time

Nibble mode read RAS hold time
Symbol
Unit
MSM411001
10
MSM411001
12
Min
Min
Max
Notes
Max
tNCP
ns
25
25
tNRRSH
ns
40
40
40
40
tNWRSH
ns
Nibble mode CAS hold time referenced to RAS
tRNH
ns
20
20
Refresh counter test cycle time
tRTC
ns
355
385
10
Refresh counter test RAS pulse width
tTRAS
ns
255
tCPT
ns
50
Nibble mode write RAS hold time
Refresh counter test CAS precharge time
10,000
275
60
10,000
10
10
NOTES: 1) An initial pause of 100 IJS is required after power-up followed by any 8 RAS cycles (Examples; RAS
4) Assumes that tRCO ~ tRCO (max.).
If tRCO is greater than the maximum recommended value shown in this table, tRAC will increase by
the amount that tRCO exceeds the values shown.
5) Assumes that tRCO ~ tRCO (max.)
6) Measured with a load circuit equivale.nt to 2 TTL loads and 100 pF.
7) Operation within the tRCO (max.) limit insures that tRAC (max.) can be met. tRCO (max.) is specified as a reference point only; if tRCO is greater than the specified tRCO (max.) limit, then access
8) twcs, tcwo and tRWO are not restrictive operating parameters. They are included in the data dheet
as electrical characteristics only; if twcs2:twcs (min.). the cycle is an early write cycle and the data
out pin will remain open circuit (high impedance) throughout the entire cycle; if tcwo2:tcwo(min.),
and tRWO 2:tRWO (min.) the cycle is read-write cycle and the data out will contain data read from the
selected cell; if neither of the above sets of conditions is satisfied the condition of the data out (at
acccess time) is indeterminate.
9) Nibble mode cycle.
10) CAS before RAS Refresh Counter Test Cycle only.
208
------------------11. DYNAMIC RAM MSM411 001 RS

READ CYCLE
tRC
RAS
VIHVIL-
CAS
vIHVIL-
Addresses
VIHVIL-
WE
VIHVIL-
DOUT
VOL-
Don'teara
RAS
CAS
Addresses
WE
VIHVIL-
vIHVIL-
VIHVILVIHVIL -
DIN
DOUT
-------------11
OPEN
~I- - - - - - - - - - - -
Don'teare
209
DYNAMIC RAM MSM411 001 RS . - - - - - - - - - - - - - - - - -
READ-WR ITE/READ-MODI FY-WRITE CYCLE
DOUT
Don'tCare
NIBBLE MODE READ CYCLE
VIH- ~~~~~~~------~~~~--~~~------~~~--------~~
V IL -
"""'"""'""~"'
DOUT
~ Don't Care
210
_________________1. DYNAMIC RAM MSM411 001 RS

NIBBLE MODE WRITE CYCLE
RAS
VIHVIL -
CAS
Addresses
WE
DIN
VIHVIL -
VIHVIL -
VIHVIL -
VIHVIL vOH-
DOUT
VOL-
Don't Care
NIBBLE MODE READ-WRITE CYCLE
RAS
VIHVIL -
CAS
Addresses
WE
DOUT
DIN
VIHVIL -
11
VIHVIL -
VIHvIL-
VOHVOL-
VIHVIL-
Don't Care
211
_ DYNAMIC RAM MSM411 001 RS ___- - - - - - - - - - - - - - - - -
NOTE: CAS = VIH, WE, DIN = Don't care
DOUT
VOHVOL-
-----------"""il
OPEN
~ Don'teare
RAS
VIH VIL -
CAS
VIHVIL-
DOUT
VOHVOL-
roe>
----------~I
= Don't care
OPEN
~ Don'teare
212
- - - - - - - - - - - - - - - - - . DYNAMIC RAM MSM411 001 RS
RAS
VIHVIL -
CAS
VIH VIL -
Addresses
VIH VIL -
WE (Read)
VIHVIL -
DOUT
vOHVOL-
WE
VIH-
(Read-Write) V1L-
~ Don't Care
RAS
VIHVIL-
CAS
VIHvIL-
Addresses
VIHVIL-
VIH-
'777"""",""""''''"'''''''''''''''"''''''''''"'''''''''''''''''''''"'
VI L -
"""''''"'''''''''"''''''''''....'''"'''''''''"''''''''''"''''''''''.....:u "1'--_ _ _ _Jr
l..-------J ,..,.,..,.,,,.,.,,.,..,.,,,.,.,""""'"'"
"'"'~'"'~'"'~"
~ Don't Care
213
DYNAMIC RAM' MSM411 001 RS ----------------~

DESCRIPTION
Simple nming Requirement
The MSM411001 has the circuit considerations for easy
operational timing requirements for high speed access
time operations. The MSM411001 can operate under
the condition of tRCD (max) = tCAC which provides an
optimal time space for address mUltiplexing. In addition, the MSM411001 has the minimal hold times of
Address (tCAH), WE (tWCH) and DIN (tDHl. And
the MSM411001 can commit better memory system
through-put during operations in an inter-leaved system.
Fast Read- While-Write cycle

The MSM411001 has the fast read while write cycle
which is achieved by excellent control of the three-state
output buffer in addition to the simplified timings
described in the previous section. The output buffer is
controlled by the state of WE when CAS' goes low.
When WF. is low during CAS transition to low, the
MSM411001 goes to early write mode where the output
becomes floating and common 1/0 bus can be used on
the system level. Whereas, when WE goes low after
tCWDfoliowing CAS transition to low, the MSM411001
goes to delayed write mode where the output contains
the data from the cell selected and the data from 0 I N
is written into the cell selected. Therefore, very fast
read write cycle becomes available.
Address Inputs
A total of twenty binary input address bits are required
to decode any 1 of 1048576 storage cell locations within the MSM411 001. Nine row-address bits are established on the input pins (Ao through A,) and latched with
the Row Address Strobe (RAS). Then ten column
address bits are established on the input pins and latched with the Column Address Strobe (CAS). All input
addresses must be stable on or before the falling edge of
RAS. CAS is internally inhibited (or "gated") by RAS
to permit triggering of CAS as soon as the Row Address
Hold Time (tRAH) specification has been satisfied
and the address inputs have been changed from rowaddresses to column-addresses.
Write Enable
The read or write mode is selected with the WE input.
A logic "high" on WE dictates read mode, logic "low"
dictates write mode. Data input is disabled when read
mode is selected.
Data Input
a strobe for the Data in (DIN) register. In a write cycle,
if WE is brought "low" (write mode) before CAS, DIN
214
is strobed by CAS, and the set-up and hold times are

referenced to CAS. In a read-write cycle, WE will be
delayed until CAS has made its negative transition.
Data Output
The output buffer is three-state TTL compatible with a
fan-out of two standard TTL loads. Data out is the
same polarity as data in. The output is in a high impedance state until CAS is brought "low". In a read cycle,
or a read-write cycle, the output is valid after tRAC
from transistion of RAS when tRCD(max) is satisfied,
or after tCAC from' transition of CAS when the transition occurs after tRCD (maxl. Data remain valid until
CAS is returned to "high". In a write cycle, the identical sequence occurs, but data is not valid.
Nibble Mode
Nibble mode allows high speed serial read, write or readmodify-write access of 2, 3 or 4 bits of data. The bits
of data that may be accessed during nibble mode are
determined by the 9 row addresses and the 9 column
addresses. The 2 bits of addresses (CA, RA,) are used
to select 1 of the 4 nibble bits for initial access. After
the first bit is accessed by normal mode, the remaining
nibble bits may be accessed by CAS "high" then "low"
while RAS remains "low". Toggling CAS causes RA,
and CA, to be incremented internally while all other
address bits are held constant and makes the next nibble
bit available for access. (See Table 1)
If more than 4 bits are accessed during nibble mode, the
address sequence will begin to repeat. If any bit is
written during nibble mode, the new data will be read
on any subsequent access. If the write operation may
be executed again on subsequent access, the new data
will be written into the selected cell location.
In nibble mode, the three-state control of DOUT Pin is
determined by the first normal access cycle.
The data output is controlled by only WE state referenced at CAS negative transition of the normal cycle
(first Nibble bitl. That is, when twcs > twcs (min) is
met, the data output will remain open ci rcuit throughout the succeeding Nibble cycle regardless of WE state.
Whereas, when tCWD > tCWD (min) is met, the data
output will contain data from the cell selected during
the succeeding nibble cycle regardless of WE state. The
write operation is done during the period where WE and
CAS clocks are low. Therefore, write operation can be
done bit by bit during each nibble operation at any
timing conditions of WE (twcs and tCWD) at the
normal cycle (first Nibble bit).
- - - - - - - - - - - - - - - - - . DYNAMIC RAM' MSM411 001 RS

Table 1
NIBBLE MODE ADDRESS SEQUENCE EXAMPLE
NIBBLE BIT
RA,
SEQUENCE
ROW ADDRESS
RAS/CAS {normal model
101010101
101010101
toggle CAS (nibble model
101010101
101010101
101010101
101010101
101010101
101010101
101010101
RAS only Refresh

by perform ing a memory cycle at each of the 512 rowaddresses (Ao through Asl at least every 8 millisecond.
because the buffer is in the high impedance state unless
CAS is brought "low". Strobing each of the 512 rowaddresses (Ao through Asl with RAS will cause all bits
in each row to be refreshed. Further RAS only refresh
results in a substantial reduction in power dissipation.
CAS before RAS Refresh

CAS before
RAS
refreshing available on
the
MSM411001 offers an alternate refresh method. If
CAS is held on "low" for the specified period (tFcsl
before RAS goes to "low", on chip refresh control clock
generators and the refresh address counter are enabled,
and an internal refresh operation takes place. After the
refresh operation is performed, the refresh address
counter is automatically incremented in preparation
for the next CAS before RAS refresh operation.
Hidden refresh cycle may takes place while maintaining

latest valid data at the output by extending CAS active
from
the
previous
memory
read
cycle.
speCial
sequence repeats

Procedure
The timing as shown in CAS before RAS Counter Test
Cycle is used for all the operations described as follows:
(11
Initialize the internal refresh counter.

operation, 8 cycles are required.
(21
Write a test pattern of data "low" into memory

cells at a single column address and 512 row
addresses.
(31
By using read-modify-write cycle, read the "low"

written at the last operation (Step (211 and write
a new data "high" in the same cycle. This cycle is
repeated 512 times, and data "high" are written
into the 512 memory cells.
Read the data "high" written at the last operation
(Step (311.
Complement the test pattern and repeat the steps
(21, (31 and (41.
(41
(51
CAS before RAS Refresh Counter Test

Cycle
101010101
generated internally
A ROW ADDRESS - Bits Ao through As are defined

by the refresh counter.
The other bit A, is set "high" internally.
A COLUMN ADDRESS - All the bits Ao through A,
are defined by latching levels on Ao throgh A, at the
In
MSM411001 hidden refresh means CAS before RAS

refresh and the internal refresh addresses from the
counter are used to refresh addresses, because CAS is
always "low" when RAS goes to "low" in hidden
refresh.
----- input addresses
As shown in CAS before RAS Counter Test Cycle, if

CAS goes to "high" and goes to "low" again while RAS
is held "low", the read and write operations are enabled.
A memory cell address (consisting of a row address (10
bitsl and a column address (10 bitsll to be accessed can
be defined as follows:
Hidden Refresh
time
COLUMN ADDRESS
CA,
For this
timing sequence using CAS before RAS
counter test cycle provides a convenient method of verifying the functionality of CAS before RAS refresh
activted circuitry.
215
DYNAMIC RAM MSM411 001 RS
.1-----------------
NIBBLE MODE
1) The case of first nibble cycle is Early write
~~
__________________________
~r__
'~ ___-JI
''-_...JI
DOUT
:)>-_____________HiQh-Z _ _ _ _ _ _ _ _ _ _ _ _ _ __
~ Early Write~NO Ope.
-tl...--Write~
..I.
w r i t e - -......
(Add Increment)
~: Valid Data
2) The case of first nibble cycle is delyed write (Read-Write)

~
RAS
\~.
_______________________-...J'
,--
\ ' - -_ _ _- J
\\.... _ _.....J
---~---------~~-DOUT
. I.
~ Read-Write
Read-Write-----t..-- Read-------+,- Read-Write .......
~: Valid Deta
FUNCTIONAL TRUTH TABLE

RAS
CAS
WE
DIN
DOUT
Read
Write
Refresh
Don't Care
Don't Care
High-Z
No
No
No
Standby
Don't Care
Valid Data
Yes
No
Yes
Read
Valid Data
High-Z
No
Yes
Yes
twcs ~ twcs (min)
Valid Data
Valid Data
Yes
Yes
Yes
tCWD ~ tCWD (min)
Don't Care
Don't Care
High-Z
No
No
Yes
RAS Only Refresh
Note
Early Write
Delayed Write or Read-Write
Don't Care
Don't Care
Valid Data
No
No
Yes
CAS-before-RAS Refresh Valid

data selected at previous Read
or Read-Write cycle is held.
Don't Care
Don't Care
High-Z
No
No
No
CAS disturb.
216
OKI
semiconductor
$~~~
--------------------------------------------------------------------------
~~
MSM511000RS
1,048,576-WORD x 1-BIT DYNAMIC RAM <Fast Page>
GENERAL DESCRIPTION
The MSM511 OOORS is a new generation dynamic RAM organized as 1,048,576 words by 1 bit.
The technology used to fabricate the MSM511 OOORS is OKl's silicon gate CMOS process technology. The device operates from a single +5V power supply. Its I/O pins are TTL compatible.
FEATURES
Silicon gate, N-well CMOS, 1 -transistor

memory cell

Family organization
Power Dissipation
Family
Access Time
(MAX)
Cycle Time
(MIN)
MSM511000-1ORS
100 ns
190 ns
385mW
MSM511000-12RS
120 ns
220 ns
330mW
Operating
(MAX)
Standby
(MAX)
11 mW

input latch
Output: TTL compatible, tristate, nonlatch
operation
Fast page mode, read modify write capability

"Gated" CAS
DOUT
Memory
Cells
1--------- DIN
--------~---
VCC
vss--
'-__________---'
OnchipVBB
217
OKI
semiconductor
----------------------------------------------------MSM511 001 RS
1,048,576-WORD x 1-BIT DYNAMIC RAM <Static Column>
GENERAL DESCRIPTION
The MSM511 001 RS is a new generation dynamic RAM organized as 1,048,576 words by 1 bit.
The technology used to fabricate the MSM511 001 RS is OKI's silicon gate CMOS process technology. The device operates from a single +5V power supply. Its 1/0 pins are TTL compatible.
FEATURES
Silicon gate, N-well CMOS, 1-transistor
memory cell

Family organization
Power Dissipation
Family
Access Time
(MAX)
Cycle Time
(MIN)
MSM511 001-1 ORS
100 ns
190 ns
385mW
MSM511001-12RS
120 ns
220 ns
330mW

input latch
Operating
(MAX)
Standby
(MAX)
11 mW
Common 1/0 capability using "Early Write"

operation
Static column mode, read modify write
capability
RAS only refresh capability
Suilt-in VSS generator circuit
Column I -_ _ _ _ _~r-----.,
Address
Buffers 1 - - - - - - - - - . /
L..,..----,-J
1 - . , - - - WE
~~~(r--es
A.-A.
DOUl
Row
Address
Buffers
Row
----Y--
VSSVec
218
Decoders
Word
Drivers
L _ _ _ _ _---l
OnchipVBB
Memory
Cells
~;:-:-l====~
DIN
.-=C=-.--=-K
__I_---=s~e_rn_l___=_c_O_ncl_U_C_.or
_ _ _ _ _ _~~
MSM514256RS
262,144-WORD x 4-BIT DYNAMIC RAM <Fast Page>
GENERAL DESCRIPTION
The technology used to fabricate the MSM514256RS is OKI's silicon gate CMOS process technology. The device operates from a single +5V power supply. Its I/O pins are TTL compatible.
FEATURES

memory cell

Family organization
Cycle Time
(MIN)
Power Dissipation
Family
Access Time
(MAX)
MSM514256-10RS
100 ns
190 ns
413mW
MSM514256-12RS
120 ns
220 ns
385mW

input latch
Operating
(MAX)
Standby
(MAX)
11 mW
Fast page mode, read modify write capability

"Gated" CAS
t - - - - - WE
OQ,-OQ,
Memory
Cells
----Y--
vssVce
L _ _ _ _ _---'
OnchipVBB
219
O
__K
__I__se
__rn_IC_O_nc:I
__
U_C_._or
______
~
MSM514257RS
262,144-WORD x 4-BIT DYNAMIC RAM <Static Column>
GENERAL DESCRIPTION
The technology used to fabricate the MSM514257RS is OKl's silicon gate CMOS process
technology. The device operates from a single +5V power supply. Its I/O pins are TTL compatible.
FEATURES

memory cell

Family organization
Power Dissipation
Family
Access Time
(MAX)
Cycle Time
(MIN)
MSM514257-10RS
100 ns
190 ns
413mW
MSM514257-12RS
120 ns
220 ns
385mW

input latch
Operating
(MAX)
Standby
(MAX)
11 mW

Static column mode, read modify write
capability
RAS only refresh capability
Column 1 - - - - - -........ 1
Address
Buffers 1 - - - - - - - - - /
I--~--WE
L....r---......
.~~~r:t-- cs
Ao-A,
Row
Address
Buffers
DQ,-DQ,
Row
De-
coders
----y--'-_____--'
vssVCC
OnchipVBB
220
Memory
Cells
OKI semiconductor
MSM37S64ARS/37S64RS
131 ,072-BIT DYNAMIC RANDOM ACCESS MEMORY
GENERAL DESCRIPTION
The Oki MSM37S64 is a fully decoded dynamic NMOS random access memory organized as
131,072 one-bit words using 65,536 bit stacked. The design is optimized for high-speed, high performance applications such as main-frame memory, buffer memory, peripheral storage and environments where low power dissipation and compact layout is required.
Multiplexed row and column address inputs permit the MSM37S64 to be housed in a standard 16
pin DIP.
The MSM37S64 is fabricated using silicon gate NMOS and Oki's advanced Double-Layer Polysilicon process. This process, coupled with single-transistor memory storage cells, permits maximum
circuit density and minimum chip size. Dynamic circuitry is employed in the design, including the
sense amplifiers.
FEATURES

transistor cell
Row access time:
150 ns max (MSM37S64-15)
200 ns max (MSM37S64-20)
Cycle time:
270 ns min (MSM37S64-15)
330 ns min (MSM37S64-20)
Low power:

"Gated" CAS
operation
Read-Modify-Write, RAS-only refresh, and
Page-Mode capability
performance

Pin Names
DIN
VSS
WE
CAS
RAS1
Function
Ao-A.
Address Inputs
RAS1, RAS2
Row Address Strobe
CAS
WE
Write Enable
DIN
Data Input
DOUT
RAS2
As"
Ao"
A!
A,"
A?
A,"
As"
A
DOUT
Data Output
VCC
Power Supply (+5V)
VSS
Ground (OV)
" Refresh Address

1. Designates Bottom Module
2. Designates Top Module
221
DYNAMIC RAM MSM37S64ARS/37S64RS
.1-----------,..---
FUNCTIONAL BLOCK DIAGRAM (ONE MODULE)
I----WE
DOUT
Row
Address
Buffers
1 - - - - - - DIN
----y--'-_____--'
vss-
VCC
Memory
Cells
OnchipVBB
(See Note)
(TA = 25C unless otlierwise noted)

Rating
Symbol
Value
Unit
VIN. VOUT
-1 to +7
Vee
-1 to +7
Topr
a t070
Storage temperature
Tstg
-55 to +150
Power dissipation
Po
los
50
mA
Note: Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. Functional operation
should be restricted to the conditions as detailed in the operational sections of this data sheet. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
222
- - - - - - - - - - - -____ DYNAMIC RAM MSM37S64ARS/37S64RS _
RECOMMENDED OPERATING CONDITIONS (Referenced to VSS)

Parameter
Symbol
Min.
Typ.
Max.
Unit
VCC
4.5
5.0
5.5
VSS
Operating
temperature
Supply Voltage
OC to +70C
Input High Voltage,
all inputs
VIH
2.4
6.5
Input Low Voltage,

all inputs
VIL
-1.0
0.8
DC CHARACTERISTICS
Parameter
Symbol
Min.
Max.
Unit
Note
Operating Current* - One Module

Selected
Avera~wer supply current
(RAS, CA cycling; tRC = min.)
ICC1
65
rnA
Standby Current
Power S~y current
(RAS = CA = VIH)
ICC2
10
rnA
Refresh Current*- One Module Selected

(RAS cycling, CAS = VIH; tRC =min.)
ICC3
45
rnA
Page Mode Current* - One Module

Selected
(RAS = VIL, CAS cycling; tpc =min.)
ICC4
65
rnA
Refresh Current* - Two Module

Selected
(RAS cycling, CAS = VIH: tRC = min.)
ICC5
80
rnA

(OV ~ VIN ~ 5.5V, all other
pins not under test = OV)
1L1
-10
10
p..A

OV ~ VOUT ~ 5.5V)
ILO
-10
10
p..A
VOH
2.4
Output Levels
Output high voltage
OOH=-5mA)
Output low voltage
OOL=4.2mA)
VOL
V
0.4
Note: ICC is dependent on output loading and cycle rates. Specified values are obtained with the
output open.
223
DYNAMIC RAM MSM37S64ARS/37S64RS - - - - - - - - - - - - CAPACITANCE

(Ta= 25C, f = 1 MHz)
Symbol
Max.
Unit
Input Capacitance (Ao - A7, DIN)
CIN1
10
pF
Input Capacitance (RAS1, RAS2)
CIN2
10
pF
Input Capacitance (CAS)
CIN3
15
pF
Input Capacitance (WE)
CIN4
12
pF
COUT
14
pF
Parameter
AC CHARACTERISTICS
Parameter
Symbol
Units
Note 1,2,3
MSM37S6415
MSM37S6420
Min.
Min.
Max.
Note
Max.
Refresh period
tREF
ms

cycle time
tRC
ns
270
330
tRWC
ns
270
330
tpc
ns
170
225
tRAC
ns
150
200
4,6
tCAC
ns
100
135
5,6

delay
tOFF
ns
40
50
Transition time
tT
ns
35
50
RAS precharge time
tRP
ns
100
RAS pulse width
tRAS
ns
150
RAS hold time
tRSH
ns
100
135
CAS precharge time
tcp
ns
60
80
CAS pulse width
tCAS
ns
100
CAS hold time
tCSH
ns
150
tRCD
ns
25
CAS to RAS precharge

time
tCRP
ns
tASR
ns
224
120
10,000
10,000
200
135
10,000
10,000
200
50
30
65
- - - - - - - - - ' - - - - _ _ . _ DYNAMIC RAM MSM37S64ARS/37S64RS -
Parameter
Symbol
Units
MSM37S6415
MSM37S6420
Min.
Min.
Max.
Note
Max.
tRAH
ns
15
20
Column Address set-up

time
tASC
ns
Column Address hold

time
tCAH
ns
45
55
Column Address hold

tAR
ns
95
120
Read command set-up

time
tRCS
ns
tRCH
ns

time
twcs
ns
-10
-10
tWCH
ns
45
55

referenced to RAS
tWCR
ns
95
120
Write command pulse

width
twp
ns
45
55
Write command to RAS

lead time
tRWL
ns
45
55
Write command to CAS

lead time
tCWL
ns
45
55
Data-in set-up time
tos
ns
Data-in hold time
tOH
ns
45
55
Data-in hold time

referenced to RAS
tOHR
ns
95
120
CAS to WE delay
tcwo
ns
60
80
RAS to WE delay
tRWO
ns
110
145
Read command hold

tRRH
ns
20
25
225
DYNAMIC RAM MSM37S64ARS/37S64RS ...- - - - - - - - - - - - -
AC CHARACTERISTICS
Parameter
Symbol
Units
Note 1,2,3
MSM37S64A15
MSM37S64A20
Min.
Min.
Max.
Note
Max.
Refresh period
tREF
ms

cycle time
tRC
ns
260
330
tRWC
ns
280
345
tpc
ns
145
190
tRAC
ns
150
200
4,6
tCAC
ns
75
100
5,6

delay
tOFF
ns
40
50
Transition time
tT
ns
35
50
RAS precharge time
tRP
ns
100
RAS pulse width
tRAS
ns
150
RAS hold time
tRSH
ns
75
100
CAS precharge time

(page mode only)
tcp
ns
60
80
CAS precharge time
tCPN
ns
35
45
CAS pulse width
tCAS
ns
75
CAS hold time
tCSH
ns
150
tRCO
ns
25

time
tCRP
ns
tASR
ns
tRAH
ns
15
20
Column Address-set-up
time
tASC
ns
Column Address hold

time
tCAH
ns
20
25
Column Address hold

tAR
ns
95
125
Read command set-up

time
tRCS
ns
226
120
10,000
10,000
200
100
10,000
10,000
200
75
30
100
- - - - - - - - - - - -______ DYNAMIC RAM MSM37S64ARS/37S64RS _
Parameter
Symbol
Units
MSM37S64A15
MSM37S64A20
Min.
Min.
Max.
Note
Max.
tRCH
ns

time
twcs
ns
-10
-10
tWCH
ns
45
55

referenced to RAS
tWCR
ns
120
155
Write command pulse

width
twp
ns
45
55

lead time
tRWL
ns
45
55

lead time
tCWL
ns
45
55
Data-in set-up time
tDS
ns
Data-in hold time
tDH
ns
45
55
Data-in hold time

referenced to RAS
tDHR
ns
120
155
CAS to WE delay
tCWD
ns
45
55
RAS to WE delay
tRWD
ns
120
155
Read command hold

tRRH
ns
Notes:
An initial pause of 100 P.s is required after power-up followed by. any 8 RAS cycles
= 5 ns
AC measurements assume at tT
VIH (Min.) and VIL (Max.) are reference levels for measuring timing of input Signals. Also
transition times are measured between VIH and VIL.
Assumes that tRCD < tRCD (Max.)

If tRCD is greater than the maximum recommended value shown in this table, tRAC will
increase by the amount that tRCD exceeds the value shown.
Assumes that tRCD < tRCD (Max.).

6
7
the data sheet as electrical characteristics only; if twcs ~ twcs (min.), the cycle is an
early write cycle and the data out pin will remain open circuit (high impedance) throughout the entire cycle; if tCWD ~ tCWD (min.) and tRWD > tRWD (min.) the cycle is readwrite cycle and the data out will contain data read from the selected cell; if neither of the
above sets of conditions is satisfied the condition of the data out (at access time) is
indeterminate.
227
DYNAMIC RAM MSM37S64ARS/37S64RS - - - - - - - - - - - - -
READ CYCLE TIMING
~-----------------tRC-----------------1~
"I
~-----------tRAs------------~
RAS1, RAS2 vVIH IL -
--___._1
1-----tAR
Ir-------'
'-----
1-----+--tRsH-----i
VII.j _
---..:....:...---+---.- f----+--tCAS----I r--lo------..
VIL -
VIHAddresses V I L -
tRCS~
~IIHL=~
!---tCAC
~1~-------tRAC----------~
DOUT VOHVOL-
--------..,1
OPEN
Valid Data
~"H", "L" = Don't
228
Care
- - - - - - - - - - - -____ DYNAMIC RAM' MSM37S64ARS/37S64RS _
WRITE CYCLE TIMING

(EARLY WRITE)
tRSH
_ _ _-++==~~=;II-tCAS-----1 .t!--Ir-"';;;';"~-"----,.
Addresses
V,H - ~
V,L
-~~~~~~Jt~~~=t~~t=~::~~::~~~~~~~~~
V IH -
DOUT
77'77:~"'7/'77i7'7'!"77,",
1;--"'---.,.1
n-r7"T7".,.....,..,.,...,...,'"?'"?'rr.,..,.,-r7"T7",..,.,,..,..,.~
V,L - ';"':"'~~~"""I~~'-V r-------"] '(.""'-~~~~~:...:...:~""'-~~""'-"-"f----tDHR------I

VOH- _ _ _ _ _ _ _--1
OPEN
VOL~ "H", "L" =Don't Care
RAS1.RAS2~:~ ::::
tRWC-tRAS
tAR
tRSH
tCAS
CAS
V,H V,L tCSH
Addresses
WE
V,H V,L V,H V,L tCAC
DOUT
VOHVOL-
D,N
V,H V,L -
tOFF
~--H-----~
229
_ DYNAMIC RAM MSM37S64ARS/37S64RS ___- - - - - - - - - - - -

(CAS: VIHo WE & DIN: Don't care)
~:~ _~
~RAH~
tASR
Addresses
DOUT
VOH -
____________
RowAddress
OPEN
VOL -
~"H",
"L" = Don't Care
tRAS----------------4;}--~
- - - - VIHRAS1,RAS2VIL_
~------~----------------~
tRSH
tCAS
VIHAdresses V I L -
tRP
tCRP
~"H" ,"L"= Don't Care
230
- - - - - - - - - - - -__ DYNAMIC RAM MSM37S64ARS/37S64RS _
Addresses
VIH -=,*'?n~1
VIL-~"f~~~~~~~~~~~~~~~~~~~~~~~~~
DIN
VIH -
~m~.J.""':':'-=~.L",~"-j,.~""':;;~_~7""'~fJ,.;. [,-~;...;..."j ,",,-rr,..,..,~...,...,"""
vlL ~ "H", "L" = Don't
Care
RAS1,RAS2 VIH VIL CAS VIH VIL -
Addresses
WE
VIH VIL -
DIN
VIH VIL -
DOUT VOHVOL~
231
DYNAMIC RAM MSM37S64ARS/37S64RS - - - - - - - - - - - - -
HIDDEN REFRESH
VIH_
Addresses V I L -
vlL
VIH--
~
tCAC
~tRAC
VOL-_ ____ OPEN

DOUT VOH-
_~----------------------Valid Data
______________________
_
Address Inputs:
A total of sixteen binary input address bits
are required to decode any 1 of 65536 storage
cell locations within the one module. Eight rowaddress bits are established on the input pins
(Ao - A7) and latched with the Row Address
Strobe (RAS). The eight column-address bits are
established on the input pins and latched with
the Column Address Strobe (CAS). All input addresses must be stable on or before the falling
edge of RAS, CAS is internally inhibited (or
"gated") by RAS to permit triggering of CAS as
to column-addresses. The top module or bottom
module is selected with RAS1 input and RAS2
input.
Write Enable:
the WE input. A logic high (1) on WE dictates
read mode; logic low (0) dictates write mode.
Data input is disabled when read mode is
selected.
Data Input:
Data is written into the MSM37S64 during a
WE or CAS is a strobe for the Data In (DIN)
register. In a write cycle, if WE is brought low
232
CAS. In a read-write cycle, WE will be delayed

Data Output:
Data-out is the same polarity as data-in. The
brought low. In a read cycle, or read-write cycle,
~output is valid after tRAC from transition of
RAS when tRCD (Max.) is satisfied, or after tCAC
from transition of CAS when the transition
occurs after tRCD (Max.). Data remain valid until
CAS is returned to a high level. In a write cycle
the identical sequence occurs, but data is not
valid.
Page Mode:
row-address into the MSM37S64 while maintaining RAS at a logic low (0) throughout all successive memory operations in which the rowaddress doesn't change. Thus the power dissipated by the negative going edge of RAS is
saved. Further, access and cycle times are decreased because the time normally required to
strobe a new row-address is eliminated.
Refresh:
______________1. DYNAMIC RAM' MSM37S64ARS/37S64RS

each of the 128 row-addresses (AD - Ae) at
least every two milliseconds. During refresh,
either VIL or VIH is permitted for A7. RAS only refresh avoids any output during refresh because
the output buffer is in the high impedance state
dissipation.
Hidden Refresh:
RAS ONLY REFRESH CYCLE may take place
while maintaining valid output data. This feature
is referred to as Hidden Refresh.
Hidden Refresh is performed by holding CAS
as VIL from a previous memory read cycle.
233
_O_K
__I__se_rn_I_C_O_nc:I_U_c_.o_r_ _ _ _~
~
MSC2301 YS9/KS9
- ~
65,536 BY 9 BIT DYNAMIC RAM MODULE
GENERAL DESCRIPTION
The Oki MSC2301 YS9/KS9 is a fully decoded, 65,536 words x 9 bit NMOS dynamic random
access memory composed of nine 64K DRAMs in plastic leaded chip carrier. The mounting of nine
PLCCs together with nine 0.2J.tF decoupling capacitors on a 30 pin glass epoxy Single-In-Line Package provides any application where high density and large capacity of storage memory are required.
The electrical characteristics of the MSC2301 YS9/KS9 are quite same as the original MSM3764A;
each timing requirements are noncritical, and power supply tolerance is very wide.
FEATURES
65,536 word x 9 bit Organization
Single +5V Supply (10% Tolerance)
30-Pin Socket Insertable Module
Refresh Period ... 2ms (128 cycles)
All Inputs, Outputs, Clocks
Fully TTL compatible
3-States Outputs
Common CAS Control for Eight Common
Data-In and Data-Out Lines
Separate CAS Control for One Separate Pair

of Data-In and Data-Out Lines
Row Access Time;
120ns max. (MSC2301-12YS9/KS9)
Low Power Dissipation;
2970mW max. (MSC2301-12YS9/KS9)
2725mW max. (MSC2301-15YS9/KS9)
Operating Temperature ... OC to 70C

A.-
A'Sf-+- r:;:;::-;:-
f---
t---
001
i-+-
e:All
J----. CAS
WE
IOvre
visWil
r----
RAS
f---o
CAS
DQ5
1 ~~
i-+- -t::;::-L
1---0 RAS
I---DOS
~1l_D07
,..L--LA.-A-
~~
'-----<- CAS
DO'
WE
RAS
1---0 "CAS
j--. CAS
WE
1 ~h
f-+- ;::I=:I
A.-A-
I----
j---. RAS
)
CAS
WE
WE
I IDVfCVf~il
!--+- ,.....l-l-A.-A-
003
A,-A-
1---0 RAS
f-+- I A~A- I
DO'
vall
DV
L-~SS
WE
I I~ccv~~h
;:::r::=:r:::
-+- A.-A1 - - RAS

1 - - CAS
WE
D08
1 ,"v,ccv~soil
;:I:J:
-+- A.-A-
~RAS
CAS9
Vcc
:JccT
Vss
234
os
,*c, ~~'* c.
0'----. 09
- - - - - - - - - - - - - - -__ DYNAMIC RAM MSC2301 YS9/KS9 _
PIN ASSIGNMENT
MSC2301YS9
MSC2301KS9
PIN No.
1
2
3
4
5
6
7
8
9
10
PIN NAME
PIN No.
VCC
11
12
13
14
15
16
17
18
19
20
CAS"
001
AO
Al
002
A2
A3
VSS
003
PIN NAME
A4
A5
004
A6
A7
005
NC
NC
NC
006
PIN No.
PIN NAME
21
22
23
24
25
26
27
28
29
30
WE
VSS
007
NC
008
09
RAS
CAS9
09
VCC
(See Note)
Symbol
Value
Unit
VIN. VOUT
-1 to +7
Vee
-1 to +7
Topr
Ot070
Storage temperature
Tstg
-40 to +125
PD
50
mA
Rating
Power dissipation
235
DYNAMIC RAM MSC2301 YS9/KS9 . 1 - - - - - - - - - - - - - - -

Parameter
(Referenced to VSS)
Symbol
Min.
Typ.
Max.
Unit
VCC
4.5
5.0
5.5
VSS
Operating
temperature
Supply Voltage
OC to +70C
Input High Voltage,
all inputs
VIH
2.4
6.5
Input Low Voltage,

all inputs
VIL
--1.0
0.8
DC CHARACTERISTICS
1 20ns MODULE
Parameter
150ns MODULE
Symbol
Unit
Min.
Max.
Min.
Max.
Operating Current
ICC1
540
495
mA
Standby Current'
(RAS = CAS =VIH)
ICC2
45
45
mA
Refresh Current'
ICC3
360
360
mA
Page Mode Current

ICC4
450
405
mA

(OV S VIN S 5.5V, all other
IL1
-90
90
-90
90
/LA

OV S VOUT S 5.5V)
ILO
-10
10
-10
10
/LA
VOH
2.4
Output Levels
Output high voltage
UOH =-5mA)
Output low voltage
UOL =4.2mA)
VOL
2.4
0.4
V
0.4
Note": ICC is dependent on output loading and cycle rates. Specified values are obtained with the
output open.
236
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ DYNAMIC RAM' MSC2301 YS9/KS9
CAPACITANCE
(Ta = 25C, f = 1 MHz)
Symbol
Typ.
Max.
Unit
CIN1
40
70
pF
CIN2
40
75
pF
Data Input/Output
Capacitance (DO)
COO
20
pF
Input Capacitance (CAS9)
CIN3
10
pF
Input Capacitance (09)
CIN4
10
pF
Output Capacitance (09)
COUT
15
pF
Parameter
Input Capacitance (AD
A7)
AC CHARACTERISTICS
Parameter
Symbol
Units
Note1,2,3
MSC230112YS/KS
Min.
Max.
MSC230115YS/KS
Min.
Note
Max.
Refresh period
tREF
ms

cycle time
tRC
ns
220
260
tpc
ns
120
145
tRAC
ns
120
150
4,6
tCAC
ns
60
75
5,6

delay
tOFF
ns
35
40
tT
ns
35
35
tRP
ns
90
RAS pulse width
tRAS
ns
120
RAS hold time
tRSH
ns
60
75
tcp
ns
50
60
CAS pulse width
tCAS
ns
60
CAS hold time
tCSH
ns
120
--
Transition time
RAS precharge time
CAS precharge time
100
10,000
10,000
150
75
10,000
10,000
150
237
_ DYNAMIC RAM MSC2301 YS9/KS9 - - - - - - - - - - - - - - - - - -
Parameter
Symbol
Units
Note 1,2,3
MSC230112YS/KS
MSC230115YS/KS
Min.
Max.
Min.
60
25
tRCD
ns
25

time
tCRP
ns
tASR
ns
tRAH
ns
15
15

time
tASC
ns
Column Address hold

time
tCAH
ns
20
20
Column Address hold

tAR
ns
80
95
Read command set-up

time
tRCS
ns
tRCH
ns

time
twcs
ns
-10
-10
tWCH
ns
40
45

referenced to RAS
tWCR
ns
100
120
twp
ns
40
45

lead time
tRWL
ns
40
45

lead time
tCWL
ns
40
45
Data-in set-up time
tDS
ns
Data-in hold time
tDH
ns
40
45
tDHR
ns
100
120
Write command pulse

width
Data-in hold time

referenced to RAS
238
Note
Max.
75
----------------1. DYNAMIC RAM MSC2301 YS9/KS9

An initial pause of 100 Ils is required after power-up followed by any 8 RAS cycles
Notes:
AC measurements assume at tT
VIH (Min.) and VIL (Max.) are reference levels for measuring timing of input signals. Also
transition times are measured between VIH and VIL.

increase by the amount that tRCD exceeds the values shown.
5
6
Assumes that tRCD < tRCD (Max.).

5 ns
READ CYCLE TIMING
VIH-
Addresses V I L -
tRCS~
~:~=~
I--tCAC
1~~--------tRAC--~----~~
DOUT
VOHVOL-
----------..,1
OPEN
Valid Data
~ "'H"', "'L"' =
Don't Care
239
DYNAMIC RAM MSC2301 YS9/KS9 - - - - - - - - - - - - - - - -
WRITE CYCLE TIMING

(EARLY WRITE)
RAS
VIH VIL tRSH

_ _ _-+-t==~~~t_I-tCAS-----I A--+---=';"';';"'---'-----.
CAS
VIH VIL -
Addresses
VIH VIL -
WE
VIH VIL -
DIN
VIH VIL -
DOUT
VOHVOL-
~------tDHR------~
OPEN

(CAS: VIH,W'E'& DIN: Don'teare)
Addresses
~R,"jt~RAS
L'R,3~~ASR~
~:~ ="'wm""'7"fT"""""'~,"""'-R-O-W-A-d-d-r-es-~--.L
VOH
DOUT
VOL ~
OPEN
240
- - - - - - - - - - - - - - -...... DYNAMIC RAM MSC2301 YS9/KS9
~-----------------tRAS--------------------.,
CAS
VIHVIL -
DOUT VOH - -----C)PI:N------<I

VOL -
1._
!!B-CS
-WE
Sl~---~---,~""""
VIH-::::::?
VIL~
~"H" ,"L"= Don't Care
tRAS
RAS
VIH VIL -
tAR
't
tCAS
CAS
tCAH
'.'H:e-
tCAS
tCRP
Addresses
WE
VIH VIL -
DIN
VIH VIL ~ "H", "L" = Don't Care
241
DYNAMIC RAM MSC2301 YS9/KS9 . - - - - - - - - - - - - - - -
HIDDEN REFRESH
1 - - - - - Read
tAR--j
Cycle----1--~-
f-tRP
Addresses
DOUT
rn!"H", "L"
Address Inputs:
A total of sixteen binary input address bits
cell locations within the MSC2301. Eight rowaddress bits are established on the input pins
(AD - A7) and latched with the Row Address
Strobe (RAS). The eight column-address bits are
Write Enable:
selected.
Data Input:
Data is written into the MSC2301 during a
write cycle. The last falling edge of WE or CAS is
cycle, if WE is brought low (write mode) before
CAS, DIN is strobed by CAS, and the set-up and
hold times are referenced to CAS.
242
Don't Care
Data Output:
brought low. In a read cycle, the output is valid
after tRAC from transition of RAS when tRCD
(Max.) is satisfied, or after tCAC from transition
of CAS when the transition occurs after tRCD
(Max.). Data remain valid until CAS is returned to
a high level. In a write cycle the identical sequence occurs, but data is not valid.
Page Mode:
row-address into the MSC2301 while maintaining RAS at a logic low (0) throughout all successive memory operations in which the rowaddress doesn't change. Thus the pow~is
sipated by the negative going edge of RAS is
saved. Further, access and cycle times are
decreased because the time normally required
to strobe a new row-address is eliminated.
Refresh:
each of the 128 row-addresses (AD - As) at
least every two milliseconds. During refresh,
either VIL or VIH is permitted for A7. RAS only refresh avoids any output during refresh because
---------------___
DYNAMIC RAM MSC2301 YS9/KS9 _
dissipation.
Hidden Refresh:

243
DYNAMIC RAM MSC2301 YS9/KS9 . - - - - - - - - - - - ' - - - - - MSC2301YS9

88.9
3.38
82.14
...............
</>3.18
I()
'"
"I:.
~I~r
2.03
';;Ill
"""""'"
~o---
I ~n~"""""""
~n~r""""
5.59
2.54
"I
.-.-
.".""".
1.781
5.08 MAX
C')
~~
ci z
+1 ~<t
<Xl
(\j
't:I
(\j
.':Ul
1.27 0.13
Glass-Epoxy Board
18pin PLCC
1.
Substrate: GLASS-EPOXY
2.
Through Hole: Copper Plating

Followed by Sn/Pb Plating
3.
Contact Pads: Copper Plating

on Copper Film (18/Lmt)
4.
Surface Coating: Photo Film Resist
Chip Condenser
Tin-Lead Solder
MSC2301KS9
88.9
3.38 I
</>3.18
LO
(\j
ci
Glass-Epoxy Board
18pin PLCC
Chip Condenser
244
1.
2.

3.

on Copper Film (18/Lmt)
4.
OKI
semiconductor
MSC2304YSS/KSS
GENERAL DESCRIPTION
The Oki MSC2304YSS/KSS is a fully decoded, 262,144 words x S bit NMOS dynamic random
access memory composed of eight 256K DRAMs in plastic leaded chip carrier (MSM41256JS). The
mounting of eight PLCCs together with eight 0.2/LF decoupling capacitors on a 30 pin glass epoxy
Single-In-Line Package provides any application where high density and large capacity of storage
memory are required. The electrical characteristics of the MSC2304 YSS/KSS are quite same as the
original MSM41256JS; each timing requirements are noncritical, and power supply tolerance is very
wide.
FEATURES
262,144 word x S bit Organization

Single +5V Supply (1 0% Tolerance)
3-States Outputs
Row Access Time;

120ns max. (MSC2304-12YSS/KSS)
150ns max:iMSC2304-15YSS/KSS)
30S0mW max. (MSC2304-12YSS/KSS)
2860mW max. (MSC2304-15YS8/KS8)
Operating Temperature ... ODC to 70 DC

ACt-As
RAS-=~~t===============~
CAS - - . - + + - - - - - - - - - "
WE-"T-""I-++-----------,
D02 -+-II-+-h-~
OQ3
OQ4 -----====:;~
Vee
~~c~.:=r7:c.I~-----~
Vss -"----I'-----4-_ _ _ _ _ _ _-----...l
245
DYNAMIC RAM MSC2304YSS/KSS
.1----------------
PIN ASSIGNMENT
MSC2304YS8
\~COCQ:J:!:K:~LD:I
- ________
MSC2304KS8
O~N~~~wR$mO~NM~~w~oomo
~~~~~~~~~~=========~~~~~~~~~~~
~
H
----_____ O~@M~~~~OOmO~@M~~~R$ma
~~~S~Sb$~==========~~~~~~~~~~~
PIN No.
PIN NAME
PIN No.
PIN NAME
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
~
CAS
D01
AO
A1
D02
A2
A3
VSS
D03
A4
A5
D04
A6
A7
16
D05
A8
NC
NC
D06
WE
VSS
D07
NC
D08
17
18
19
20
21
22
23
24
25
26
27
28
29
30
.lli2.
RAS
NC
NC
VCC
(See Note)
Symbol
Value
Unit
VIN. VOUT
-1 to +7
Vee
-1 to +7
Topr
o to 70
Storage temperature
Tstg
-40 to +125
PD
50
mA
Rating
Power dissipation
Note: Perrolanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. Functional operation
246
- - - - - - - - - - - - - - - 1 . DYNAMIC RAM MSC2304YSS/KSS

Parameter
Symbol
Min.
Typ.
Max.
Unit
VCC
4.5
5.0
5.5
VSS
Operating
temperature
Supply Voltage
0Cto+70C
Input High Voltage,
all inputs
VIH
2.4
6.5
Input Low Voltage,

all inputs
VIL
-1.0
0.8
DC CHARACTERISTICS
120ns MODULE
Parameter
150ns MODULE
Symbol
Unit
Min.
Max.
Min.
Max.
Operating Current"
ICC1
560
520
mA
Standby Current
(RAS = CAS = VIH)
ICC2
40
40
mA
Refresh Current
ICC3
440
400
mA
Page Mode Current"

ICC4
440
400
mA

(OV :::: VIN :::: 5.5V, all other
1L1
-80
80
-80
80
/LA

OV :::: VOUT :::: 5.5V)
ILO
-10
10
-10
10
/LA
VOH
2.4
Output Levels
Output high voltage
(iOH=-5mA)
Output low voltage
(iOL=4.2mA)
VOL
2.4
0.4
V
0.4
output open.
247
.DYNAMICRAMMSC2304YSS/KSS.------------------------------CAPACITANCE
(Ta = 25C, f = 1 MHz)
Symbol
Typ.
Max.
Unit
Input Capacitance (Ao - Aal
CIN1
37
60
pF
CIN2
35
65
pF
Data Input/Output
Capacitance (DO)
COO
20
pF
Parameter
AC CHARACTERISTICS
Parameter
Symbol
Units
MSC230412YS/KS
Min.
MSC230415YS/KS
Max.
Min.
Note
Max.
Refresh period
tREF
ms

cycle time
tRC
ns
230
260
tpc
ns
125
145
tRAC
ns
120
150
4,6
tCAC
ns
60
75
5,6

delay
tOFF
ns
40
40
tT
ns
50
50
tRP
ns
100
RAS pulse width
tRAS
ns
120
RAS hold time
tRSH
ns
60
75
tcp
ns
55
60
CAS pulse width
tCAS
ns
60
CAS hold time
tCSH
ns
120
tRCO
ns
25

time
tCRP
ns
Transition time
RAS precharge time
CAS precharge time
248
100
10,000
10,000
150
75
10,000
10,000
150
60
25
0
75
- - - - - - - - - - - - - - - - . DYNAMIC RAM MSC2304YS8/KS8
Parameter
Symbol
MSC230412YS/KS
Units
Min.
Max.
MSC230415YS/KS
Min.
tASR
ns
tRAH
ns
15
20

time
tASC
ns
Column Address hold

time
tCAH
ns
30
35
Column Address hold

tAR
ns
90
110
Read command set-up

time
tRCS
ns
tRCH
ns

time
twcs
ns
tWCH
ns
40
45

referenced to RAS
tWCR
ns
100
120
twp
ns
40
45

lead time
tRWL
ns
40
45

lead time
tCWL
ns
40
45
Data-in set-up time
tDS
ns
Data-in hold time
tDH
ns
40
45
tDHR
ns
100
120
Write command pulse

width
Data-in hold time

referenced to RAS
Note
Max.
Note 1,2,3: Under recommended operating conditions
249
DYNAMIC RAM MSC2304YSS/KSS

Notes:
.1---------------
An initial pause of 100 p's is required after power-up followed by any 8 RAS cycles
2 AC measurements assume at tT = 5 ns
3 VIH (Min.) and VIL (Max.) are reference levels for measuring timing of input signals. Also
4

increase by the amount that tRCD exceeds the values shown.
5 Assumes that tRCD < tRCD (Max.).

7
READ CYCLE TIMING
tRC
RAS
VIH VIL -
CAS
VIH VIL -
Addresses
VIHVIL -
WE
tRcsH
VIH-~r
VIL-
VOHDOUT
VOL-
!--tCAC
I-
tRAC
I
OPEN
tOFF
Valid Data
~OOHOO,
250
ooLoo = Don't Care
DYNAMIC RAM' MSC2304YSS/KSS - - - - - - - - - - - - - - -
~----------------tRAS---------------------
VIHAdresses VI L -
~"H","L"=Don't CarE
Addresses
VIH VIL -~~!ll~~~!ll!f~~~~

VIH -,,""""~~
VIL-~"f~~~~~~~~~~~~~~~~~~~~~~~~~
DIN
VIH V IL -
~'4'o"l1'------III~~ l'----J'f '(.""'"""'~l\--;"";"-Ji """"'''''''...:..::~"'''

252
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _.... DYNAMIC RAM MSC2304YSS/KSS
HIDDEN REFRESH
Addresses
I tRCS
DOUT
Address Inputs:
cell locations within the MSC2304. Nine rowaddress bits are established on the input pins
(Ao - A8I and latched with the Row Address
Strobe (RAS). The Nine column-address bits are
edge of RAg, CAS is internally inhibited (or
Write Enable:
selected.
Data Input:
write. The last falling edge of WE or CAS is a
strobe for the Data In (DIN) register. In a write
Data Output:

Page Mo~e:
row-address into the MSC2304 while
maintainingRAS at a logic low (0) throughout all
successive memory operations in which the
row-address doesn't change. Thus the power
dissipated by the negative gOing edge of RAS is
Refresh:
each of the 256 row-addresses (Ao - A7) at
least every four milliseconds. During refresh,
either VIL or VIH is permitted for As. RAS only refresh avoids any output during refresh because
dissipation.
Hidden Refresh:
253
DYNAMIC RAM . MSC2304YSS/KSS

MSC2304YS8
, - - - - - - - - - - - ..
88.9
82.14
Glass-Epox Y Board
18pin PlCC
1.
2.
Substrate: GlASS-EP
Through Hole.
OXY
Followed by Copper Plating
3.
Plating
Contact
pper Plating
Followed by S
on Copper FI n/(Pb Plating
S rf
1m 18/Lmt)
u ace Coating: Ph 00
t Film
. Resist
Chip Condenser
4.
S
pads:~:b
88.9
82.14
10
C\I
ChipCond enser
1.
2.
Substrate: GlASS-EP
Through Hole.
OXY
Followed by S Copper Plating
n/PbPI t"
3
. Contact Pads. C
a Ing
Followed by
opper Plating
b
on Copper Fil nt Plating
4. Surf
m 18/Lmt)
ace Coating: Photo Film Resist
Tin-lead Solder
254
- - - - - - - - - - - - - - -..... DYNAMIC RAM MSC2304YSS/KSS
MSC2304YSS/KSS (SIP/SIM) DERATING CURVE
(OC)
70
....
60
:;J
CIl
a.
E
........ . .
AirFlow
- - - - :Om/s
"....-
"
"
Not Allowable
-~----"" .... ....
- - - - - - : lm/s
- - - - - - : 3m/s
50
Allowable
CIl
l-
e:
CIl
:0
40
I-
30
20L----4____- L____-L____~~--~-2
3
5
4 f
l/tRC. Cycle Rate
4.35 MHz
(MHz)
255
OKI
semiconductor
MSC2304YS9/KS9
GENERAL DESCRIPTION
The Oki MSC2304YS9/KS9 is a fully decoded, 262,144 words x 9 bit NMOS dynamic random
access memory composed of nine 256K DRAMs in plastic leaded chip carrier (MSM41 256JS). The
mounting of nine PLCCs together with nine 0.2/-tF decoupling capacitors on a 30 pin glass epoxy
Single-In-Line Package provides any application where high density and large capacity of storage
memory are required. The electrical characteristics of the MSC2304YS9/KS9 are quite same as the
original MSM41256JS; each timing requirements are noncritical, and power supply tolerance is very
wide.
FEATURES
262,144 word x 9 bit Organization
Single +5V Supply (10% Tolerance)
3-States Outputs
Separate CAS Control for One Separate Pair

of Data-In and Data-Out Lines
Row Access Time;
1 20ns max. (MSC2304-1 2YS9/KS9)
3465mW max. (MSC2304-12YS9/KS9)
3218mW max. (MSC2304-15YS9/KS9)
Operating Temperature ... OC to 70C
. :::J-r--r;:;:I----- RAS
I-----
D01
.-+-
------t
CAll
WI':
IDvfc
Vi~'l
DOS
r-A~A.
RAS
CAll
WE
r IDICCVf~~
f-+- r-'---IA~A.
.-+-~
I-----
~CAS
1-----liA!l
~RAS
CAS
WE
WE
L ,ovre vf~ Il
D02
ooe
r-'-'-
r'---'-
~Ao-A8
I----- i'iAS
I------ CAS
DO.
'--+-
WE
0
.Dvfc vr
~Ao-A8
~AAll
fl
f------=
WE
D07
r-'-'-
r-'---'-
r--
~=
e ail
WE
~~SS
I ,~ccv~,\'1
f-+- ~.
r----- CAS
A~A.
_RAS
DO.
.'t,cc v~~il
RAS
WE
008
"v,ccV~SOI
Lr-- rl--l..
A~A.
~AAS
CAS9
CAll
WE
D9
VCC
VSS
256
~c,
___~ C.
D
0 _ 09
JCCVr
- - - - - - - - - - - - - - - - 1 . DYNAMIC RAM MSC2304YS9/KS9
PIN ASSIGNMENT
MSC2304YS9
MSC2304KS9
PIN No.
1
2
3
4
5
6
7
8
9
10
PIN NAME
PIN No.
VCC
11
12
13
14
15
16
17
18
19
20
CAS
D01
AO
A1
D02
A2
A3
VSS
D03

Rating
PINNAME
A4
A5
D04
A6
A7
D05
A8
NC
NC
D06
PIN No.
PIN NAME
21
22
23
24
25
26
27
28
29
30
WE
VSS
D07
NC
D08
09
RAS
CAS9
D9
VCC
(See Note)
Symbol
Value
Unit
VIN, VOUT
-1 to +7
Vee
-1 to +7
Topr
o to 70
Storage temperature
Tstg
-40 to +125
PD
50
mA
Power dissipation
257
DYNAMIC RAM MSC2304YS9/KS9 . - - - - - - - - - - - - - - -

Parameter
Symbol
Min.
Typ.
Max.
Unit
Vee
4.5
5.0
5.5
VSS
Supply Voltage
Operating
temperature
ooe to +70 oe
Input High Voltage,
all inputs
VIH
2.4
6.5
Input Low Voltage,

all inputs
VIL
-1.0
0.8
DC CHARACTERISTICS
120ns MODULE
Parameter
150ns MODULE
Symbol
Unit
Min.
Max.
Min.
Max.
Operating Current'
ICC1
630
585
mA
Standby Current
(RAS = CAS =VIH)
ICC2
45
45
mA
Refresh Current
(RAS cycling, CAS = VIH; tRC =min,)
ICC3
495
450
mA
Page Mode Current

(RAS = VIL, CAS cycling; tpc =min,)
ICC4
495
450
mA

(OV :::: VIN :::: 5.5V, all other
IL 1
-90
90
-90
90
/LA

OV :::: VOUT :::: 5.5V)
ILO
-10
10
-10
10
/LA
VOH
2.4
Output Levels
Output high voltage
(lo~=-5mA)
Ou put low voltage

(lOL=4.2mA)
VOL
2.4
0.4
V
0.4
output open.
258
- - - - - - - - - - - - - - - - . DYNAMIC RAM MSC2304YS9/KS9
CAPACITANCE
(Ta = 25C, f = 1 MHz)
Symbol
Typ.
Max.
Unit
CIN1
40
70
pF
CIN2
40
75
pF
Data Input/Output
Capacitance (DO)
COO
20
pF
Input Capacitance (CAS9)
CIN3
10
pF
Input Capacitance (09)
CIN4
10
pF
Output Capacitance (09)
COUT
15
pF
Parameter
Input Capacitance (Ao - As)
--
----
AC CHARACTERISTICS
MSC2304-1 2YS/ MSC2304-15YS/
KS
KS
Parameter
Symbol
Units
Note
Min.
Max.
Min.
Max.
Refresh period
tREF
ms

cycle time
tRC
ns
230
260
tpc
ns
125
145
tRAC
ns
120
150
4,6
tCAC
ns
60
75
5,6

delay
tOFF
ns
40
40
tT
ns
50
50
tRP
ns
100
RAS pulse width
tRAS
ns
120
RAS hold time
tRSH
ns
60
75
tcp
ns
55
60
CAS pulse width
tCAS
ns
60
CAS hold time
tCSH
ns
120
Transition time
RAS precharge time
CAS precharge time
100
10,000
10,000
150
75
10,000
10,000
150
259
DYNAMIC RAM MSC2304YS9/KS9 B - - - - - - - - - - - - - - -
Parameter
Symbol
Units
MSC230412YS/KS
MSC230415YS/KS
Min.
Max.
Min.
60
25
tRCO
ns
25

time
tCRP
ns
tASR
ns
tRAH
ns
15
20

time
tASC
ns
Column Address hold

time
tCAH
ns
30
35
..column Address hold

tAR
ns
90
110
Read command set-up

time
tRCS
ns
tRCH
ns

time
twcs
ns
tWCH
ns
40
45

referenced to RAS
tWCR
ns
100
120
twp
ns
40
45

lead time
tRWL
ns
40
45

lead time
tCWL
ns
40
45
Data-in set-up time
tos
ns
Data-in hold time
tOH
ns
40
45
tOHR
ns
100
120
Write command pulse

width
Data-in hold time

referenced to RAS
260
Note
Max.
75
- - - - - - - - - - - - - - - 1 . DYNAMIC RAM MSC2304YS9/KS9

NOTES: 11 An initial pause of 1oolols is required after power-up followed by any 8 ~ cycles (Examples; RAS
onlyl before proper device operation is achieved.
21 AC measurements assume tT = 5 ns.
31 VIH (Min.) and Vil (Max.) are reference levels for measuring timing of input signals. Also, transition
times are measured between VIH and Vil.
41 Assumes that tACO < tACO (max.l.
If tACO is greater than the maximum recommended value shown in this table, tAAC will increase by
the amount that tACO exceeds the values shown.
51 Assumes that tACO < tACO (max.)
61 Measured with a load circuit equivalent to 2 TTL loads and 100pF.
71 Operation within the tACO (max.1 limit insures that tAAC (max.) can be met. tACO (max.1 is specified as a reference point only; if tACO is greater than the specified tACO (max.) limit, then access
READ CYCLE TIMING
~------------------tAC------------------~
VIH _
---~ f...---tAR------<~
Vil -
VIH Vil -
VIHAddresses VI l -
WE
VIH-~
Vil I_
00UT VOHVOl-
I--
tRAC ___tC_A
__
C____--IIr-_____..t
OPEN
Valid Data
tOFF
[)-------
~"H",
"l" = Don't Care
261
DYNAMIC RAM MSC2304YS9/KS9 - - - - - - - - - - - - - - -
WRITE CYCLE TIMING

(EARLY WRITE)
RAS
VIH VIL tRSH
CAS
VIH VIL -
Addresses
VIH VIL -
_ _ _--++==~~=;_II-tCAS------t A-+....;;,;,.~-"--.......
WE
VIH - /j
VIL -
DIN
VIH VIL -
DOUT
VOHVOL-
r------tDHR-----~
OPEN

(CAS: VIH,M& DIN: Don't care)
___
RAS
VIHVIL-
VOH DOUT
VOL -
OPEN
262
------------------------------___ OYNAMICRAMMSC2304YS9/KS9_
VI
Adresses V I L
~"H","L"=Don't Care
V IH - ",""'+'.,.,.,.,..j
VIL -~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
DIN
V IH - ,.,.,""'~J"":';""';;';";"..J "''"''-.li...;.:.--=;.;.;....J....,,,..,..-::~.,,n...r.;........;;.;.~.n'.,..,.,~77',..,..:;~
VIL ~ "H", "L" = Don't Care
263
DYNAMIC RAM MSC2304YS9/KS9 . - - - - - - - - - - - - - - HIDDEN REFRESH
Addresses
tRCS
DOUT
Address Inputs:
cell locations within the MSC:!304. Nine rowaddress bits are established on the input pins
(Ao - As) and latched with the Row Address
Strobe (RAS). The Nine column-address bits are
Write Enable:
Data input is disabled when read mode is selected.
Data Input:
write. The last falling edge of WE or CAS is a
strobe for the Data In (DIN) register. In a write
Data Output:
264

Page Mode:
row-address into the MSC2304 while
maintaining RAS at a logic low (0) throughout all
successive memory operations in which the
row-address doesn't change. Thus the power
dissipated by the negative going edge of RAS is
Refresh:
each of the 256 row-addresses (Ao - A7) at
least every four milliseconds. During refresh,
either VIL or VIH is permitted for As. RAS only refresh avoids any output during refresh because
dissipation.
Hidden Refresh:
- - - - - - - - - - - - - - - - - 1 1 . DYNAMIC RAM MSC2304YS9/KS9

MSC2304YS9
889
3.38
'I
82.14
5.08 MAX
;:tiIlliCJ; ~
<1>3.18
y
L()
(!)
~I~r
,;lll
cn:rm:r'
'ct:rm:r
2.5411
5.59
203
1.270.13
Glass-Epoxy Board
18pin PLCC
1.
2.

3.

on Copper Film (18j!mt)
4.
Chip Condenser
Tin-Lead Solder / .
MSC2304KS9
889
338 1
<l>318-
OL()
~O
c:ic:i
+1
L()
C\J
c:i
L()
18 pin PLCC
C\J
c:i
Chip Condenser
1.
2.

3.

on Copper Film (18j!mt)
4.
265
DYNAMIC RAM MSC2304YS9/KS9 - - - - - - - - - - - - - - -
MSC2304YS9/KS9 (SIP/SIM) DERATING CURVE
(OC)
70
._-""""--, ...........'
'..
...
I!!
Q)
Co
50
AirFlow
..... ...........
"'"' ' .
60
Not Allowable
.........
Allowable
Q)
- - - :Om/s
_ . - . _ :1m/s
- - - - - - : 3m/s
t-
<:
Q)
:0
E
40
c(
~
30
20
1ItRC. Cycle Rate
266
4.35 MHz
(MHz)
MOS
STATIC
RAMS
OKI
semiconductor
MSM5114RS
4096-BIT (1024 x 4) CMOS STATIC RAM
GENERAL DESCRIPTION
The Oki MSM5114 is a 4096-bit static Random Access Memory organized as 1024 words by 4 bits using Oki's
reliable Silicon Gate CMOS technology. It uses fully static circuitry and therefore requires no clocks or refreshing
to operate. Microwatt power dissipation typical of all CMOS is exhibited in all static states. Directly TTL compatible inputs, outputs and operation from a single +5V supply simplify system designs. Common data input/output
pins using three-state outputs are provided.
The MSM5114 series is offered in an 18-pin plastic (RS suffix) package. The series is guaranteed for operation from
OC to 70C and over a 4V to 6V power supply range.
FEATURES
Fully Static Operation
Low Power Dissipation
40j.lW Max. Standby Power
192 mW/MHz Max. Operating
Power
Max. A _ Time (NS)

Max. Op....ting Power (MW/MHzI
Max_ Standby Power (,.WI
Data Retention to VCC=2V

Single 4 - 6V Power Supply
High Density 300-mil 18-Pin Package
Common I/O Capability using ThreeState Outputs
5114-2
200
192
40
Directly TTL/CMOS Compatible

Silicon Gate CMOS Technology
Interchangeable with Intel 2114L
Devices
5114-3
300
192
40
5114
450
192
40
~.f-} ".'I.I~II~~
J
I I
l~
"---1>--1
A,---{)---!
MEMORY ARRAY
ROW
A, ---1>:=:1 SELECT
641<64
A'---1>:=:I
A.-~-1>--1
D
cs
WE
I/O
Mode
Hi-Z
Not Selected
es:
Write 1
Write 0
To A.: Address Inputs

WE: Write Enable
Chip Select
1/0,_1/0.: Data Input/Output
VCC: +6V Supply
VSS: Ground
268
O-out
Read
- - - - - - - - - - - - - - - - - - 1 . STATIC RAM MSM5114RS

Rating
Symbol
Supply Voltage
Value
VCC
Conditions
Unit
-0.3 to 7.0
Input Voltage
VIN
-0.3 to V CC + 0.3
Data I/O Voltage
VD
-0.3 to VCC + 0.3
Storage Temperature
T stg
-55 to 150
Respect to VSS
Nota: Stresses above those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the
device. This is a stress rating only and functional operations of the device at these or at any other condition
above those indicated in the operational sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
OPERATING CONDITIONS
Symbol
Parameter
Supply Voltage
VCC
I nput Signal Level

Min.
Typ.
Max.
Unit
VIH
2.4
VCC
VIL
-0.3
0.8
Topr
70
Conditions
5V 10%
DC CHARACTERISTICS
(Vcc = 5V 10%; Ta = OC to
Parameter
Input Load Current
+ 70
C, unless otherwise noted.)

Symbol
Min.
Typ.
Max.
Unit
Conditions
III
-1
p,A
VIN=OtoVCC
Data I/O Leakage Current
ILO
-1
p,A
VI/O = 0 to VCC
Output High Voltage
VOH
Output Low Voltage
VOL
Standby Supply Current
ICCS
Operating Supply Current
ICC
2.4
0.4
0.2
19
50
35
lOUT = -1.0 mA
10UT= 1.6mA
p,A
mA
VIN = 0 or VCC,
VCS =VCC
VIN = 0 or VCC,
tRC = 1 p,s
269
STATIC RAM MSM5114RS - - - - - - - - - - - - - - - - - AC CHARACTERISTICS

READ CYCLE
(Vcc ~ 5V 10%, Ta = oc to +70C)
Parameter
Symbol
5114-2
Min_
5114
5114-3
Max.
200
Min.
Max.
Min.
Unit
Max.
450
Read Cycle Time
tRC
Access Time
tAC
200
300
450
ns
Chip Selection to Output

Valid
tco
200
300
450
ns
Chip Selection to Output

Active
tcx
Output 3-state from

Oeselection
tOTO
Output Hold from Address

Change
tOHA
300
20
20
20
60
SO
10
ns
ns
ns
100
10
10
ns
READ CYCLE
tRC
/
tAC
/
i---tOTOtco
tOHA-j--r---tcxINPUT/OUTPUT
Notes:
V I L
'\
1.
2.
3.
4.
5.
A Read occurs du ring the overlap of a low CS and high WE.

Input Pulse levels: O.SV to +2.4V
Input Rise and Fail Time: 10 ns
Timing Measurement Reference Levels: 1.5V
Output Load: 1 TTL Gate and CL ~ 50 pF
WRITE CYCLE
(VCC ~ 5V 10%, Ta = oc to +70C)
5114-2
Parameter
270
Symbol
Min.
Max_
5114
5114-3
Min.
Max.
Min.
Max.
Unit
Write Cycle Time
twc
200
300
450
ns
Write Time
tw
150
190
250
ns
Write Release Time
tWR
20
30
50
ns
Address Setup Time
tAS
20
20
20
ns
Data Setup Time
tos
120
150
200
ns
Data Hold From Write Time
tOH
10
10
'10
ns
-------------------1. STATIC RAM MSM5114RS

WRITE CYCLE
twc
tw
---tAS--"
twR-
tDs-----;
r--INPUT/OUTPUT
Notes:
I\-
1.
2.
3.
4.
5.
6.
7.
DATA IN STABLE
tDH
A Write occurs during the overlap of a low CS and low WE.

Input Pulse Levels: 0.8V to +2.4V
Input Rise and Fall Time: 10 ns
Timing Measurement Reference Levels: 1.5V
two Overlap time of a low CS and low WE.
tAS: Low WE from address or low CS from address
tWR, tDS and tDH are defined from High CS or High WE. whichever occurs first.
LOW VCC DATA RETENTION CHARACTERISTICS

(T a = 0 C to
+ 70 C, unless otherwise noted.)

Parameter
Symbol
Min.
Typ.
Max.
Unit
V
V CC for Data Retention
VCCH
Data Retention Current
ICCH
CS to Data Retention Time
tsu
ns
Operation Recovery Time
tR
tRC
ns
0.1
20
IJA
Conditions
= 0 or VCC. VCS = VCC

VCC = 2V VCS = VCC
VIN
VIN
= OV or VCC
LOW VCC DATA RETENTION WAVEFORM

~'!--~~-STANDBY MODE~~~~~-
5V ~---=.V..!;C~C,--+_ _---,
4.5V - - - - -
VIH - - - - VCCH----
------
--- - - - - '-----------'
VIL
GND------------------ -- -
- - - ------ - ---
271
STATIC RAM MSM5114RS
.11-------------------
CAPACITANCE
(T a
= 25"C, f = 1 MHzl
Parameter
Symbol
Min.
Max.
Unit
CI/O
10
pF
Input Capacitance
CIN
pF
Note: This parameter is pariodically sampled and not 100% tested.
272
Typ.
Input/Output Capacitance
OKI
semiconductor
MSM2128RS
2 KW x 8 BIT STATIC RAM
GENERAL DESCRIPTION
The OKI MSM2128 is a 16384 bits static Random Access Memory organized as 2048 words by 8 bits using
Advanced N-channel Silicon Gate MOS technology_ 't uses fully static circuitry throughout and no clocks or refresh
are required. The reduced standby power dissipation is automatically performed by CS control. Single +5 V Power
supply. All inputs and outputs are directly TTL compatible. Common data I/O using three-state outputs. The 24 pin
package is pin compatible with standard 16 K UV Erasable Programmable ROM.
FEATURES
Single power supply
External clock and refresh.operation not required
Access time
MSM2128-12RS
120ns (maxI
MSM2128-15RS
150ns (maxI
200ns (maxI
MSM2128-20RS
Low power dissipation
MSM2128-15RS/20RS
during operation
550mW (maxI
MSM2128-12RS
660mW (maxI
110 mW (maxI
during standby
TTL compatible I/O

Three-state I/O
Common data I/O capability
Power down mode using chip select signal
Convertibility of pins used in 16KEPROM MSM2716
A.
A,
2'::
(Top Viewl
A,
A,
2
3
..
II,
A,
110)
VSS
110 .
2'
I/O~
200lt
IIO~
"
'2
19 AIO
17
liD.
,.
110,
110,
liDs
'3 1104
Ao "vAIO: Address Inputs
----:'-
:c~'-
:---
I/O~
110,
:..'-
IIO K
16COLUMNS
x8Block
r--
:r-
liD!
SELECT
2'::
AI(>
22 A9
-GND
128ROWS
RO"
2'::
A.
1/0 1
m
s
,. cs
,.
,. ,.
A,
A, 7
A,
110 1 9
liD!
:"-
A,
24 Vee
23 A,
--Vee
r-MEMORY ARRAY
A.
A,
PIN CONFIGURATION
~
INPUT
COLUMN I/O CIRCUITS

COLUMN SELECT
DATA
CONTROL
~~~~
h1h' n~~
hn
I/O, 'V I/O. ; Data Input/Output

Vee: Power (5V)
VSS: Ground
WE: Write Enable
es: ehip Select
OE: Output Enable
273
STATIC RAM MSM2128RS . - - - - - - - - - - - - - - - - - - ABSOLUTE MAXIMUM RATINGS

Rating
Symbol
Value
Supply Voltage
Vee
-0.5 to 7
Input Voltage
VIN
-0.5 to 7
Conditions
Unit
Respect to V ss
Topr
o to 70
Storage Temperature
T stg
-55 to 150
Power Dissipation
Po
1.0
DC AND OPERATING CHARACTERISTICS

+ 70C, VCC = 5V 10%, unless otherwise notes.)
(Ta = oc to
Parameter
212812RS
Symbol
Typ.
Min.
2128-15/20RS
Max.
Min.
Typ.
Conditions
Unit
Max.
Input Load
Current
III
-10
10
-10
10
/LA
Vee = Max.
VIN = GND to Vee
Output Leakage
Current
ILO
-10
10
-10
10
/LA
CS = OE = VIH,
Vee = Max.
V out = GND to Vee
Operating
Current
ICC
120
100
mA
Vee = Max. CS = VIL

I I/O = 0 mA teye = Min.
Standby
Current
ISS
15
15
mA
Vee = Min. to Max.

CS = VIH
Peak Power-on
Current
ISSp
20
20
mA
Vee = GND to Vee = Min.

CS = Lower of Vee
or VIH
0.8
VIH
Input Voltage
Output Voltage
VIL
-0.5
VOH
2.4
6
0.8
-0.5
Vee
2.4
0.4
VOL
Notes 1. Typical limits are at Vee
5
0
Respeet to Vss
Vee
10H
= -1.0 mA
0.4
10L
= 2.1 mA
= 5V, Ta = 25C, and specified loading.
AC CHARACTERISTICS
(T a
= oc to + 70C, VCC = 5V 10%, unless otherwise noted.)
AC TEST CONDITIONS
Parameter
2.0V
I nput Low Level
0.8V
I nput Rise and Fall Times
10 ns
Input and Output Timing Levels
1.5V
Output Load
274
Conditions
I nput High Level
CL = 100 pF, 1TTL Gate
-------------------11. STATIC RAM MSM2128RS

READ CYCLE
(1)
Parameter
2128-12RS
Symbol
Min.
Max.
212815RS
Min.
Max.
2128-20RS
Min.
Max.
Unit
ns
200
Read Cycle Time
tRC
Address Access Time
tAC
120
150
200
ns
Output Enable to
Output Delay
tOE
50
60
70
ns
120
150
200
ns
Ch ip Select Access Time
tco
Chip Selection to
Output in Low Z
tCX(2)
Chip Selection to
Output in High Z
tOTD(3)
Output Hold from

Address Time
tOHA
Chip Select to
Power Up Time
tpu
Chip Select to
Power Down Time
tpD
120
150
10
10
0
40
ns
10
50
60
ns
10
10
10
ns
ns
50
60
Conditions
80
ns
READ CYCLE NO. 1(8)(9)
I/O(out)
READ CYCLE NO. 2(8)(10)
I/O(out)
VCC
Supply
Current
ICC
Notes:
------+-J+---;
tpu
1. ~ is high for Read Cvcle.

2. Device is continuously selected. CS = VI L.
3. Address valid prior to or coincident with "CS" transition low.
275
STATIC RAM MSM2128RS - - - - - - - - - - - - - - - - - -
WRITE CYCLE
(4)(5)
Parameter
Symbol
212812RS
Min.
Max.
212815RS
Min.
Max.
212820RS
Min.
Max.
Unit
Write Cycle Time
twc
120
150
200
ns
Chip Selection to End

of Write
tcw
90
120
150
ns
ns
Address Setup Time
tAS
20
20
20
Write Pulse Width
twp
SO
80
100
ns
Write Recovery Time
tWR(S)
10
10
10
n.
Data Valid to End of Write
tOS(S)
50
70
90
ns
Data Hold Time
tOH(S)
10
15
15
ns
Write Enabled to Output

in High Z
tOTWI7l
Output Active from

End of White
twx
Notes
1.
2.
3.
4.
5.
S.
7.
40
0
5
twc
A."'A,.
twp
WE"
I/O
(OOUT)
tos
I/O
(DIN)
276
0
5
SO
ns
ns
A read occurs during the overlap of a low CS, a low OE and a high WE.
tcx is specified from CS or CE, whichever occurs last.
tOTO is specified from CS or CE, wh ichever occurs first.
A write occurs during the overlap of a low CS and a low WE.
OE may be allowed in a Write Cycle both high and low.
tWR, tos, and tOH are specified from CS or WE, whichever occurs first.
tOTW is specified by the time when DATA OUT is floating, not defined by output level.
WRITE CYCLE NO. 1(11 )113)
50
Conditions
-------------------11. STATIC RAM MSM2128RS

WR ITE CYCLE NO. 2112 ) 113)
~---------------twc---------------~
t----tcw - - - - - - - 1
Notes
1. WE control mode
2. CS control mode
3. When 1/0 pins are Data output mode, don't force inverse signal to these pins.
FUNCTION TRUTH TABLE

CS
WE
OE
Mode
Output
Power
Not Selected
High Z
Standby
Write
High Z
Active
Read
DOUT
Active
Not Selected
High Z
Active
CAPACITANCE
(Ta = 25C, f = 1 MHz)
Max.
Unit
Conditions
Parameter
Symbol
ClIO
Min.
pF
VI/O = OV
Input Capacitance
CIN
pF
VIN =OV
Note: This parameter is periodically sampled and not 100% tested.
277
OKI
semiconductor
MSM5128RS
2048-WORD x 8-BIT C-MOS STATIC RAM
GENERAL DESCRIPTION
The MSM5128RS is a 2048-word by 8-bit CMOS static RAM featuring 5V power supply operation and direct TTL
input/output compatibility. Since the circuitry is completely static, external clock and refreshing operations are
unnecessary, making this device very easy to use. The MSM5128RS is also a CMOS silicon gate deVice which requires
very little power during stanciby (maximum standby current of 50ltA) when there is no chip selection. Stored data is
retained if the power voltage drops to 2V, thereby enabling battery back-up.
A byte system is adopted, and since there is pin compatibility with standard ultra-violet EPROMs, this device is ideal
for use as a peripheral memory for microcomputers and data terminal units etc. In addition, CS and OE signals
enable OR ties with the output terminals of other chips, thereby facilitating simple memory expansion and bus line
control etc.
FEATURES
Single 5V Supply
Battery Back-up at 2V
Operating temperature range Ta = _40C to -+a5C
Standby;
5128-20
5128-12/15
1.0 itA MAX Ta = 25C
0.3 itA MAX Ta = 25C
10llA MAX Ta = 60C
1.0 IlA MAX Ta = 60C
50 itA MAX Ta = 85C
Operation;
200mW TYP
High Speed (Equal Access and Cycle Time)
MSM5128-12/15/20; 120 ns/150 ns/200 ns MAX
Direct TTL Compatible. (Input and Output)
3-State Output
Pin Compatible with
16K EPROM
(MSM2716)
16K NMOS SRAM (MSM2128)
PIN CONFIGURATION
(Top View)
1/0, C>--<r-----l:t:::-f~1
I/O, o-!.---"*",:H
1/0, o-l#--~:H
1/0, o-m.-~:H
I/O, o-++++.-~:H
I/O,o-*~--1
liD, "=m~;:g=1:t_~
1/0,0
13 110.
A. 'VA,.: Address INPUTS

110, 'VIIO.: Oat8 Input/Output
CS: Chip Select
WE: Write Enable
OE: Output Enable
VCC, VSS: Supply Voltage
278
_ _ _ _ _ _ _.,..--_ _ _ _ _ _ _ _ _ _-11. STATIC RAM MSM5128RS
TRUTH TABLE
Mode
CS
O"E"
Standby
High Z
High Z
DOUT
DIN
Reed
Write
I/O Operation
X: H or L

Symbol
Value
Unit
Supply Voltage
Rating
VCC
-0.3 to 7.0
Input Voltage
VIN
Topr
-40 to 85
DC
Storage Temperature
T stg
-55 to 150
DC
Power Dissipation
PD
1.0
-0.3 to VCC
Conditions
Respect to GND
+ 0.3
Ta = 25'C
RECOMMENDED OPERATING CONDITION

Parameter
Supply Voltage
Symbol
Min.
Typ.
Max.
Unit
VCC
4.5
5.5
5.5
Input Voltage
Output Load
VCCH
VIH
2.2
VIL
-0.3
CL
TTL
VSS
Data Retention Voltage
Conditions
5V 10%
VCC + 0.3
0.8
100
pF
5V 10%
279
STATIC RAM MSM5128RS - - - - - - - - - - - - - - - - - - _
DC CHARACTERISTICS
Parameter
Symbol
Input
Leakage
Current
III
Output
Leakage
Current
MSM5128-12
Typ.
MSM5128-15
Max.
Min.
-1
ILO
-1
VOH
2.4
Min.
Typ.
MSM5128-20
Typ.
-1
-1
/J.A
VIN=OtoVCC
-1
-1
/J.A
CS=VIHor
OE = VIH
VI/O = 0 to VCC
2.4
IOH =-1 mA
Output
Voltage
0.4
VOL
Test Condition
Min.
2.4
Max.
Unit
Max.
0.4
0.4
IOL =4 mA
(5128-12)
IOL=2.1 mA
(5128-15/20)
Ta
i 250 C
Standby
60C
Supply ICCS
Current
85C
ICCS1
Operating
Supply
Current
0.2
0.2
1.0
1.0
0.1
1.0
10
/J.A
CS;; VCC - 0,2V

VIN = 0 to VCC
CS = VIH
tcyc = Min. cycle
50
0.3
0.3
0.3
mA
40
60
37
55
35
50
mA
40
72
37
66
35
60
mA
ICCA
Min.
cycle
Ta = 0-85C
Ta=-40-85 C
AC CHARACTERISTICS
Test Condition
Conditions
Parameter
I nput Pulse Level

Input Aise and Fall Times
10 ns
I nput and Output

Timing Aeference Level
1.5V
Output Load
CL=100 pF, 1 TTL Gate
--------------~--------------------------------------
READ CYCLE
(V cc
= 5V 10%, Ta = -4o"C to +85 C)

Parameter
280
Symbol
MSM5128-12
MSM5128-15
MSM5128-20
Min.
Min.
Min.
Max.
120
Max.
150
Max.
200
Unit
Aead Cycle Time
tAC
Add ress Access Tim e
tAC
120
150
200
ns
Chip Select Access Time
tco
120
150
200
ns
Output Enable to Output Valid
tOE
80
100
120
ns
Chip Selection to Output Active
tcx
10
15
20
ns
Output Hold Time From

Address Change
tOHA
10
15
20
ns
Output 3-state from Deselection
tOTD
50
50
ns
60
ns
- - - - - - - - - - - - - - - - - - - . STATIC RAM 'MSM5128RS
READ CYCLE
Note.: 1. A Read occurs during the overlap of a low <:S, a low OE and a high WE.
2. tcx is specified from CS or OE, whichever occurs last.
3. tOTO is specified from CS or OE, whichever occurs first.
4. tOHA and tOTO are specified by the time when DATA OUT is floating.
WRITE CYCLE
(Vcc= 5V 10%, Ta = -40C to +85C)
Parameter
Write Cycle Time
Symbol
MSM5128-12
MSM5128-15
MSM5128-20
Min.
Min.
Min.
Max.
Max.
Unit
Max.
twc
120
150
200
ns
Address to Write Setup Time
tAS
15
20
20
ns
Write Time
tw
70
90
120
ns
Write Recovery Time
tWR
15
20
20
ns
Data Setup Time
tos
50
60
80
ns
Data Hold from Write Time
tOH
10
10
Output 3-5tate from Write
tOTW
50
50
ns
60
ns
Notes: 1. A Write Cycle occurs during the overlap of a low CS and a low WE.
2.
3.
4.
5.
6.
7.
OE may be both high and low in a Write Cycle.

tAS is specified from CS or WE, whichever occurs last.
tw is an overlap time of a low CS and a low WE.
twR, tos and tOH are specified from CS or WE, whichever occurs first.
When I/O pins are Data output mode, don't force inverse signal to those pins.
281
STATIC RAM MSM5128RS - - - - - - - - - - - - - - - - - WRITE CYCLE
>~-----

(Ta = _400 C to +8So C, un less otherwise noted)
5128-20
5128-12/15
Parameter
VCC for Data Retention
Symbol
VCCH
ICCH
MIN MAX MIN MAX

2
25C
0.2
60C
1.0
Conditions
V,N = OV to VCC, CS = VCC
O.S
p.A
8SoC
Unit
V,N
20
tsu
ns
tR
tRC
tRC
ns
--!-----STANDBy MODE
SV _---'-V..::C"'C'---+-_ _---.
VCC = 2V CS = VCC
= OV to
VCC
--~~-
4.SV - - - - -
VCCH---CS
VIL-"-'-~
GND--- - - - - - - - - - - - - - - - - - -
- - ------- - ---
CAPACITANCE
(Ta = 2SoC, f = 1 MHz)
Parameter
Symbol
Max.
Unit
CliO
pF
Input Capacitance
C,N
pF
Min.
282
Typ,
OKI
semiconductor
MSM5128 - 20GSK
2048-WORD x 8-BIT C-MOS STATIC RAM (E3-S-013-32)
GENERAL DESCRIPTION
The MSM5128GS is a 2048-word by 8-pit CMOS static RAM featuring 5V power supply operation and direct TTL
unnecessary, making this device very easy to use. The MSM5128GS is also a CMOS silicon gate device which requires
very little power during standby (maximum standby current of 50/JA) when there is no chip selection. Stored data is
control etc.
FEATURES
Single 5V Supply
Operating temperature range Ta = _40C to +85C
Standby;
1.0 /JA MAX Ta = 25C
10 IlA MAX Ta = 60C
50 IlA MAX Ta = 85C
Operation;
200 mW TYP
MSM5128-20; 200 ns MAX

.3-State Output
24 Pin Flat PKG

PIN CONFIGURATION
(Top View)
Ao
As 0--------A60----
A.
24
Vee
A.
23
A,
A.
A,
A,
22
A,
21
20
WE
01'
A,
19
A,"
A,
18
cs
A"
17
lIDs
110 1
16
1/0.
1/0,
10
15
1/0,
110.1
11
14
1/0,
VSS
12
13
1/0 4
A, D - - - - P d ROW
A,
A,
MEMORY ARRAY
128 ROWS
16 COLUMNS
x8 BLOCK
A"
1/0 1
l/Ol
1/0) o-M----t;,::l-jINPUT
1/0 4 o-ttI<t-----t;,::l-j DATA
I/O s o--ttt~---t;,::l-jeDNT 1/0 6
RDL
1/0 7
II0 g
Ao "vA. o : Address INPUTS

I/O. "vl/O.: Data Input/Output
CS: Chip Select
WE: Write Enable
OE: Output Enable
VCC, VSS: Supply Voltage
283
STATIC RAM MSM51 28-20GSK . - - - - - - - - - - - - - - - - TRUTH TABLE

Mode
es
WE
OE
Standby
High Z
High Z
DOUT
DIN
Read
Write
I/O Operation
X: H or L

Symbol
Value
Unit
Supply Voltage
Rating
Vce
-0.3 to 7.0
I nput Voltage
VIN
-0.3 to VCC + 0.3
Topr
-40 to 85
Storage Temperature
T stg
-55 to 150
Power Dissipation
PD
1.0
Conditions
Respect to GN D
Ta = 25C

Parameter
Supply Voltage
Symbol
Vec
Min.
4.5
I nput Voltage
Output Load
284
VeCH
VIH
2.2
VIL
-0.3
eL
TTL
Max.
Unit
5.5
VSS
Typ.
Conditions
5V 10%
V
5.5
Vee + 0.3
0.8
100
pF
5V 10%
- - - - - - - - - - - - - - - - - . STATIC RAM MSM5128-20GSK

DC CHARACTERISTICS
(Vee = 5V 10%, Ta = _40C to +85 C)
MSM5128-20
Parameter
Symbol
Min_
Typ_
Max_
Unit
Test Condition
Input Leakage
Current
III
-1
IJ.A
VIN = 0 to VCC
Output Leakage
Current
ILO
-1
IJ.A
CS = VIH or
OE = VIH
VI/O = 0 to VCC
VOH
2.4
Output Voltage
0.4
VOL
IOH = -1 rnA
IOL = 2.1 rnA
Ta
~
Standby Supply
Current
ICCS
1.0
10
85C
50
ICCSl
Operating
Supply Current
0.1
60C
ICCA
0.3
IJ.A
CS;;; VCC - 0.2V

VIN = 0 to VCC
rnA
CS = VIH
tcyC = Min. cycle
35
50
rnA
35
60
rnA
Min.
cycle
l
I
Ta=0-85C
Ta = -40 - 85C
AC CHARACTERISTICS
Test Condition
Parameter
Conditions
Input Pulse Level

Input Rise and Fall Times
10 ns
I nput and Output

Timing Reference Level
1.5V
Output Load
CL=100 pF. 1 TTL Gate
READ CYCLE
(Vee = 5V 10%, Ta = -4o"C to +85 C)
MSM5128-20
Parameter
Read Cycle Time
Symbol
tRC
Unit
Min.
Max.
ns
200
Add ress Access Ti me
tAC
200
ns
tco
200
ns
Output Enable to Output Val id
tOE
120
ns
tcx
20
ns
Output Hold Time from Address Change
tOHA
20
ns
tOTO
60
ns
285
STATIC RAM MSM5128-20GSK
.1-----------------
READ CYCLE
Notes:
1.
2.
3.
4.
A Read occurs during the overlap of a low CS, a low OE and a high WE.
tex is specified from CS or OE, whichever occurs last.
tOTD is specified from CS or OE, whichever occurs first.
tOHA and tOTD are specified by the time when DATA OUT is floating.
WRITE CYCLE
(Vcc= 5V 10%, Ta= -40C to +S5C)
MSM512S:20
Parameter
Unit
Symbol
Min.
twc
200
ns
tAS
20
ns
Write Time
tw
120
ns
ns
Writ!' Cycle Time
Write Recovery Time
tWR
20
Data Setup Time
tDS
SO
ns
tDH
10
ns
Output 3State from Write
tOTW
Notes:
286
Max.
1.
2.
3.
4.
5.
60
A Write Cycle occurs during the overlap of a low CS and a low WE.
tAS is specified fromCS or WE, whichever occurs last.
twR, tDS and tDH are specified from CS or WE, whichever occurs first.
6. tOTW is specified by the time when DATA OUT is floating, not defined by output level.
7. When I/O pins are Data output mode, don't force inverse signal to those pins.
ns
- - - - - - - - - - - - - - - - - . STATIC RAM MSM5128-20GSK
WRITE CYCLE
=>
twc
) Vf'..
V
f'..
tw
"i'\
/V
f--twR-
f--tAS--
" -i- " -;~

tOTW
1/0
""
______
tDS_ f--tDH
8ATA IN STABLi
>>--~~~-

(Ta = -40C to +85C, unless otherwise noted)
Typ.
Max.
Unit
Conditions
VIN = OV to VCC, CS = VCC
Symbol
Min.
VCCH
ICCH
tsu
ns
tR
tRC
ns
Parameter
5V __V-'--"'C"'-C_-+-_ _- ,
0.05
20
- - - ST ANDBY MODE
/JA
VCC = 2V CS = VCC
VIN = OV to VCC
---+---
4.5V - - - - -
VCCH - - - VIL
GND--- - - - - - - - - - - - - - - - - - -
- - - --- --- - ---
287
STATIC RAM MSM5128-20GSK . - - - - - - - - - - - - - - - - CAPACITANCE

(Ta = 25C, f = 1 MHz)
Parameter
Symbol
Max.
Unit
CI/O
pF
Input Capacitance
CIN
pF
Min.
288
Typ.
OKI
semiconductor
MSM5126RS
2048-WORD x 8-BIT C-MOS STATIC RAM (E3-S-014-321
GENERAL DESCRIPTION
The MSM5126RS is a 2048-word by 8-bit CMOS static RAM featuring 5V power supply operation and direct TTL
unnecessary, making this device very easy to use. The MSM5126RS is also a CMOS silicon gate device which requires
very little power during standby (maximum standby current of 30"AI when there is no chip selection. Stored data is
control etc.
FEATURES
Single 5V Supply
Operating temperature range Ta = _30C to +85C
Standby; 1.0 "A MAX T a = 25 C
5.0 "A MAX T a = 60C
30 "A MAX Ta = 85C
Operation; 200 mW TYP
High Speed (Equal Access and Cycle Timel

MSM5126-20/25; 200 ns/250 ns MAX
Direct TTL Compatible. (Input and Output!
3-State Output
Pin Compatible with
16K EPROM
(MSM27161
16K NMOS SRAM (MSM21281
Aoo-----~=1---,
A,c>--
A,o-----
PIN CONFIGURATION
(Top Viewl
~vcc
A, o-------t/l:::l
A, C>------D<"::1.
A, o------t(\:=1
A"
110,
I/O,
~Vss
0------11\=1.__---1
o-~--~=-f
o-t.---*"H
I
I/O./ O ' U
1105
lID,
I/O,
liD,
o-++++m-~H
o-ttHH-tt~:i-i.
__---1
A. 'VA,.: Address INPUTS

I/O, 'VI/O.: Data Input/Output
CS: Chip Select
WI:: Write E nabla
OE: Output Enable
VCC, vSS: Supply Voltage
289
STATIC RAM MSM5126RS - - - - - - - - - - - - - - - - - -
TRUTH TABLE
Mode
CS
WE"
OE
Standby
High Z
DOUT
DIN
Read
Write
I/O Operation
High Z
X: H or L

Symbol
Value
Unit
Supply Voltage
VCC
-0.3 to 7.0
Input Voltage
VIN
Rating
-0.3 to VCC
Conditions
Respect to GND
+ 0.3
Topr
-30 to 85
Storage Temperature
T stg
-55 to 150
Power Dissipation
PD
1.0
Ta = 25C

Parameter
Supply Voltage
Symbol
Min.
Typ.
Max.
Unit
VCC
4.5
5.5
Input Voltage
Output Load
VCCH
VIH
2.2
VIL
-0.3
CL
TTL
290
VSS
Conditions
5V 10%
5.5
VCC + 0.3
0.8
100
pF
5V 10%
- - - - - - - - - - - - - - - - - - - . STATIC RAM 'MSM5126RS
DC CHARACTERISTICS
(VCl; = sv 10%, Ta = _30C to +8S0C)
MSM512S-20/25
Parameter
Test Condition
Symbol
Min.
Unit
Max.
Typ.
Input
Leakage
VIN =Oto VCC
ILl
-1
p-A
-5
p-A
Current
CS=VIHor
Output
Leakage
OE= VIH
ILO
Current
Output
Voltage
Standby
VI/O=OtoVcC
0.4
IOL =2.0mA
VOL
CS ~ VCC - 0.5V
VCC = 2V to 5.5V
VI=OtoVCC
ICCS
Supply
Current
Ta
25C
0.05
Operating
ICCA
Current
1.0
Ta" SOC
5.0
Ta = 85C
30
CS = VIH
ICCS,
Supply
2.4
IOH=-l mA
VOH
p-A
mA
CS = OV, VIN = VIH/VIL lOUT = 0 mA
40
70
mA
CS = OV, VIN = VCC/GNO, lOUT = 0 mA
30
55
mA
tCYC = Min. cycle
AC CHARACTERISTICS
Test Condition
Conditions
Parameter
o.sv
I nput Pulse Level
VIH = 2.4V, VIL =
10 ns
I nput and Output

2.2V 0.8V
Output Load
CL=100 pF. 1 TTL Gate
READ CYCLE
(Vcc= 5V 10%, Ta= _30C to +85C)
Parameter
Read Cycle Time
Address Access Time
Symbol
tRC
MSM512S-20
Min.
Max.
200
MSM512S-25
Min.
Unit
Max.
250
ns
tAC
200
250
ns
tco
200
250
ns
100
100
ns
tOE
tcx
10
10
ns

Address Change
tOHA
10
10
ns
Output 3-state from Oeselection
tOTO
80
80
ns
291
STATIC RAM MSM5126RS - - - - - - - - - - - - - - - - - - -
READ CYCLE
~------------tRC--------------~
A.'VA,.
I/O
Notes: 1. A Read occurs during the overlap of a low
-es,
a low OE and a high WE.

2. tcx is specified from CS or OE, whichever occurs last.
3. tOTO is specified from CS or OE, whichever occurs first.
4. tOHA and tOTO are specified by the time when DATA OUT is floating.
WRITE CYCLE
(V cc = 5V 10%, Ta = _30C to +85C)
Parameter
MSM5126-20
MSM5126-25
Min.
Min.
Max.
Max.
Unit
Write Cycle Time
twc
200
250
ns
Address to Write Setup Ti me
tAS.
ns
Write Time
tw
160
200
ns
tWR
10
10
ns
tDS
80
120
ns
ns
Write Recovery Time

Data Setup Time
tDH
Output 3-State from Write
tOTW
Notes:
292
Symbol
1.
2.
3.
4.
5.
6_
7.
80
80
A Write Cycle occurs during the overlap of a low CS and a low WE.
twR, tDS and tDH are specified from CS or WE, whichever occurs first.
ns
- - - - - - - - - - - - - - - - - - - . STATIC RAM MSM5126RS

WRITE CYCLE
I/O

(Ta = -30 e to +85C. unless otherwise noted)
0
Parameter
Typ.
Symbol
Min.
VCCH
Max.
Unit
ICCH
tsu
ns
tR
tRC
ns
V
0.05
30
p.A
- 1 - - - - STANDBY MODE
5V _ _
V.:;.C.:;.C_+-_ _---,
Conditions
VIN = OV to VCC. CS = VCC
VCC = 2V to 5.5V. VI = OV to VCC
CS? = VCC - 0.5V
----+-~-
tR
4.5V - - - - -
VCCH - - - VIL
- - -
- - - - '-------------'
CS
GND--- - - - - - - - - - - - - - - - - - -
- - - --- --- - ---
CAPACITANCE
(Ta = 25C. f = 1 MHz)
Parameter
Symbol
Typ.
Max.
CliO
10
pF
Input Capacitance
elN
10
pF
Min.
Unit
293
OKI
semiconductor
MSM5165RS/JS
8,192-WORD x 8-BIT CMOS STATIC RAM (E3-S-017-321
GENERAL DESCRIPTION
The MSM5165RS/JS is a 8192-word by 8-bit CMOS static RAM featuring 5V power supply operation and direct TTL
input/output compatibility_ Since the circuitry is completely static, external clock and r.efreshing operations are
unnecessary, making this device very easy to use. The MSM5165RS/JS is also a CMOS silicon gate device which
requires very low power during standby (standby current of lmA) when there is no chip selection.
for use as a peripheral memory for microcomputers and data term inal units etc. In addition, CE, CE, and OE signals
control etc.
FEATURES
.3-State Output
Pin Compatible with
64K EPROM
(MSM2764)
.28-pin DIP PKG
Single 5V Supply
etc -
70C
Standby;
5.5 mW MAX
Operation; 248 mW MAX
120 - 200 ns MAX
32-pin PLCC
PIN CONFIGURATION
(Top View)
(TOP VIEW)
<f <C uz uz
Ao - A"
Address INPUTS
I/O, - 1/08 : Data Input/Output
CE" CE,
: Chip Select
WE
: Write Enable
DE
Output Enable
VCC, VSS : Supply Voltage
294
~ I~
PIN CONFIGURATION
w
A,
A8
A;
A,
A,
All
A3
NC
110,-110, : Data INPUT/OUTPUT
A,
BE
A,
eE l ,GE 2
WE
: Chip Select
: Write Enable
AIO
BE
: OUTPUT Enable
A.
VCC. Vss : S!JPpfy Voltage
NC
1/0 8
lID,
1/0 7
14
g~
Vl
Vl
>
U
Z
ggg
Ao'"-A'2
: Address INPUTS
- - - - - - - - - - - - - - - - - - . STATIC RAM MSM5165RS/JS

A,o-----~=f--~
A. o-----Qc::1
A, 0-----"'.--1
A,
ROW
A. o-----Qc:::l:
A o----Qc:::l
~vcc
~Vss
Allo----QO
All o-----~=t__---1
1/0.
1/0,
1/0,
I/O.
1/0,
I/O.
O-..--~-;
o-~-~::1
INPUT
DATA
CON-
TROL
1/0, o-tt-t1fffl-l:l-:-1
1/0, o-+++t+H~=t-L_J
CE,
eel
WE
~ ~==3i~----------------------------~
295
STATIC RAM MSM5165RS/ JS - - - - - - - - - - - - - - - - - -
TRUTH TABLE
Mode
CE,
CE,
WE
OE
Standby
Read
Wreite
I/O Ope rat ion

High Z
High Z
DOUT
DIN
X: H or L

Symbol
Value
Unit
Supply Voltage
VCC
-0.3 to 7.0
I nput Voltage
VIN
-0.3 to VCC + 0.3
Rating
o to 70
Conditions
Respect to GND
Topr
Storage Temperature
T stg
-55 to 150
Power Dissipation
Po
1.0
Ta
25C

Parameter
Supply Voltage
Symbol
VCC
Min.
4.5
Output Load
5.5
Unit
V
2.2
VCC + 0.3
VIL
-0.3
0.8
100
pF
CL
Conditions
5V 10%
VIH
TTL
296
Max.
VSS
I nput Voltage
Typ.
5V 10%
- - - - - - - - - - - - - - - - - - . STATIC RAM MSM5165RS/JS

DC CHARACTERISTICS
MSM5165
Paramter
Symbol
Min.
Typ.
Max.
Unit
Test Condition
Input
Leakage
III
-1
IlA
VIN = Oto VCC
ILO
-1
IlA
OE = VIH
Output
VOH
2.4
Voltage
VOL
Current
Output
CE I = V I H or CE., = V I L or
Leakage
Current
VI/O = 0 to VCC
0.4
IOH = -1 mA
IOL = 2.1 mA
CE, ~ VCC - 0.2V, CE, ~ VCC - 0.2V
ICCS
0.02
mA
VIN = 0 to VCC
CE , ;'; 0.2V
Standby
Supply
VIN = 0 to VCC
Current
CE, = VIH, CE , = VIL
ICCS1
Operating
Supply
CD
ICCA
Current
mA
tcyc = Min, cycle

TCYC = Min, cycle
mA
15
TCYC=1Ils
516512
55 mA
516515
50 mA
516520
45 mA
AC CHARACTERISTICS
Test Condition
Parameter
Conditions
Input Pulse Level

10 ns
Input and Output

1.5V
Output Load
CL =100 pF, 1 TTL Gate
READ CYCLE
(V cc = 5V 10%, Ta = OCC to 70CC)
Parameter
Symbol
MSM516512
MSM516515
MSM516520
Min.
Min.
Min.
Max.
Max.
Unit
Max.
Read Cycle Time
tRC
Address Access Time
tAC
120
150
200
ns
Chip Enable Access Time
tco
120
150
200
ns
tOE
60
70
90
ns
tcx
10
1Q
10
ns

Address Change
tOHA
10
15
20
ns
Output Enable to Output Active
tox
Output 3state from Output Disable
tOTO
Output 3state from Chip Deselection
tCTD
120
150
ns
200
ns
40
50
60
ns
60
70
80
ns
297
STATIC RAM MSM5165RS/JS - - - - - - - - - - - - - - - - READ CYCLE
~-----------tRC----------~
1/0 --------....;::;.:..:.....*""~
Notas:
1.
2.
3.
4.
A Read occurs during the overlap of a low CE I , a high CE " a low OE and a high WE.
tcx is specified from CE I ' CE, or OE, whichever occurs last.
tOTO is specified from CE I , CE , or OE, whichever occurs first.
tOHA and tOTO are specified by the time when DATA OUT is floating.
WRITE CYCLE
(V cc = 5V 10%, Ta = OC to +70C)
Item
Write Cycle Time
twc
MSM5165-12
MSM5165-15
MSM5165-20
Min.
Min.
Min.
Max.
120
Max.
150
Unit
Max.
200
ns
tAS
ns
Write Time
tw
70
90
120
ns
Write Recovery Time
tWR
15
15
15
ns
Data Setup Time
tDS
50
60
80
ns
tDH
ns
tOTW
Chip Selection to End of Write
40
50
60.
ns
120
150
ns
tcw
100
Address Valid to End of Write
tAW
100
120
150
ns
Output Active from End of Write
twx
ns
Notes:
298
Symbol
1.
2.
3.
4.
5.
6.
7.
A Write Cycle occurs during the overlap of a low CE I , a high CE, and a low WE.
tAS is specified from CE I ' CE, or WE, whichever occurs last.
tw is an overlap time of a low CE I , a high CE , and a low WE.
twR, tDS and tDH are specified from CE I , CE. or WE, whichever occurs first.
When 1/0 pins are Data output mode, don't force inverse signal to those pins.
-----------------11. STATIC RAM MSM5165RS/JS

WRITE CYCLE
~------------~C------------~
CE,
I/O (DIN)
--------+-----1(
CAPACIT ANCE
(Ta = 2SoC, f = 1 MHz)
Parameter
Symbol
Max.
Unit
CliO
pF
Input Capacitance
CIN
pF
Min.
Typ.
299
OKI
semiconductor
MSM5165LRS IJS
8,192-WORD x 8-BIT CMOS STATIC RAM (E3-S-017-321
GENERAL DESCRIPTION
The MSM5165LRS/JS is a 8192-word by 8-bit CMOS static RAM featuring 5V power supply operation and direct TTL
unnecessary, making this device very easy to use. The MSM5165LRS/JS is also a CMOS silicon gate device which
requires very low power during standby (standby current of 100/tA) when there is no chip selection.
for use as a peripheral memory for microcomputers and data terminal units etc. In addition, CE, CE, and OE signals
control etc.
FEATURES
3-5tate Outpu t
Pin Compatible with
64K EPROM
(MSM2764)
.28-pin DIP PKG
.32-pin PLCC
Single 5V Supply
rt'C - 7rt'C
Standby; 0.55 mW MAX
120 - 200 ns MAX
PIN CONFIGURATION
(TOP VIEWI
cf<~~~I~ uw
PIN CONFIGURATION
A,
A,
Ao - A"
I/O, - I/O.
CE l ' CE,
WE
OE
:
:
:
:
,
Address INPUTS
Data Input/Output
Chip Select
Write Enable
Output Enable
300
All
Ao-A 12
NC
1/0,-110, : Data INPUT/OUTPUT
OE
CE1 .CE 2
Chip Select
WE
AlO
OE
CE,
VCC. Vss
Write Enable
OUTPUT Enable
Supply Voltage
I/O,
I/O,
: Address INPUTS
I/O,
- - - - - - - - - - - - - - - - - 1 . STATIC RAM MSM5165LRS/ JS

A,o-----~=f--~
A, 0--------Qc:::::J
A, 0--------".--1
As 0------
A, o------l:;id:
A 10 o--------QO
Au o--------QO
AI, o------i?;:=t..__~
1/0 1 ()---<.------t/----j--,
I/O, o-~-----t:?---H
I/O, o-tff---~:-I
1/0,0-+++.-----1>+1
I/O, o-+t+~---I>+1
I/O,o-+t+tff----I>+1
I/O, o-++tItt1--tt::f1
I/O, o-+t+fttt~---H
CE,
CE,
WE
~ ~==5i~------------------------------~
301
STATIC RAM MSM5165LRS/JS - - - - - - - - - - - - - - - TRUTH TABLE

WE
OE
High Z
DOUT
Standby
Read
Wreite
I/O Ope rat ion
CE,
CE ,
Mode
High Z
DIN
X: H or L

Symbol
Value
Unit
Supply Voltage
VCC
-0.3 to 7.0
I nput Voltage
VIN
-0.3 to VCC + 0.3
Topr
Storage Temperature
T stg
-55 to 150
Power Dissipation
Po
1.0
Rating
Conditions
Respect to GND
o to 70
Ta = 25C

Parameter
Supply Voltage
Symbol
VCC
Min.
4.5.
Input Voltage
Output Load
302
VCCH
VIH
2.2
VIL
-0.3
CL
TTL
Max.
Unit
5.5
Conditions
5V 10%
VSS
Typ.
5.5
VCC + 0.3
0.8
100
pF
5V 10%
- - - - - - - - - - - - - - - - - 1 . STATIC RAM MSM5165LRS/ JS
DC CHARACTERISTICS
MSM5165L
Paramter
Symbol
Unit
Min.
Typ.
Test Condition
Max.
Input
Leakage
III
-1
/lA
ILO
-1
/lA
Output
VOH
2.4
Voltage
VOL
VIN=OtoVCC
Current
Output
CEI = VIH or CE,
Leakage
= VIH
VI/a = 0 to VCC
IOH = -1 mA
IOL
Current
0.4
= VIL
or
OE
= 2.1
mA
CEI ~ VCC - 0.2V, CE, ~ Vec - 0.2V or

2
Ices
100
VIN
/lA
=0
to VCC
CE, ~ 0.2V
Standby
Supply
VIN = 0 to VCC
Current
CEI
IceSl
Operating
Supply
CD
ICCA
Current
mA
= VIH,
CE, = VIL
tcyc = Min, cycle

T CYC
= Min, cycle
mA
TCYC = 1 /lS
15
AC CHARACTERISTICS
Test Condition
Parameter
Conditions
I nput Pulse Level

10 ns
Input and Output

1.5V
Output Load
CL=100pF,1 TTL Gate
READ CYCLE
(Vee = 5V 10%, Ta = OC to
70C)
Parameter
MSM5165-12
MSM5165-15
MSM5165-20
Min.
Min.
Min.
Symbol
Max.
120
Max.
150
Unit
Max.
ns
Read Cycle Time
tRC
Address Access Time
tAC
120
150
200
ns
Ch ip Enable Access Time
tco
120
150
200
ns
90
ns
60
200
tOE
tcx
10
10
70
10
ns

Address Change
tOHA
10
15
20
ns
tox
Output 3-state from Output Disable
tOTD
40
50
60
ns
Output 3-state from Chip Deselection
tCTD
60
70
80
ns
ns
303
STATIC RAM MSM5165LRS/JS - - - - - - - - - - - - - - - - READ CYCLE
~-----------tRC----------~
--------=..:..:.....*
I/O
Notes:
1.
2.
3.
4.
A Read occurs during the overlap of a low CE l ' a high CE" a low OE and a high WE.
tcx is specified from CE l ' CE, or OE, whichever occurs last.
tOTD is specified from CE I ' CE, or OE, whichever occurs first.
tOHA and tOTD are specified by the time when DATA OUT is floating.
WRITE CYCLE
(V cc = 5V 10%, Ta = OC to
+70C)
MSM5165L-12
Item
MSM5165L-15
MSM5165L-20
Unit
Symbol
Min.
Max.
Min.
Max.
Min.
Max.
Write Cycle Time
!WC
120
150
200
tAS
ns
Write Time
tw
70
90
120
ns
Write Recovery Time
tWR
15
15
15
ns
tDS
50
60
80
ns
ns
Data Setup Time
ns
tDH
tOTW
tcw
100
120
150
ns
Address Val id to End of Write
tAW
100
120
150
ns
twx
ns
Notes:
304
40
50
60
A Write Cycle occurs during the overlap of a low CE I , a high CE, and a low WE.
tAS is specified from CE I ' CE, or WE, whichever occurs last.
tw is an overlap time of a low CE I , a high CE, and a low WE.
5. tWR, tDS and tDH are specified from CE I , CE, or WE, whichever occurs first.
6. tOTW is specified by the time when DATA OUT is floating, not defined by output level.
7. When I/O pins are Data output mode, don't force inverse signal to those pins.
1.
2.
3.
4.
ns
- - - - - - - - - - - - - - - - -... STATIC RAM MSM5165LRS/JS
WRITE CYCLE
~I~~-------------~C--------------~
~-----tw------~
CE I
~--+---+----tAW--------~
I+~~--+-----tcw------_~!
I/O (DIN)
I/O (DOUT)
-------1-----1(
------_./

(Ta = OC to +70C, unless otherwise noted)
Parameter
Symbol
Min.
VCCH
Typ.
Max.
Unit
Conditions
CEI~ VCC -O.2V, CE,~ VCC-O.2V
V
CE, .s O.2V
VCC = 3V, CE I ~ VCC - O.2V,
ICCH
50
JJ.A
CE,~ VCC - 0.2V
VCC = 3V, CE,.s0.2V

tsu
ns
tR
tRC
ns
305
STATIC RAM MSM5165LRS/JS - - - - - - - - - - - - - - - _
CE I CONTROL
STANDBY MODE
CE I
CE , ::::' VCC - 0.2V
ov
CE, CONTROL
4.5V
CE,
VCCH
VIL
OV
CAPACITANCE
na ~ 25C. f ~ 1 MHz)
Max.
Unit
CI/O
pF
CIN
pF
Parameter
Symbol
Input Capacitance
Min.
306
Typ.
o
__K__I__se_rn_IC_O_nc:I_U_c_._or_ _ _ _ _~
MSM5188US
16,384-WORD
x 4-BIT HIGH SPEED STATIC CMOS RAM
GENERAL DESCRIPTION
The MSM5188 is a static CMOS RAM organized as 16384 words by 4 bits. It features 5V single
power supply operation and direct TTL input/output compatibility. Since the circuitry is completely
static, external clock and refreshing operations are unnecessary which makes this device very easy
to use.
The MSM5188 is offered in a 22-pin slim package.
FEATURES
Single 5V supply (1 0%)

Completely static operation
Operating temperature range Ta = 0 to 70C
Low power dissipation
Standby. . . . . . . . . . . . . . . . . . 11 mW MAX
Operation ................ 605 mW MAX
Access time
45/55/70 ns MAX
Direct TTL compatible (Input and output)
3-State output
22 pin DIP PKG (300 mil width)
A,
A,
A,
A
A,
A,
A"
A"
A"
A"
A"
A"
A"
lID!
10,
PIN CONFIGURATION
0--~
"""
:0""U-
10,
10.
1/0,
Address input
I/O,toI/O.
Data input/output
cs
WE
CS
Chip Select
WE
Write Enable
VCC.VSS
Supply Voltage
INPUT
DATA
CONTROL
I--
I--
COLUMN 1/0
CIRCUIT
COLUMN SELECT
I---
I:=-
Ao AI A2 A3 A4
1104
AotoA13
I--
~~~~~
110,
Function
--aVec
--oVss
512ROWW
32 COLUMNS
x 4 BLOCK
ROW
SELECT
1/0,
Pin Names
MEMORY ARRAY
"<)---
A"
CS
vSS
I--
1h=:
307
_STATIC RAM MSM5188US _ . . _ - - - - - - - - - - - - - - - - - -
Rating
Supply Voltage
Symbol
Value
Condition
VCC
Unit
-0.3 to 7.0
-0.3 to 7.0
Ta = 25DC Respect to VSS

Input Voltage
VIN
Power Dissipation
PD
Topr
Storage Temperature
Tstg
Ta =25DC
1.0
DC
Oto +70
-55 to +150
DC
Parameter
Symbol
Conditions
Min.
Typ.
Max.
Unit
Supply Voltage
VCC
4.5
5.0
5.5
"H" Input Voltage
VIH
2.2
VCC +0.3
-0.3
0.8
30
pF
TTL Load
VCC =5V 10%

"L" Input Voltage
VIL
CL
Output Load
N
When pulse width is equal to or smaller than 20 ns, VIH max = VCC + 1.OV, VIL min = -1.OV.
DC CHARACTERISTICS
(VCC = 5V1 0%, Ta = ODC to 70 DC)
Parameter
Symbol
Conditions
Min.
Typ.
Max.
Unit
III
VI =OtoVCC
-1
/LA
ILO
CS=VIH
VI/O =OtoVCC
-1
/LA
"H" Output Voltage
VOH
IOH=-4mA
2.4
"L" Output Voltage
VOL
IOL =8 mA
ICCS
CS ~ VCC - 0.2V
VIN ~0.2VOR
VIN ~ VCC - 0.2V
mA
ICCS1
CS =VIH
TCYC = min cycle
18
mA
ICCA
Min cycle
110
mA
Standby Supply Current
Operating Supply Current
308
V
0.4
- - - - - - - - - - - - - - - - - - - - 1 1 . STATIC RAM MSM5188US

CAPACITANCE
(Ta = 25C, f = 1 MHz)
Parameter
Symbol
Condition
Min.
Max.
Unit
Input Capacitance
CI
VI =OV
pF
1/0 Capacitance
CliO
VI/O =OV
pF
AC CHARACTERISTICS TEST CONDITIONS

Parameter
Conditions
Input Pulse Level
VIH = 3.0V, VIL = OV
5 ns
Input/Output Timing Reference Level
1.5V
Output Load
CL = 30 pF, 1 TTL GATE
READ CYCLE
(VCC = 5V 10%, Ta = OC to 70C)
5188-45
Parameter
5188-55
5188-70
Symbol
Unit
Min.
Max.
Min.
Max.
Min.
Max.
Read Cycle Time
TRC
45
55
70
ns
Address Access Time
TAC
45
55
70
ns
TCO
45
55
70
ns
TCX
ns
Output Hold Time from

Address Change
TOHA
ns
Output 3-state from

Deselection
TOTO
Chip Selection to Power

upTime
TpU
Chip Deselection to Power

DownTime
TpD
25
30
30
55
ns
ns
0
45
70
ns
Notes: 1. Read Condition: During the overlap of a low CS and a high WE.
2. TCX and TOTD are measured 200 mV from steady state voltage with specified loading
in Figure 2.
309
.STATICRAMMSM5188US.-------------------------------------5V
5V
4800
4800
DOUT-_-~
DOUT------<.__-....
30pF
CL
2550
Figure 1
Figure 2
Output Load
WRITE CYCLE
(VCC = 5V1 0%, Ta
5 pF
CL
2550
Note: CL includes
scope and jig.
Output Load
OC to 70C)
5188-45
Parameter
5188-55
5188-70
Symbol
Unit
Min.
Max.
Min.
Max.
Min.
Max.
Write Cycle Time
TWC
45
55
70
ns
TCW
40
45
55
ns
TAW
40
45
55
ns
TAS
ns
Write Time
TW
30
35
40
ns
Write Recovery Time
TWR
10
10
ns
Data Setup Time
TDS
25
25
30
ns
TDH
ns
Output 3-state from Write
TOTW
TOW
Notes:
25
0
0
25
0
0
30
ns
ns
1.
2.
3.
4.
5.
Write condition: During the overlap of a low CS and a low WE.

TAS is specified from a low CS or a low WE, whichever occurs last after the address is set.
TW is an overlap time of a low CS and a low WE.
TWR, TDS and TDH are specified from a high CS or a high WE, whichever occurs first.
TOTW and TOW are measured 200 mV from steady state voltage with specified loading
in Figure 2.
6. When I/O pins are Data output mode, don't force inverse input signals to those pins.
READ CYCLE TIMING 1
--*-
AO-A"~-~TAC
DOUT -----T:...>O<..!.H.!!.A-'---t
310
Xd--------V-a-lid-D-at-a-------
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ STATIC RAM MSM5188US
READ CYCLE TIMING 2
-----. \:
,<-
lCO
TOTO
TCX
Open
DOUT
r--.XX~
TpU
Valid Data
Open
TPDI]
___ l ____
ICC
PowerS upply
ISS
50%
f-50%
iL-
WRITE CYCLE TIMING 1

(WE Control)
TWC
----;.
---I
1-
bk
:I
1-/77777
lAW
TAS
WE
TCW
TWRi
TW
'Sk-\
I
<-
TDS
TDH
Valid Data
f-
TOW
TOTW
Open
DOUT
l\
WRITE CYCLE TIMING 2

(CS Control)
TWC
Ao -A13
-----.
--'
TCW
~<-
--,
TAW
TWR
TW
\\\\\\\\\\\
11/1111
-,
TDS
TDH
3t
TOTW
DOUT
Valid Data
-*
Open
311
OKI
semiconductor
MSM51257RS/JS
32,768-WORD x 8-BIT CMOS STATIC RAM
GENERAL DESCRIPTION
The MSM51257 RS/JS is a 327G8-word by 8-bit CMOS static RAM featuring 5V power supply operation and direct
TTL input/output compatibility. Since the circuitry is completely static, external clock and refreshing operations
are unnecessary, making this device very easy to use. The MSM51257RS/JS is also a CMOS silicon gate device
which requires very low power during standby (standby current of 1 mAl when there is no chip selection.
CS and OE signals enable OR ties with the output terminals of other chips, thereby facilitating simple memory expansion and bus line control etc.
FEATURES
3-State Output
28-pin DIP PKG
.32-pin PLCC
Single 5V Supply
O"c -
70C
Standby;
5.5 mW MAX
Operation; 385mW MAX
85-120 ns MAX
PIN CONFIGURATION
(TOP VIEW)
.{ .j
u
Z
~ I~
PIN CONFIGURATION
.j
A6
A,
A,
A,
A,
A"
A,
NC
A,
OE
A,
A"
CS
WE
01'
CS
Vee, Vss : Supply Voltage
Address) NPUTS
Ao -- A14
liD, - liD, ; Data Input/Output
CS
WE
DE
1/0 7
Chip Select
: Write Enable
i
Output Enable
Vcc, VSS ; Supply Voltage
312
1/0,
g g >'"'"
ggg
A o -A I4
: Address INPUTS
1/0]-110 8 : Data INPUT IOUTPUT
: Chip Select
; Write Enable
: OUTPUT Enable
- - - - - - - - - - - - - - - - - . STATIC RAM' MSM51257RS/JS
~vcc
E-------O
Vss
cs~
WE
~ ~~3{~----------------------------~
313
STATIC RAM MSM51257RS/JS - - - - - - - - - - - - - - - -
TRUTH TABLE
1/0 Operation
Mode
CS
WE
OE
Standby
High Z
DOUT
Read
Wreite
High Z
DIN
X: H or L

Symbol
Value
Unit
Supply Voltage
VCC
-0.3 to 7.0
I nput Voltage
VIN
-0.3 to V CC + 0.3
Rating
Conditions
Respect to GND
o to 70
Topr
Storage Temperature
T stg
-55 to 150
Power Dissipation
Po
1.0
Ta
= 25C

Parameter
Supply Voltage
Symbol
Min.
Typ.
Max.
Unit
VCC
4.5
5.5
VSS
Input Voltage
Output Load
VIH
2.2
VIL
-0.3
CL
TTL
314
Conditions
5V 10%
V
VCC + 0.3
0.8
100
pF
5V 10%
- - - - - - - - - - - - - - - - - . STATIC RAM MSM51257RS/JS

DC CHARACTERISTICS
Paramter
MSM51257
Symbol
Min.
Typ.
Max.
Unit
Test Condition
Input
Leakage
III
-1
jjA
VIN = 0 to VCC
ILO
-1
jjA
OE = VIH
Output
VOH
2.4
Voltage
VOL
Standby
ICCS
Current
Output
CS
Leakage
Current
= VIH or
V I/O = 0 to VCC
0.02
10H = -1 mA
0.4
10L =2.1 mA
mA
CS
;::; VCC - 0.2V
VIN = 0 to VCC
Supply
Current
ICCSl
Operating
Supply
70
ICCA
CS
mA
= VIH
tcyc = Min, cycle
mA
MIN CYCLE
Current
AC CHARACTERISTICS
Test Condition
Conditions
Parameter
I nput Pulse Level
VIH = 2.4V, VI L = 0.6V
5ns
I nput and Output

Tim ing Reference Level
1.5V
Output Load
CL=l00 pF, 1 TTL Gate
READ CYCLE
(V cc = 5V 10%, Ta = OC to 70C)
Parameter
Read Cycle Time
Symbol
tRC
MSM51257-85
MSM51257-10
MSM51257-12
Min.
Min.
Min.
Max.
85
Max.
ns
120
100
Unit
Max.
tAC
85
100
120
ns
tco
85
100
120
ns
tOE
45
50
60
ns
tcx

Address Change
Address Access Time

10
10
10
ns
tOHA
10
10
ns
tOTD
tox
30
0
5
35
0
5
40
ns
ns
315
STATIC RAM MSM51257RS/JS - - - - - - - - - - - - - - - READ CYCLE
~------------tRC----------~
I/O
Notes:
1.
2.
3.
4.
--------:;;.:....*-f-(
A Read occurs during the overlap of a low CS, a low OE and ahigh WE.
tcx is specified from CS or OE, whichever occurs last.
tOTO is specified from CS or OE, whichever occurs first.
WRITE CYCLE
(Vee = 5V 10%, Ta = DoC to +70C)
Item
Write Cycle Time
MSM5125785
MSM5125710 MSM5125712
Min.
Min.
Symbol
twc
Max.
Max.
Min.
Max.
Unit
85
100
120
ns
tAS
ns
Write Tima
tw
65
75
90
ns
Write Recovery Time
tWR
10
10
ns
Data Setup Time
tDS
35
40
50
ns
tDH
Output 35tate from Write
tOTW
tcw
75
90
100
ns
tAW
75
90
100
ns
twx
15
ns

Notes:
316
1.
2.
3.
4.
5.
6.
7.
30
35
ns
40
A Write Cycle Occurs during the overlap of a low CS, and a low WE.
tw is an overlap time of a low CS,and a low WE.
tWR tDS and tDH are specified from CS or WE, whichever occurs first.
to-rW is specified by the time when DATA OUT is floating, not defined by output level.
ns
- - - - - - - - - - - - - - - - - . STATIC RAM' MSM51257RS/JS

WRITE CYCLE
~-------------~C------------~
~------tw------~
CS
~--+---+----tAW--------~
~~.--+-----tcw------~!
I/O (DIN)
-------4-----1(
CAPACITANCE
(Ta ~ 25C, f ~ 1 MHz)
Max.
Unit
CliO
pF
Input Capacitance
CIN
pF
Parameter
Symbol
Min.
Typ.
317
OKI
semiconductor
MSM51257LRS/JS
32,768-WORD x 8-BIT CMOS STATIC RAM
GENERAL DESCRIPTION
The MSM51257LRS/JS is a 32768-word by 8-bit CMOS static RAM featuring 5V power supply operation and direct
TTL input/output compatibility. Since the circuitry is completely static,external clock and refreshing operations are
unnecessary, making this device very easy to use. The MSM51257LRS/JS is also a CMOS silicon gate device which
requires very low power during standby (standby current of 1OOIlA) when there is no chip selection.
CS and OE signals enable OR ties with the output terminals of other chips, thereby facilitating simple memory
expansion and bus line control etc.
FEATURES
Single 5V Supply
rfc - 7rfC
Standby; 0.55 mW MAX
85-120 ns MAX

3-State Output
.28-pin DIP PKG
32-pin PLCC
PIN CONFIGURATION
(TOP VIEW)
.<J~~I~<
PIN CONFIGURATION
NC
DE
AIO
cs
A. - A,.
Address INPUTS
liD, - liD, : Data InputlOutput

CS
: Chip Select
WE
: Write Enable
DE
i Output Enable
318
I/O,
1/0,
~O-A14
Address INPUTS
110,-110, : Da .. INPUT/OUTPUT
CS
WE
DE
: Chip Select
: Write Enable
: OUTPUT Enable
VCC. VSS : Supply Voltage
- - - - - - - - - - - - - - - - 1 . STATIC RAM MSM51257LRS/JS
4--------0
Vee
-E----OVss
es~~
We
m ~==~~-------------------------------~
319
STATIC RAM MSM51257LRS/ JS - - - - - - - - - - - - - - - - -
TRUTH TABLE
I/O Ope rat ion
Mode
CS
WE
OE
Standby
High Z
High Z
DOUT
Read
Wreite
DIN
X: H or L

Symbol
Value
Unit
Supply Voltage
VCC
-0.3 to 7.0
I nput Voltage
V,N
-0.3 to VCC + 0.3
Rating
o to 70
Topr
Storage Temperature
T stg
-55 to 150
Power Dissipation
PD
1.0
Conditions
Respect to GND
Ta ~ 25C

Parameter
Supply Voltage
Symbol
VCC
Min.
4.5
Input Voltage
Output Load
320
VccH
V,H
2.2
V,L
-0.3
CL
TTL
Max.
Unit
5.5
VSS
Typ.
Conditions
5V 10%
V
5.5
VCC + 0.3
0.8
100
pF
5V 10%
-----------------I.STATICRAMMSM51257LRS/JS.
DC CHARACTERISTICS
Paramter
MSM51257
Symbol
Min.
Typ.
Max.
Unit
Test Condition
Input
Leakage
III
-1
IJA
VIN=OtoVCC
ILO
-1
IJA
OE = VIH
Output
VOH
2.4
Voltage
VOL
Standby
ICCS
Current
Output
CS
Leakage
Current
= VIH or
VI/O = 0 to VCC
IOH = -1 mA
0.4
IOL = 2.1 mA
100
IJA
~ VCC - 0.2V
CS
VIN = 0 to VCC
Supply
Current
ICCS1
Operating
Supply
mA
Cs
mA
MIN CYCLE
= VIH,
70
ICCA
Current
AC CHARACTERISTICS
Test Condition
Conditions
Parameter
Input Pulse Level
VIH = 2.4V, VIL = 0.6V
5ns
I nput and Output

1.5V
Output Load
CL=100 pF, 1 TTL Gate
READ CYCLE
(V cc = 5V 10%, Ta = OC to 70C)
Parameter
Symbol
MSM51257L-85 MSM51257L-l0 MSM51257L-12

Min.
Max.
Min.
Max.
Min.
Unit
Max.
Read Cycle Time
tRC
Address Access Time
tAC
85
100
120
ns
tco
85
100
120
ns
Output Enable to Output Val id
tOE
45
50
60
ns
85
100
ns
120
10
lQ
10
ns
tOHA
10
10
ns
Output 3state from Oeselection
tOTO
tox
tcx

Address Change
30
0
5
35
0
5
40
ns
ns
321
.STATICRAMMSM51257LRS/JS - - - - - - - - - - - - - - - -
READ CYCLE
~-----------tRC----------~
1/0
Notal:
1.
2.
3.
4.
-------......::::.:..:....-K-~
A Read occurs during the overlap of a low CS, a low OE and ahigh WE.
tcx is specified from CS or OE, whichever occurs last.
tOTO is specified from CS or OE, whichever occurs first.
WRITE CYCLE
(Vee = 5V 10%, Ta = OC to +700 C)
MSM51257L85 MSM51257L10 MSM51257L12

Item
Symbol
Unit
Min.
Max.
Min.
Max.
Min.
Max.
Write Cycle Time
twc
85
100
120
ns
tAS
ns
Write Time
tw
65
75
90
ns
Write Recovery Time
twR
10
10
ns
Data Setup Time
tos
35
40
50
ns
tOH
ns
Output 3State from Write
tOTW
30
35
40
ns
tcw
75
90
100
ns
tAW
75
90
100
ns
twx
15
ns
Notes:
322
1.
2.
3.
4.
5.
6.
7.
A Write Cycle occurs during the overlap of a low CS, and a low WE.
tw is anoverlap time of a low CS, and a low WE.
tWR, tos and tOH are specified from CS or WE, whichever occurs first.
tOTW is specified by the time when DATA OUT is floating, not defined by output leve\.
When 110 pins are Data output mode, don't force inverse signal to those pins.
- - - - - - - - - - - - - - - -... STATIC RAM MSM51257LRS/JS
WRITE CYCLE
~-------------~C------------~
CS
I/O (DIN) ------~I----~
I/O (DOUT) _ _ _ _ _ _ _J

(Ta = OC to +70C, unless otherwise noted)
Parameter
Typ.
Symbol
Min.
VCCH
ICCH
tsu
ns
tR
tRC
ns
Max.
50
Unit
Conditions
C S ~ VCC - 0.2V
p.A
VCC
3V, CS ~ VCC - 0.2V
323
.STATICRAMMSM51257LRS/JS - - - - - - - - - - - - - - - CS CONTROL
VCC
4.5V
CS ~ VCC - O.2V
CAPACITANCE
(Ta = 25C, f = 1 MHz)
Parameter
Symbol
Min.
Ma~.
Unit
CliO
pF
Input Capacitance
CIN
pF
324
Typ.
MOS
MASK
ROMS
OKI
semiconductor
MSM3864RS
8,192 WORD x 8 BIT MASK ROM
GENERAL DESCRIPTION
The MSM3864RS is an N-channel silicon gate MOS device MASK ROM with a 8,192 word x 8 bit capacity. It operates on a 5V single power supply and the all inputs and outputs are TTL compatible. The adoption of an asynchronous system in the circuit requires no external clock assuring extremely easy operation. The availability of power
down mode contributes to the low power dissipation which is as low as 30mA (max) when the chip is not selected.
The application of a byte system and the pin compatibility with standard UV EPROMs make the device most
suitable for use as a large-capacity fixed memory for microcomputers and data terminals.
As it provides CE, OE, and CS as the control signal, the connection of output terminals of other chips with the wired
OR is possible ensuring an easy expansion of memory and bus line control.
FEATURES
5V single power supply
.8,192 words x 8 bits
Access time: 250 ns MAX
Input/output TTL compatible

3-state output
Power down mode

28-pin DIP
PIN CONFIGURATION
Ao
(Top View)
A,
NC
A"
A,
27 CS2 (CS2)(NCI
26
CSlICS111NCI
A"
A,
25
A,
A,
Address
2. A,
A,
A,
buffer
A,
A,
\,J
28 v"
A,
23 A"
A,
22 OE
A,
21
A,
20 CE
Ao 10
19 0,
Do
18 0,
0,
"12
(OE)
A"
17 D,
0, 13
16~D4
14
15ho,
v"
A,
DE
Output enable
Vee, Vss
Ao""-'A12
00-07
Power supply
Address input
CE
Data output
Ch ip enable
CS1, CS2
Chip select
Note: Please specify the OE active

level and CS active level or
open in ordering this IC.
326
A,
A,
A"
A"
A"
--------------------------------------_._MASKROMMSM3864RS_
(Ta
= 25'C)
Rating
Symbol
Value
Unit
Conditions
Vee
-0.5 to 7
Respect to V 55
Respect to V 55

Input Voltage
VI
-0.5 to 7
Output Voltage
Vo
-0.5 to 7
Respect to Vss
Power Dissipation
PD
Per package
c
c
Operating' Temperature
T opr
a to 70
Storage Temperature
T stg
-55 to 150
OPERATING CONDITION AND DC CHARACTERISTICS

Rating
Symbol
Parameter
Measuring Condition
Unit
Min.
I nput Signal Level

Power Supply Current
Max.
Vee
4.5
5.5
Vss
VIH
-0.5
VIL
Output Signal Level
Typ.
VOH
10H = -4001J.A
VOL
10L = 2.1 mA
2.4
0.8
Vee
V
V
0.4
10
IJ.A
III
VI = OV or Vee
-10
ILO
Vo = OV or Vee
Chip not selected
-10
10
IJ.A
a mA
Icc
Vee = Max. 10 =
100
mA
Vee= Max. CE = VIH, 10= OmA
Ices
30
mA
Vee = GND - Vee Min.
60
mA
70
Peak Power ON Current
Ipo
T opr
CE = Vee or VIH
-
AC CHARACTERISTICS
TIMING CONDITIONS
Parameter
Conditions
Input Signal Level

Input Rising, Falling Time
tr=tf=15 ns
Input Voltage=1.5V
Timing Measuring Point Voltage
Output Voltage=0.8V & 2.0V
Loading Condition
327
MASK ROM . MSM3864RS
.1-------------------
READ CYCLE
(VCC = 5V 10%, VSS = OV, Ta = OC to +700 C)
Specification Value
Symbol
Parameter
Cycle Time
Typ.
Max.
250
tAA
250
ns
tACE
250
ns
tco
100
ns
100
tc
Address Access Time

Chip Enable
Access Time
Output Delay Time
tLZ
10
tHZ
10
Output Retaining Time
tOH
10
Power Up Time
tpu
Power Down Time
tPD
Output Setting Time

Output Disable Time
1) READ CYCLE-1
Remarks
Unit
Min.
ns
ns
100
ns
ns
ns
ns
(1)
~------------------tc------------------
Address
CS
DE (3)
(CS) or (DE)
(4)
i------tHZ
Dout
2) READ CYCLE-2(2)
i------------------tc---------------~
1~------tACE------~
CS
DE (3)
(CS) or (DE)
Dout
tpu
Vcc
supply
current
328
- - - - - - - - - - - - - - - - - -___
MASK ROM . MSM3864RS
Notes: (1)
(2)
(3)
(4)
el: is "L" level.

The address is decided at the same time as or ahead ofCE"L" level.
The OE and CS are shown in the negative logic here, however the active level is freely selected.
tLz is determined by the later level, CE "L"tCS "L" or ~ "L".
tHz is determined by the earlier CE "H"tCS "H" or OE "H".
While, tHz shows the time until floating and it is therefore not determined by the output level.
INPUT/OUTPUT CAPACITANCE
ITa = 25C, f = 1 MHz)
Parameter
Symbol
Specification
Value
Min.
Input Capacitance
Output Capacitance
CI
Co
Unit
Remarks
pF
VI=OV
10
pF
VO=OV
Max.
329
OKI
semiconductor
MSM38128ARS
16,384 WORD x 8 BIT MASK ROM (E3-5-028-32)
GENERAL DESCRIPTION
The MSM38128ARS is an N-channel silicon gate MOS device MASK ROM with a 16,384 word x 8 bit capacity. It
operates on a 5V single power supply and the all inputs and outputs are TTL compatible. The adoption of an asyn
chronous system in the circuit requires no external clock assuring extremely easy operation. The avaUability of power
The application of a byte system and the pin compatibility-with standard UV EPROMs make the device most suitable
for use as a large-capacity fixed memory for microcomputers and data terminals.
As it provides CE, OE, and CS as the control signal, the connection of output terminals of other chips with the wired
OR is possible ensuring an easy expand operation of memory and bus line control.
FEATURES
16384 words x 8 bits

.3-state output
Power down mode

28-pin DIP
PIN CONFIGURATION
(Top View)
NC
A"
A,
11
1 '--" 28 Vee
2
27 CS(CSJfNCi
26 A"
25 A,
A.
A,
24 A,
A.
23 A"
A,
22 OE (OE)
A,
21 A"
20 CE
A,
A. 10
19 0,
Do 11
18 D.
0, 12
17 0,
0, 13
16 D.
V.. 14
15 0,
OE
Output enable
Vee, Vss
Ao"'" Au
~- 07
Power supply
Address input
Data output
CE
Chip enable
Ch ip sel act
es
Note: Please specify the OE active

level and CS active level or
open in ordering this IC.
330
A.
A,
- - 0 Vee
A,
A,
A.
A,
A.
A,
A,
A,
A"
A"
A"
A"
-...oVss
buffer
CSor
OE CE
CS or
NC
Control
DEar
OE
- - - - - - - - - - - - - - - - - _ _ . _ MASK ROM MSM38128ARS _

(Ta = 25CI
Rating
Symbol
Value
Unit
Conditions
Vcc
-0.5 to 7
Respect to V ss

Input Voltage
VI
-0.5 to 7
Respect to V ss
Output Voltage
Vo
-0.5 to 7
Respeet to V ss
Power Dissipation
Per paekage-
Po
Topr
o to 70
Storage Temperature
T stg
-55 to 150

Symbol
Parameter
Vee
Vss
VIH
I nput Signal Level
Rating
Measuring Condition
VIL
Unit
Min.
Typ.
Max.
4.5
5.5
0.8
2
-0.5
ILl
VI =OVorV ee
-10
ILO
Vo = OVor Vee
Ch ip not selected
-10
10
/J.A
lee
Vee = Max. 10 = 0 mA
100
mA
lees
Vee
30
mA
Ipo

CE = Vee or VIH
60
mA
Qperating Temperature
Topr
70
Output Signal Level

VOH
10H =-400/J.A
VOL
10L = 2.1 mA
= Max.
2.4
Vee
0.4
10
/J.A
AC CHARACTERISTICS
TIMING CONDITIONS
Parameter
Conditions
I nput Signal Level

tr=tf=15 ns
Input Voltage=15V

Loading Condition

CL=100 pF + 1 TTL
331
.MASKROMMSM38128ARS ------------------------------------READ CYCLE

(VCC
5V 10%, VSS
OV, Ta
OC to +70C)
Specification Value
Parameter
Cycle Time
Address Access Time
Symbol
Typ.
Max.
250
tAA
250
ns
tACE
250
ns
tco
tc
Chip Enable
Access Time
Output Delay Time
100
ns
ns
10
100
ns
10
ns
tLZ
Output Disable Time
tHZ
tOH
Power Up Time
tpu
Power Down Time
tpD
ns
Output Setting Time
Unit
Min.
10
ns
100
ns
1) READ CYCLE-1 (1)
Address
CS
OE (3)
(CS) or (OE)
(4)
i-----tHZ
Dout
2) READ CYCLE-2(2)
i-----------tc--------------~
1~----tACE------~
CS
OE (3)
(CS) or (OE)
Dout
Vcc
supply
current
332
Remarks
------------------------------------___ MASKROMMSM38128ARS_
Notes:
(1)
(2)
(3)
(4)
CE is "L" level.
The address is decided at the same time as or ahead o(CE "L" level.
The 0 E and CS are shown in the negative logic here, however the active level is freely selected.
tLz is determined by the later level, CE "L",CS "L" or 01: "L".
tHz is determined by the earlier CE "H",CS "H" or OE "H".
While, tHz shows the time until floating and it is therefore not determined by the output level.
(Ta = 25C, f = 1 MHz)
Parameter
Symbol
Specification
Value
Min.
Input Capacitance
Output Capacitance
Unit
Remarks
Max.
CI
pF
V,=OV
Co
10
pF
VO=OV
333
OKI
semiconductor
MSM38256RS
32768 WORD x 8 BIT MASK ROM (E3-S-029-321
GENERAL DESCRIPTION
The MSM38256RS is an N-channel silicon gate MOS device ROM with a 32,768 word x 8 bit capacity. It operates on a 5V single power supply and the all inputs and outputs are TTL compatible. The adoption of an asynchronous system in the circuit requires no external clock assuring extremely easy operation. The availability of power
The application of a byte system and the pin compatibility with standard UV EPROMs make the device most suitable
for use as a large-capacity fixed memory for microcomputers and data terminals.
Since it provides CE, CS and OE signals, the connection of output terminals of other chips with the wired OR is
possible ensuring an easy expand operation of memory and bus line control.
FEATURES
.3-state output

Power down mode

28-pin DIP
PIN CONFIGURATION
(Top View)
ICS)(NCI CS
28
A"
A,
27 A..
A.
II
CS
~
Vee, VIS
A.-A,.
~-07
Note:
334
A.
A,
v""
26 A"
25 A.
A,
24 A,
A.
23 All
A,
22
A,
21
A"
A,
20
CE
OE
A. 10
19 D,
Do 11
18 D.
D, 12
17 D,
D, 13
16 D.
Vss 14
15 0 3
A,
A,
A.
A,
A.
A,
10E)
Chip Select
Output enable
Address input
Oata output
Chip anable
The OE active level and CS

active level are specified by
customer.
--aVe<
--a
v"
A.
A,
All
DE
or
DE
L-_..r~CS
A I4 O---
CS
NC
- - - - - - - - - - - - - - - - - -.... MASK ROM . MSM38256RS

(Ta = 25C)
Symbol
Value
Unit
Power Supply Voltaga
Vee
-0.5 to 7
Input Voltaga
VI
-0.5 to 7
Output Voltage
Vo
-0.5 to 7
Topr
Oto 70
Storaga Temperature
T stg
-55 to 150
Rating
Conditions
Respect to V SS

Rating
Parameter
Symbol
Power Supply Voltaga
Measuring Condition
4.5
5.5
-0.5
0.8
Vee
VOH
10H = -400 IlA
VOL
10L = 2.1 mA
III
VI =OVorV ee
ILO
Vo = OVor Vee
Ch ip not selected
lee
lees
Ipo
T opr
Max.
Vee
VIL
Output Signal Level
Typ.
Vss
VIH
I nput Signal Level
Unit
Min.
2.4
0.4
-10
10
IlA
-10
10
IlA
120
mA
Vee = Max.
30
mA

CE = VCC or VIH
60
mA
70
AC CHARACTERISTICS
TIMING CONDITIONS
Parameter
Conditions
Input Signal Level

tr=tf=15 ns
Input Voltage=I.5V
Output Voltage=0.8 & 2.0V
Loading Condition
CL=100 pF + 1 TTL
335
.MASKROMMSM38256RS -----------------------------------READ CYCLE

(VCC
5V 10%, VSS
Parameter
Symbol
Cycle Time
tc
= OV, Ta = OC to +70 C)
Specification Value
Min.
Typ.
Max.
Unit
ns
250
tAA
250
ns
tACE
250
ns
Output Delay Time
tco
100
ns
Output Setting Time
tLZ
100
ns
Address Access Time

Chip Enable
Access Time
ns
10
Output Disable Time
tHZ
10
tOH
10
Power Up Time
tpu
Power Down Time
tpD
ns
ns
100
ns
1) READ CYCLE-1 (1 )
Address
~(3)
(4)
i----tHZ
Dout
2) READ CYCLE-2(2)
i----------tc-------~
OE
(3)
CS
Dout
tpu
Vcc
supply
current
336
Icc
Ices
Remarks
- - - - - - - - - - - - - - - - - -.... MASK ROM . MSM38256RS

Notes:
(1)
'CE is "L"level.
(2)
(3)
(4)
or: and CS are shown in the negative logic here, however the active level is freely selected.
The address is decided at the same time as or ahead of CE "L" level.
tco and tLZ are determined by the later CE "L", OE "L" or CS "L".
tHz is determined by the earlier CE "H", OE "H" or ~ "H".
tHz shows time until floating therefore it is not determined by the output level.
INPUT IOUTPUT CAPACITANCE

(Ta = 2SC, f = 1 MHz)
Parameter
Symbol
Specification
Value
Min.
Unit
Remarks
Max.
Input Capacitance
CI
pF
VI=OV
Output Capacitance
Co
10
pF
VO=OV
337
OKI
semiconductor
MSM38256ARS
32768 WORD x 8 BIT MASK ROM (E3-S-030-32)
GENERAL DESCRIPTION
The MSM38256ARS is an Nchannel silicon gate E/DMOS device ROM with a 32,768 word x 8 bit capacity. It
operates on a 5V single power supply and the all inputs and outputs are TTL compatible. The adoption of an asyn
chronous system in the circuit requires no external clock assuring extremely easy operation. The availability of power
down mode contributes to the low power dissipation which is as low as 6mA (max) when the chip is not selected. The
application of a byte system and the pin compatibility with standard UV EPROMs make the device most suitable for
use as a large-capacity fixed memory for microcomputers and data terminals.
Since it provides CE, DE, CS signals, the connection of output terminals of other chips with the wired OR is possible
ensuring an easy expand operation of memory and bus line control.
FEATURES

3-5ta18 output
Power down mode

28-pin DIP
PIN CONFIGURATION
(Top View)
28 Vee
ICSICSINCI
A"
A,
27 A..
26 A"
A" 4
25 A.
A,
24 A,
A,.
23 Au
A,
6
7
A,
A,
21 A"
20
22
DE
cr
Ao to
19 0,
Do 11
18 0,
0, 12
17 0,
0, 13
16 D.
VSS 14
15 D3
A.
A,
- - 0 Vec
A,
A,
A.
A,
A,
A,
- - 0 V ..
buffer
A.
A,
CE.OE,CS
A"
Au
A"
A"
A I4
Control
DE
L-_ _.r~cs
o--
0,
CS
m
CE
DE
(CS) CS
Vee, Vss
A.-A,.
De-D,
(NC)
Chip enable
Output enable
Chip select
Address input
Data output
No Connection
Note: CS active level is specified

by customers.
338
NC
- - - - - - - - - - - - - - - - -_____ MASK ROM MSM38256ARS _

(Ta = 25C)
Symbol
Value
Unit
Vee
-0.5 to 7
Input Voltage
VI
-0.5 to 7
Output Voltage
Vo
-0.5 to 7
Rating
Topr
Oto 70
Storage Temperature
T stg
-55 to 150
c
c
PD
1.0
Power Dissipation
Conditions
Respect to V SS
Per package

Rating
Parameter
Symbol
Measuring Conditions
Min.
Typ.
Max.
Unit
Vee
4.5
5.5
Vss
"H" Input Signal Level
VIH
2.2
"L" Input Signal Level
VIL
-0.5
0.8
"H" Output Signal Level
VOH
10H = -400p,A
Vee
"L" Output Signal Level
VOL
10L = 2.1 mA
III
VI =OVor Vee
ILO
Vo=OVorVee
Chip not selected
Icc
2.4
0.4
-10
10
p,A
-10
1:>
p,A
60
mA
Ices
Vee = Max.
mA
Peak Power On Current
Ipo

CE = Vee or VIH
60
mA
70
Topr
Load Capacitance
CL
Fan Out
TTL Load
100
pF
Piece
AC CHARACTERISTICS
TIMING CONDITIONS
Parameter
Conditions
Input Signal Level

tr=tf=15 ns
Input VOltage=1.5V
Output Voltage=0.8 & 2.0V
Loading Condition
339
.MASKROMMSM38256ARS.I------------------------------------READ CYCLE
Symbol
Parameter
Specification Value
Min.
Typ.
Unit
Max.
ns
Cycle Time
tc
Address Access Time
tAA
150
ns
tACE
150
ns
150
Chip Enable
Access Time
Output Delay Time
tco
Output Setting Time
tLZ
Output Disable Time
tHZ
10
tOH
10
Power Up Time
tpu
Power Down Time
tpD
50
ns
ns
10
50
ns
ns
ns
100
ns
1) READ CYCLE-1 (1)
~-----------------~-------------~~
Address
CS
__ (3)
CS or OE
(4)
i------tHZ
Dout
2) READ CYCLE-2(2)
tc
CE
cs
en::
CS or 0
(3)
Dout
tpu
Vcc
supply
current
340
Icc
Iccs
Remarks
- - - - - - - - - - - - - - - - -____ MASK ROM . MSM38256ARS _

Notes:
(1)
(2)
(3)
(4)
cr is "L" level.
CS are shown in the negative logic here, however the active level is freely selected.
teo and tLZ are determined by the later CE "L", OE "L" Or CS "L".
tHz is determined by the earlier CE "H", OE "H" or CS "H".
ITa
25C, f = 1 MHz)
Parameter
Symbol
Specification
Value
Min.
Unit
Remarks
Max.
Input Capacitance
C,
pF
V,~OV
Output Capacitance
Co
pF
VO=OV
341
_O_K
__I__se
__
rn_i_c_O_ncl
__U_c_._o_r_____~
MSM38512RS
~
65536 WORD x 8 BIT MASK ROM
GENERAL DESCRIPTION
The MSM3851:?RS is an N-channel silicon gate E/DMOS device ROM with a 65,536 word x 8 bit capacity. It
operates on a 5V single power supply and the all inputs and outputs are TTL compatible. The adoption of an asynchronous system in the circuit requires no external clock assuring extremely easy operation. The availability of power
down mode contributes to the low power dissipation which is as low asl0mA(max) when the chip is not selected. The
application of a byte system and the pin compatibility with standard UV EPROMs make the device most suitable for
use as a large-capacity fixed memory for microcomputers and data terminals.
Since it provides CE, OE, signals, the connection of output terminals of other chips with the wired OR is possible
ensuring an easy expand operation of memory and bus line control.
FEATURES
512k bits: 65,536 words x 8 bit
high speed: access time 200 ns maX
low power: active current 60 mA max
standby Current lamA max
wide tolerance operating: Vcc ~ 5 V 10%
fully static operating: using no clock
fully TTL compatible
pin compatible to 512k EPROM
packaged to 28 pins plastic
fabricated with 2um NMOS silicon gate technology
PIN CONFIGURATION
(Top View)
[J
A"
A"
21 A..
A,
A,
A,
A.
26 A"
25 A.
A,
24 A.
A,
A,
A.
23 A"
A,
A,
22
6E
A,
21
A"
A.
A,
A,
20
CE
A, 10
19 0,
00 11
18 D.
0, 12
11 0,
0, 13
16 0,
v.. 14
15 D)
DE
Vee, Vss
A.-A,s
CE
D.- D7
342
28 Vee
Output enable
Address input
Chip enable
Data output
--0
A.
A.
A"
A"
A"
A"
A"
A"
Vee
Memorv cell
A,
Matrix
65536 x 8 bit
buffer
--oVss
- - - - - - - - - - - - - - - - - -..... MASK ROM MSM38512RS

(Ta
= 25"C)
Rating
Symbol
Value
Unit
Vee
-0.5 to 7
Conditions
Respect to VSS
I nput Voltage
VI
-0.5 to 7
Respect to VSS
Output Voltage
Vo
-0.5 to 7
Respect to VSS
Power Dissipation
Par package
PD
Topr
o to 70
Storage Temperature
Tstg
-55 to 150

Parameter
Symbol
Vee
Vss
Rating
Measuring Condition
Unit
Min.
Typ.
Max.
4.5
5.5
2.2
0.8
Input Leak Current
III
VI =OVorVcc
-10
Outpl/t Lea k Current
It.:O
VO= OVor VCC

Ch ip not selected
-10
10
!LA
60
mA
10
mA
VIH
Input Signal Level
VIL
Output Signal Level
-0.3
VOH
10H = -400 !LA
2.4
VOL
10L = 2.1 mA
Icc
Ices
0.4
10
!LA
AC CHARACTERISTICS
TIMING CONDITIONS
Parameter
Conditions
I nput Signal Level
VIH2.4V,VIL
tr = tf = 15 ns
0.6V
Input Voltage = 1.5V

Output Voltage = O.BV & 2.0V
Loading Condition
CL= 100pF
+ 1 TTL
343
MASK ROM MSM38512RS ...- - - - - - - - - - - - - - - - - READ CYCLE

Parameter
xxxxxxValue
Symbol
Unit
Min.
Typ.
Max.
tc
200
ns
tAA
Address Access Time
200
ns
Chip Enable
Access Time
tACE
200
ns
Cycle Time
Output Delay Time
tco
50
ns
Output Setting Time
tLZ
10
ns
Output Disable Time
tHZ
10
50
ns
tOH
10
ns
Power Up Time
tpu
ns
Power Down Time
tPD
100
ns
1) READ CYCLE-1
(1)
~~----------------tc--------------~
Address
(Note 4)
tHZ
Dout
2)
READ CYCLE-2(2)
~-----------------~-----------------
1-_ _ _ tACE (Note 2)
Dout
tpu
Vcc
supply
current
344
Icc
Ices
Remarks
------------------------------------__._MASKROMMSM38512RS_
Notes: (1)
(2)
(3)
(4)
CE is "L" level
tLZ is determined by the later level, CE "L" or OE "L".
tHZ is determined by the earlier CE "H" or OE "H".
While, tHZ shows the time until floating and it is therefore not determined by the output level.
(Ta: 2S'C, f : 1 MHz)
Parameter
Symbol
Specification
Value
Min.
Unit
Remarks
Max.
Input Capacitance
CI
pF
VI: OV
Output Capacitance
Co
10
pF
VO: 0'(1
345
OKI
semiconductor
MSM28101AAS
JAPANESE-CHARACTER GENERATING 1M BIT MASK ROM (E3-S-032-32l
GENERAL DESCRIPTION
The MSM 28101 AAS is aIM Bit Mask ROM using the N-channel silicon gate MOS process which stores 3,760 characters of numeric characters, Japanese cursive and square syllabarys, JIS 1st standard Japanese-characters, etc., in one
chip.
Because of its large capacity, Japanese-character pattern of 3,760 characters can be generated with only one chip.
Furthermore, since the dot matrix character form of 18 lines x 16 strings is available from the data out pin by only
inputting the J IS Japanese-character code into the address pin, the MSM28101 AAS is efficient and optimum for
constituting the Japanese-character terminal.
The power supply voltage is of 5 V single power supply, the input level is of TTL compatible, the data output is of
3-state output, the data valid is the output of the open collector and is packaged on the 40-pin DIP.
FEATURES
18 x 16 chinese-character font
output
Configuration
Duplex configuration of cellarray using the defect permissible
technique
Storage capacity 1082880 Bits
Number of
3,418 characters
generating
characters
Storage
Partition 0 - 7 and partition
character range 16 - 47 of Japanese-character
code system for JIS information
processing
14 Bits (A.-Au)
Address input
16Bits (D.-D 15 ,3-state)
Data output
16 Bits x 18 times transfer
Output mode
Address enable 1 each (AE)
Data valid
Clock
Used temperature
Access time
Data transfer
rate
Interface
Power supply
voltage
Power consumption
Package
Memory cell
Function
1 each (DV, open collector output)

1 each (</>T) DC - 1.5MHz
Ta ~ 0 - 70C
10 IJS MAX
22 IJs/character
TTL level
5V single power supply (5%)
700 mWTYP
Side-brazed 40-pin DIP
Multi-gate ROM
This specification is subject to change without notice
PIN CONFIGURATION
(Top View)
Ao"'A13: Addroess input

Do ...... ~: Data output
AE: Address enable
DV: Data valid output
</>T: Clock input
VCC: Power supply voltage (5V)
VSS: GND (OV)
(Note) Connect all VCC and VSS terminals.
346
- - - - - - - - - - - - - - - - -_____ MASK ROM MSM281 01 AAS _
1lV
AE
I>r
A"
I>.
A,
Data
latch
1M Bit cell array
Decoder
A,
D";
Ir,
A,
14bit
Ir,
A.
D";
A,
A,
ll,
Address
Buffer
I>.
A,
D";
A,
rr.
A,
AlO
Decoder
I>.
OW
Data
1M Bit cell array
latch
A"
I),;
14 bit
A"
I),;
A"
rr,;
rr,;
lJ,;

(Ta = 25C)
Rating
Input Terminal Voltage
Output Terminal Voltage
Power Dissipation
Storage Temperature
Symbol
Vcc
VIN
VOUT
Conditions
Value
Unit
Respect to Vss
-0.5 -7
Respect to Vss
-0.5 -7
Respect to Vss
-0.5 -7
PD
0-70
Topr
-35 - 125
Tstg
C
C

Specification value
Symbol
Conditions
Vcc
5V 5%
Vss
Parameter
Input Signal Level

Min.
Typ.
Max.
Unit
4.75
5.25
VIH
Respect to Vss
2.0
VIL
Respect to Vss
-0.5
O.S
Topr
70
V
C
347
.MASKROMMSM28101AAS.I------------------------------------DC CHARACTERISTICS
(Vcc = 5V 5%, Ta =
oc to + 70C)
Parameter
Symbol
Conditions
Specification value
Typ.
Min.
Max.
Vcc
2.4
Unit
V
VOH
IOH=-0.2 mA
VOL
IOL =1.6 mA
III
VIN=O -Vcc
-10
10
p.A
ILO
VOUT=O -Vcc
VAE=0.8V
-10
10
p.A
Output Signal Level
0.4
Average Power Supply Current
ICCA
tRC=22/LS
tC=650 ms
tAR=300 ns
170
mA
Steady State Power Supply Current
ICCS
V AE=0.8V
170
mA
AC CHARACTERISTICS
TIMING CONDITIONS
Parameter
Conditions
Input Signal Level

tr = tf = 15 ns

Input Timing Level
1.5V
Loading Condition
CL = 50 pF, 1TTL Gate
READ CYCLE
(Vcc = 5V 5%, Ta = OC to +70C)
Specification Value
Parameter
Symbol
Conditions
Min.
Typ.
Max.
Unit
Read Cycle Time
tRC
22
p.S
Address Setti ng Ti me
tAS
ns
AE Pulse Width
tAE
300
ns
Address Retaining Time
tAH
100
DV Access Time
tvA
10
p.S
DV Delay Time
tvD
150
ns
DV Retaining Time
tVH
100
ns
T Pulse Width
tH
200
ns
T Delay Time
tL
450
ns
tDH
50
ns
AE Setting Time
tAES
ns
348
ns
- - - - - - - - - - - - - - - - - -___ MASK ROM MSM28101 AAS _
ADDRESS
(Ao -A
13
)
AE
VALID
DON'T CARE
-]'-tAS--tAHC------
------I
~---------------------tRC------------------~
DOUT
(0.-0-;-,)
High Impedance
(Note
(Note
(Note
(Note
(Note
1)
2)
3)
4)
5)
(Note 6)
High Impedance
DV is determined by the falling of qn-.

DV changes with the falling of qn-.
qn- and On DATA are repeated 18 times during DV is Low.
The On timing levels are 2.0 V and 0.8 V.
Sometimes it will not normally operate unless input is made at least once with
AE as the dummy after input of power supply.
DV is an open collector output and On is a 3stage output.
(Ta =
25C, f = 1 MHz)
Parameter
Symbol
Conditions
Specification val ue
Min.
Typ.
Max.
Unit
Input Capacitance (excluding AE)
CIN
VIN
= OV
pF
Input Capacitance (AE terminal!
CIN
VIN
= OV
15
pF
VOUT
= OV
pF
Output Capacitance
COUT
349
_ MASK ROM MSM281 01 AAS _____- - - - - - - - - - - - - - - - -
FUNCTIONAL CHARACTERISTICS
Parameter
Specification
Unit
Font Type
18 lines x 16 strings dot matrix
Output Mode
16 bits x 18 times transfer
Number of Generating
characters
3418
(Note 11
(Note
11
Word
o-
7 (Non chinese-character area)

16 - 47 (JIS -1st standard)
Storage Character Range
Remarks
Partition
(Note 2)
The correspondence of the 181ines x 16 strings matrix and the data out pins are as shown in the diagram
below_
Output for the character portion will be Low (VOLI and the output for the background portion will be
High (VoHI-
4_-------16Iines--------
18
-II-l-~+--l t=AT17
t= AT 18
................1.-.......1
ttftfffttt'fttft
Data out pins Do
DV
0; 0; 0.0::;
Os 0. D., D.
D.D,oDIID12D'30,.lJ,";
~I----~11~------------------~
qyr~
I
I- .1AT,
(Note 2)
The correspondence of the 1st and 2nd bytes of JIS C 6226 and the address pins are as shown below.
Second byte
JIS C 6226
b,
Address Pin
350
.1
AT.
A'3
I b. I bs I b. I b3 I b. I
I A,. I All I A,o I A. I A. I
First byte
b,
b,
A,
A.
I b. I
I As I
bs
A.
I b. I b3 I b. I b,
I A3 I A. I A, I A.
OKI
semiconductor
MSM28201AAS
1M BIT MASK ROM FOR JAPANESE-CHARACTER PATTERN (E3-S-033-32)
GENERAL DESCRIPTION
The MSM28201 AAS is aIM-bit mask ROM employing an N-channel silicon gate MOS process, and with 3760 Japanese-characters (kanji conforming with JIS No.2 standards) incorporated in single chip.
With this large capacity, 3760 Japanese-character patterns can be generated in a single chip. And by only a single
input of JIS Japanese-character code via the address pin, 18-row x 16-column dot matrix character forms can be
obtained from the data output p.in, making this device ideal for construction of functionally versatile Japanese-character terminals.
The power supply voltage is 5V single, the input level TTL compatible, outputs are tri-state data out, and data valid
is denoted by open collector. The device is mounted in a 40-pin DIP.
FEATURES
Function . . . . . . . 18 x 16 chinese-character font
output
Configuration . . . . Duplex configuration employing
defect permissible technique
Storage capacity. . . 1082880 bits
Number of generated
characters . . . . . . 3384 characters
Accommodation. _ . Japanese-character encoded
character region
partitions 48 to 87 for JIS
data processing.
Address input . . . . 14 bits (Ao to All)
Data output _ . . . . 16 bits (Do to 0", tristate)
Output mode . . . . 16 bit x 18 transfers
Address enable . . .
Data valid . . . . . .
Clock . . . . . . . . .
Operating temperature . . . . . . . _ ..
Access time . . . . .
Data transfer rate . .
Interface . . . . . . .
Power consumption.
Package. . .
.
Memory cell . . . . .
1 (AE)
1 (DV, open collector output)
1 (4)T) DC to 1.5MHz
Ta=OC to 70C
10 lotS MAX.
22 lots/character
TTL level
5V si ngle ( 5%)
700 mW TYP
Side-brazed 40-pin DIP
Multi-gate ROM
PIN CONFIGURATION
(Top View)
Ao - Au:
Do A E:
DV:
4>T:
Vcc:
Vss:
t>.,:
Address inputs
Data outputs
Address enable
Data valid output
Clock input
Power supply voltage (5 V)
GND (0 V)
Note: All Vss pins are to be connected
351
MASK ROM . MSM28201AAS - - - - - - - - - - - - - . . . , - - - - - - -
1W
AE
...
A"
J:iO
A,
Decoder
A,
A,
1M 81teel1 array
Data
latch
1),
n;
n;
14bit
A,
1),
A,
A.
J:iO
Address
Buffer
D:
A,
n;
A.
--00;
A,
0;
Decoder
1M Biteell artay
A"
Data
0-;;;
latch
0;;
AI:
14 bit
0;;
A"
0;;
D;<
-----0 ~

(Ta = 25C)
Rating
Symbol
Conditions
Value
Unit
Vcc
Respect to Vss
-0.5-7
Input \toltage
VI
Respect to Vss
-0.5-7
Output Voltage
Vo
Respect to Vss
-0.5-7
Power Dissipation
Po
Topr
0-70
Storage Temperature
Tstg
-35-125

Parameter
Symbol
Conditions
Min
Vcc
Vss
5V 5%
Range Value
Typ
Max
Unit
5.25
V
V
4.75
"H" Input Voltage
VIH
Respect to Vss
2.0
"L" Input Voltage
VIL
Respect to Vss
-0.5
0.8
Topr
70
352
------------------------------------___ MASKROMMSM28201AAS_
DC CHARACTERISTICS
(Vcc= SV S%, Ta= OCto +70C)
Parameter
Symbol
Range Value
Conditions
Unit
Min.
"H" Output Voltage
VOH
IOH --0.2 mA
"L" Output Voltage
VOL
IOL = 1.6 mA
III
VI = 0 - VCC
ILO
Average Power Supply Current

Rated Power Supply Current
Typ.
Max.
2.4
Vo = 0 - VCC
VAE = 0.8V
VCC
-10
10
p.A
-10
10
p.A
170
mA
170
mA
tRC = 22p.S, tc = 6S0 ns

ICCA
tAE = 300ns
ICCS
VAE = 0.8V
0.4
AC CHARACTERISTICS
TIMING CONDITIONS
Parameter
Conditions
Input Signal Level

Input Rise/Fall Time
tr=tf=lSns
Input Timing Level
1.SV
CL =SOpF, lTTL Gate
Output Load
READ CYCLE
(VCC = SV S%, Ta = oc to +70C)
Parameter
Symbol
Specification Value
Conditions
Min.
Typ.
Unit
Max.
Read Cycle Time
tRC
22
p.S
Address Setting Time
tAS
ns
AE Pulse Width
tAE
300
ns
Address Retaining Time
tAH
100
DV Access Time
tvA
ns
10
p.S
DV Delay Time
tVD
ISO
ns
DV Retaining Time
tVH
100
ns
<t>T Pulse Width
tH
200
ns
<t>T Delay Time
tL
4S0
ns
SO
ns
ns
tDH
AE Setting Time
tAES
353
.MASKROMMSM28201AAS -----------------------------------
Address
(A. -AnI _ _ _J
DON'T CARE
VALID
AE
tVA
(Note 31
OUT
(o.-OISI
----------r---------<
High Impedance
Notes:
(Note 4)
High Impedance
1. OV is determined by the .pT falling edge.

2. OV is changed by the.pT falling edge.
3 . .pT and OnOATA are repeated 18 times when OV is low.
4. On timing levels of 2.0V and 0.8V.
5. Normal operation may not be possible unless there is at least one AE dummy input after
the power is switched on.
6. OV denotes open collector output, and IJrl the tristate output.
(Ta=25C, f=1 MHzl
Range Value
Parameter
Symbol
Conditions
Min.
Typ.
Max.
Unit
Input Capacitance (excluding AEI
CI
VI=OV
15
pF
Input Capacitance (AE pin)
CI
VI=OV
35
pF
Output Capacitance
Cci
VO=OV
10
pF
354
-------------------------------------.MASKROMMSM28201AAS.
FUNCTIONAL CHARACTERISTICS
18-row x 16-column dot matrix
Output Mode
16 bit x 18 transfers
Number of Characters Generated
(Note 1)
Word
3384
48~87
Character Accommodation Region
Remarks
Unit
Range
Parameter
Font Format
(JIS No.2 standard)
(Note 2)
Partition
Note 1. The relation between the 18-row x 16-eolumn matrix and the data output pins is outlined below. The output
is low (VOL) for the character portion. and high (VOH) for the background area .
....- - - - - - - 1 6 columns ------.~~

t=6.7 1
t=6'1' 2
I
I
I
I
I
I
I
18
I
I
I
I
I
I
I
t=6T 18
ttf::i;t::;~~;tt
Oataoutputpins
0;; 0, Dz 0,0. 0, D. D, 0. D.
0'00.,012 0.,0..0"
Note 2. The address pins are related to the JIS C6226 no.l and no.2 bytes in the following way.
No.1 byte
No.2 byte
JIS C 6226
Address Pin
b,
Au
b.
bs
I b. I
b,
I bz 1 b,
I Au I A" I A,. I A. I A. I A,
b,
I b, I b, I
A.
I As I A. I A. I A. I A, I A.
b.
I b. I b z I b,
355
OKI
semiconductor
MSM53256RS
32,768 WORD x 8 BIT MASK ROM
GENERAL DESCRIPTION
The MSM53256RS is a silicon gate CMOS devic.e ROM with 32,768 words x 8 bit capacity. It operates on a 5V
single power supply and all inputs and outputs are TTL compatible. The adoption of an asynchronous system in the
circuit requires no external clock assuring extremely easy operation. The availability of power down mode contributes to the low power dissipation when the chip is not selected. The application of a byte system is most suitable
for use as a large capacity fixed memory for microcomputers and data terminals.
Since it provides signals, the connection of output terminals of other chips with the wired OR is possible ensuring an
easy expand operation of memory and bus line control.
FEATURES
256k bits: 32,768 words x 8 bits

High speed: access time 150 ns max
Low power: active current 15 mA max
standby current 0.1 mA max

Pin compatible to 256k EPROM
Packaged to 28 pins plastic
Fabricated with CMOS silicon gate technology
Wide tolerance operating: Vcc = 5V 10%

Fully static operating: using no clock
PIN CONFIGURATION
(Top View)
(NClleS)
cs
A"
A,
A,
27 A"
26 A"
25 A,
- - 0 Vss
A,
A.
A,
2. A,
A,
23 A"
A,
A,
22
OE
A,
21
A,
A,
A"
A,
20
CE
18 0,
0, 12
17 0,
D2 (13
16 D.
Vssl14
15 0,
D.
CS
OE
Vcc, Vss
A o -A'3
0 0 -0,
: Chip select
Output enable
Address input
Data output
: CHip enable
Note: CS active level is specified

by customer.
356
--0
A,
19 0,
Vee
A,
A,
A.
A. 10
CE
A.
28 Vee
A"
A"
A"
A"
DC
DE
L..
too-<>
cs
0'
cs
NC
--------------------------------------.MASKROMMSM53256RS.
(Ta = 25C)
Rating
Symbol
Value
Unit
Conditions
Vee
-0.3 to 7
Respect to Vss
Input Voltage
VI
-0.3 to Vee + 0.3
Respect to V ss
Output Voltage
Vo
-0.3 to Vee + 0.3
Respect to Vss
Power Dissipation
Po
Per package
T opr
o to 70
Storage Temperature
T stg
-55 to 150

Rating
Symbol
Parameter
Input Signal Level
Output Signal Level
Unit
Measuring Condition
Min.
Typ.
Max.
Vee
4.5
5.5
Vss
VIH
2.2
Vee +0.3
VIL
-0.3
0.8
VOH
10H = -4001J.A
2.4
0.4
VOL
10L = 2.1 mA
III
VI = OV or Vee
-10
10
IJ.A
ILO
Vo = OV or Vee
Chip not selected
-10
10
IJ.A
ICCA
Vee = Max. 10 = 0 mA,

tc = 150 ns
15
mA
ICCS
Vee = Max. CE = Vee - 0.2V
0.1
mA
ICCSl
Vee = Max.
CE = VIH min.
0.5
mA
70
Topr
AC CHARACTERISTICS
TIMING CONDITIONS
Parameter
Conditions
Input Signal Level
VIH = 2.4V, VI L = 0.6V
tr=tf=15 ns
Input Voltage=1.5V

Loading Condition

CL=100pF + 1 TTL
357
.MASKROMMSM53256RS -----------------------------------READ CYCLE

(Vee
= 5V 10%, VSS = OV, Ta = oOe to

Symbol
Parameter
+70 e)
0
Specification Value
Min.
Typ.
Max.
150
Unit
ns
Cycle Time
tc
Address Access Time
tAA
150
ns
tACE
150
ns
Chip Enable
Access Time
Output Delay Time
tco
Output Setting Time
tLZ
50
Output Disable Time
tHZ
10
tOH
10
1) READ CYCLE-1
(1)
ns
ns
10
50
ns
ns
~----------------tc-------------~
Address
(4)
1------tHZ
Dout
2) READ CYCLE-2(21
~----------------tc--------------"""
es
es or
>= (31
u<:
Dout
358
Remarks
________________________________________ MASKROMMSM53256RSNotes:
(1) CE" is L" level.

The address is decided at the same time as or ahead 01 CE uL u level.
(3) CS are shown in the negative logic here, however the active level is freely selected.
(4) teo and tLZ are determined by the later CE "L", OE "L" or CS "L".
tHz is determined by the earlier CE uH", OE "H" or CS uH".
U
(2)
(Ta
25C, 1 ~ 1 MHz)
Parameter
Symbol
Specification
Value
Min.
Unit
Remarks
Max.
Input Capacitance
CI
pF
VI~OV
Output Capacitance
Co
pF
VO~OV
359
OKI
semiconductor
MSM531000RS
131,072 WORD x 8 BIT MASK ROM (E3-S-031-32l
GENERAL DESCRIPTION
The MSM531000RS is a silicon gate CMOS device ROM with 131,072 words x 8 bit capacity. It operates on a 5V
single power supply and all inputs and outputs are TTL compatible. The adoption of an asynchronous system in the
circuit requires no external clock assuring extremely easy operation. The availability of power down mode contributes to the low power dissipation when the chip is not selected. The application of a byte system is most suitable
for use as a large capacity fixed memory for microcomputers and data terminals.
Since it provides signals, the connection of output terminals of other chips with the wired OR is possible ensuring an
easy expand operation of memory and bus line control.
FEATURES
131 ,072 words x 8 bits
I nput/output TTL compatible

3-state output
28-pin DIP
PIN CONFIGURATION
(Top View)
A"
A"
A,
A.
A,
~-D7
360
27 A"
26 A"
25 A
2. A,
A,
23 A"
A,
A,
22 A"
21 A"
A,
20
CE
A, 10
19 D,
D,
"
18 D.
D, 12
17 D,
D, 13
16 D,
V"
Vee, Vss
Ao.-..;AI3
A,
28 voc
"
15 D,

Address input
Data output
Chip enable
Vee
A,
---0
A,
--OVss
A,
A,
A,
A.
A,
buffer
A.
A,
CE
A"
A"
A"
A"
A"
A"
A"
Control
-------------------------------------.MASKROMMSM531000RS.
(Ta = 25C)
Rating
Symbol
Value
Conditions
Unit
Vee
-0.3 to 7
Respect to V ss
Input Voltage
VI
-0.3 to Vee + 0.3
Respect to V ss
Output Voltage
Va
-0.3 to Vee + 0.3
Respect to Vss
Power Dissipation
PD
Per package
T opr
o to 70
Storage Temperature
T stg
-55 to 150

Rating
Symbol
Parameter
Power Su pply Voltage
Max.
4.5
5.5
2.2
Vee +0.3
-0.3
0.8
VOH
10H = -400/iA
2.4
0.4
-10
10
/iA
-10
10
/iA
15
mA
0.1
mA
0.5
mA
70
Vee
VIH
VIL
au tput Signal Level
VOL
III
VI = OV or Vee
ILO
ICCA
ICCS
ICCSl
Topr
Min.
10L = 2.1 mA
Unit
Typ.
Vss
Input Signal Level
Measuring Condition
Va = OV or Vee
Chip not selected
Vee = Max. 10 = 0 mA,
tc = 250 ns
Vee = Max. CE = Vee - 0.2V
Vee = Max.
CE = VIH min.
-
AC CHARACTERISTICS
TIMING CONDITIONS
Parameter
Conditions
Input Signal Level
VIH = 2.4V, VI L = 0.6V
tr=tf=15 ns
Input Voltage=1.5V

Loading Condition
CL =100 pF + 1 TTL
361
MASK ROM MSM531000RS - - - - - - - - - - - - - - - - - READ CYCLE

(VCC = 5V 10%,
vss = OV, Ta = oc to +70C)

Specification Value
Parameter
Symbol
Unit
Min.
Typ.
Max.
250
ns
250
ns
CyCle Time
tc
Address Access Time
tAA
tACE
250
ns
ns
80
ns
ns
Chip Enable
Access Time
Address Setti ng Time
tAS
Output Setting Time
tLZ
10
Output Disable Time
tHZ
10
Output F'letaining Time
tOH
10
Remarks
ns
READ CYCLE
tc
Address
-tOH-CE
Note 1
tHZ
Dout
Valid Data
Note: tHZ shows the time until floating and it is therefore not determined by the output level.
362
- - - - - - - - - - - - - - - - -____ MASK ROM . MSM531000RS _
(Ta = 25C. f = 1 MHz)
Parameter
Specification
Value
Symbol
Min.
Max.
Unit
Remarks
Input Capacitance
CI
pF
VI=OV
Output Capacitance
Co
.-
pF
VO=OV
363
MOS
EPROMS
OKI
semiconductor
MSM2764AS
8192 x 8 BIT UV ERASABLE ELECTRICALLY PROGRAMMABLE
READ-ONLY MEMORY
GENERAL DESCRIPTION
The MSM2764 is a 8192 words x 8 bit ultraviolet erasable and electrically programmable readonly memory. Users can freely prepare the memory content, which can be easily changed, so the
MSM2764 is ideal for microprocessor programs, etc. The MSM2764 is manufactured by the N channel double silicon gate MOS technology and is contained in the 28 pin package.
FEATURES
+5V single' power supply
8192 words x 8 bit configuration
Access time:
MAX200 ns (MSM2764-20)
MAX250 ns (MSM2764-25)
MAX300 ns (MSM2764-30)
Power consumption:
MAX525 mW (during operation)
MAX184 mW (during stand-by)
Perfect static operation
INPUT/OUTPUT TTL level
(three state output)
PIN CONFIGURATION
(Top View)
---vee
PGM
-vpp
CE
---GND
DE
OE
AoA1 ______ A12

This specification may be changed without notification.
366
____________________________
__________
~.EPROMMSM2764AS.
FUNCTION TABLE
eE
(20)
OE
(22)
PGM
(27)
Vpp
(1 )
vee
Read
VIL
VIL
VIH
+5V
+5V
Dout
Output Disable
VIL
VIH
VIH
+5V
+5V
High impedance
Stand-by
VIH
+5V
+5V
High impedance
Program
VIL
VIL
+21V
+6V
DIN
Program Verify
VIL
VIL
VIH
+21V
+6V
Dout
Program Inhibit
VIH
+21V
+6V
High impedance
Mode
Outputs
(2B)
-; ean be either VIL or VIH

Ta ......................... -1 ooe Tstg ....................... -55e VIN. VOUT ................. -0.6V Vee ....................... -0.3V Vpp ....................... -0.6V Po ........................ 1.5W
Temperature Under Bias

Storage Temperature
AlllnputlOutput Voltages
Vee Supply Voltage
Program Voltage
Power Assembly Voltage
BOoe
125e
13.5V
7V
23V
The voltage with respect to GND.
<READ OPERATION>
RECOMMENDED OPERATION CONDITION
Limit
Parameter
Symbol
Min.
Typ.
Max.
Vee Power Supply

Voltage
Vee
4.75
5.0
5.25
Vpp Voltage
Vpp
4.15
5.0
5.B5
Operating
Temperature
VIH
2.00
6.25
"L" Level Input

Voltage
VIL
-0.1
O.B
Symbol
V
V
ooe -70 oe
"H" Level Input

Voltage
Remarks
Vee=5VO.25V
Vpp=Vee0.6V
The voltage with respect to GND
367
.EPROMMSM2764AS ----------------------------------------DC CHARACTERISTICS

(VCC = 5V5%, Vpp = VCC0.6V, Ta = OC - 70C)
Limits
Parameter
Symbol
Conditions
Unit
Min.
Typ.
Max.
III
VIN =5.25V
10
/LA
ILO
VOUT =5.25V
10
/LA
VCC Power Current (Stand-by)
ICC,
CE =VIH
35
mA
VCC Power Current (Operation)
ICC2
CE =VIL
100
mA
Program Power Current
Ipp,
Vpp = VCC0.6V
mA
2.0
VCC+1
-0.1
0.8
Input Voltage "H" Level
VIH
Input Voltage "L" Level
VIL
Output Voltage "H" Level
VOH
IOH = -400 /LA
2.4
Output Voltage "L" Level
VOL
IOL = 2.1 mA
0.45
AC CHARACTERISTICS
2764-20
Parameter
Symbol
2764-25
2764-30
Conditions
Unit
Min.
Max.
Min.
Max.
Min.
Max.
Address Access Time
tACC
CE =OE =VIL,
PGM =VIH
200
250
300
ns
CE Access Time
tCE
OE =VIL,
PGM =VIH
200
250
300
ns
OE Access Time
tOE
CE =VIL,
PGM =VIH
70
100
120
ns
Output Disable Time
tDF
CE =VIL,
PGM =VIH
60
85
105
ns
Measurement condition
Input pulse level .......................... 0.45V and 2.4V
Input timing reference level ............... 0.8V and 2.0V
Output load .............................. 1TTL GATE + 100pF
Output timing reference level .............. 0.8V and 2.0V
368
----------------------------------------____ EPROMMSM2764AS_
TIME CHART
Address input
CE
Data output
369
.EPROMMSM2764AS.I---------------------------------------<PROGRAMMING OPERATION>
DC CHARACTERISTICS
(VCC = 6V0.25V, Vpp = 21 V0.5V, Ta = 25C5C)
Limits
Parameter
Symbol
Conditions
Unit
Min.
Typ.
Max.
III
VIN =5.25V
10
JLA
Vpp Power Current
Ipp
CE =PGM =VIL
30
mA
VCC Power Current
ICC
100
mA
VIH
2.0
VCC+1
VIL
-0.1
0.8
VOH
IOH = -400 JLA
2.4
VOL
IOL=2.1 mA
0.45
AC CHARACTERISTICS
(VCC = 6V0.25V, Vpp = 21 V0.5V, Ta = 25C5C)
Limits
Parameter
Symbol
Conditions
Unit
Min.
Typ.
Max.
Address Set-up Time
tAS
JLs
OE Set-up Time
tOES
JLs
Data Set-up Time
tos
JLs
Address Hold Time
tAH
JLs
Data Hold Time
tOH
JLs
Output Enable to Output

Float Delay
tOFP
130
ns
Vpp Power Set-up Time
tvs
JLs
PGM Initial Program Pulse Width
tpw
0.95
1.0
1.05
ms
PGM Overprogram Pulse Width
topw
3.8
63
ms
CE Set-up Time
tCES
JLs
Data Valid from OE
tOE
150
ns
370
------------------------------------------.EPROMMSM2764AS.
TIME CHART
ADDRESS N
Data - - - {
input/output
Vpp
PGM------,
OE
CAPACITANCE
(Ta = 25C, f = 1 MHz)
Parameter
Symbol
Conditions
Min.
Typ.
Max.
Unit.
Input Capacitance
CIN
VIN =OV
pF
Output Capacitance
COUT
VOUT =OV
12
pF
371
OKI
semiconductor
MSM27128AS
READ-ONLY MEMORY
GENERAL DESCRIPTION
MSM27128 is ideal for microprocessor programs, etc. The MSM27128 is manufactured by the N
channel double silicon gate MOS technology and is contained in the 28 pin package.
FEATURES
+5V single power supply
Access time:
MAX200 ns (MSM27128-20)
MAX250 ns (MSM27128-25)
MAX300 ns (MSM27128-30)
Power consumption:
INPUT/OUTPUTTTL level
PIN CONFIGURATION
(Top View)
+--VCC
PGM
-vpp
CE
-GND
Oe
DE
AoAl------
A13
372
_______________________________________._EPROMMSM27128ASFUNCTION TABLE
eE
(20)
OE
(22)
PGM
(27)
Vpp
(1)
vee
(2B)
Read
VIL
VIL
VIH
+5V
+5V
Dout
Output Disable
VIL
VIH
VIH
+5V
+5V
High impedance
Stand-by
VIH
+5V
+5V
High impedance
Program
VIL
VIL
+21V
+6V
DIN
Program Verify
VIL
VIL
VIH
+21V
+6V
Dout
Program Inhibit
VIH
+21V
+6V
High impedance
Mode
Outputs

Ta ......................... -1O o e Tstg ....................... -55e VIN. VOUT ................. -0.6V Vee ....................... -0.3V Vpp ....................... -0.6V PD ........................ 1.5W

Storage Temperature
AlllnputlOutput Voltages
Vee Supply Voltage
Program Voltage
BOoe
125e
13.5V
7V
23V
< READ OPERATION>

Limit
Parameter
Symbol
Min.
Typ.
Max.
Vee Power Supply

Voltage
Vee
4.75
5.0
5.25
VppVoltage
Vpp
4.75
5.0
5.25
Operating
Temperature
VIH
2.00
6.25
"L" Level Input

Voltage
VIL
-0.1
O.B
Symbol
V
V
ooe -70 oe
"H" Level Input

Voltage
Remarks
Vee=5V5%
Vpp=Vee0.6V
373
.EPROMMSM27128AS --------------------------------------DC CHARACTERISTICS

Limits
Parameter
Symbol
Conditions
Unit
Min.
Typ.
Max.
III
VIN =5.25V
10
/LA
ILO
VOUT =5.25V
10
/LA
ICC,
CE =VIH
35
mA
ICC2
CE =VIL
100
mA
Ipp,
Vpp = VCC0.6V
mA
VIH
2.0
VCC+1
VIL
-0.1
0.8
VOH
IOH = -400 /LA
2.4
VOL
IOL =2.1 mA
0.45
AC CHARACTERISTICS
27128-20
Parameter
Symbol
27128-25
27128-30
Conditions
Unit
Min.
Max.
Min.
Max.
Min.
Max.
Address Access Time
tACC
CE =OE =VIL,
PGM =VIH
200
250
300
ns
CE Access Time
tCE
OE =VIL,
PGM =VIH
200
250
300
ns
OE Access Time
tOE
CE =VIL,
PGM =VIH
75
100
120
ns
Output Oisable Time
tOF
CE =VIL,
PGM =VIH
60
105
ns
Outputload .............................. 1TTL GATE + 100pF
374
60
--------------------------------------___ EPROMMSM27128AS_
TIME CHART
Address input
Data output
375

(VCC = 6V0.25V. Vpp = 21 V0.5V. Ta = 25C5C)
Limits
Parameter
Symbol
Conditions
Unit
Min.
Typ.
Max.
III
VIN =5.25V
10
/LA
Vpp Power Current
Ipp
CE=PGM =VIL
30
rnA
VCC Power Current
ICC
100
rnA
VIH
2.0
VCC+1
VIL
-0.1
0.8
VOH
IOH = -400 /LA
2.4
VOL
IOL =2.1 rnA
0.45
AC CHARACTERISTICS
(VCC = 6V0.25V. Vpp = 21 V0.5V. Ta = 25C5C)
Limits
Parameter
Symbol
Conditions
Unit
Min.
Typ.
Max.
Address Set-up Time
tAS
OE Set-up Time
tOES
Data Set-up. Time
tDS
Address Hold Time
tAH
/Ls
Data Hold Time
tDH
/Ls

Float Delay
tDFP
130
ns
tvs
/Ls
tpw
0.95
1.0
1.05
ms
topw
3.8
ms
tCES
63
CE Set-up Time
/Ls
Data Valid from OE
tOE
150
ns
376
/Ls
/Ls
/Ls
--------------------1. EPROM MSM27128AS

TIME CHART
ADDRESS N
Data ---<
input/output
Vpp
PGM------,
tOES
OE
CAPACITANCE
(Ta = 25C, f = 1 MHz)
Parameter
Symbol
Conditions
Min.
Typ.
Max.
Unit.
Input Capacitance
CIN
VIN =OV
pF
Output Capacitance
COUT
VOUT =OV
12
pF
377
OKI
semiconductor
MSM27256AS
READ-ONLY MEMORY
GENERAL DESCRIPTION
The MSM27256 is a 32768 words x 8 bit ultraviolet erasable and electrica"y programmable readonly memory. Users can freely prepare the memory content, which can be easily changed, so the
FEATURES
Access time:
MAX150 ns (MSM27256-15)
MAX200 ns (MSM27256-20)
MAX250 ns (MSM27256-25)
Power consumption:
PIN CONFIGURATION
(Top View)
-Vcc
PGM
-Vpp
CE
-GND
OE
OE
AoA1 ______ A14

378
--------------------1. EPROM MSM27256AS

FUNCTION TABLE
eE
(20)
OE
(22)
Vpp
(1 )
vee
(28)
Read
VIL
VIL
+5V
+5V
Dout
Output Disable
VIL
VIH
+5V
+5V
High impedance
Stand-by
VIH
+5V
+5V
High impedance
Program
VIL
VIH
+12.5V
+6V
DIN
Program Verify
litH
VIL
+12.5V
+6V
Dout
Program Inhibit
VIH
VIH
+12.5V
+6V
High impedance
Mode
Outputs
-; Can be either VIL or VIH

Storage Temperature
All Input/Output Voltages
Vee Supply Voltage
Program Voltage
Ta ........................
Tstg .... . . . . . . . . . . . . . . . . ..
VIN. VOUT .............. "
Vee .........
Vpp ......................
PD .......................
-10 o e - 80 0 e
-55e - 1250 e
-0.6V - 13.5V
-0.3V -7V
-0.6V - 13.5V
1.5W
<READ OPERATION>
Parameter
Limit
Symbol
Min.
Typ.
Max.
Vee Power Supply

Voltage
Vee
4.75
5.0
5.25
Vpp Voltage
Vpp
4.75
5.0
5.25
Operating
Temperature
VIH
2.00
6.25
"L" Level Input

Voltage
VIL
-0.1
0.8
Symbol
V
V
aoc -70 oe
"H" Level Input

Voltage
Remarks
Vee=5V5%
Vpp=Vee
379
.EPROMMSM27256AS ---------------------------------------DC CHARACTERISTICS

(VCC = 5V5%, Vpp = VCC, Ta = OC - 70C)
Limits
Parameter
Symbol
Conditions
Unit
Min.
Typ.
Max.
III
VIN =5.25V
10
/-lA
ILO
VOUT =5.25V
10
/-lA
ICC,
CE =VIH
35
mA
ICC2
CE =VIL
100
mA
Ipp,
Vpp=VCC
mA
VIH
2.0
VCC+1
VIL
-0.1
0.8
VOH
IOH =-400/-lA
2.4
VOL
IOL =2.1 mA
0.45
AC CHARACTERISTICS
Parameter
Symbol
27256-15
27256-20
27256-25
Min. Max.
Min. Max.
Min. Max.
Conditions
Unit
Address Access Time
tACC
CE =OE =VIL
150
200
250
ns
CE Access Time
tCE
OE =VIL
150
200
250
ns
OE Access Time
tOE
CE =VIL
70
75
100
ns
Output Oisable Time
tOF
CE =VIL
50
55
60
ns
380
----------------------------------------~.EPROMMSM27256AS.
TIME CHART
Address input
OE
Data output
381

(VCC = 6V0.25V, Vpp = 12.5V0.5V, Ta = 25C5C)
Limits
Parameter
Symbol
Conditions
Unit
Min.
Typ.
Max.
III
VIN =5.25V
10
JA-A
Vpp Power Current
Ipp
CE =VIL,OE =VIH
50
rnA
VCC Power Current
ICC
100
rnA
VIH
2.0
VCC+1
VIL
-0.1
0.8
VOH
IOH =-400JA-A
2.4
VOL
IOL=2.1 rnA
0.45
AC CHARACTERISTICS
(VCC = 6V0.25V, Vpp = 12.5V0.5V, Ta = 25C5C)
Limits
Parameter
Address Set-up Time
Symbol
tAS
Conditions
-
Unit
Min.
Typ.
Max.
JA-s
JA-s
JA-s
OE Set-up Time
tOES
Data Set-up Time
tos
Address Hold Time
tAH
JA-s
Data Hold Time
tOH
JA-s

Float Delay
tOFP
130
ns
tvs
JA-s
CE Initial Program Pulse Width
tpw
0.95
1.0
1.05
ms
CE Overprogram Pulse Width
topw
2.85
78.75
ms
Data Valid from OE
tOE
150
ns
382
--------------------------------------___ EPROMMSM27256AS_
TIME CHART
ADDRESSN
Data ---<
input/output
Vpp
PGM-------~
t-+fooIIf-tOES
CAPACITANCE
(Ta = 25C, f = 1 MHz)
Parameter
Symbol
Conditions
Min.
Typ.
Max.
Unit.
Input Capacitance
CIN
VIN =OV
pF
Output Capacitance
COUT
VOUT=OV
12
pF
383
OKI
semiconductor
MSM27512AS
READ-ONLY MEMORY
GENERAL DESCRIPTION
FEATURES
Access time:
MAX150 ns (MSM27512-15)
MAX200 ns (MSM27512-20)
MAX250 ns (MSM27512-25)
Power consumption:
PIN CONFIGURATION
(Top View)
-Vcc
PGM
CE
-GND
OE
AoAl
_____
A15
04
03
384
-----------------------------------------.EPROMMSM27512AS.
FUNCTION TABLE
Pins
CE
(20)
OElVpp
(22)
VCC
(28)
Read
VIL
VIL
+5V
Dout
Output Disable
VIL
VIH
+5V
High impedance
Stand-by
VIH
+5V
High impedance
Program
VIL
Vpp
+6V
DIN
Program Inhibit
VIH
Vpp
+6V
High impedance
Mode
Outputs

Storage Temperature
AlllnputiOutput Voltages
VCC Supply Voltage
Program Voltage
Ta ......................... -10C Tstg ....................... -55C VIN. VOUT ................. -0.6V VCC ....................... -0.3V Vpp ....................... -0.6V PD ........................ 1.5W
80C
125C
13.5V
7V
13.5V
<READ OPERATION>
Limit
Parameter
Symbol
Min.
Typ.
Max.
VCC Power Supply

Voltage
VCC
4.75
5.0
5.25
"H" Level Input

Voltage
VIH
2.00
6.25
"L" Level Input

Voltage
VIL
-0.1
0.8
Operating
Temperature
Remarks
Symbol
V
OC -70C
VCC=5V5%
V
V
385
.EPROMMSM27512AS ---------------------------------------DC CHARACTERISTICS

(VCC = 5V5%, Ta = OC - 70C)
Limits
Symbol
Parameter
Conditions
Unit
Min.
Typ.
Max.
III
VIN =5.25V
10
J.tA
ILO
VOUT =5.25V
10
J.tA
ICC,
CE =VIH
35
rnA
ICC2
CE =VIL
100
rnA
2.0
VCC+1
-0.1
0.8
VIH
VIL
VOH
IOH =-400J.tA
2.4
VOL
IOL = 2.1 rnA
0.45
AC CHARACTERISTICS
(VCC = 5V5%, Ta = OC - 70C)
Parameter
Symbol
27512-15
27512-20
27512-25
Min.
Max.
Min.
Max.
Min. Max.
Conditions
Unit
Address Access Time
tACC
CE =OElVpp =
VIL
150
200
250
ns
CE Access Time
tCE
OElVpp =VIL
150
200
250
ns
OE Access Time
tOE
CE =VIL
70
75
100
ns
Output Disable Time
tDF
CE =VIL
50
55
60
ns
Input pulse level .......................... 0.45Vand 2.4V
Output load .............................. HTL GATE + 100pF
TIME CHART
Address input
Data output
386
_________________________________________I.EPROMMSM27512AS.
DC CHARACTERISTICS
(VCC = 6VS%, Vpp = 12.5V0.SV, Ta = 2S 0 CSOC)
Limits
Parameter
Symbol
Unit
Conditions
Min.
Typ.
Max.
III
VIN =5.25V
10
p.A
Vpp Power Current
Ipp
CE =VIL
50
mA
VCC Power Current
ICC
100
mA
VIH
2.0
VCC+1
VIL
-0.1
0.8
VOH
IOH = -400 p.A
2.4
VOL
IOL = 2.1 mA
0.45
AC CHARACTERISTICS
(VCC = 6V0.25V, Vpp = 12.5V0.5V, Ta = 25C5C)
Limits
Parameter
Address Set-up Time
Symbol
Conditions
Unit
Min.
Typ.
Max.
tAS
p's
Data Set-up Time
tDS
p's
Address Hold Time
tAH
p's
Data Hold Time
tDH
p's
CE Enable to Output
Float Delay
tDFP
130
ns
tvs
p's
CE Initial Program Pulse Width
tpw
0.95
1.0
1.05
ms
CE Overprogram Pulse Width
topw
2.85
78.75
ms
OElVpp Hold Time
tOEH
p's
Data Valid from CE
tDV
p's
OElVpp Recovery Time
tVR
p's
387
.EPROMMSM27512AS.--------~------------------------------
TIME CHART
Address
ADDRESS N
input
Data
input/output
OElVpp
CE
tpw
topw
CAPACITANCE
(Ta = 25C, f = 1 MHz)
Parameter
Symbol
Conditions
Min.
Typ.
Max.
Unit.
Input Capacitance
CIN
VIN =OV
pF
Output Capacitance
COUT
VOUT =OV
12
pF
388
OKI
semiconductor
~~
---------------------------------------------------------------------~~~
MSM271000AS

READ-ONLY MEMORY
GENERAL DESCRIPTION
The MSM271 000 is a 131072 words x 8 bit ultraviolet erasable and electrically programmable
read-only memory. Users can freely prepare the memory content, which can be easily changed, so
the MSM271 000 is ideal for microprocessor programs, etc. The MSM271 000 is manufactured by the
N channel double silicon gate MOS technology and is contained in the 32 pin package.
FEATURES

Access time:
MAX120 ns (MSM271 000-12)
MAX150 ns (MSM271 000-15)
MAX200 ns (MSM271 000-20)
Power consumption:
INPUT/OUTPUTTTLlevel
PIN CONFIGURATION
A"
NC
000,
0,
A'3
As
Ae
A11
+---Vcc
PGM
PGM
OE
A2
AlO
A,
CE
Ao
0,
+---Vpp
CE
CE
OE
OE
""""--GNO
06
AoA,
---
--
A16
ThiS specification may be changed without notification
389
.EPROMMSM271000AS .-------------------------------------FUNCTION TABLE

Pins
eE
(22)
OE
(24)
PGM
(31)
Vpp
(1 )
Vee
(32)
Read
VIL
VIL
VIH
+5V
+5V
Dout
Output Disable
VIL
VIH
VIH
+5V
+5V
High impedance
Stand-by
VIH
+5V
+5V
High impedance
Program
VIL
VIL
+12.5V
+6V
DIN
Program Verify
VIL
VIL
VIH
+12.5V
+6V
Dout
Program Inhibit
VIH
+12.5V
+6V
High impedance
Mode
Outputs
-; ean beeitherVILorVIH

Ta ......................... -1 oDe - 80 De
Tstg ....................... -55 De - 125 De
VIN. VOUT ................. -0.6V -13V
Vee ....................... -0.3V - 7V
Vpp ....................... -0.6V -13.5V
Po ........................ 1.5W

Storage Temperature
All Input/Output Voltages
Vee Supply Voltage
Program Voltage
<READ OPERATION>
Limit
Parameter
Symbol
Min.
Typ.
Max.
Vee Power Supply

Voltage
Vee
4.75
5.0
5.25
Vpp Voltage
Vpp
4.75
5.0
5.25
VIH
2.00
6.25
"L" Level Input

Voltage
VIL
-0.1
0.8
Remarks
Symbol
V
V
oDe -70 De
"H" Level Input

Voltage
390
Operating
Temperature
Vee=5V0.25V
Vpp=Vee
V
V
--------------------------------------____ EPROMMSM271000AS_
DC CHARACTERISTICS
(VCC = 5V5%, Vpp = VCC, Ta =
ovc -
70C)
Limits
Symbol
Parameter
Conditions
Unit
Min.
Typ.
Max.
III
VIN =5.25V
10
/LA
ILO
VOUT =5.25V
10
/LA
ICC,
CE =VIH
35
rnA
ICC2
CE =VIL
100
rnA
Ipp,
Vpp=VCC
rnA
VIH
2.0
VCC+ 1
VIL
-0.1
0.8
VOH
IOH = -400 /LA
2.4
VOL
IOL = 2.1 rnA
0.45
AC CHARACTERISTICS
271000-12 271000-15 271000-20
Parameter
Symbol
Conditions
Unit
Min. Max.
Min. Max.
Min. Max.
Address Access Time
tACC
CE =OE =VIL,
PGM =VIH
120
150
200
ns
CE Access Time
tCE
OE =VIL,
PGM =VIH
120
150
200
ns
OE Access Time
tOE
CE =VIL,
i5GM =VIH
50
60
75
ns
Output Oisable Time
tOF
CE =VIL,
PGM =VIH
40
50
55
ns
391
.EPROMMSM271000AS -------------------------------------TIME CHART
Address input
Data output
392
--------------------------------------____ EPROMMSM271000AS_
<PROGRAMMING OPERATION>
DC CHARACTERISTICS
(VCC = 6V0.25V, Vpp = 12.5V0.5V, Ta = 25C5C)
Parameter
Limits
Symbol
Conditions
Unit
Min.
Typ.
Max.
III
VIN =5.25V
10
p.A
Vpp Power Current
Ipp
CE = PGM =VIL
50
mA
VCC Power Current
ICC
100
mA
VIH
2.0
VCC+1
VIL
-0.1
0.8
VOH
IOH = -400 p.A
2.4
VOL
IOL =2.1 mA
0.45
AC CHARACTERISTICS
(VCC = 6V0.25V, Vpp = 12.5V0.5V, Ta = 25C5C)
Limits
Parameter
Symbol
Conditions
Unit
Min.
Typ.
Max.
Address Set-up Time

OE Set-up Time
tAS
p's
tOES
p's
Data Set-up Time
tos
p's
Address Hold Time
tAH
p's
Data Hold Time
tOH
p's

Float Delay
tOFP
130
ns
tvs
p's
tpw
0.95
1.05
ms
topw
2.85
78.75
ms
CE Set-up Time
tCES
p's
Data Valid from OE
tOE
150
ns
1.0
393
.EPROMMSM271000AS -------------------------------------TIME CHART
ADDRESSN
----<
Data
input/output
Vpp
PGM-----~
tOES
CAPACITANCE
(Ta = 25C, f = 1 MHz)
Parameter
Symbol
Conditions
Min.
Typ.
Max.
Unit.
Input Capacitance
CIN
VIN =QV
pF
Output Capacitance
COUT
VOUT =QV
12
pF
394
OKI
semiconductor
MSM271024AS
READ-ONLY MEMORY
GENERAL DESCRIPTION
The MSM271024 is a 65536 words x 16 bit ultraviolet erasable and electrically programmable
the MSM271 024 is ideal for microprocessor programs, etc. The MSM271 024 is manufactured by the
N channel double silicon gate MOS technology and is contained in the 40 pin package.
FEATURES
Power consumption:

Access time:
MAX120 ns (MSM271 024-12)
MAX150 ns (MSM271 024-15)
MAX200 ns (MSM271 024-20)
PIN CONFIGURATION
NC
A14
A13
A"
All
o.
Vss
AlO
A,
...-----..- Vee
PGM
PGM
4------
Vss
A.
CE
CE
A,
Of
OE
Vpp
...-----GND
This specificatIOn may be changed without nOTification
395
.EPROMMSM271024AS.-------------------------------------FUNCTION TABLE
Pins
eE
(2)
OE
(20)
PGM
(39)
Vpp
(1 )
Vee
(40)
Read
VIL
VIL
VIH
+5V
+5V
Dout
Output Disable
VIL
VIH
VIH
+5V
+5V
High impedance
Stand-by
VIH
+5V
+5V
High impedance
Program
VIL
VIL
+12.5V
+6V
DIN
Program Verify
VIL
VIL
VIH
+12.5V
+6V
Dout
Program Inhibit
VIH
+12.5V
+6V
High impedance
Mode
Outputs

Storage Temperature
Vee Supply Voltage
Program Voltage
Ta ......................... -10C Tstg ....................... -55C VIN, VOUT ................. -0.6V Vee ....................... -0.3V Vpp ....................... -0.6V PD ........................ 1.5W
BOoe
1 25e
13V
7V
13.5V
<READ OPERATION>
Limit
Parameter
Symbol
Min.
Typ.
Max.
Vee Power Supply

Voltage
Vee
4.75
5.0
5.25
Vpp Voltage
Vpp
4.75
5.0
5.25
"H" Level Input

Voltage
"L" Level Input
Voltage
2.00
6.25
VIL
-0.1
0.8
396
Remarks
Symbol
V
V
ooe -70 oe
VIH
Operating
Temperature
Vee=5V0.25V
Vpp=Vce
V
V
----------------------------------------.EPROMMSM271024AS.
DC CHARACTERISTICS
(VCC = 5V5%. Vpp = VCC. Ta = OC - 70C)
Limits
Parameter
Symbol
Conditions
Unit
Min.
Typ.
VIN =5..25V
10
/LA
10
/LA
Max.
III
ILO
VOUT =5.25V
ICC,
CE =VIH
35
rnA
ICC2
CE =VIL
100
rnA
Ipp,
Vpp =VCC
rnA
VIH
2.0
VCC+1
VIL
-0.1
0.8
VOH
IOH = -400 /LA
2.4
VOL
IOL =2.1 rnA
0.45
AC CHARACTERISTICS
(VCC = 5V5%. Vpp = VCC. Ta = OC - 70C)
271024-12 271024-15 271024-20
Parameter
Symbol
Unit
Conditions
Min.
Max.
Min.
Max.
Min. Max.
Address Access Time
tACC
CE =OE =VIL.
PGM =VIH
120
150
200
ns
CE Access Time
tCE
OE =VIL.
PGM =VIH
120
150
200
ns
OE Access Time
tOE
CE =VIL.
PGM =VIH
50
60
75
ns
Output Disable Time
tDF
CE =VIL.
PGM =VIH
40
50
55
ns
397
.EPROMMSM271024AS.I---------------------------------------TIME CHART
Address input
CE
Data output
398
-------------------------------------- EPROMMSM271024AS.
< PROGRAMMING OPERATION>

DC CHARACTERISTICS
(VCC = 6V0.25V, Vpp = 12.5V0.5V, Ta = 25C5C)
Limits
Parameter
Symbol
Conditions
Unit
Min.
Typ.
Max.
III
VIN =5.25V
10
p.A
Vpp Power Current
Ipp
CE =PGM =VIL
50
mA
VCC Power Current
ICC
100
mA
VIH
2.0
Vce+ 1
VIL
-0.1
0.8
VOH
IOH = -400 p.A
2.4
VOL
IOL=2.1 mA
0.45
AC CHARACTERISTICS
(Vee = 6V0.25V, Vpp = 12.5V0.5V, Ta = 25C5C)
Limits
Parameter
Symbol
Conditions
Unit
Min.
Typ.
Max.
Address Set-up Time
tAS
p's
OE Set-up Time
tOES
p's
Data Set-up Time
tos
p's
Address Hold Time
tAH
p's
Data Hold Time
tOH
p's

Float Delay
tOFP
130
ns
tvs
p's
tpw
0.95
1.0
1.05
ms
topw
2.85
78.75
ms
CE Set-up Time
tCES
p's
Data Valid from OE
tOE
150
ns
399
.EPROMMSM271024AS ---------------------------------------TIME CHART
ADDRESSN
-----<
Data
input/output
Vpp
PGM--------,.
tDH
tOES
CAPACITANCE
(Ta = 25C, f = 1 MHz)
Parameter
Symbol
Conditions
Min.
Typ.
Max.
Unit.
Input Capacitance
CIN
VIN =OV
pF
Output Capacitance
COUT
VOUT =OV
12
pF
400
semiconductor
g~~-------------~,
~~
MSM27C64AS

READ-ONLY MEMORY
GENERAL DESCRIPTION
The MSM27C64 is a 8192 words x 8 bit ultraviolet erasable and electrically programmable readonly memory. Users can freely prepare the memory content, which can be easily changed, so the
MSM27C64 is ideal for microprocessor programs, etc. The MSM27C64 is manufactured by the
CMOS double silicon gate technology and is contained in the 28 pin package.
FEATURES
Access time:
MAX200 ns (MSM27C64-20)
MAX250 ns (MSM27C64-25)
MAX300 ns (MSM27C64-30)
Power consumption:
MAXO.55 mW (during stand-by)
PIN CONFIGURATION
(Top View)
-Vcc
PGM
-Vpp
CE
-GND
DE
DE
401
.EPROMMSM27C64AS ---------------------------------------FUNCTION TABLE
eE
(20)
OE
(22)
PGM
(27)
vpp
vee
(1)
(2B)
Read
VIL
VIL
VIH
+5V
+5V
Dout
Output Disable
VIL
VIH
VIH
+5V
+5V
High impedance
Stand-by
VIH
+5V
+5V
High impedance
Program
VIL
VIL
+21V
+6V
DIN
Program Verify
VIL
VIL
VIH
+21V
+6V
Dout
Program Inhibit
VIH
+21V
+6V
High impedance
Mode
Outputs

Storage Temperature
Ta ......................... -1 ooe - BOoe

Tstg ....................... -55e - 125e
VIN, VOUT ................. VIN = -0.6V - 13.5V,
VOUT = -0.3V - Vee + 1V
Vee ....................... -0.3V -7V
Vpp ....................... -0.6V - 23V
PD ........................ 1.5W
Vee Supply Voltage

Program Voltage
<READ OPERATION>
Limit
Parameter
Symbol
Min.
Typ.
Max.
Vee Power Supply

Voltage
Vee
4.5
5.0
5.5
Vpp Voltage
Vpp
3.B
5.0
6.2
VIH
2.00
6.5
"L" Level Input

Voltage
VIL
-0.1
0.8
The voltage with respecllo GND
Remarks
Symbol
V
V
ooe -70 oe
"H" Level Input

Voltage
402
Operating
Temperature
Vee=5V10%
Vpp=Vee0.7V
----------------------------------------~.EPROMMSM27C64AS.
DC CHARACTERISTICS
(VCC = 5V1 0%, Vpp = VCC0.7V, Ta = OC - 70C)
Limits
Parameter
Symbol
Conditions
Unit
Min.
Typ.
Max.
III
VIN =5.5V
10
JLA
ILO
VOUT=5.5V
10
JLA
ICC,
100
JLA
ICC2
CE =VIH =VCC
CE =VIL
30
rnA
Vpp Power Current
Ipp,
Vpp = VCC0.7V
100
JLA
2.0
VCC+1
-0.1
0.8
VIH
VIL
VOH
IOH = -400 JLA
4.0
VOL
IOL = 2.1 rnA
0.45
AC CHARACTERISTICS
(VCC =5V10%, Vpp =VCC0.7V, Ta =OC -70C)
Parameter
Symbol
27C64-20
27C64-25
27C64-30
Min. Max.
Min. Max.
Min. Max.
Conditions
Unit
Address Access Time
tACC
CE =OE =VIL,
PGM =VIH
200
250
300
ns
CE Access Time
tCE
OE =VIL,
PGM =VIH
200
250
300
ns
OE Access Time
tOE
CE =VIL,
PGM =VIH
75
100
120
ns
Output Disable Time
tDF
CE =VIL,
PGM =VIH
60
85
105
ns
403
_EPROMMSM27C64AS ___--------------------------------------TIME CHART
Address input
Data output
404
----------------------------------------~.EPROMMSM27C64AS.
DC CHARACTERISTICS
(VCC = 6V0.25V, Vpp = 21 V0.5V, Ta = 25C5C)
Limits
Parameter
Symbol
Conditions
Unit
Min.
Typ.
Max.
III
VIN =5.5V
10
/LA
Vpp Power Current
Ipp
CE =PGM =VIL
30
mA
VCC Power Current
ICC
30
mA
VIH
2.0
VCC+1
VIL
-0.1
0.8
VOH
IOH = -400 /LA
2.4
VOL
IOL =2.1 mA
0.45
AC CHARACTERISTICS
(VCC = 6V0.25V, Vpp = 21 V0.5V, Ta = 25C5C)
Limits
Parameter
Symbol
Conditions
Unit
Min.
Typ.
Max.
/LS
/Ls
tAS
OE Set-up Time
tOES
Data Set-up Time
tDS
/Ls
Address Hold Time
tAH
/Ls
Data Hold Time
tDH
/Ls

Float Delay
tDFP
130
ns
tvs
/Ls
tpw
0.95
1.0
1.05
ms
topw
3.8
63
ms
CE Set-up Time
tCES
/Ls
Data Valid from OE
tOE
150
ns
Address Set-up Time
405
_EPROMMSM27C64AS_._-------------------------------------TIME CHART
ADDRESSN
Data -----<I
input/output
Vpp
PGM------------~
tOES
CAPACITANCE
(Ta = 25C, f = 1 MHz)
Parameter
Symbol
Conditions
Min.
Typ.
Max.
Unit.
Input Capacitance
CIN
VIN =OV
pF
Output Capacitance
COUT
VOUT =OV
12
pF
406
OKI
semiconductor
C\I~~
---------------------------------------------------------------------- ~~
MSM27C1 28AS

READ-ONLY MEMORY
GENERAL DESCRIPTION
The MSM27C128 is a 16384 words x 8 bit ultraviolet erasable and electrically programmable
the MSM27C128 is ideal for microprocessor programs, etc. The MSM27C128 is manufactured by
the CMOS double silicon gate technology and is contained in the 28 pin package.
FEATURES

Access time:
MAX200 ns (MSM27C128-20)
MAX250 ns (MSM27C128-25)
MAX300 ns (MSM27C128-30)
Power consumption:
PIN CONFIGURATION
(Top View)
-VCC
PGM
-Vpp
CE
-GND
OE
OE
AoA, ______
A13
407
.EPROMMSM27C128AS .-------------------------------------
FUNCTION TABLE
CE
(20)
01;
(22)
PGM
(27)
Vpp
(1)
VCC
(28)
Read
VIL
VIL
VIH
+5V
+5V
Dout
Output Disable
VIL
VIH
VIH
+5V
+5V
High impedance
Stand-bY
VIH
+5V
+5V
High impedance
Program
VIL
VIL
+21V
+6V
DIN
Program Verify
VIL
VIL
VIH
+21V
+6V
Dout
Program Inhibit
VIH
+21V
+6V
High impedance
Mode
Outputs

Storage Temperature
Ta ......................... -10C - 80C

Tstg ....................... -55C - 125C
VIN, VOUT ................. VIN = -0.6V - 13.5V,
VOUT = -0.3V - VCC + 1V
VCC ....................... -0.3V - 7V
Vpp ....................... -0.6V - 23V
Po ........................ 1.5W
VCC Supply Voltage

Program Voltage
<READ OPERATION>
Limit
Parameter
Symbol
Min.
Typ.
Max.
VCC Power Supply

Voltage
VCC
4.5
5.0
5.5
Vpp Voltage
Vpp
3.8
5.0
6.2
VIH
2.00
6.5
"L" Level Input

Voltage
VIL
-0.1
0.8
Remarks
Symbol
V
V
OC -70C
"H" Level Input

Voltage
408
Operating
Temperature
VCC=5V10%
Vpp=V CCO.7V
- - - - - - - - - - - - - - - - - - -.........
_ EPROM 'MSM27C128AS _
DC CHARACTERISTICS
(VCC = 5V1 0%, Vpp = VCC0.7V, Ta = OC - 70C)
Limits
Parameter
Symbol
Conditions
Unit
Min.
Typ.
Max.
III
VIN =5.5V
10
!LA
ILO
VOUT=5.5V
10
!LA
ICCl
CE =VIH =VCC
100
!LA
ICC2
CE=VIL
30
mA
Vpp Power Current
IPPl
Vpp =VCC0.7V
100
!LA
VIH
2.0
Vce+ 1
VIL
-0.1
0.8
VOH
IOH = -400 !LA
4.0
VOL
IOL =2.1 mA
0.45
AC CHARACTERISTICS
(Vec = 5V1 0%, Vpp = Vce0.7V, Ta = ooe -70C)
27C128-20 27C128-25 27C128-30
Parameter
Symbol
Conditions
Unit
Min. Max. Min. Max.
Min. Max.
Address Access Time
tACC
CE =OE =VIL,
PGM =VIH
200
250
300
ns
CE Access Time
tCE
OE=VIL,
PGM =VIH
200
250
300
ns
OE Access Time
tOE
CE =VIL,
PGM =VIH
75
100
120
ns
Output Disable Time
tDF
CE =VIL,
PGM =VIH
60
85
105
ns
409
.EPROMMSM27C128AS.I-------------------------------------TIME CHART
Address input
CE
Data output
410
--------------------------------------I.EPROMMSM27C128AS.
DC CHARACTERISTICS
(VCC = 6V0.25V, Vpp = 21 V0.5V, Ta = 25C5C)
Limits
Parameter
Symbol
Conditions
Unit
Min.
Typ.
Max.
III
VIN =5.5V
10
p.A
Vpp Power Current
Ipp
CE = PGM =VIL
30
mA
VCC Power Current
ICC
30
mA
VIH
2.0
VCC+1
VIL
-0.1
0.8
VOH
IOH = -400 p.A
2.4
VOL
IOL =2.1 mA
0.45
AC CHARACTERISTICS
(VCC = 6V0.25V, Vpp = 21 V0.5V, Ta = 25C5C)
Limits
Parameter
Symbol
Conditions
Unit
Min.
Typ.
Max.
Address Set-up Time
tAS
p's
OE Set-up Time
tOES
p's
Data Set-up Time
tDS
p's
Address Hold Time
tAH
p's
Data Hold Time
tDH
p's

Float Delay
tDFP
130
ns
tvs
p's
tpw
0.95
1.0
1.05
ms
topw
3.8
63
ms
CE Set-up Time
tCES
p's
Data Valid from OE
tOE
150
ns
411
.EPROMMSM27C128AS --------------------------------------TIME CHART
ADDRESS N
---<I
Data
input/output
Vpp
PGM-------,I
tOES
CAPACITANCE
(Ta = 25C, f = 1 MHz)
Parameter
Symbol
Conditions
Min.
Typ.
Max.
Unit.
Input Capacitance
CIN
VIN =OV
pF
Output Capacitance
COUT
VOUT =OV
12
pF
412
._D_._K
__I__se_ITI_I_c_O_ncl_u_c_.or
_ _ _ _ _ _~
MSM27C1024AS
READ-ONLY MEMORY
GENERAL DESCRIPTION
The MSM27C1 024 is a 65536 words x 16 bit ultraviolet erasable and electrically programmable
the MSM27C1 024 is ideal for microprocessor programs, etc. The MSM27C 1024 is manufactured by
the CMOS double silicon gate technology and is contained in the 40 pin package.
FEATURES
65536 words x 1 6 bit configuration
Access time:
MAX1 00 ns (MSM27C1 024-1 0)
MAX150 ns (MSM27C1 024-15)
MAX200 ns (MSM27C1 024-20)
Power consumption:
PIN CONFIGURATION
4-----
Vee
PGM
CE
+-----------GNO
DE
OE
413
_EPROMMSM27C1024AS ___------------------------------------FUNCTION TABLE
eE
(2)
OE
(20)
PGM
(39)
Vpp
(1)
vee
(40)
Read
VIL
VIL
VIH
+5V
+5V
Dout
Output Disable
VIL
VIH
VIH
+5V
+5V
High impedance
Stand-by
VIH
+5V
+5V
High impedance
Program
VIL
VIL
+J2.5V
+6V
DIN
Program Verify
VIL
VIL
VIH
+12.5V
+6V
Dout
Program Inhibit
VIH
+12.5V
+6V
High impedance
Mode
Outputs

Storage Temperature
Ta ......................... -1 ooe - BOoe

Tstg ....................... -55e - 1 25e
VIN, VOUT ................. VIN = -0.6V - 13V,
VOUT = -0.3V - Vee + 1V
Vee ...................... -0.3V - 7V
Vpp ....................... -0.6V - 13.5V
PD ........................ 1.5W
Vee Supply Voltage

Program Voltage
<READ OPERATION>
Limit
Parameter
Symbol
Min.
Typ.
Max.
Vee Power Supply

Voltage
Vee
4.5
5.0
5.5
Vpp Voltage
Vpp
4.5
5.0
5.5
VIH
2.00
6.5
"L" Level Input

Voltage
VIL
-0.1
O.B
Remarks
Symbol
V
V
ooe -70 oe
"H" Level Input

Voltage
414
Operating
Temperature
Vee=5V0.5V
Vpp=Vee
---------------------------------------.EPROMMSM27C1024AS.
DC CHARACTERISTICS
(VCC = 5V1 0%. Vpp = VCC. Ta = OC - 70C)
Limits
Parameter
Symbol
Conditions
Unit
Min.
Typ.
Max.
III
VIN =5.25V
10
J-tA
ILO
VOUT =5.25V
10
J-tA
ICCl
CE =VIH =VCC
50
J-t
ICC2
CE =VIL
30
mA
IPPl
Vpp =VCC
50
J-t
VIH
2.0
VCC+1
VIL
-0.1
0.8
VOH
IOH =-400J-tA
2.4
IOL = 2.1 mA
0.45
VOL
AC CHARACTERISTICS
(VCC = 5V1 0%. Vpp = VCC. Ta = OC -70C)
Parameter
Symbol
Conditions
27C100010
27C100015
27C100020
Min.
Max.
Min. Max.
Min.
Max.
Unit
Address Access Time
tACC
CE =OE =VIL.
PGM =VIH
100
150
200
ns
CE Access Time
tCE
OE =VIL.
PGM =VIH
100
150
200
ns
OE Access Time
tOE
CE = VIL.
PGM =VIH
45
60
75
ns
Output Disable Time
tDF
CE =VIL.
PGM =VIH
35
50
55
ns
Input timing reference level ............... O.BV and 2.0V
Output timing reference level .............. O.BV and 2.0V
415
.EPROMMSM27C1024AS.------------------------------------TIME CHART
Address input
Data output
416
---------------------------------------I.EPROMMSM27C1024AS.
DC CHARACTERISTICS
(VCC = 6V0.25V, Vpp = 12.5V0.5V, Ta = 25C5C)
Limits
Parameter
Symbol
Conditions
Unit
Min.
Typ.
Max.
III
VIN =5.25V
10
p.A
Vpp Power Current
Ipp
CE =PGM =VIL
50
mA
VCC Power Current
ICC
30
mA
VIH
2.0
VCC+1
VIL
-0.1
0.8
VOH
IOH =-400p.A
2.4
VOL
IOL = 2.1 mA
0.45
AC CHARACTERISTICS
(VCC = 6V0.25V, Vpp = 12.5V0.5V, Ta = 25C5C)
Limits
Parameter
Symbol
Conditions
Unit
Min.
Typ.
Max.
Address Set-up Time
tAS
p's
OE Set-up Time
tOES
p's
Data Set-up Time
tDS
p's
Address Hold Time
tAH
p's
Data Hold Time
tDH
p's

Float Delay
tDFP
130
ns
tvs
p's
tpw
0.95
1.05
ms
topw
2.85
78.75
ms
CE Set-up Time
tCES
p's
Data Valid from OE
tOE
150
ns
1.0
417
_EPROMMSM27C1024AS-.------------------------------------TIME CHART
ADDRESSN
Data ---<
input/output
Vpp
PGM-------~
tOES
CAPACITANCE
(Ta = 25C. f = 1 MHz)
Parameter
Symbol
Conditions
Min.
Typ.
Max.
Unit.
Input Capacitance
CIN
VIN =OV
pF
Output Capacitance
COUT
VOUT =OV
12
pF
418
MOS
E2 ROMS
OKI
semiconductor
MSM2816ARS
2K x 8 BIT ELECTRICALLY ERASABLE PROM
GENERAL DESCRIPTION
The MSM2816A is a 2,048 word x 8 bit electrically erasable programmable readonly memory (E' PROM). The
MSM2816A operates from a single 5V power supply, has a static standby mode, and features easiest programming.
Though the MSM2816A requires no high voltage during reading or writing, it is still operable in the highvoltage mode
as well.
The process of updating byte data in the 5V programming mode is initiated by setting the write signal at the TTL low
(L) level for 200 ns. Address and data bus information is latched within the Ie, and the system is made available to
other tasks during the write cycle.
The MSM2816A erases a selected byte automatically before writing new information to it. The erase/write cycle
completes within a maximum period of 10 ms. In addition to the byte erase/write function, the MSM2816A supports
a mode permitting the entire chip to be cleared at 10 ms or less.
The MSM2816A is ideally suited for applications involving the use of a nonvolatile memory to make modifications
to a system. Typical applications include selfcontrollable equipments, memorizing ratio of tariffs at terminals on the
sales counter, storing keywords' for encoding data, programmable character generators, and storing map information
in air navigation systems.
FEATURES
Single 5V power supply
Highspeed access time.
250 ns
300 ns
350 ns
450 ns
TTL level byte write. . . . . . . . . .. 10 ms
Internally latched address data during write
MAX.
MAX.
MAX.
MAX.
MAX.
Automatic erase before write

Automatic completion of write
Inadvertent write protection
Input and output TTL compatible
JEDEecompliance pin configuration
Pin compatible to Xicor 2816A, Intel 2816/2816A
PIN CONFIGURATION
A,
vee
A,
A,
A,
(Top View)
Ao
'V
1/ 0
DE
A"
CE
A,
1100
1/06
1/0 1
1/5
1/2
1/0 4
vss
420
lID,
12
13
II0 a
Function
Pin names
A IO
'V
1/07
Address i npu ts
Data inputs/outputs
CE"
Chip enable
DE
Output enable
WE
Write enable
Vee
+5V
VSS
Ground
---------------------------------------I.EEPROMMSM2816ARS.
x buffers,
16,384 bit
E' PROM array
latch and
decoder
A. 'VA,.
Address
inputs
Y buffers,
latch and
decoder
I/O buffers
and latch
Control
logic
I/O. 'V I/O,
Data inputs/outputs
MODE SELECTION
~
O"l:
WE
V IH
V IL
V IL
V IH
V IL
V IH
LS
V IL
V IH
V IL
V IL
V IL
V OE
Mode
I/O
Standby
High Z
Read
Power
Standby
DOUT
Active
5V byte write
DIN
Active
V IH
Program (READ AND

WRITE) inhibit
High Z
Active
V IH
Vpp
Byte erase
DIN=VIH
Active
V IH
Vpp
Byte write
DIN
Active
Vpp
Chip erase
DIN-V IH
Active
High-voltage programming mode
Note: X;Don'tcare(VIHorV IL )
421
.EEPROMMSM2816ARS.I-------------------------------------DEVICE OPERATION
Read Mode
Data in the MSM2816A can be read by applying a TTL
high signal to WE:, and a low signal to C'E and ~. The
data for tAA time from address inputs; for tCE time
from a low on DE, and for tOE from a low on 01:,
whichever occurs last, is valid. Once a TTL high signal
is applied to DE or CE, the I/O pins are in a high impedance state to prevent data bus contention within
the system.
Write Mode
The MSM2816A has two write modes:
5V programming mode (standard)
In this mode, a write cycle is initiated by applying
a TTL low signal to WE and CE and a high signal to
DE. Address inputs are latched on the trailing edge
of WE or C'E whichever is the slower. Data on the
I/O pins is latched on the leading edge of WE or
CEo The address and data are latched for 200 ns
by using TTL level write signal. Once the data is
latched, the MSM2816A erases the byte that is selected within 10 ms automatically and writes new data
to it.
In the meantime, the system is available to other tasks,
but the I/O pins are in a high impedance state while
writing is in progress. The system recognizes the completion of a write operation by comparing the data
last written against previous data. When this method
of verification is to be used, the output may be
pulled up to V CC with a resistor so that all read data
prior to the completion of the write operation should
be '1'.
High-voltage programming mode
While the MSM2816A merely requires a single 5V
power supply to write, it is also operable in the highvoltage mode to remain compatible with existing
E2 PROMs. In this mode, all selected bytes must be
erased before new data can be written to them. The
byte erase operation can be initiated the same way as
a high-voltage write operation, except that a TTL
high level is applied to every I/O pin. To be able to

write new data to a byte in the high-voltage mode, it
is necessary to apply a TTL high level to DE and a
TTL low level to CE before WE is raised to a voltage
(Vpp) between 12V and 22V. The MSM2816A has
no constrain on Vpp rising or falling edges, and data
present on the I/O pins is written to memory within
a maximum period of 9 ms from address inputs.
High-voltage Chip Erase

The data in all memory cells is erased within 9 ms when
DE is initially raised to 12-22V, then WE is raised to
12-22V while applying a TTL high signal to every I/O
pin. After the erasure, all data bits in the device are set
to TTL high level (logic '1 ').
Standby Mode
The 2816A has a standby mode which reduces the
active power dissipation by about 55% when a TTL
high level is applied to CEo
Number of repetitive write cycles
The MSM2816A is designed to support applications
requiring up to 10,000 write cycles per byte.
Inadvertent write protection
The MSM2816A has following four functions to
prevent inadvert write during power up, power down,
and during line noise occurrence.
(1) VCC level detection
Writing to the device is automatically inhibited
when VCC has fallen to 3.0V or below.
(2) Time delay
Any write operation is automatically inhibited
while VCC is 5-20 ms in the Vwl state when the
MSM2816A is being powered up.
This features allows sufficient time for the system
to apply a TT L high signal to WE or C E before
write occurs.
(3) OE gating
The MSM2816A inhibits all write operations while
DE is low.
(4) WE noise protection
No write cycle may be initiated by write pulses
for 20 ns or shorter.
Absolute Maximum Ratings (Note 1)
Ambient temperature under bias . . .
Storage temperature . . . . . . . . . . . . . . . . . . .
Voltage on any pin with respect to ground (Note 2) .
DC output current . . . . . . . . . . . . .
DE and WE voltage in high-voltage mode . . . . . . .
Notes:
422
-10C "v +85C

-65C "v +125C
-0.5V"v +6V
5mA
22.5V
1. Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the
device. This is a stress rating only and functional operation of the device at these or other conditions
above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
2. The device incorporates a special circuit to sat"eguard it against electrostatic damage. For added assurance,
avoid operating the device above the maximum ratings indicated.
---------------------------------------.EEPROMMSM2816ARS.
DC OPERATING CHARACTERISTICS
Limits
Parameter
Symbol
Condition
MIN
MAX
Unit
Input low voltage
VIL
0.8
Input high voltage
VIH
2.0
0.4
2.4
3.0
3.5
Output low voltage
VOL
IOL=2.1.mA
Output high voltage
VOH
10H = -400 "A
Write inhibit VCC voltage
VWI
WE voltage (erase/write)
(Note 1)
OE voltage (chip erase)
(Note 1)
VPP
12
22
VOE
12
22
VPP current (byte erase/write)

(Note 1)
Ipp(W)
CE = VIL
10
"A
Vpp current !inhibit)
(Note 1)
Ipp(J)
Vpp = 22V, CE = VIH
"A
(Note 1)
Ipp(C)
10
"A
VOE current (chip erase)
(Note 1)
10E
VOE = Vpp = 22V
10
"A
I nput leakage current
ILl
VIN = 0
10
"A
ILO
VOUT = 0
10
"A
Operating supply current
ICC
CE = OE = VIL
All I/O S = OPEN
Other pins = 5.25V
10
Vpp current (chip erase)
110
mA
Standby supply current
ISB
CE = VIH, OE = VIL
All I/O S = OPEN
Other pins = 5.25V
40
mA
Note 1:
'V
5.25V
'V
5.25V
These parameters apply only in the high-voltage programming mode.
CAPACITANCE
ITA = 25C, f = 1.0 MHz, VCC = 5V)
Parameter
Input/output capacitance
I nput capacitance
Symbol
Conditions
MAX
Unit
CliO
VI/O = OV
10
pF
CIN
VIN =OV
pF
423
.EEPROMMSM2816ARS.--------------------------------------AC CHARACTERISTICS
(1)
(Note 1)
Read cycle
Symbol
Parameter
MSM2816A
-250
MSM2816A
-300
MSM2816A
-350
MSM2816A
-450
MIN
MIN
MIN
MIN
MAX
300
350
450
ns
250
300
350
450
ns
100
120
135
150
ns
tCE
250
tAA
tOE
Output enable access

time
Output set time (CE)
tLZ
10
Output disable time

(C1':)
tHZ
10
Output set time (OE)
tOLZ
10
Output disable time

(OE)
tOHZ
10
70
Output hold time
tOH
20
20
100
10
10
100
20
Data Out
424
10
80
WE
AC test conditions
Input pulse voltage level
Pu Ise rise/fall time
Input/output timing level
Load conditions
10
10
OE
o 'V 3V
10 ns
1.5V
1 TTL, CL = 100 pF.
10
10
10
CE
450
100
10
Addre.,
Note 1:
10
100
350
Unit
MAX
tRC
Address access time
MAX
300
Read cycle time
Chip enable access time
250
MAX
ns
ns
100
ns
10
ns
10
100
ns
20
ns
--------------------------------------_..EEPROMMSM2816ARS.
(2)
Write cycle
(5V programming mode)
Limits
Parameter
Symbol
MIN
MAX
Unit
Write cycle time
twc
10
ms
Address setup time
tAS
10
ns
Address hold time
tAH
70
ns
Write setup time
tcs
ns
Write hold time
tCH
tcw
150
tOES
10
ns
tOEH
10
ns
ns
Write pulse width (IT)

Output enable setup time
Output enable hold time
ns
ns
Write pulse width (WE) (Note 1 )
twp
150
Data latch time
tDL
50
ns
tDV
IlS
Data setup time
tDS
50
ns
Data hold time
tOH
10
ns
Write inhibit time during power-up
tlNIT
20
ms
Data valid time
(Note 2)
WE control write cycle
Address
High Z
Data Out
Data In
Data Valid
~~
t D s - l - t DH- '
425
EEPROMMSM2816ARS.I-------------------------------------- CE control write cycle
..
twc
Address
CE
OE
%<><>0'
WE
Data Out
tDVData In
Data Valid
)000
tDS-J...-tDH
Notes:
(3)
1.
2.
WE is noise protected. No write cycle may be initiated by write pulses for 20 ns or shorter.
Data must be set valid within 1 liS after the start of a write cycle.
Write/erase cycle
(High-voltage programming mode)
(V CC = 5V 5%, Ta = DoC "v 70 C)
Limits
Parameter
Vpp address setup time
Vpp CE setup time
Vpp data setup time
Symbol
Conditions
Unit
MAX
MIN
tAS
10
ns
tcs
10
ns
tDS
ns
50
ns
70
ms
Data hold time
tCH
Vpp = 6V
Write pulse width
twp
Vpp = 12V
Write recovery time
tWR
Vpp = 6V
50
ns
Chip erase setup time
tos
Vpp=6V, VOE= 12V
10
ns
Chip erase hold time
tOH
Vpp=6V, VOE= 12V
10
ns
Vpp OE setup time
taos
Vpp = 6V
10
ns
Vpp OE hold time
taoH
Vpp = 6V
10
Write inhibit time during power-up
tlNIT
VCC
20
ms
426
> VWI
ns
---------------------------------------.EEPROMMSM2816ARS
Byte erase/write cycle
)K
Address
K
I---tcs-
..
'"
_IWR_
--
Data In
xY
Vpp
--
tDS ~
......
Data Valid
tBOS
XXXxxxx
r-}- r-
twp
tAS
V IH
Vpp(WE Pin)
tWR
I\.
.....
I
tBOH
xx
tDH I--
Ch ip erase cycle
CE
"
V IH
Vpp(WE Pin)
tWR
- -
Vpp
V IH
/tDS
Data In
OE
twp
f+-tcs
""-
-- "-tDH ' \
V OE
"-
,.tOH-"
... tOS ....
PRODUCT INFORMATION
Model name
Access time
MSM2816A AS-250
250
MSM2816A AS-300
300
MSM2816A AS-350
350
MSM2816A AS-450
450
MSM2816A RS-250
250
MSM2816A RS-300
300
MSM2816A RS-350
350
MSM2816A RS-450-
450
Package
o "v 70C
Cerdip
o "v 70C
Plastic
427
IIi) CROSS REFERENCE LIST

1. DYNAMIC RAM ............................................................. 431
2. STATIC RAM ............................................................... 436

3. MASK ROM ................................................................. 438
4. EPROM .................................................................... 439
5. E2P ROM ................................................................... 441
I.
(Note)
'--.--'-_---'1.
OrStruc- Total
ture
Bit gani-
Number of
Pin
zation
Oki
MSM3764-15
150
Ip.C
MSM3764-20
200
64k
65536
xl
Package Material
'---------Access Time (ns) max.

P:
PLASTIC
G: CERDIP
C; SIDE-BRAZED
1. DYNAMIC RAM
NMOS
Type No.
1P.C
Hitachi
Intel
Texas
Mostek
Motorola
NEC
Toshiba
HM4864-2
2164-15
TMS4164-15
MK4164-15
MCM6665-15
IlPD4164-3
TMM4164C-3
1501 C
150 1 C
1501
HM4864-3
2001
1501
MK4164-20
200 1 C
150 1 C
MCM6665-20
200 1 C
1501
IlPD4164-2
2001
J:
PLCC
YS: SIMM
KS: SIP
Mitsubishi
Fujitsu
M5K4164-15
MB8264-15
150 1 P.C
150 1 C
TMM4164C-4
M5K4164-20
MB8264-20
200 1 C
200 1 C
150 1 P.c
150
M5K4164A-l0 MB8264A 10
16
1001 P.G
100 1 P.C
MSM3764A-12 HM4864A-l
120
Ip.C
1201 P.G
MSM3764A-15 HM4864A-2
150
jP.C
1501 P.G
MSM3764A-20 HM4864A-3
200
1P.C
2001 P.G
TMS4164A-12
MCM6665A-12 IlPD4164A-4 TMM4164A-2 M5K4164A-12 MB8264A-12
120 1P.C
TMS4,164A-15
150 1P_C
TMS4164A-20
200 1P.C
120
MK4564
150 I
1 C
120IpG.C
120 I P
MCM6665A-15 IlPD4164A-3 TMM4164A-3

150
1 C
150IpG.c
MCM6665A-20 IlPD4164A-2
200
1 C
200IpG.c
150 1 P
120 I P.C
1201 P G
M5K4164A-15 MB8264A-15
1501 P.G
1501 P.C
M5K4164A-20 MB8264A-20
200 I P.C
200 I P.G
MSM37S64-15
150
oen
I P
en
MSM37S64-20
::D
m
m
::D
m
'"
200 1 P
NMOS 128k
131072
xl
16
MSM37S64A15
150
....
r-
MSM37S64A20
U)
200
1P
o::D
iii
-f
--

....
Co)
I\J
Struc- Total ori_\ Num

gani- ber 0
ture
Bit
zation Pin
Oki
Hitachi
Intel
Texas
Mostek
Motorola
NEC
Toshiba
Mitsubishi
MCM6256-10
100
MSM41256-12
HM50256-12
120 I P.C.J
120 I P.G
MSM41256-15
HM50256-15
150 I P.C.J
150 1 P.G
MSM41256-20
HM50256-20
200 I P.C
200 1 P.G
TMS4256-12
120 I
TMS4256-15
150 1 P
TMS4256-20
200 1 P
120 I P.C
150 I P.C
120
P.C
MK4556-15
MCM6256-15
150 1 P
1501 P.C
"PD41256-12 TMM41256C- M5M4256512

12
120 Ip.G.c
120 I P.G
"PD41256-15 TMM41256C15
150 Ip.G.c
150
-1
P.G
120
I P.C
MSM4256S15
150 1 P.C
MK4556-20
"PD41256-20
M5M4256S20
200 1 P
200 Ip.G.C
200 1 P.C
HM50256-12
120 I P.G
HM50256-15
150 I P.G
TMS4256-12
120 1 P
TMS4256-15
150 I
MCM6256-12
120
TP.C
MB81256-10
en
MB81256-12
120
MB81256-15
100 I
"PD41256-12
120 Ip.G.C
MCM6256-15
"PD41256-15
150 I P.C
150 Ip.G.c
TMM41256C- M5M4256S- MB81256-12

12
12
1201 P.G
1201 P.C
120 1 P
TMM41256C- MSM4256S- MB81256-15

15
15
150 I P.G
150 I P.C
150 I
MSM41257A10
"PD41257-10
MB81257-10
100 I P.C
1001 P.c
100 1 P.C
MSM41257A12
HM50257-12
120 1 P.C
1201 P.C
MSM41257A15
150
I P.C
HM50257-15
150
I P.C
TMS4257-12
120 I
TMS4257-15
150
TP
MCM6257-12 "PD41257-12
120 I P.C
120 I P.C
MCM6257-15 "PD41257-15
150
TP.C
150
TP.C
TMM4125712
120 I P.C
TMM4125715
150
TP.C
M5M41257- MB81257-12
12
120 I P.C
120 I P.C
M5M41257- MB81257-15
15
150 I P.C
:D
oen
:D
m
"II
m
:D
m
Z
m
r-
iii
150 1 P
MB81256-10
100 I P.C
100 I P.C
MSM41256-15
120 I
MCM6256-12
100
MCM6256-10
MSM41256A10
MSM41256ANMOS 256k 262144 16

12
xl
MK4556-12
I P_C
Fujitsu
150 I P.C
-I
Or- NumStruc- Total

ture
Bit gani- ber 0
zation Pin
Oki
Hitachi
Intel
Texas
MSM41464-10 H M50464P-l 0
100 I
100 I
120 I
100 I
120 I
MSM41464-15 HM50464P-15
150 I
150 I
150
Mitsubishi
MB81464-10
Fujitsu
100 I
MB81464-12
120 I P
150
120 I
MB81464-15
150
MH2560912
1201vs.KS
30
Toshiba
/lPD41464C-l 5 TMM41464P-15
MSC2301-12
NMOS 512k 65536
x8
NEC
/lPD41464C-12 TMM41464P-12
18
120 I
Motorola
/lPD41464C-l0
MSM41464-12 HM50464P-12
256k 65536
x4
Mostek
120
I VS
MSC2301-15
1501vs.KS
MSC2301-12
TM4164-12
120 IVS.KS
576k 65536 30
x9
120 I
MSC2301-15
KS
TM4164-15
150 IVS.KS
150 I
KS
MSC2304-12
1201vs.KS
2048k
30
262.144
x8
:D
MSC2304-15
1501vs.KS
MSC2304-12
120 IVS.KS
2304k
HM561003-12
1201vs.KS
30
262,lr
MSC2304-15
HM561003-15
MH25609-12
120
I VS
MH25609-15
x9
150IVS.KS
150 [VS.KS
150 I VS
en
en
:D
m
m
:D
m
'TI
m
r-
Cii
-I
.I>-
E3
c.J
~
Or- NumStruc- Total

gani- ber of
Bit
ture
zation Pin
Hitachi
Oki
100
120
1M
Mostek
Motorola
NEC
Toshiba
100
:D
:D
P
MB8ll00
"PD411000
IP
120
120
IP
120
100
I
I
MB8ll00l
120
P
TC511000-10
IP
1001
120
TC511000-12
120
~M511000-15
1048576
xl
18
150
P
TC511001-10
MSM511001-10
100
100
MSM511001-12 HM511001-12
120
iii
MSM511000-12 HM511000-12
120
m
I"'"
MSM511000-10
100
:D
MSM414256-12
120
;A
n
MSM414256-10
1M
rn
rn
MSM411001
CMOS
Fujitsu
MSM411001
100
262144 20
x4
Mitsubishi
"PD411000
MSM411000
NMOS
Texas
MSM411000
1048576 18
xl
Intel
120
HM511001-15
150
IP
TC51100i-12
120
....
Or- NumStruc- Total

gani- ber of
ture
Bit
zation Pin
Oki
Hitachi
Intel
Texas
Mostek
Motorola
NEC
Toshiba
Mitsubishi
Fujitsu
MSM514256-10
100
MSM514256-12
CMOS
1M 262144 20
x4
120
MSM514257-10
100
IP
MSM514257-12
120
o
::u
o
(/)
(/)
::u
m
"'II
m
::u
m
r-
en-I
01
El

.l>e,)
2.
STATIC RAM
Ol
::D
Struc- Total Or- Numgani- ber of

ture
Bit
zation Pin
Hitachi
Oki
Intel
Texas
Mostek
Motorola
NEC
Toshiba
Mitsubishi
oen
Fujitsu
en
::D
TMM2016P-l
100
m
m
::D
m
MB8178
100
"'"
MSM2128-12
NMOS 16k
2048
x8
120
24
MSM2128-15
150
I'PD4016C-3
150
MSM2128-20
200
I
I
TMM2016P
150
I'PD4016C-2 TMM2016P-2
200
MSM5114-2
200
m
,...
en
....
200
58725-15
150
I P.C
MB8178
150
58725
200
P.C
I'PD444-3
200
I'PD444-2
250
CMOS
4k
1024
x4
MSM5114-3
18
300
MSM5114
450
HM4334-3
300
HM4334-4
450
I'PD444-1
300
I'PD444
450
TC5514
450
1P
M58981-45
450
IG
TC5514-1
P
650
TC5514-2
800
Or- NumStruc- Total

gani- ber of
ture
Bit
zation Pin
Oki
Hitachi
MSM5128-12
HM6116L-2
120
MSM512815
150
CMOS 16k
2048
x8
MSM5128-20
120
Intel
Mostek
Motorola
NEC
Toshiba
HM6116L-4
Mitsubishi
Fujitsu
M5M5117-12
HM6116L-3
150
Texas
120
150
/LPD446-2
M5M5117-15
/LPD446-3
150
TC5517-2
MB8416-15
150
MB8416-20
24
200
200
200
/LPD446-1
250
MSM5126-20
200
HM6116L-4
200
200
/LPD446-1
MSM5126-25
250
/LPD446-7
250
200
TC5517
250
200
M5M5117
250
TC5517-2
200
TC5517
250
/LPD445
450
MSM5165-12
120
8192
x8
MSM5165-15
120
MSM5165-20
200
150
M5M5165-12
120
/LPD4364-15
45
16384
x4
~
"'"
MSM5188-55
150
/LPD4364-20
200
/LPD4362-45
45
IP
/LPD4362-55
22
55
MSM5188-70
70
Em
TC5565-1
P
MB8464-15
150
::D
(')
CMOS 64k
MSM5188-45
HM6264-15
28
150
HM6264-12
55
/LPD4362-70
70
150
o
t/)
t/)
::D
"TI
m
::D
m
Z
(')
rei)
-I

.....
U)
(Xl
3.
o
:u
MASK ROM
Or- NumStruc- Total

gani- ber of
Bit
ture
zation Pin
Intel
Hitachi
Oki
MSM2965
24
300
Texas
Mostek
Motorola
MK36000-5
MCM68A-364
300
P.G
8192
x8
350
MSM3864
28
NMOS
250
128k
16384
28
x8
32768 28
x8
NMOS
250-
250
256k
65536
28
x8
MSM38512
200
28
150
CMOS
1M 131072 28
x8
z
om
P.G
IP
r-
TMM2364
250
iii
-I
200
MK38000
250
I P.G
P
M5M23256
250
1P
MSM53256
32768
x8
650
TMM23128
:u
m
'TI
m
:u
m
M58334
I P.C
450
4501pG
o
o
o
Fujitsu
I P.C
I'PD2364
2364A
Mitsubishi
MSM3a256A
150
512k
350
MSM38128A
MSM38256
256k
Toshiba
MCM68A-364
HN48364
64k
250
NEe
MSM531 000
250
4.
EPROM
Or- NumStruc Total

gani- ber of
ture
Bit
zation Pin
Oki
Hitachi
MSM2764-20
200
MSM2J64-25
250
MSM276430
64k
8192
x8
28
300
Intel
Texas
Mostek
HN482764G- 02764-2
20
200
HN482764G
250
HN482764G
30
300
Motorola
NEG
Toshiba
Mitsubishi
IlP027640 2 TMM27640-2
200lG
200
02764
IlP027640
250lG
250
02764-3
200
MBM2764-20
200
TMM27640
250
300
250
300
P2764A
IP
200
250
16384
x8
28
200
250
300
IlP0271280
250lG
250
MSM27128-30 HN4827128G- 027128-3

30
300
Ip
IlP0271280-2 TMM271280- M5L27128K-2

20
MSM27128-25 HN4827128G- 027128

25
128k
TMM2764AP
MSM27128-20
200
TMM2764AP
250
MEM2764-30
02764A
NMOS
JG
MBM276425
IlP027640-3
300lG
Fujitsu
200
300
027128A
TMM27128025
250
M5L27128K
(-1)
250
300
TMM27128AO
P27128A
200
MBM2712825
250
o
:D
o
M5L27128K- MBM27128-30
3
IP
IlP0271280-3
300lG
250
300
en
en
:D
MBM27128A
200
."
m
:D
m
TMM24128AP
._.
200
r-
ei)
-I
.l>-
e.>
<0
E3

~
~
Or- NumStruc- TotaL

gani- ber of
ture
Bit
zation Pin
Oki
Hitachi
Intel
Texas
Mostek
Motorola
NEG
Toshiba
'150
200 [
200
28
P27256
250
MSM27256-25 HN27256G-25
250
250
IP
200
28
:D
250
200
200
MBM2725625
250
TMM27256D
150
MSM27512-15
150
G
M5L27512K-2
MSM27512-20
200
200
MSM27512-25 HN27512G-25
250
250
27512
250
IG
MSM271 00012
120
MSM271 0001M 131072 32 15

x8
150
MSM271 00020
200
27010200V05
200
IG
m
Z
om
-I
250
:D
M5L27256K
IG
m
"'II
m
Ui
27256
200
512k ~5536
x8
TMM24256AP
I'PD27256D
NMOS
:D
o
en
en
TMM27256AD- M5L27256K- MBM2725620

2
20
MSM27256-20
32768
256k
x8
Fujitsu
TMM27256D15
MSM27256-15
150
Mitsubishi
M5L27512K
200
MBM2751225
250
Or- NumStruc- Total

gani- ber of
ture
Bit
"ation Pin
Oki
Hitachi
Intel
Texas
Mostek
Motorola
NEC
Toshiba
Mitsubishi
Fujitsu
MSM271 02412
120
MSM27102415
150
NMOS 1M
65536
x 16
27210150/05
150
40
IG
27210170/05
1701 G
MSM27102420
200
5.
27210200/05
200
IG
E2 P ROM
Or- NumStruc- Total

ber of
ture
Bit ganization Pin
Hitachi
Oki
MSM2816A25
250
Intel
NMOS 16k
2048
x8
24
300
250
IP
350
MSM2816A45
450
Mostek
Motorola
NEC
Toshiba
Mitsubishi
Fujitsu
:D
oen
en
:D
MSM2816A35
Texas
2816A
MSM2816A
30
.............
--
m
m
:D
m
"'II
2816A-3
350
nm
r-
en-I
APPLICATIONS
64K BIT DYNAMIC RAM APPLICATIONS NOTES ................................... 445
1. MEMORY DRIVER .......................................................... 445
2. DECOUPLING CAPACITORS ................................................ 446
3. PRINTED CIRCUIT BOARD .................................................. 446
4. PERIPHERAL CONTROL CIRCUIT ........................................... 447
5. NOTES ON MOUNTING 1 MB MEMORY ON A BOARD ......................... 448
6. MEMORY SYSTEM RELIABILITY ............................................ 449
7. MEMORY COMPARISON STANDARD ........................................ 451
CMOS RAM BATTERY BACK-UP ................................................... 454
1. SYSTEM POWER AND BATTERY SWITCHING CIRCUIT ...................... 454
2. SWITCHING CIRCUIT MODIFiCATIONS ...................................... 454
3. DATA RETENTION MODE ................................................... 456
4. INTERFACiNG .............................................................. 457
5. MISCELLANEOUS .......................................................... 457
MASK ROM KANJI GENERATION MEMORY DESCRIPTION ................. , ....... 457
1. KANJI GENERATION MEMORIES ............................................ 458
2. MSM38256 SERIES ......................................................... 459
64K BIT DYNAMIC RAM APPLICATION NOTES

1.
MEMORY DRIVER
There are problems in driving MOS ICs by a TTL driver:

increase of driver delay time due to capacitive load and
ringing waveform at the falling edge.
An example of the increase of delay time due to capacitive load is shown in the following figure.
The number of load memory elements must be taken
into consideration when designing the timing.
In case of LS type
PROPAGATION DELAY TIME
vs
LOAD CAPACITANCE
20
..s
VCC= 5V
18 RL = 25n
= 25C
16 Ta
E 14
i=
i;" 12
/ ' ~V
10
---/
8
6
4
2
o
o
elf the number of load memory el&ments is 20 - 40

(150 - 300pF} on a two layer board, an undershoot
of -2 to -3V (peak voltage} occurs. Therefore, measures against ringing must be taken as described in the
following.
e Measures against ringing
(1) No consideration is required for the rising edge
since there is a margin.
(2} Since ringing may be considered as a reflection
due to mismatching between the driver output
impedance and signal line impedance, it can be
prevented by line matching (termination}.
For memory arrays, however, termination with
pull up or bleeder resistance is not effective.
Instead, series resistance (damping resistance} is
suitable for memory arrays.
(3} The optimal value of series resistance differs
depending upon the speed, pattern status, and
driver. Experience will help in determining the
optimal series resistance .
As a general ru Ie, a resistance of 10 - 100n is
suitable.
However the speed will be lowered if the resistance is too large. An example is shown in
attached drawing 3.
(4} Make the signal lines as short as possible. Multilayer board design is effective in reducing the
undershoot (as the signal line impedance is
lowered}.
10 20 30 40 50 60 70 80 90 100
CL - Load Capacitance - pF
In case of L type
'5112, '5113, '5114
AVERAGE PROPAGATION DELAY TIME
CLOCK TO OUTPUT
vs
LOAD CAPACITANCE
16
VCC= 3V
i;" 14 RL = 280n
a;
C
= 25C
Ta
c:
12
.~
10
r:t
..
/'
.....- .....-
V V
...J
+N
::t:
~
::t:
25
50
ill
75 100 125 150 175200
...J
CL - Load Capacitance - pF
445
APPLICATIONS - - - - - - - - - - - - - - - - - - - - - - -
2. DECOUPLING CAPACITORS
The dynamic MOS RAM is featured by the- great
power current at the active time in comparison
to that at the standby time.
For example, the rated value (Icc!) of the mean
power current of the MSM3764 is 4SmA, while
the standby current (lcc2) of the MSM3764-1S
(150ns version) is SmA. The former is approximately
10 times greater than the latter. The peak current
of the MSM3764 approaches 90mA in the worst case.
It is approximately 20 times as great as the standby
current Icc2.
Therefore,. the power circuit must be designed so
as to prevent the above current variation from
causing an erroneous operation of the memory.
A by-pass capacitor must be inserted for this
purpose. There are two types of by-pass capacitors: high frequency capacitor and low frequency
capacitor.
2.1 High Frequency Capacitor
In the Icc current waveform, the peak current
rises at a high speed such as 10ns, and a high
frequency noise represented by thl! following
expression is caused to occur by the L component of the current applied to the capacitor:
32 bit system in a practical use.

As an example of capacitor which satisfies the
requirements in both 2.1 and 2.2 above, a
small-sized
tantalum
capacitor with excellent
high frequency characteristics is shown in the
following table. It is desirable to mount a low
frequency capacitor near the power input pin in
order to suppress the fluctuation of power supplied from outside, even if this capacitor is
mounted.
Manufacturer
Oki Ceramic Co.
Model
Capacity (I'F)
Model CA
tantalum. capacitor
Model CB
0.1 - 20l'F
The
frequency characteristics of the above
capacitor and the power bus bar are illustrated
in attached figure 1 .
3. PRINTED CIRCUIT BOARD

3.1 Number of Layars
Considering the measures against power noise which was
described in 2. above and the routing to be described in
3.2, two layers are enough in principle.
3.2 Routing
To reduce the fluctuation AV, the value of L

must be reduced.
For this purpose, the capacitor must be placed as
close as possible to the power pin of the IC. Further, sufficient capacity for supplying the peak
current is required. The standard capacity for a
double sided circuit board (two layer circuit
board) is O.OS - O.lI'F or more. The capacity
may be less than this value for a multi layer
circuit board since the L component is less than
the former.
When designing a board, mount one capacitor
with excellent high frequency characteristics for
every two or three MOS IC memory chips, near
the power pins of these IC chips.
2.2 Low Frequency Capacitor
iII
A low frequency capacitor is required for suppressing the power fluctuation due to a sudden
current variation (for example, current variation
caused by a status change from the standby
status to the continuous access status or concurrent refreshment of the entire board) in a board
unit. The power fluctuation in this case is a slow
variation of several handred ns.
For this reason, the low frequency capacitor
must have a capacity larger than the high frequency capacitor.
Though the capacity requirement depends upon
the number of memories which operate simultaneously (bit width), SOI'F is enough for a 16-
446
An example of routing on a two-layer circuit board is

shown in attached drawing 2. In designing the routing,
note the following four points:
The MOS drive line based on the TTL must be as
short as possible to prevent ringing (reflection) and
reduce crosstal k.
(III Considerations are required to lower the impedance of the power line (including the ground). (For
example, make a solid or grid-formed power line
pattern. It is desirable that the power line pattern
has width of at least 1.27mm.)
(1111 If a signal line is to be branched for multi drive,
the line must be branched at the driving end.
(See the following figure.) And, the memory
matrix must be designed in an integrated form, and
peripheral drivers must be placed near the memory
matrix.
(I)
Memory element
-----------------------.APPLICATIONS.
4. PERIPHERAL CONTROL CIRCUIT

The three types of dynamic RAM control ICs shown in
the following teble are available at present.
Model
Manufacturer
Functions
o Sevenbit address multiplexer (for 16K bit
dynamic RAM)
o Sevenbit refresh address count function
o Direct dirving capability of memory elements (for
approx. 20 elements. 250 pF/25 ns 15 pF/9 ns)
o Application to a 64K bit dynamic RAM, example
(see the following figure)
Intel
i3242
Motorola
MC-3242
Texas Instruments
(T. Il
74 LS601
603
o Refresh timer using an RC multivibrator

o Timing generation
o Refresh address (7-bit address)
Advanced Micro
Device (AMD)
Am2964A
o Address latch/multiplex function (16-bit address)

o Refresh address counter
o RAS decoder (2 - 4)
Intel
i-8203
o 8-bit address multiplexer (for 16K/64K DRAM)

o Direct dring capability of memory element
o Including timing control
REF
ENABLE
Ao------.--1--L-----~----------------r_~
3242
A,.------~---L
__~-----1---------------------L--l
MSM3764
A,
A,. ______---.J
A.. --------i
ROW ENABLE
HI
447
_APPLICATIONS __- - - - - - - - - - - - -_ _ _ _ _ _ _ __
5. NOTES ON MOUNTING 1 MB
MEMORY ON A BOARD
The advent of a 64K bit dynamic RAM such as the
MSM3764 has made it extremely easy to mount 1 M8
Point to be noted
Mounting of
memory
elements
memory on a board from the viewpoint of mounting

space. In this case, however, note the following points
since the number of memory elements mounted is so
large as 128 - 176 (when redundant bits are provided).
Consideration
Memory elements may be integrated or
divided.
(Design the memory array(s) to make
the drive lines shortest.)
Practical example
81
IMemory
IIIIIII
array
EmEBrEmE
Memory array
Memory array
Memory
element
drivi ng method
Measures
against noise
Timing design
Thermal design
m
448
Take care about the delay time and

undershoot noise of the drive element.
(If the condition VILmin = -lV recom
mended for the MOS dynamic RAM
operation is satisfied, the memory elements
will display the full reliability.)
Drive element
IS::
Element
Delay
time
(mA)
Noise
IOL
7404
Medium
speed
16
74S04
High
speed
20
o Two layers are enough for a board.

(Pay attention to the power line pattern.)
o High frequency noise
Mount a 0.1 - 1 "F capacitor for every two

memory elements.
o Low frequency noise
Mount a tantalum capacitor etc. of 50 "F

or more near the power input pin of the
memory package.
o Prevent skew between each timing in order

to enhance the system access speed.
Use ICs of the same tipe for racing timing

(for example, RAS or CAS).
o Make a sufficient margin in timing design.
Skew and mounting delay
Thermal design under the worst condition

is required.
Operation at a case temperature of 70C

must be guaranteed.
-----------------------.APPLICATIONS.
Aeliability
n
n-l)
A = (rH) + nC, (rH"rs)
(1 - rH
6. MEMORY SYSTEM RELIABILITY

6.1
CD
~
Probabil ity of no hard error
Reliability O_mination FactoR
The memory system reliability depends upon the four

factors shown in the left column of the following table.
These factors are determined as shown in the right
column of this table.
Memory system
reliability factor
Factor determination
Systemrequ ired
reliability
Determined by the user-required

specifications (MTB F).
Unit capacity
'" [MB] = [word depth] x

[bit count]
Parts reliability
Logic element
Memory element
:::::::z:
Hard error
Soft error
<D
~
Probability of one bit hard error followed

by no hard or soft error
Find a value for t when the value of A is e-, .

The following calculations are based on the assumption
that there is a low probability of two bit soft error
occurrence.
(2)
CD
Cost
Memory unit reliability

Assume a memory unit whose size is n bits in bit
width and k blocks in address capacity. The
memory element reliability is expressed as
follows:
r = e-Xt (X: error rate)
One bit correction
Find a value for t which satisfies the following
expression:
A = {(r)n + nC, r n - 1 (1 _r)}k =e-'
-
6.2 Hard Error and Soft Error

(I)
Hard error
A hard error is a permanent error which occurs each
lime a certain address is accessed.
(I il
Soft error
A soft error is a transient error that does not repeat. The
following are the three causes for soft errors:
(1)
(2)
(3)
(4)
(5)
(6)
I nsufficient power margin

Insufficient system noise margin
Particle failure
I nsufficient power margin
Insufficient system noise margin
particle failure
Items (1) through (5) are largely influenced by the

system design. For item (6), it is required to consider
whether a remedy such as ECC should be taken or not
to satisfy the system-required reliability based on the
perts reliability (pertaining to hard errors and soft
errors). See 1.3 and 1.4 for details.
6.3 Measures for Reliability Enhancement
The following are the two typical means for the enhancement of system reliability.
(1)
(2)
Parity..
ECC
.. Error detection only (makes no

contribution to the MTBF enhancement)
.The SEC-OED" is used in general
MT B F for a hard error and a soft error

(1) Memory element reliability
Hard error
Soft error
rH = e-XHt (XH: Hard error rate)

rS = e-XSt (XS: Soft error rate)
<D
Probability of all bits being correct
Probability of error occurrence for only one

bit
Only parity error detection without bit correction

Find a value for t which satisfies the following
expre~i~n: _,
R = (r)
=e
'
-'-"-----"1
I
k blocks
n bits
6.5 Reliability Calculation Result Example

(1)
Comparison of 64k byte, 128k byte, and 256k

byte configurations (without ECC)
CD 64kbyte
Element
XH
(Fit)
XS
(Fit)
MTBF
(years)
64k
100
1000
11.5
200
10.6
100
15.9
50
21.1
100
Jiingle.s.rror .correct - .Qouble ~rror Qetect

(one bit error correction and two bit error detection)
6.4 Reliability Calculation Method
'---'----.-...:..;.-.:....<-......:~
G)
16k
50
200
12.7
100
21.1
50
31.7
m
449
APPLICATIONS - - - - - - - - - - - - - - - - - - - - - - -
12Bkbyte
Element
AH
(Fit)
AS
(Fit)
64k
100
1000
5.B
200
5.3
100
7.9
100
MTBF
(years)
50
10.6
200
6.3
100
10.6
50
15.9
16k
256kbyte
Element
AH
(Fit)
AS
(Fit)
MTBF
(years)
64k
100
1000
2.9
200
2.6
100
4.0
50
5.3
200
3.2
100
5.3
50
7.9
100
16k
50
50
Notes:
(2)
1. The bit width is 9 bits for each case.

2. 1 bit is used for parity error detection.
Comparison of 1 M byte configurations (with ECC)
Reliability (years)
Element
AH (Fit)
AS (Fit)
Bit width: 22 bits
Bit width: 39 bits
100
(100%)
1000
B.2 (0.76)
7.9 (0.79)
100
(50% 50%)
1000
13.9 (0.76)
14.5 (0.79)
100
(100%)
100
B.3 (1.05)
6.B (1.0B)
100
(50% 50%)
100
13.0 (1.05)
10.7 (1.0B)
64k
16k
Notes:
450
1. When the bit width is 22 bits, six bits are

used for the ECC.
2. When the bit width is 39 bits, seven bits are
used for the ECC.
3. Values in parentheses are the reliabilities in
the case of parity error detection without
ECC.
4. The (50%, 50%) in the AH column means

that 50% of th-e hard error rate AH is han
died as the total bit hard error rate and the
remaining 50% is handled as the one bit
hard error rate (which reflects the hard
error mode analysis result confirmed so far!.
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ APPLICATIONS.
7. MEMORY COMPARISON
STANDARD
In general, power, speed, and usability are required for

memory elements. At present, 64K bit dynamic RAMs
can be supplied by a lot of manufacturers, and these
elements have almost unified specifications.
Point
to be noted
In designing a circuit board to achieve stable system

operation, however, considerations must be given to the
specification values and margins against the spacification
values, pertaining to the points shown in the following
table. Factors that will affact the stable system opera
tion are power, tempereture, aging, clock skew, uneven
operation of peripheral ICs, and so forth.
Actual item to be considered

o Currents (lcc1, Icc3, and Icc4) at the operating
Power
time and current (lcc2) at the standby time

o Current waveform (especially the peak current
value)
Timing
margin
o Address setup (tASR, tASe) and hold (tRAH,
tCAH) timing
o Data setup (tOS) timing and write pulse width
(tyVp)
Voltage
margin
Reason
The power system must be noted.
(example: with battery backup)
The noise margin must be strict for
memories with large peak current.
In system designing, these timing pulses
are directly related to the access time.
These timing pulses are related to the
cycle time in writing.
Voltage, temperature, and dependability of each

timing (especially the tREF and tRAcI
The temperature inclination must be

little for the timing pulses tREF and
tRAC
It is impossible to achieve the ideal voltage status

when used with ina system.
A sufficient voltage margin must be

provided under consideration of various
factors which will affact the system
operation stability.
Attached drawing 1
Frequency characteristics of capacitor and O!PAC
50
---Model CB tantalum 1.01'F

capacitor (manufactured
by the Oki Seramic)
a/PAC sactional view
Jrr.1
(n)
Pin 3 Pin 1
10
Model CB
(1.0I'F)
Pin 2
aPAC
(between pins
1 and 2)
aPAC
(between pins
2 and 3)
500PF
/V'-<o_--
600PF
0.5
0.05
0.5
50
OJ
100
(MHZ)
451
APPLICATIONS - - - - - - - - - - - - - - - - - - - - - Attached drawing 2

Two layer board circuit pattern example
,t:::
""
~
t--~I~
I~ [W'
f"..
,~
~
r
Vss
CAS
WE
-=
RAS
A6-----,--1
AO
A3~
A2
A4~
Al
I~,
Ii ~
!j
QJ~,
:::air....
I::ii>
--; ~t>n
'j;:;
H.ll: I""
Ir--e
'QJ 14(
~~
)9 ~
)BRIt
~ ~
:en
:en ..,.,.
,
c-=:
)I<,
'G'
UJ':
I..a: w
w~
~I-
~~
49
Ec:....-=-m.
II!
~,~
!- ~
J
~'e- f!R~
~@'
::::ti>"lri.
~
Aii
:~ :11-
;Jl.
--
G:
:<Il'
::n;-
,~
:::air",
-;;;:
~ '~
t-';;:;-
~ I~
'lM
.~
..
~ H
-~
B
!-Q
r;;;-
~Ie
I~
>-
'US
- I~~
'9'119
~,6J
::al~
'~
c- ~,
--'=--9-
'-
~-=-
--
<1"W'
-G'tJ'
~e-' r=
,~~
.-
-_..
-;;;-
f-ED.tr
l~
"
ef-W'
;--;
=4i In-..
~-l9'-
.it- ill
.....
~'e
Ii
l~
.~
III
~,~
~ $
~Ie
~e
,
fC;;;;
I@' ,
:Ln ~
t-
III
:1T;'~
19:
~-
-G tJ
- f-6) r@'
'~
---
.~
@iQ(
~
m
:9: 'lM
&' ~
l49 W
:a;-r"n
:<n 1m.
Ie
~~
'i ~ 'I --:;: : ,
G'
""
;;;- ""
~I
Ii
~F
~ i~
--= ,
"
,'~
g ~e
IA
t1t
tI
10 l:P
~,I~
,~'
~tir
[(Ii
~,~
452
)!!
"'G-"
II
.-< ILG_~
1eJ'
1a1
- lEi; fe,
Rj ~
II [l~ J
~ Ie ~
}il
J!I
~I{J'
~~
~~
'{B'
!lE-'@'IG{
.~ -I
-
ijJ
A~=U
~~ ,~
"
A7
v CC
i@
'ill
I~~
,~
,im
,--; ~
/;9,
I ;GI
~ ~
.f)
:lII
,~ ~
@ }9
'W ~ 'B, Gl
1'1
'iJ ~
.B.
,~
3,
~ 'e-
High
(iif requency
:{if
.~
Ii
~,/
~
~
'?
G
Ii ,~
It; lB
~
)jl
I~ ~
capacitor
G@'
~-
f-e,l9'
j;;-1!r f-
~ t~
,
me
T
~ ---=-
6-
If
- - - - - - - - - - - - - - - - - - - - - - . APPLICATIONS.
Attached drawing 3
Input waveform example
Horizontal:
Vertical:
50 ns/div )
1 volt/div
5Hl
[[
453
CMOS RAM BATTERY BACK-UP

A practical example of formation of nonvolatile data by CMOS static RAM battery
back-up is outlined below.
1. System power and battery switching
circuit
The simplest RAM power supply (CMOS Vcc) is out
lined in Fig. 1. In this case, the CMOS Vcc for normal
operation is kept at a voltage 0.7V below the system
voltage by the voltage drop across a diode (forward
direction).
System
battery
Battery
Fig. 1
Note: CS floating capability

Power down possible irrespective of other input
levels when memory has not been selected (i.e.
when CS = H).
Consequently, if the TTL Vcc level is greater than the
CMOS RAM supply voltage, and the RAM driver is at
the TTL Vcc level, the CMOS RAM input voltage will
exceed CMOS Vcc + 0.3V (a situation which must be
avoided). Therefore, in order to reduce the voltage
difference between CMOS Vee and TTL Vcc with the
battery voltage set to at least 4.5V or 4.75V (due to
tl1e RAM operating supply voltage range), the 02 diode
may be added to abtain a system voltage level at least
O.7V above 4.5 - 4.75V (which will keep CMOS Vcc
and TTL Vcc within the respective CMOS and TTL
operating supply voltage ranges).
To cope with (1) and (3), a CMOS driver which will also
operate at a low voltage Vcc during data hold may be
employed, or else, the open collector and open drain
buffer may be pulled up to CMOS Vcc in order to drive
the RAM.
A control circuit for coping with (2) when an abnormal
system power supply is detected is also required.
2. Switching Circuit Modifications
Fig. 2 is an example of use of a chargeable Ni-Ca battery

as the back-up battery. While the system power is being
employed, the NiCa battery is gradually charged up via
Rc. As in Fig. 1, the diode voltage drop also poses a
problem in this circuit.
Modification of the diode switching circuit can employ

PNP trans.istors. Voltage drops by PNP transistor V CE
are smaller by about 0.2V, and this can lead to the
generation of a system "power fail" signal.
02 (optional)
r--~--I
System
battery - . T - T T L V C C
CMOS Vcc
01
Rc
+
: NiCa battery
TTL
Vee
2N3638
System
battery
11'-1
3.9V
~} Option
Rc
470
1N914
1K Y
v'
"'-
2N222~
--
Fig. 2
The conditions for formation of non-volatile data (data

retention) by battery back-Up are listed below.
(1 r The input signal H level must not exceed Vcc +
0.3V when the CMOS RAM Vcc power voltage is
dropped.
(2) ~ (or CS) must maintain CMOS Vcc "H" level.
(3) In order to minimize power consumption, WE,
AD, DIN (or 1/0) must be se! to GND level or to
the same "H" level as CMOS Vcc. (This is not
necessary, however, for CMOS RAMs with chip
select floating capability).
454
Fig. 3
Fig. 3 outlines a switching circuit employing a PNP
transistor. The Rc used when a chargeable battery is
employed is replaced by a diode when a non-chargeable
battery is used. In this case, switching occurs at the
zener diode voltage, so "power fail" must be detected
by another circuit, and C"E set to CMOS Vcc "high"
level.
- - - - - - - - - - - - - - - - - - - - - - - . APPLICATIONS.
Figs. 4 and 5 are examples of circuits capable of generating a POWER FAIL output signal. In these circuits, the
C2 capacitance must be rather large, the important
POWER
FAIL
TTL Vee
System
battery
0,
c,l+
...
point being the need for a smooth gradual change in

CMOS Vee when the system power is cut. See next page
for further details.
l-
R,
R. --;
... Rc
D,
R.
0,
--l +lc,
CMOS Vee
0,
0,
/0,1
R.
Rs
D,
Rs,l
:
:
:
:
:
2N2907 or 2SA495
2N2222 or 2SC372
R2
: 100
lK
: 47K
500 R4
: 200
3.6V Rc
Ni-Cad : 3.6V
(70mAH)
"*'
Fig. 4
. - - - - - - -..... POWER FAIL signal

.-----~----_r-_+------__+
System ...- - t - -.........

battery
+ C,
;;:..=-+-_r--~-~~---t___+
TTL Vee or system Vee
CMOS Vee
-=-Ni-Cad
1500mAH
Fig. 5
5V
4.5~ Determined by CT
' 1 - - - - - - - Example.
t=O
3V? 2.0V
..:.. Battery
I3V
CE? 3V
2.5V
' i - - - - - - - CMOS Vee

CT = C2 + (another decoupling capacitor)
GND
rn
-0.1 - 0.2V
? 1.5V
Fig_ 6
455
APPLICATIONS - - - - - - - - - - - - - - - - - - - - - 3. Data Retention Mode
is cut until it reaches the power voltage for data retention (practically equivalent to the battery voltage, or
else reduced by the diode voltage drop). And although
CE traces the slope of CMOS Vcc reduction at this time,
a smooth change in CE is also a necessary condition for
actual circuits.
(4) When switching to retention mode, or from retention mode to operation mode, CE must exhibit a
smooth change. If noise is generated in CE in this case,
the data will be subject to rewriti ng.
The RAM driver (peripheral circuit) is determined

according to conditions (1) and (3) required for data
retention. In Oki Electric CMOS RAMs, the power
voltage during data retention is kept at a minimum of
2.0V. The CE (or CS) voltage at this time has to be kept
at about Vcc -0.2V. And as was mentioned earlier, the
CMOS Vee must drop smoothly when the system power
r---
Operation mode
Cmos Vcc SV 10%
CE input VTH =
Vee - 2.0V
Must be free of noise

(RAMP waveform)
'I
(MIN)
::.......::f,==========~t=======~::2.0V (MIN)
'F
I. +
Other inputs VIL =
Data retention mode
Vcc - 0.2V
0.8V(MG~X~-----Jt---~r: _ _ _ _ _ _ I~ _ _ _ _ _ O.SV(MAX)
t
=0
May be longer
Fig. 7
(S) When switching to operation mode, commence
operation after elapse of tRC (read cycle time) following
Data
retention
mode
CMOS Vee
CE
-t
Operation
mode
.-/------+--...:.:.;.='--- CMOS Vee = SV 10%
I
'
Vcc reaching the operating power voltage range.
'
:....t-------.-i, - - - - - - ~- V I H = Vee - 2.0V

2.SV = 1/2Vcc
(MIN)
I '
'
C"E VIL = 0.8V (MAX)

GND-----~---- -1~-----~-----GND
May be longer
tRC min.
Fig. 8
456
- - - - - - - - - - - - - - - - - - - - - - - - . APPLICATIONS.
4.
Interfacing
A) TTL Interface
In the case of CMOS RAM drive by TTL, use an opencollector type TTL according to conditions (1) and (3).
When the system power line (i.e. TTL Vcc) is cut, the
open-collector TTL 02 in Fig. 9 is turned off, followed
by 01 also being turned off, resulting in the CMOS
RAM input being pulled-up to CMOS Vcc.
Switching CirCUi~ System power line

or TTL Vcc
CMOS Vcc
TTL Vcc
----,
lK
1
r-~I------~--~IN
CMOS
RAM
I
I
________ -.1
Fig. 9
When the power line voltage in LS type TTL is dropped
to ground, the output is also dropped to ground,
thereby making the pull-up resistors for address line
buffers etc no longer necessary. In this case, however, it
will not be possible to employ this as a control line
buffer which must be switched to "high" during CE (or
CS) data retention.
(6) I n order to minimize the consumption current
during data retention, all inputs except CE (or CS, this
being designated as either "high" or "low") must be
---
f~
j
CMOS Vce
Vcc
CMOS
RAM
l'
CMOS Interface
In systems where the CMOS RAM is driven by CMOS
buffer, operation must be at the data retention power
voltage, and the corresponding output voltage must
satisfy the requirements indicated in Figs. 7 and 8.
B)
r-Ll
-" !
1 ';"
1
mai ntai ned at either G N D or CMOS V cc_ (Th is does

not apply, however, for CMOS RAMs equipped with CS
floating function).
I
I
L -;;:-1
.,I"
Fig. 10
5. Miscellaneous
In order to further reduce power consumption during
data retention by even a small margin, the use of aMOS
FET as the transistor generating the POWER FAIL
output signal is recommended. This is in order to
prevent flow of current from the 14k!l resistor.
rn
457
MASK ROM KANJI GENERATION MEMORY

DESCRIPTION
1. KANJI GENERATION MEMORIES
Number
of codes
Character storing
capacity
Configuration
Character
style
Bit
capacity
Access
JIS standard No.1

3418 characters
15 x 16
Gothic style
25yK bits
250ns max
J IS standard No.2
3418 characters
15 x 16
Gothic style
256K bits
250ns max
JISstandard No.1
3418 characters
24 x 24
Ming style
256K bits
250ns max
JIS standard No.2

3418 characters
24 x 24
Ming style
256K bits
250ns max
18
J IS standard No.1
3418 characters
24 x 24
Ming style
128K bits
450ns max
10
JIS standard No.1

3418 characters
16 x 18
Gothic style
128K bits
450ns max
MSM28101A
J IS standard No.1
3418 characters
16 x 18
Gothic style
1 M bits
1 OMS max
(16 x 18 transfer)
MSM28201A
J IS standard No.2
3384 characters
16 x 18
Gothic style
1M bits
1OMS max
(16 x 18 transfer)
IC
models
MSM38256-19
MSM38256-22
~
."
E
"E
MSM38256-32
MSM38256-35
time
"0
""Sl-
MSM38256-10
.c
.!?
MSM38256-18
:r:
MSM38256-38
MSM38256-46
MSM38128-00
"0
"c. .-~
""
MSM38128-17
"0"
MSM38128-18
.!!?~
~E
MSM38128-27
"0
" .-"0
c.~
.5E
ill
458
- - - - - - - - - - - - - - - - - - - - - - - . APPLICATIONS.
2. MSM38256 SE R I ES
21 15 x 16 Font
(1) Model names
MSM3B256-19-22 (four codes); JIS standard No.1 (2,965 characters) + Non-kanji (524 characters)
MSM3B256-32-35 (four codes); JIS standard No.2 (3,384 characters)
These models are similar in electrical characteristics to the MSM3B256 mask ROM. The CS and OE signals are active
low.
(2) Split character patterns, and their storage

Split character patterns
The character patterns are standard OK I

character patterns .
Each character consists of two chips.
Character data is generated at high level, and
background data i's generated at low level.
Character data is stored in a 16 x 16 dot
pattern area, left-justified.
Storage
I #3
#1
#4
Each group of four chips forms one set to

store about 4K characters.
(K - 1024)
#2
/ 2 K characters
/2K characte rs
#1
#2
#3
#4
J IS standard No.1
MSM38256-19
MSM3B256-20
MSM38256-21
MSM38256-22
J IS standard No.2
MSM38256-32
MSM38256-33
MSM38256-35
[II
459
_APPLICATIONS
_a_------_ _ _ _ _ _ _ _ _ _ _ _ _ _ __
13) Address code conversions

The following address code conversions are required to access character patterns with the JIS C6226 kanji code:
Ii) Converting JIS standards Nos. 1 and 2 Ibyte 1 = 50H - 6FH area)
C6226
D
ROM address
Conversion address
Iii)
Converting non-kanji and JIS standard No.2 Ibyte 1
70H - 74H)
C6226
D
ROM address
Conversion address
Use A15 as a CE control signal because it is not supported as a ROM address. IFor further details, see the circuit
example.)
m
460
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ APPLICATIONS.
15 x 16 font circuit configuration example
Font data
16 bit
j[
Byte 1 X, -Xl
Chip
1
t
String address
Conversion
in a character
rule choice--+
2
4
CE CE
J IS standard
No.1 ROM
module
3
CE CE
4
J IS standard
No.2 ROM
module
Y,
Q;
o
"0
U
co
"0
'"~
'"
"0
co
r--..
21H-28H
Non-kanji
r3,--O,--H_-_4_F_H'-f--'-1K-+-I J I S standard No. 1

,
ROM select
'---JIS stan50H-6FH
dard No.1
70H-77H
JIS standard No.2 ROM select
I"
J IS standard No.2
iII
461
APPLICATIONS - - - - - - - - - - - - - - - - - - - - - - 2-1
24 x 24 Font
(1 ) Model names
MSM38256-1 0~18 (nine codes); J IS standard No.1 (2,965 characters) + Nonkanji (524 characters) + Half-size
characters (159).
MSM38256-38~46; J IS standard No.2 (3,384 characters)
These models are similar in electrical characteristics to the MSM38256 mask ROM. The CS and DE signals are
active low.
(2) Split character patterns, and their storage

Split character patterns
The character patterns are standard J IS
character patterns.
Each character consists of nine chips.
Character data is generated at high level, and
background data is generated at low level.
Storage
(K
'-_--''-_--'_ _
m
462
= 1024)
-.r~4K characters
J IS standard No.1
J IS standard No.2
#1
MSM38256-10
MSM38206-38
#2
MSM3825611
MSM38256-39
#3
MSM38256-12
MSM3825640
#4
MSM38256-13
MSM3825641
#5
MSM38256-14
MSM38256-42
#6
MSM38256-15
MSM38256-43
#7
MSM38256-16
MSM38256-44
#8
MSM3825617
MSM3825645
#9
MSM3825618
MSM38256-46
- - - - - - - - - - - - - - - - - - - - - -____ APPLICATIONS _
(3) Address code conversions
The following address code conversions are required to access character patterns with the JIS C6226 and C6229
kanji code:
(i)
Converting JIS standards Nos. 1 and 2 (byte 1 = 50H-6FH area)
C6226
A,
YI
ROM address
Conversion address
Iii)
Converting non-kanji and JIS standard No.2 (byte 1
= 70H-74H
area)
C6226
A,
Y,
ROM address
Conversion address
(iii) Converting half-size characters (C6220 code)

C6220
1z, 1z,l z.1 z, 1z. 1z,l Z,I z, I
ROM address
A,
Conversion address
z,
463
APPLICATIONS ...- - - - - - - - - - - - - - - - - - - - - - (4)
24 x 24 font circuit configuration example
Font data
1'"2"'-47"'
bict -----,1
,..--.-'----'T:":""::"-i
Chip
~
Byte 1 X.-X,
r-_A__3__
- A_"__~}~~-+~:~~:~
I"
~}-~:-+~:~~:~
Byte2Y.-Y,
add~ess
String
in a character
Chip select
Halfsize font
specification --
L,;'---':7,.t--~8...J.--9=--.J
--.J )
J IS standard
No.1 ROM
module
L/
~Half-size
Y.=O
X. -X, =
" ["'\. characters
--!. -----=- 21 H-':-28=-H:-++--++N:-:o-n---;-k-+an--'j~ih
Y
~/
,
li;
30H-4FH
t;;"O
'" 0
u"O
I
',1./
50H-6FH
70H-77H
*
'
~- - JIS standard
"I
,
J IS standard
No.2
m
464
r JIS
standard No.1
ROM select
No.1
J IS standard No.2 ROM select
J IS standard No.2
ROM module
OKI Electric Industry Co.. ltd.

10 ~ 3 Shlbaura 4-chome. M inato - ku.
Tokyo 108, Japan
Tel
Tokyo 45 4 ~ 21 1 1
Telex J22627
Fax
Tokyo 452 - 591 2 (Gill)
Elect ronICS devIces Group
?verseas M arketmg Dept
OK I Semiconductor Group
650 N Mary Avenue
Sunnyvale. CalIf 940 8 6 . USA
Tel
408 - 720 - 1900
Tele, 91033 8 0508 OKI SUVL
Fa'
408 - 720 - 1918 IGIII!
OKI Electric Europe GmbH

Nlede rkasseler Lohweg 8
D 4 000 Dusseldorf 11
West Germany
Tel
0211-59550
Telex 8584312
Fa,
02 " -59'669 IGIIII
OKI Electroni cs (Hong Kong) ltd.

16th Floor FaIrmont House.
8 Colton Tree Dnve. Hong Kong
rei
5 - 26311 1- 3
Telex 62 4 59 OK IHK HX
Fa,
5 -200 1021GIIIJ

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MEMORY

IC MEMORY UNE-UP AND

MASK ROM CUSTOMER

CROSS REFERENCE LIST

IC MEMORY LINE-UP AND TYPICAL CHARACTERISTICS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

CMOS STATIC RAMS ............................................................

MASK ROMS ....................................................................

16 PIN PLASTIC ................................................................. 15

16 PIN STACK PLASTIC. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..

18 PIN PLCC .................................................................... 16

18 PIN PLASTiC ................................................................. 17

18 PIN SIDE-BRAZED ............................................................ 17

22 PIN PLCC .................................................................... 18

22 PIN PLASTIC ................................................................. 18

24 PIN PLASTIC ................................................................. 19

24 PIN CERDIP .................................................................. 19

24 PIN PLASTIC FLAT ............................................................ 20

26 PIN SOJ ...................................................................... 20

28 PIN PLASTIC ................................................................. 21

28 PIN CERDIP .................................................................. 21

32 PIN PLCC .................................................................... 22

4. SEMICONDUCTOR MEMORY FAILURES ................................. , . . . . . . .. 31

EPROM WRITING AND ERASURE ...................................................... 39

MASK ROM CUSTOMER PROGRAM SPECIFICATIONS ................................

TERMINOLOGY AND SYMBOLS ....................................................... 51

MOS DYNAMIC RAMS

65,536-Word x 1-Bit RAM (NMOS) . . . . . . . . . . . . . . . . . . . . . . . . . .. 76

MSM3764AASIARS 65,536-Word x 1-Bit RAM (NMOS) . . . . . . . . . . . . . . . . . . . . . . . . . .. 92

262,144-Word x 1-Bit RAM (NMOS) < Page Mode> .......... 108

262,144-Word x 1-Bit RAM (NMOS) < Page Mode> .......... 122

65,536-Word x 4-Bit RAM (NMOS) ........................... 163

262,144-Word x 4-Bit RAM (NMOS) ......................... 178

1,048,576-Word x 1-Bit RAM (NMOS) ....................... 191

1,048,576-Word x 1-Bit RAM (NMOS) <Nibble Mode> ....... 204

1,048,576-Word x 1-Bit RAM (NMOS) <Fast Page> ......... 217

1,048,576-Word x 1-Bit RAM (NMOS) <Static Column> ...... 218

262,144-Word x 4-Bit RAM (CMOS) <Fast Page> ........... 219

262,144-Word x 4-Bit RAM (CMOS) <Static Column> ....... 220

MSM37S64ARS/37S64RS 131,072-Word x 4-Bit RAM (NMOS) .................. 221

2,048-Word x 8-Bit RAM (CMOS) ............................ 278

2,048-Word x 8-Bit RAM (CMOS) ............................ 283

(NMOS) ............................ 273

2,048-Word x 8-Bit RAM (CMOS) ............................ 289

8,192-Word x 8-Bit RAM (CMOS) ............................ 294

8,192-Word x 8-Bit RAM (CMOS) ............................ 300

16,384-Word x 4-Bit RAM (CMOS) ........................... 307

32,768-Word x 8-Bit RAM (CMOS) ........................... 312

MSM51257LRS/JS 32,768-Word x 8-Bit RAM (CMOS) ........................... 318

MOS MASK ROMS

8, 192-Word x 8-Bit MASK ROM (NMOS) ..................... 326

x 8-Bit MASK ROM (NMOS) .................... 330

32,768-Word x 8-Bit MASK ROM (NMOS) .................... 334

32,768-Word x 8-Bit MASK ROM (NMOS) .................... 338

65,536-Word x 8-Bit MASK ROM (NMOS) .................... 342

1 M Bit MASK ROM (NMOS) .................................. 346

1 M Bit MASK ROM (NMOS) .................................. 351

8-Bit MASK ROM (CMOS) .................... 356

8-Bit MASK ROM (CMOS) .................. 360

8,192-Word X 8-Bit EPROM (NMOS) ......................... 366

16,384-Word X 8-Bit EPROM (NMOS) ........................ 372

8-Bit EPROM (NMOS) ........................ 378

8-Bit EPROM (NMOS) ........................ 384

131,072-Word X 8-Bit EPROM (NMOS) ...................... 389

16-Bit EPROM (NMOS) ...................... 395