VNH3SP30

FULLY INTEGRATED H-BRIDGE MOTOR DRIVER

TYPE
VNH3SP30

RDS(on) (*)
34m

IOUT
30 A

VCCmax
40 V

(*) Typical per leg at 25C

OUTPUT CURRENT:30 A

5V LOGIC LEVEL COMPATIBLE INPUTS

UNDERVOLTAGE AND OVERVOLTAGE
SHUT-DOWN
OVERVOLTAGE CLAMP
THERMAL SHUT DOWN
CROSS-CONDUCTION PROTECTION
LINEAR CURRENT LIMITER
VERY LOW STAND-BY POWER
CONSUMPTION
PWM OPERATION UP TO 10 KHz
PROTECTION AGAINST:
LOSS OF GROUND AND LOSS OF VCC

MultiPowerSO-30

DESCRIPTION
The VNH3SP30 is a full bridge motor driver
intended for a wide range of automotive
applications. The device incorporates a dual
monolithic HSD and two Low-Side switches. The
HSD switch is designed using STMicroelectronics
VIPower M0-3 technology that allows to efficiently
integrate on the same die a true Power MOSFET
with an intelligent signal/protection circuitry. The
Low-Side switches are vertical MOSFETs
manufactured
using
STMicroelectronics
proprietary EHD (STripFET) process.

BLOCK DIAGRAM
VCC

OVERTEMPERATURE A

OV + UV

OVERTEMPERATURE B

CLAMP A

HSA

CLAMP B

LOGIC

DRIVER

DRIVER
HSB

HSA

CURRENT
LIMITATION A

HSB

CURRENT
LIMITATION B

OUTA

OUTB

LSA

GNDA

April 2004

DRIVER

DRIVER
LSB

LSA

DIAGA/ENA INA

PWM

INB DIAGB/ENB

LSB

GNDB

1/26

VNH3SP30

The three dice are assembled in MultiPowerSO-30

package on electrically isolated leadframes. This
package, specifically designed for the harsh
automotive environment offers improved thermal
performance thanks to exposed die pads.
Moreover, its fully symmetrical mechanical design
allows superior manufacturability at board level.
The input signals INA and INB can directly
interface to the microcontroller to select the motor
direction and the brake condition. The DIAG A/ENA
or DIAGB/EN B, when connected to an external pull

up resistor, enable one leg of the bridge. They also

provide a feedback digital diagnostic signal. The
normal condition operation is explained in the truth
table on page 7. The PWM, up to 10KHz, lets us to
control the speed of the motor in all possible
conditions. In all cases, a low level state on the
PWM pin will turn off both the LSA and LSB
switches. When PWM rises to a high level, LSA or
LSB turn on again depending on the input pin
state.

CONNECTION DIAGRAM (TOP VIEW)

OUTA
Nc
Vcc
Nc

30

OUTA
Heat Slug3

INA
ENA/DIAGA
Nc
PWM

Nc
OUTB

GNDA
OUTA
Nc
Vcc

VCC
Heat Slug1

Nc
ENB/DIAGB
INB
Nc
Vcc

OUTA
Nc
GNDA
GNDA

Nc
OUTB
GNDB
GNDB
GNDB

OUTB
Heat Slug2

15

16

Nc
OUTB

PIN DEFINITIONS AND FUNCTIONS

PIN No
1, 25, 30

SYMBOL
OUTA, Heat
Slug2

2, 4,7,9,12,14,17, 22,
NC
24,29
VCC, Heat
3, 13, 23
Slug1
5
INA
6
ENA/DIAGA
8
PWM
9
NC
ENB/DIAGB
10
11
15, 16, 21
26, 27, 28
18, 19, 20

INB
OUTB, Heat
Slug3
GNDA
GNDB

FUNCTION
Source of High-Side Switch A / Drain of Low-Side Switch A
Not connected
Drain of High-Side Switches and Power Supply Voltage
Clockwise Input
Status of High-Side and Low-Side Switches A; Open Drain Output
PWM Input
Not connected
Status of High-Side and Low-Side Switches B; Open Drain Output
Counter Clockwise Input
Source of High-Side Switch B / Drain of Low-Side Switch B
Source of Low-Side Switch A (*)
Source of Low-Side Switch B (*)

(*) Note: GND A and GNDB must be externally connected together

2/26

VNH3SP30
PIN FUNCTIONS DESCRIPTION
NAME
VCC
GNDA
GNDB
OUTA
OUTB
INA
INB
PWM
ENA/DIAGA
ENB/DIAGB

DESCRIPTION
Battery connection.
Power grounds, must always be externally connected together.
Power connections to the motor.
Voltage controlled input pins with hysteresis, CMOS compatible. These two pins control the state of
the bridge in normal operation according to the truth table (brake to VCC, Brake to GND, clockwise and
counterclockwise).
Voltage controlled input pin with hysteresis, CMOS compatible. Gates of Low-Side FETS get
modulated by the PWM signal during their ON phase allowing speed control of the motor
Open drain bidirectional logic pins. These pins must be connected to an external pull up resistor.When
externally pulled low, they disable half-bridge A or B. In case of fault detection (thermal shutdown of a
High-Side FET or excessive ON state voltage drop across a Low-Side FET), these pins are pulled low
by the device (see truth table in fault condition).

BLOCK DESCRIPTIONS
(see Electrical Block Diagram page 4)
NAME
LOGIC CONTROL
OVERVOLTAGE + UNDERVOLTAGE
HIGH SIDE CLAMP VOLTAGE
HIGH SIDE AND LOW SIDE DRIVER
LINEAR CURRENT LIMITER
OVERTEMPERATURE PROTECTION
FAULT DETECTION

DESCRIPTION
Allows the turn-on and the turn-off of the High Side and the Low Side
switches according to the truth table.
Shut-down the device outside the range [5.5V..36V] for the battery
voltage.
Protect the High-Side switches from the high voltage on the battery
line in all configuration for the motor.
Drive the gate of the concerned switch to allow a good RDS(on) for the
leg of the bridge.
In case of short circuit for the High-Side switch, limits the motor current
by reducing its electrical characteristics.
In case of short-circuit with the increase of the junctions temperature,
shuts-down the concerned High-Side to prevent its degradation and to
protect the die.
Signalize an abnormal behavior of the switches in the half-bridge A or
B by pulling low the concerned ENx/DIAGx pin.

3/26

VNH3SP30

ABSOLUTE MAXIMUM RATING

Symbol
VCC
Imax1
IR
IIN
IEN
Ipw
VESD
Tj
Tc
TSTG

Parameter
Supply voltage
Maximum output current (continuous)
Reverse output current (continuous)
Input current (INA and INB pins)
Enable input current (DIAGA/ENA and DIAGB/ENB pins)
PWM input current
Electrostatic discharge (R=1.5k, C=100pF)

Value
-0.3.. 40
30
-30
+/- 10
+/- 10
+/- 10
4

KV

5
Internally Limited
-40 to 150
-55 to 150

kV
C
C
C

- Logic pins
- Output pins: OUTA, OUTB, VCC
Junction operating temperature
Case operating temperature
Storage temperature

Unit
V
A
A
mA
mA
mA

CURRENT AND VOLTAGE CONVENTIONS

ICC
VCC

IINA
IINB
IENA
IENB

VCC

IN A

OUTA

INB

OUTB

DIAGA/ENA

IOUTA
IOUTB
VOUTA
VOUTB

DIAGB/ENB
PWM

GNDA GNDB

Ipw
GND
VINA VINB VENA VENB

Vpw

IGND

4/26

VNH3SP30

THERMAL DATA
See MultiPowerSO-30 Thermal Data section.
ELECTRICAL CHARACTERISTICS (VCC=9V up to 18V; -40C<Tj<150C; unless otherwise specified)
POWER
Symbol
VCC
RONHS
RONLS
RON
Is
Vf

IL(off)

Parameter
Test Conditions
Operating supply voltage
On state high side resistance ILOAD=12A; Tj=25C
On state low side resistance ILOAD=12A; Tj=25C
On state leg resistance
ILOAD=12A
ON state; VINA=VINB=5V
Supply current
OFF state
High Side Free-wheeling
If=12A
Diode Forward Voltage
Tj=25C; VOUTX=ENX=0V;
VCC=13V
High Side Off State Output
Current (per channel)
Tj=125C; VOUTX=ENX=0V;

Min
5.5

Typ
23
11

0.8

VCC=13V

Max
36
30
15
90
15

Unit
V
m
m
m
mA

40

1.1

Unit
kHz
s
s
s
s

SWITCHING (V CC=13V, RLOAD=1.1)

Symbol
f
tD(on)
tD(off)
tr
tf
tDEL

Parameter
PWM frequency
Turn-on delay time
Turn-off delay time
Output voltage rise time
Output voltage fall time
Delay time during change of
operation mode

Test Conditions

Min
0

Typ

Input rise time < 1s (see fig. 3)

Input rise time < 1s (see fig. 3)
(see fig. 2)
(see fig. 2)

100
85
1.5
2

Max
10
300
255
3
5

(see fig. 1)

600

1800

Min

Typ

Max
5.5

36
30

43
45

Unit
V
V
A

150

170

200

135
7

15

PROTECTION AND DIAGNOSTIC

Symbol
VUSD
VOV
ILIM
TTSD
TTR
THYST

5/26

Parameter
Undervoltage shut-down
Overvoltage shut-down
Current limitation
Thermal shut-down
temperature
Thermal Reset Temperature
Thermal Hysteresis

Test Conditions

VIN = 3.25 V

C
C

VNH3SP30

PWM
ELECTRICAL CHARACTERISTICS (continued)
Symbol
Vpwl
Ipwl
Vpwh
Ipwh
Vpwhhyst
Vpwcl
Vpwtest
Ipwtest

Parameter
Test Conditions
PWM low level voltage
Low level PWM pin current Vpw=1.5V
PWM high level voltage
High level PWM pin current Vpw=3.25V
PWM hysteresis voltage
Ipw = 1 mA
PWM clamp voltage
Ipw = -1 mA
Test mode PWM pin voltage
Test mode PWM pin current Vpwtest = -2.0V

Min

Typ

Max
1.5

1
3.25
10

Unit
V
A
V
A
V
V

0.5
VCC+0.3

VCC+0.7

VCC+1.0

-5.0
-3.5
-2000

-3.5
-2.0
-500

-2.0
-0.5

V
V
A

Min

Typ

Max
1.5

LOGIC INPUT (IN A/INB)

Symbol
VIL
IINL
VIH
IINH
VIHYST
VICL

Parameter
Input low level voltage
Input current
Input high level voltage
Input current
Input hysteresis voltage
Input clamp voltage

Test Conditions

IIN=1mA

0.5
6.0

6.8

8.0

Unit
V
A
V
A
V
V

IIN=-1mA

-1.0

-0.7

-0.3

Test Conditions
Normal operation

Min

Typ

Max

Unit

1.5

VIN=1.5V

1
3.25

VIN=3.25V

10

ENABLE (LOGIC I/O PIN)

Symbol
VENL
IENL
VENH
IENH
VEHYST
VENCL

VDIAG

Parameter
Enable low level voltage

(DIAGX/ENX pin acts as an

input pin)
Low level Enable pin current VEN= 1.5V
Normal operation
Enable high level voltage
(DIAGX/ENX pin acts as an
input pin)
High level Enable pin
VEN= 3.25V
current
Normal operation
Enable hysteresis voltage
(DIAGX/ENX pin acts as an
input pin)
IEN=1mA
Enable clamp voltage
IEN=-1mA
Fault operation
Enable output low level
(DIAGX/ENX pin acts as an
input pin)
voltage

3.25

10
0.5

A
V

6.0

6.8

8.0

-1.0

-0.7

-0.3

0.4

IEN=1 mA

6/26

VNH3SP30

WAVEFORMS AND TRUTH TABLE

TRUTH TABLE IN NORMAL OPERATING CONDITIONS
In normal operating conditions the DIAGX/ENX pin is considered as an input pin by the device. This pin must be externally
pulled high.
INA

INB

DIAGA/ENA

DIAGB/ENB

OUTA

OUTB

1
1
0
0

1
0
1
0

1
1
1
1

1
1
1
1

H
H
L
L

H
L
H
L

Comment
Brake to VCC
Clockwise
Counter cw
Brake to GND

PWM pin usage:

In all cases, a 0 on the PWM pin will turn-off both LSA and LSB switches. When PWM rises back to 1, LS A or LSB
turn on again depending on the input pin state.
NB: in no cases external pins (except for GNDB and GNDA) are allowed to be connected with ground.

TYPICAL APPLICATION CIRCUIT FOR DC TO 10KHz PWM OPERATION

VCC

Reg 5V
+5V
+5V
3.3K

3.3K

VCC

1K

1K

DIAGB/ENB

DIAGA/ENA

1K

PWM

HSA

OUTA

OUTB

HSB

C
1K

INA

INB

CW
(*)

LSA

LSB

10K

GNDA

CCW
GNDB

S
G

b) N MOSFET
D

(*) Open load detection in off mode

7/26

1K

VNH3SP30
REVERSE BATTERY PROTECTION
Three possible solutions can be thought of:
a) a Schottky diode D connected to V CC pin
b) a N-channel MOSFET connected to the GND pin (see Typical Application Circuit on page 7)
c) a P-channel MOSFET connected to the V CC pin
The device sustains no more than -30A in reverse battery conditions because of the two Body diodes of
the Power MOSFETs. Additionally, in reverse battery condition the I/Os of VNH2SP30 will be pulled down
to the VCC line (approximately -1.5V). Series resistor must be inserted to limit the current sunk from the
microcontroller I/Os. If I Rmax is the maximum target reverse current through C I/Os, series resistor is:
VIOs V CC
R = ------------------------------IRm ax

OPEN LOAD DETECTION IN OFF-MODE

It is possible for the microcontroller to detect an open load condition by adding a simply resistor (for
example 10k) between one of the outputs of the bridge (for example OUTB) and one microcontroller
input. A possible sequence of inputs and enable signals is the following: INA=1, INB=X, ENA= 1, ENB=0.
- normal condition: OUTA=H and OUTB=H
- open load condition: OUTA=H and OUT B=L: in this case the OUTB pin is internally pulled down to
GND. This condition is detected on OUTB pin by the microcontroller as an open load fault.
SHORT CIRCUIT PROTECTION
In case of a fault condition the DIAGX/EN X pin is considered as an output pin by the device.
The fault conditions are:
- overtemperature on one or both high sides;
- short to battery condition on the output (saturation detection on the Low-Side Power MOSFET).
Possible origins of fault conditions may be:
OUTA is shorted to ground ---> overtemperature detection on high side A.
OUTA is shorted to VCC ---> Low-Side Power MOSFET saturation detection. (1)
When a fault condition is detected, the user can know which power element is in fault by monitoring the
IN A, INB, DIAGA/EN A and DIAGB/ENB pins.
In any case, when a fault is detected, the faulty half bridge is latched off. To turn-on the respective output
(OUTX) again, the input signal must rise from low to high level.
(1) An internal operational amplifier compares the Drain-Source MOSFET voltage with the internal reference (2.7V Typ.).
The relevant Lowside PowerMOS is switched off when its Drain-Source voltage exceeds the reference voltage.

TRUTH TABLE IN FAULT CONDITIONS (detected on OUTA)

INA

INB

DIAGA/ENA

DIAGB/ENB

OUTA

OUTB

OPEN

OPEN

OPEN

OPEN

OPEN

OPEN

OPEN

OPEN

OPEN

Fault Information

Protection Action
8/26

VNH3SP30

TEST MODE
The PWM pin allows to test the load connection between two half-bridges. In the test mode (Vpwm =-2V)
the internal Power Mos gate drivers are disabled. The INA or INB inputs allow to turn-on the High Side A
or B, respectively, in order to connect one side of the load at VCC voltage. The check of the voltage on
the other side of the load allow to verify the continuity of the load connection. In case of load
disconnection the DIADX/ENX pin corresponding to the faulty output is pulled down.
ELECTRICAL TRANSIENT REQUIREMENTS
ISO T/R
7637/1
Test Pulse
1
2
3a
3b
4
5
ISO T/R
7637/1
Test Pulse
1
2
3a
3b
4
5
Class
C
E

9/26

Test Level

Test Level

Test Level

Test Level

Test Levels

II

III

IV

Delays and Impedance

-25V
+25V
-25V
+25V
-4V
+26.5V

-50V
+50V
-50V
+50V
-5V
+46.5V

-75V
+75V
-100V
+75V
-6V
+66.5V

-100V
+100V
-150V
+100V
-7V
+86.5V

2ms, 10
0.2ms, 10
0.1s, 50
0.1s, 50
100ms, 0.01
400ms, 2

Test Levels Result

Test Levels Result

Test Levels Result

Test Levels Result

II

III

IV

C
C
C
C
C
C

C
C
C
C
C
E

C
C
C
C
C
E

C
C
C
C
C
E

Contents
All functions of the device are performed as designed after exposure to disturbance.
One or more functions of the device are not performed as designed after exposure to disturbance
and cannot be returned to proper operation without replacing the device.

VNH3SP30
HALF-BRIDGE CONFIGURATION
The VNH3SP30 can be used as a high power half-bridge driver achieving an on resistance
per leg of 22.5m. Suggested configuration is the following:
VCC
INA
INB
DIAGA/ENA
DIAGB/ENB
PWM

IN A
INB
DIAGA/ENA
DIAGB/ENB
PWM
OUTA

OUTB

GNDA

OUTB

OUTA

GNDA

GNDB

GNDB

MULTI-MOTORS CONFIGURATION
The VNH3SP30 can easily be designed in multi-motors driving applications such as seat
positioning systems where only one motor must be driven at a time. DIAGX/ENX pins allow
to put unused half-bridges in high impedance. Suggested configuration is the following:

VCC
INA
INB
DIAGA/ENA
DIAGB/ENB
PWM

INA
IN B
DIAGA/ENA
DIAGB/ENB
PWM
OUTA

OUTB

GNDA

GNDB

M1

10/26

M2

OUTB

OUTA

GND A

GNDB

M3

VNH3SP30

Figure 1: Definition of the delay times measurement (example of clockwise operation)

VINA,

t
VINB

t
PWM

t
ILOAD
tDEL

tDEL

Figure 2: Definition of the Low Side Switching times

PWM

t
VOUTA, B

90%

tf

80%

20%

10%

tr

11/26

VNH3SP30

Figure 3: Definition of the High side Switching times

VINA,

tD(on)

tD(off)

t
VOUTA

90%

10%

12/26

VNH3SP30

Waveforms

NORMAL OPERATION (DIAGA/EN A=1, DIAGB/EN B=1)

DIAGA/ENA
DIAGB/ENB
INA
INB
PWM
OUTA
OUT B
(int. pin) GATEA
(int. pin) GATEB

NORMAL OPERATION (DIAG A/EN A=1, DIAGB/ENB=0 and DIAGA/EN A=0, DIAGB/ENB=1)
DIAGA/ENA
DIAGB/ENB
INA
INB
PWM
OUTA
OUT B
(int. pin) GATEA
(int. pin) GATEB

CURRENT LIMITATION/THERMAL SHUTDOWN or OUTA SHORTED TO GROUND

INA
INB
ILIM
IOUTA

TTSD

Tj
DIAGA/ENA
DIAGB/ENB
(int. pin) GATEA
(int. pin) GATEB
normal operation

13/26

OUTA shorted to ground

normal operation

VNH3SP30

Waveforms (Continued)

OUTA shorted to VCC and undervoltage shutdown

INA
INB
OUTA
OUTB
(int. pin) GATEA
(int. pin) GATEB
DIAGB/ENB
DIAGA/ENA
VCC

normal operation

OUTA shorted to VCC

normal operation

undervoltage shutdown

Load disconnection test (INA=1, PWM=-2V)

INA
INB
PWM
(test mode)
OUTA
OUTB
(int. pin)GATEA
(int. pin) GATEB
DIAGA/ENA
DIAGB/ENB
load connected

load disconnected

load connected back

14/26

VNH3SP30

Off State Supply Current

On State Supply Current

Is (mA)

Is (uA)

50
45

Vcc=18V

Vcc=18V
INA or INB=5V

40
35

30
25

20

15
2
10
1

5
0

0
-50

-25

25

50

75

100

125

150

-50

175

-25

25

50

75

100

125

150

175

Tc (C)

Tc (C)

High Level Input Current

Input Clamp Voltage

Iinh (A)

Vicl (V)

7.75

Vin=3.25V

Iin=1mA

7.5

7.25

6.75

6.5

6.25

6
-50

-25

25

50

75

100

125

150

175

-50

-25

25

Tc (C)

50

75

100

125

150

175

Tc (C)

Input High Level Voltage

Input Low Level Voltage

Vih (V)

Vil (V)

3.6

2.8

3.4

2.6
2.4

3.2

2.2
3
2
2.8
1.8
2.6
1.6
2.4

1.4

2.2

1.2

1
-50

-25

25

50

75

Tc (C)

15/26

100

125

150

175

-50

-25

25

50

75

Tc (C)

100

125

150

175

VNH3SP30

Input Hysteresis Voltage

High Level Enable Pin Current

Ienh (A)

Vihyst (V)

2
1.8

Vcc=13V

Ven=3.25V

1.6
6
1.4
5

1.2

1
0.8

0.6
2
0.4
1

0.2

0
-50

-25

25

50

75

100

125

150

175

-50

-25

25

50

75

100

125

150

100

125

150

175

Tc (C)

Tc (C)

High Level Enable Voltage

Low Level Enable Voltage

Venl (V)

Venh (V)

2.8

4
3.8

2.6

Vcc=9V

Vcc=9V

3.6

2.4

3.4

2.2

3.2
2
3
1.8
2.8
1.6
2.6
1.4

2.4

1.2

2.2

2
-50

-25

25

50

75

100

125

150

175

-50

-25

25

50

75

175

Tc (C)

Tc (C)

Enable Clamp Voltage

Enable Output Low Level Voltage

Vdiag (V)

Vencl (V)

0.6

0.525

7.75

Ien=1mA

Ien=1mA

0.45

7.5

0.375

7.25

0.3

0.225

6.75

0.15

6.5

0.075

6.25

6
-50

-25

25

50

75

Tc (C)

100

125

150

175

-50

-25

25

50

75

100

125

150

175

Tc (C)

16/26

VNH3SP30

PWM High Level Voltage

PWM Low Level Voltage

Vpwl (V)

Vpwh (V)

2.8

5
4.5

2.6

Vcc=9V

Vcc=9V

2.4

3.5

2.2

3
2
2.5
1.8
2
1.6

1.5

1.4

1.2

0.5
0

1
-50

-25

25

50

75

100

125

150

-50

175

-25

25

Tc (C)

50

75

100

125

150

175

100

125

150

175

100

125

150

175

Tc (C)

Overvoltage Shutdown

PWM High Level Current

Ipwh (A)

Vov (V)

54
52

Vcc=9V
Vpw=3.25V

50
48

46
44

42

40
2
38
1

36
34

0
-50

-25

25

50

75

100

125

150

-50

175

-25

25

50

75

Tc (C)

Tc (C)

Current Limitation

Undervoltage Shutdown

Ilim (A)

Vusd (V)

80

75

6.5

70
6
65
5.5

60
55

50

4.5

45
4
40
3.5

35
30

3
-50

-25

25

50

75

Tc (C)

100

125

150

175

-50

-25

25

50

75

Tc (C)

17/26

VNH3SP30

On State High Side Resistance Vs. Tcase

On State High Side Resistance Vs. VCC

Ronhs (mOhm)

Ronhs (mOhm)

80

80

70

70

Iload=12A
Vcc=9V; 13V; 18V

60

Iload=12A
60

50

50

40

40

30

30

20

20

10

10

Tc= 150C

Tc= 25C

Tc= -40C

0
-50

-25

25

50

75

100

125

150

175

10

11

12

13

Tc (C)

On State Low Side Resistance Vs. Tcase

15

16

17

18

19

20

On State Low Side Resistance Vs. VCC

Ronls (mOhm)

Ronls (mOhm)

40

40

35

35

Iload=12A
Vcc=9V; 13V; 18V

30

14

Vcc (V)

Iload=12A
30

25

25

20

20

15

15

10

10

Tc= 150C

Tc= 25C

Tc= -40C

0
-50

-25

25

50

75

100

125

150

175

10

11

12

Tc (C)

13

14

15

16

17

18

19

20

Vcc (V)

Delay Time during change of operation mode

On State Leg Resistance

Ron (mOhm)

tdel (s)

90

1000

80

900
800

70

700
60
600
50
500
40
400
30

300

20

200

10

100
0

0
-50

-25

25

50

75

Tc (C)

18/26

100

125

150

175

-50

-25

25

50

75

Tc (C)

100

125

150

175

VNH3SP30

Turn-on Delay Time

Turn-off Delay Time

td(on) (s)

td(off) (s)

100

150

90

140

80

130

70

120

60

110

50

100

40

90

30

80

20

70

10

60
50

0
-50

-25

25

50

75

100

125

150

-50

175

-25

25

50

75

100

125

150

175

Tc (C)

Tc (C)

Output Voltage Rise Time

Output Voltage Fall Time

tf (s)

tr (s)

4.5

0.9

4
0.8
3.5
0.7

3
2.5

0.6

0.5

1.5
0.4
1
0.3

0.5
0

0.2
-50

-25

25

50

75

Tc (C)

100

125

150

175

-50

-25

25

50

75

100

125

150

175

Tc (C)

19/26

VNH3SP30

MultiPowerSO-30 THERMAL DATA

MultiPowerSO-30 PC Board

Layout condition of Rth and Zth measurements (PCB FR4 area= 58mm x 58mm, PCB thickness=2mm,
Cu thickness=35m, Copper areas: from minimum pad lay-out to 16cm2).

CHIPSET CONFIGURATION

HIGH SIDE
CHIP
HSAB

LOW SIDE
CHIP A

LOW SIDE
CHIP B

LSA

LSB

Auto and mutual Rthj-amb Vs PCB copper area in open box free air condition (according to page 20
definitions)
C/W

45

RthA
RthB = RthC
RthAB = RthAC
RthBC

40
35
30
25
20
15
10
5
0
0

52
10
15
cm of Cu Area (refer to PCB layout)

20

20/26

VNH3SP30

THERMAL CALCULATION IN CLOCKWISE AND ANTI-CLOCKWISE OPERATION IN STEADYSTATE MODE

HSA

HSB

LSA

LSB

ON

OFF

OFF

ON

OFF

ON

ON

OFF

TjHSAB
PdHSA x RthHS + PdLSB x
RthHSLS + Tamb
PdHSB x RthHS + PdLSA x
RthHSLS + Tamb

TjLSA
PdHSA x RthHSLS + PdLSB x
RthLSLS + Tamb
PdHSB x RthHSLS + PdLSA x
RthLS + Tamb

TjLSB
PdHSA x RthHSLS + PdLSB x
RthLS + Tamb
PdHSB x RthHSLS + PdLSA x
RthLSLS + Tamb

Thermal resistances definition (values according to the PCB heatsink area)

RthHS = RthHSA = R thHSB = High Side Chip Thermal Resistance Junction to Ambient (HSA or HSB in ON
state)
RthLS = R thLSA = R thLSB = Low Side Chip Thermal Resistance Junction to Ambient
RthHSLS = R thHSALSB = RthHSBLSA = Mutual Thermal Resistance Junction to Ambient between High Side
and Low Side Chips
RthLSLS = RthLSALSB = Mutual Thermal Resistance Junction to Ambient between Low Side Chips

THERMAL CALCULATION IN TRANSIENT MODE (*)

TjHSAB = ZthHS x PdHSAB + ZthHSLS x (PdLSA + PdLSB) + Tamb
TjLSA = ZthHSLS x PdHSAB + ZthLS x PdLSA + ZthLSLS x PdLSB + Tamb
TjLSB = ZthHSLS x PdHSAB + ZthLSLS x PdLSA + Z thLS x PdLSB + Tamb
Single pulse thermal impedance definition (values according to the PCB heatsink area)
ZthHS = High Side Chip Thermal Impedance Junction to Ambient
ZthLS = ZthLSA = ZthLSB = Low Side Chip Thermal Impedance Junction to Ambient
ZthHSLS = ZthHSABLSA = ZthHSABLSB = Mutual Thermal Impedance Junction to Ambient between High Side
and Low Side Chips
ZthLSLS = ZthLSALSB = Mutual Thermal Impedance Junction to Ambient between Low Side Chips

Pulse calculation formula

Z TH

where

= R TH + Z THtp ( 1 )
= tp T

(*) Calculation is valid in any dynamic operating condition. Pd values set by user.

21/26

VNH3SP30

MultiPowerSO-30 HSD Thermal Impedance Junction Ambient Single Pulse

10 0

Footprint
4 cm2
8 cm2
16 cm2

ZthHS

Footprint
4 cm2
8 cm2
16 cm2

10

C/W

ZthHSLS

0 .1
0 .0 0 1

0 .0 1

0 .1

t i m e ( se c )

10

100

10 0 0

MultiPowerSO-30 LSD Thermal Impedance Junction Ambient Single Pulse

100

Footprint
4 cm2
8 cm2
16 cm2

Z thLS

Footprint
4 cm2
8 cm2
16 cm2

10

C/W

ZthLSLS

0 .1
0 .0 0 1

0 .0 1

0 .1

t i m e ( se c )

10

100

1000

22/26

VNH3SP30

Thermal fitting model of an H-Bridge in MultiPowerSO-30

Thermal Parameter (*)

Area/island (cm2)
R1=R7 (C/W)
R2=R8 (C/W)
R3 (C/W)
R4 (C/W)
R5 (C/W)
R6 (C/W)
R9=R10=R15=R16 (C/W)
R11=R17 (C/W)
R12=R18 (C/W)
R13=R19 (C/W)
R14=R20 (C/W)
R21=R22=R23 (C/W)
C1=C7 (W.s/C)
C2=C8 (W.s/C)
C3 (W.s/C)
C4=C13=C19 (W.s/C)
C5 (W.s/C)
C6 (W.s/C)
C9=C15 (W.s/C)
C10=C11=C16=C17 (W.s/C)
C12=C18 (W.s/C)
C14=C20 (W.s/C)

Footprint
0.05
0.3
0.5
1.3
1.4
44.7
0.6
0.8
1.5
20
46.9
115
0.001
0.005
0.02
0.3
0.6
5
0.001
0.003
0.075
2.5

(*) The blank space means that the value is the same as the previous one.

23/26

16

39.1

31.6

23.7

36.1

30.4

20.8

11

3.5

4.5

5.5

VNH3SP30

MultiPowerSO-30 MECHANICAL DATA

DIM.

mm.
MIN.

TYP

2.35

A2

1.85

2.25

A3

0.1

0.42

0.58

0.23

17.1

18.85

E1

15.9

17.3
19.15

16

16.1

1
5.55

F2

4.6

5.1

F3

9.6

10.1

0.8

0.32
17.2

F1

24/26

MAX.

6.05

1.15
10deg

0deg

7deg

VNH3SP30

MultiPowerSO-30 SUGGESTED PAD LAY-OUT

25/26

VNH3SP30

Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences
of use of such information nor for any infringement of patents or other rights of third parties which may results from its use. No license is
granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are
subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products
are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics.
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26/26

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www.datasheetcatalog.com
Datasheets for electronics components.