Professional Documents
Culture Documents
Transistor fT Calculation
VDD
id
ig
vgs
Cgs
gm = Cox
Cgs
VGS
id
gm
=
i g 2fCgs
becomes 1.
T = 2fT =
VGS Vt
2
L
(VDD = 2.5V)
(VDD = 1.8V)
2
Wp
Lp
Vout
Vin
Wn
Ln
Wp
Lp
Wn
Ln
Wn
VDD Vt
Ln
CL
rise
Wp
VDD Vt
Lp
rise = fall =
CL
fall
L2min
=
n
# W &
1
4
=
%%1+ p ((
$ Wn ' VDD Vt T
Vout
ID
= 18ps
fT = 57GHz
EECS 270C / Winter 2014
6.4
T
4
VDD
Vin
IDD
Vin
Vout
Vout
ISS
ISS
sub
IDD
VSS
data out
clock in
clock out
VSS
"
Rs = 5 Ls = 5nH
VDD
"
clock out
Rs = 0
Ls = 0
clock out
Rs = 5
Ls = 5nH
VSS
"
data out
Full speed of transistors not exploited due to n-channel & pchannel gate in parallel at load.
Single-ended operation causes current spikes leading to VDD/
VSS bounce.
Single-ended operation also highly sensitive to VDD/VSS bounce
leading to jitter.
Vout+
Vin+
Vout-
CL
CL
ISS
Differential operation
Vin-
VIN(DC )
1
ISS R
2_
1
ISS R
2 _
VOUT(DC )
VOUT(DC )
W
L
VGS _
1
Vin(DC ) = Vout (DC ) = VDD ISS R
2
VS
W
L
ISS
)
VIN(DC
+
VGS
VS > VBIAS Vt
VS = Vin(DC ) VGS
VBIAS
VDD
R
VDD-ISSR
ISS
VDD
VDD
CL
CL
W
L
W
L
VDD-ISS
R
ISS
Vswing = ISS R
Vswing VGS Vt
|I D =ISS
2ISS
nCox
W
L
Vmin
Vswing
1
W
=R
Cox
ISS
Vmin
2
L
Vswing
> 1 for correct operation
Vmin
10
Av = gm R = R Cox
Recall
W
L SS
Vswing
1
W
=R
Cox
ISS > 1
Vmin
2
L
Vswing Av
=
Vmin
2
Av 2
= R(WLCox )
Note: rising & falling
time constants are the same
11
12
Av2 = nCox
W
L SS
)(
n
A = 2 Vswing
L
2
v
Vswing
Av2 n
= 2 Vswing
13
Thought Experiment
W
L
W
L
W
L
W
L
ISS
ISS
W
1
2 Vmin
, CL 2
L
2
= RC 2
R
Slower!
2
Prof. M. Green / U.C. Irvine
14
gm Av
2
=
T T T
n-channel ac simulation
to determine fT:
ID
= 8ps
2.9
T
fT = 57GHz
EECS 270C / Winter 2014
Irvine
Prof. M. Green / U.C.
15
Vswing = ISS R
Once Vswing has been chosen, designer can trade off between gain &
bandwidth by parameterizing between R & ISS:
= R(WLCox )
Av = R Cox
W
L SS
Higher gain:
ISS
16
1.
ISS
17
VDD
"
data in
data out
clock in
clock out
VSS
"
Rs = 5 Ls = 5nH
clock out
Rs = 0
Ls = 0
VDD
"
VSS
"
clock out
Rs = 5
Ls = 5nH
data out
18
tp
2tp
inverter
buffer
CML:
Vout+
Vin+
Vout
Vout
Vin
buffer
inverter
EECS 270C / Winter 2014
Vin
Vin+
Vout+
19
R
Vout-
1x
Vin+
W
L
R
Vout+
W
L
Vin-
ISS
R/n
Vout-
R/n
Vout+
W
L
W
n
L
nx
Vin+
Vin-
nISS
20
For fanout of n:
= nCL R
Av2
2
=
V
2 swing
nL
21
%
C
= nCL + Cp R / n = WLCox R ''1+ p
& nCL
)(
nW
ox L
2
v
A = 2nC
)(
nISS R / n
= 2nCox
(
**
)
W
L
ISSR2
1
%
(
C
A
2
p
**
= 2n Vswing ''1+
L
& nCL )
2
v
22
ID
+
V
GS _
Square-law behavior
Weak inversion (exponential)
VGS
3.
4.
Choose minimum scaling factor after laying out some test buffers of various
sizes and determining approximate value of interconnect capacitance Cp.
23
standard layout
shared drain
(1/2 diffusion capacitance)
ID I max
Imax independent of W
determined by electromigration limits
EECS 270C / Winter 2014
24
R = 900
ISSR = 360mV
tp = 10ps
R too small
W
4 m
=
L 0.18 m
R = 1200
ISSR = 480mV
tp = 12ps
*R optimum*
R = 1500
ISSR = 600mV
tp = 14ps
R too large
25
ISS = 200 A
R = 2.4 k
Av = 7.1 dB
BW = 5.5 GHz
ISS = 400 A
R = 1.2 k
Av = 3.9 dB
BW = 11.5 GHz
26
GBW
GSCALE MSCALE
W
GSCALE MSCALE
L
GSCALE MSCALE
ISS
GBW
27
28
Poly resistor:
p-channel MOSFET:
1
C Cpoly sub
2
1
C Cdepletion + Cchannel gate + Cchannel sub
2
gate
channel
sub
29
p-channel MOSFET:
1
C Cpoly sub
2
Wpoly = 0.6
Lpoly = 2.5
= 0.1 fF
= Wdiff = 2.5 m
Wchannel
Lchannel = 0.18 m
Ldiff = 0.3 m
C Cdepletion +
=
0.9 fF
1
Cchannel gate + Cchannel sub
2
+ 1.8 fF + .03 fF
)
= 2.8 fF
30
M1
Wp = 2.5 m
Ldiff = 0.3 m
Cd2 = 2.8 fF
M1
M2
M2
M1
M1
Cd1 = 3.7 fF
Cg1 = 5.8 fF
31
resistor load
R = 1.2 k
td = 16 ps; PWout = 100 ps
p-channel load
(W/L)p = 2.5 m / 0.18 m
td = 20 ps; PWout = 98 ps
32
p-channel load
ID
R
= 1.5% mismatch
R
ID
= 4% mismatch
DCD
ISI
33
MA
MA
MA
MB
MA
MB
34
BP
I2
BN
VBP VBN
I1 I2
ISS
VBP VBN
Slope = gm
-ISS
35
IBP IBN
VB(cm) = 1.0
VB(cm) = 1.3
VB(cm) = 1.6
DC current:
IBP IBN
VB(cm) = 1.3
VB(cm) = 1.0
VBP VBN
Transient response:
(400mV amplitude sine
wave applied to BP/BN)
VB(cm) = 1.6
t
EECS 270C / Winter 2014
36
VDD
Output levels:
+
ISS Rcm
Rcm
Vlow
(
= (V
)
) I
DD
ISSRcm
SS
Vswing = ISSR
ISS
37
SELA
R
OUTP
OUTN
AP
AN
BP
SELA
BN
SELB
ISS
AP/N
BP/N
OUTP/N
38
CML Latch
By setting BP/N = OUTP/N, we can construct a CML latch:
OUTP
OUTN
DP
DN
CKP
CKN
ISS
39
CML D Flip-Flop
XP
XN
OUTP
OUTN
DP
DN
CKP
XP
CKN
XN
CKN
CKP
CKP/N
Output OUTP/N is synchronized with
CKP/N falling edge.
DP/N
OUTP/N
EECS 270C / Winter 2014
40
slope=1/rgg
VGG
1
ISS
2
dc operating points
VGG
rgg =
2
2R
=
<0
1/ R gm 1 gm R
41
gm R > 1
gm R 1
XP/N
gm R 1
transparent latch
42
QIN
XN
DP
XP
QIP
OUTP
OUTN
QIP
XP
DN
CKP
CKN
QIN
XN
CKN
CKP
GBW parameter
can be increased to
ensure bistability.
R=1000
gmR > 1
R=800
gmR 1
R=600
gmR < 1
43
1x
1x
1x
C
Fanout = n
= nRC f3dB =
1
2
44
nx
kx
k2
m stages
Now is increased by k << n
Delay = mktp
Power = P1(1 + k + k2 + + n)
Power dissipated by first stage
As fclock 1/tp then k 1; number of stages and total power become very large.
EECS 270C / Winter 2014
45
1
1
(1 2LC) + j (L / R)
Y = + jC +
=
R
j L
jL
1
Resonant frequency: r =
LC
Y=
1
at resonance
R
If lossless inductors were available, we could achieve high gain at any frequency
simply by choosing the correct inductor value.
46
Resistor:
l
R=
t w
Capacitor:
C lw
(+ fringing)
substrate
Inductor:
t
) # 2 &
t +w,
l
0.2+ln%
. pH/m
( + 0.50049 +
t
+
w
3
'
l* $
47
l
t
) # 2 &
t +w,
l
0.2+ln%
. pH/m
( + 0.50049 +
t
+
w
3
'
l* $
48
number of turns n = 2
49
50
Cox1
Rsub1 Csub1
L:
Rs:
Cint:
Cox:
Csub/Rsub:
Rs
Cox2
Csub2 Rsub2
Self/mutual inductance
Series resistance
Interwinding capacitance
Oxide capacitance
Substrate capacitance/resistance
51
Parasitic capacitances usually combine with load capacitance L should be decreased slightly
Series Rs has more important effect:
L
C
L'
Rs
Y=
1
1
+ jC +
R
Rs + jL
Y" =
1
1
+ jC +
R"
jL"
At resonance, Im [Y(jr)] = 0:
2
1 $ Rs '
r =
& )
LC % L (
r =
( )
( )
1
R"
L" =
L
1 CRs
2
L
# L &
R
"
=
R
||
%
(
$ CRs '
1
L#C
Y " j r =
1 CRs
Y j r = +
R
L
52
Differential-mode ground
Sets common-mode
output voltage
53
54
55
IL
Vswing
Vswing
Iin =
R"
Vswing
IL =
L#
IL = 16mA
Spiral inductor should be wide enough
to meet ac electromigration specs.
56
LC lossless
transmission line
(Z0)
+
R
Vin
1
H(s) =
2
| H( j ) |
Vout
1
CR
1+ s
2
+
R
Vin
H(s) =
| H( j ) |
0.5
0.5
Vout
_
1 sTd
e
2
for R = Z0
Td = LC
H( j )
2
CR
H( j )
90 !
slope = -Td
57
Cd
Cg
Cd
Cg
Series peaking
EECS 270C / Winter 2014
58
Using R
Vx-
Vin+
Vin-
Lser
Cd
Vx+
Lser
Cd
set Lser Cd R2
expense
of extra delay.
Cg
Cd = Cg = 16 fF
R = 400
Frequency response:
Vx
Vin
Lser = 0
BW = 6.3 GHz
Transient response:
Vx (Lser = 3.5 nH)
Lser = 3.5 nH
BW = 8.3 GHz
Vx (Lser = 0)
#V &
% x (
$ Vin '
Vin
Lser = 3.5 nH
Lser = 0
59
Shunt-Peaking (1)
60
Properties of Shunt-Peaking
Frequency response:
L
R
Z( j ) = R
2
1 LCL + jCL R
1+ j
CL
L
R
Z(s) = R
1+ sCL R + s 2LCL
1+ s
Resonant frequency:
1 $ CL R2 '
r =
&1
)
LCL %
L (
2
Im s
OX
Re s
L = 0:
L 0:
zero at s = R/L pole at s = 1/RC
additional pole at
s (1/CR + R/L)
No resonance for
L
<1
2
CL R
61
Shunt-Peaking -- AC Response
L
= 0.3
CL R2
CL = 38 fF
L = 1.8 nH
BW = 9.4 GHz
R = 400
Use of shunt-peaking
increases small-signal bandwidth
L
= 0.6
CL R2
L=0
BW = 6.3 GHz
L = 3.7 nH
BW = 14.3 GHz
62
L = 3.7 nH
td = 6.7 ps
L = 1.8 nH
td = 8.5 ps
L=0
td = 13.4 ps
L = 1.8 nH
tout = 50.0 ps
ISI = 0 mUI
L=0
tout = 48.7 ps
ISI = 26 mUI
63
L
= 0.6
2
CL R
L
=0
2
CL R
L
= 0.3
2
CL R
64
65
L
long metal lines
CL
CL
CP
CP
RP
L
RP
CL
CL
66
CP = 0
L
=0
CL R2
L
= 0.3
CL R2
ISI (UI)
L
= 0.6
CL R2
CP = 0.2CL
L
=0
CL R2
L
= 0.3
CL R2
metal 6
metal 6
d
metal 5
metal 5
d
Distance d between two metal layers is much smaller than lateral distances
(e.g., w, l, s)
68
i1
+
1
_
i1
i2
L1
L2
+
1 L1
_
+
2
_
+
L2 2
_
i2
Passivity constraint: k 1
# & ) L M ,# i &
1
% 1(=+ 1
.% (
$ 2 ' *M L2 -$i 2 '
i series = i 1 = i 2
Lseries =
series
= L1 + L2 + 2M
i series
Multi-layer inductors are more appropriate for shunt-peaking than resonant structures
due to additionalcontact resistance.
69
Effective Capacitance:
Leffective 4L
Ci
1
1
Ceffective Ci + C j
3
12
Cj
70
71
Impedance inversion:
Ideal gyrator:
i1
Rgyr
i2
iin
v1
v2
vin
Rgyr
v 2 = Rgyr i1
( )
2
Zin = Rgyr
sC
v1 = Rgyr i 2
Matrix representation (Z-parameters):
" % )
$ v1 ' = + 0
#v 2 & *Rgyr
EECS 270C / Winter 2014
Rgyr ," i1 %
.$ '
0 -#i 2 &
72
v2 =
i2
RG
1
i1
gm
_
i1
v1
#
1&
v1 = % RG (i 2
gm '
$
(Assume RG gm > 1)
+
Complete Z-parameters (lossy/active gyrator):
" v % )1 g
$ 1' = + m
#v 2 & +*1 gm
RG 1 gm ," i1 %
.$ '
.-# i 2 &
1 gm
73
" v % )1 g 1 g R ," i %
m
G
1
$ 1' = + m
.$ '
1 gm -#i 2 &
#v 2 & *1 gm
vin
74
Zsource
1 " 1+ sCgs RG %
=
$
'
gm #1+ s Cgs gm &
75
Zsource
Leff
Cgs RG RG
=
gm
T
RG
1
gm
vin
1
gm
Cgs
gm
Cgs
1
Cgs RG
gmRG > 1
RG
gm
RG
1
gm
76
Low-frequency gain:
Av =
gm 1
W1
=
gm 2
W2
L 0.3CL R2
"W %
4
$ ' =
# L &1 0.18
gm 2RG = 0.3
CL
Cgs
"W %
2.5
$ ' =
# L &2 0.18
ISS = 400 A
Cgs RG
C
= 0.3 2L
gm 2
gm 2
77
RG = 4k
RG = 2k
RG = 0
78
Differential signals:
RG = 0
PW = 97ps
RG = 5k
PW = 100 ps
RG = 10k
PW = 104 ps
79
Single-ended
input
Single-ended
outputs
80
differential
single-ended
81