D:\test\ADAPTIVE_XY_mesh_routing.

syr
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Release 7.1i - xst H.38

Copyright (c) 1995-2005 Xilinx, Inc. All rights reserved.
--> Parameter TMPDIR set to __projnav
CPU : 0.00 / 0.19 s | Elapsed : 0.00 / 0.00 s
--> Parameter xsthdpdir set to ./xst
CPU : 0.00 / 0.19 s | Elapsed : 0.00 / 0.00 s
--> Reading design: ADAPTIVE_XY_mesh_routing.prj
TABLE OF CONTENTS
1) Synthesis Options Summary
2) HDL Compilation
3) HDL Analysis
4) HDL Synthesis
5) Advanced HDL Synthesis
5.1) HDL Synthesis Report
6) Low Level Synthesis
7) Final Report
=========================================================================
*
Synthesis Options Summary
*
=========================================================================
---- Source Parameters
Input File Name
: "ADAPTIVE_XY_mesh_routing.prj"
Input Format
: mixed
Ignore Synthesis Constraint File
: NO
---- Target Parameters
Output File Name
Output Format
Target Device

: "ADAPTIVE_XY_mesh_routing"
: NGC
: acr2

---- Source Options

Top Module Name
Automatic FSM Extraction
FSM Encoding Algorithm
Mux Extraction
Resource Sharing

:
:
:
:
:

ADAPTIVE_XY_mesh_routing
YES
Auto
YES
YES

---- Target Options

Add IO Buffers
Equivalent register Removal
MACRO Preserve
XOR Preserve

:
:
:
:

YES
YES
YES
YES

---- General Options

Optimization Goal
Optimization Effort
Keep Hierarchy
RTL Output
Hierarchy Separator
Bus Delimiter
Case Specifier

:
:
:
:
:
:
:

Speed
1
YES
Yes
/
<>
maintain

---- Other Options

lso
verilog2001
safe_implementation
Clock Enable
wysiwyg

:
:
:
:
:

ADAPTIVE_XY_mesh_routing.lso
YES
No
YES
NO

=========================================================================

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=========================================================================
*
HDL Compilation
*
=========================================================================
Compiling verilog file "ADAPTIVE_XY_mesh_routing.v"
Module <ADAPTIVE_XY_mesh_routing> compiled
No errors in compilation
Analysis of file <"ADAPTIVE_XY_mesh_routing.prj"> succeeded.
=========================================================================
*
HDL Analysis
*
=========================================================================
Analyzing top module <ADAPTIVE_XY_mesh_routing>.
PORT_NUM = 5
X_NODE_NUM = 4
Y_NODE_NUM = 4
SW_X_ADDR = 2
SW_Y_ADDR = 1
CONGESTION_WIDTH = 4
PORT_NUM_BCD_WIDTH = 3
X_NODE_NUM_WIDTH = 2
Y_NODE_NUM_WIDTH = 2
LOCAL = 0
EAST = 1
NORTH = 2
WEST = 3
SOUTH = 4
W_VS_S = 3
W_VS_N = 2
E_VS_N = 1
E_VS_S = 0
Module <ADAPTIVE_XY_mesh_routing> is correct for synthesis.
=========================================================================
*
HDL Synthesis
*
=========================================================================
Synthesizing Unit <ADAPTIVE_XY_mesh_routing>.
Related source file is "ADAPTIVE_XY_mesh_routing.v".
Found 32x3-bit ROM for signal <port_num_next>.
Found 4-bit comparator greater for signal <$n0000> created
Found 4-bit comparator less for signal <$n0001> created at
Found 4-bit comparator greater for signal <$n0002> created
Found 4-bit comparator less for signal <$n0003> created at
Found 3-bit subtractor for signal <xdiff>.
Found 3-bit subtractor for signal <ydiff>.
Summary:
inferred
1 ROM(s).
inferred
2 Adder/Subtractor(s).
inferred
4 Comparator(s).
Unit <ADAPTIVE_XY_mesh_routing> synthesized.

at line 57.
line 70.
at line 58.
line 62.

=========================================================================
*
Advanced HDL Synthesis
*
=========================================================================
Advanced RAM inference ...
Advanced multiplier inference ...
Advanced Registered AddSub inference ...
Dynamic shift register inference ...

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=========================================================================
HDL Synthesis Report
Macro Statistics
# ROMs
32x3-bit ROM
# Adders/Subtractors
3-bit subtractor
# Comparators
4-bit comparator greater
4-bit comparator less

:
:
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:
:
:
:

1
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2
4
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2

=========================================================================
=========================================================================
*
Low Level Synthesis
*
=========================================================================
Optimizing unit <ADAPTIVE_XY_mesh_routing> ...
=========================================================================
*
Final Report
*
=========================================================================
Final Results
RTL Top Level Output File Name
: ADAPTIVE_XY_mesh_routing.ngr
Top Level Output File Name
: ADAPTIVE_XY_mesh_routing
Output Format
: NGC
Optimization Goal
: Speed
Keep Hierarchy
: YES
Target Technology
: acr2
Macro Preserve
: YES
XOR Preserve
: YES
Clock Enable
: YES
wysiwyg
: NO
Design Statistics
# IOs

: 15

Macro Statistics :
# Comparators
#
4-bit comparator greater
#
4-bit comparator less
# Xors
#
1-bit xor2

:
:
:
:
:

4
2
2
10
10

Cell Usage :
# BELS
: 82
#
AND2
: 31
#
AND3
: 3
#
AND4
: 1
#
INV
: 36
#
OR2
: 11
# IO Buffers
: 13
#
IBUF
: 10
#
OBUF
: 3
=========================================================================
CPU : 2.02 / 2.22 s | Elapsed : 2.00 / 2.00 s
-->
Total memory usage is 133580 kilobytes
Number of errors
:
Number of warnings :
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Number of infos

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