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VDD
RD
C3
C1
C2 RL
vs RG
I
-VSS
Lecture 22-1
Common Source Amplifier
• Design the amplifier for maximum possible output voltage swing
VDD
RD K=0.25mA/V2
C3 Vt=2V
RS C1 VDD=10V
C2
RG=500k ( >> RS)
RL=10kΩ
λ=0.02
vs RG
I=1mA
-VSS
Lecture 22-2
Common Source Amplifier
VDD
RD
K=0.25mA/V2
C3 Vt=2volts
RS C1 VDD=10volts
RG=500k ( >> RS)
C2 RL=10kΩ
vs RG
I=1mA
-VSS
Lecture 22-3
Common Source Amplifier
• Analyze the circuit --- first solve for the dc bias point:
IC
VCC
+ 10V 1.000 mA
RD
6KΩ
M1-NMOS C1
L=10U 1UF
W=10U + -
C12 D VOUTAC VD
1UF + +
+ - S C2 0.000 pV 4.000 V
- -
1UF RL
VSSIN RG VIN + - 10KΩ
+ SIN 5E5Ω +
0.000 pV IS
-
1mA
VS
VSS +
+ -10V -3.837 V
-
Lecture 22-4
Small Signal Model
VDD
RD G D
C3
C1 vs RG RD RL
gm vs ro
C2 RL
S
vs RG
I
-VSS
Lecture 22-5
Small Signal Model
G D
vs RG gm vs ro RD RL
Lecture 22-6
ac Response
frequency
e2 e3 e4 e5 e6 e7
12
11
10
DB(VOUTAC/VIN)
Lecture 22-7
Transient Response
time
0.0 0.1 0.2 0.3 0.4 0.5 0.6 ms
1
-1
VOUTAC VIN
Lecture 22-8
Transient Response Distortion?
time
0.0 0.1 0.2 0.3 0.4 0.5 0.6 ms
1
-1
Lecture 22-9
ac Response
frequency
e2 e3 e4 e5 e6 e7
12
11
10
DB(VOUTAC/VIN)
Lecture 22-10
Improving the Gain
• Assuming that the peak ac output is less than 1.0 volt, we can use a larger
value of RD to increase the gain but still keep the transistor out of the triode
region
IC
VCC
+ 10V 1.000 mA
RD
10KΩ
M1-NMOS C1
L=10U 1UF
W=10U + -
C12 D VOUTAC VD
1UF + +
+ - S C2 0.000 pV 0.000 pV
- -
1UF RL
VSSIN RG VIN + - 10KΩ
+ SIN 5E5Ω +
0.000 pV IS
-
1mA
VS
VSS +
+ -10V -3.920 V
-
Lecture 22-11
Improving the Gain
frequency
e2 e3 e4 e5 e6 e7
14
13
12
11
10
DB(VOUTAC/VIN)
Lecture 22-12
Improving the Gain
• But further increase in RD is not possible
time
0.0 0.1 0.2 0.3 0.4 0.5 0.6 ms
1
-1
Lecture 22-13
Current Mirrors
3.3V
M1 M2
Lecture 22-14
Current Mirrors - Output Resistance
3.3V
R IREF Io
ID
M1 M2
Lecture 22-15
Current Mirrors-Accuracy
3.3V
R IREF Io
ID
M1 M2
Lecture 22-16
Current Steering
+
V SG5
M4 -
M5
3.3V
I4
R IREF I2 I5
I3
ID
M1 M2 M3
Lecture 22-17