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UPSC Engineering Services Examination

MODE

Subjectwise Test No. 4 (Conventional) : Control Systems & Digital Electronics

EXPLANATIONS
1. (a)
0/0
a
0/0

1/0
0/0
1/0
g

1/1

0/0

0/0

c
1/0
0/0

1/1
1/1
0/0

f
1/1

Considering the input sequence 01010110110 starting from the initial state a. Each input of 0 or 1 produces
an output of 0 or 1 and causes the circuit to go the next state. From the state diagram, we obtain the output
and state sequence for the given input sequence as follows. With the circuit in initial state a, an input of 0
produces an output of 0 and circuit remains in state a. With present state at a and input of 1 and the output
is 0 and the next state is b. With present state b and an input of 0, the output is 0 and the next state is c.
Continuing this process, we find the complete sequence to be as follows:
State

a a b c d

e f

g f

g a

Input

0 1 0 1 0

1 1 0

1 1 0

Output 0 0 0 0 0

1 1 0

1 1 0

In each column, we have the present state, input value and output value. The next state is written on top of
the next column.

ESE-2015 : TEST SERIES

ELECTRICAL ENGINEERING

We now proceed to reduce the number of states. Two states are said to be equivalent if, for each
member of the set of inputs, they give exactly the same output and send the circuit either to the same
state or to an equivalent state. When two states are equivalent one of them can be removed
without altering the input-output relationship.

able:
State T
Table:
Present state
a
b
c
d
e
f
g

Output
Next state
x = 0 x =1 x = 0 x = 1
a
b
0
0
c
d
0
0
a
d
0
0
e
f
0
1
a
f
0
1
g
f
0
1
a
f
0
1

Now apply the statement written above under inverted comma, we look for two present states that go
to the same next state and have the same output for both input combinations. Such states are g and e.
They both go to states a and f and have outputs of 0 and 1, for x = 0 and x = 1 respectively. Therefore
states g and e are equivalent, and one of these states can be removed. The row with present state g
is removed, and state g is replaced by state e.

Reducing State T
able:
Table:
Present state
a

Next state
Output
x = 0 x =1 x = 0 x = 1
a
b
0
0

b
c

c
a

d
d

0
0

0
0

e
f

a
e

f
f

Present state f now has next states e and f and outputs 0 and 1 for x = 0 and x = 1, respectively. The
same next states and outputs appear in the row with present state d. Therefore states f and d are
equivalent, and state f can be removed and replaced by d. The final reduced table is shown below:

able:
Reduced State T
Table:
Present state

Copyright:

Next state

Output

x =1 x = 0
b
0

x=1
0

x=0
a

b
c

c
a

d
d

0
0

0
0

The state diagram for the reduced table consists of only five states. This state diagram satisfies the
original input-output specifications and will produce the required output sequence for any given input
sequence.
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Test 4 (Conventional) : Control Systems & Digital Electronics

State

a a b c d

e d

Input

0 1 0 1 0

1 1 0

e d

1 0 0

Output 0 0 0 0 0

1 1 0

1 0 0

e a

Reduced state diagram:

0/0
a
0/0

0/0

b
1/1

0/0

1/0

1/0
1/0

0/0
d
1/1

1. (b)
Given that

f(A, B, C, D) = (0, 1, 5, 7, 10, 14, 15)

Let us implement this function using 8 : 1 multiplexer.
Let B, C, D are the select line S2, S1, S0 respectively.
So now find the inputs I0 to I7.
I0

I1

I2

I3

I4

I5

I6

I7

10

11

12

13

14

15

Now the circuit will be

I0
I1
A

I2

I3
I4

8:1
Mutiplexer

I5

I6
1

I7

S2 S1 S0
B C D

2. (a)
TTL gates
Advantages
1. It is the fastest saturating logic family. TTL gates are available in the form of high-speed, high-speed
Schottky, low-power, low-power Schottky, and a variety of other types.
2. It has good noise immunity.
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3. Power dissipation is in the miliwatt range. With low-power Schottky, this is reduced to 2mW/gate.
4. Good fan out; can drive up to 10 gates.
Disadvantages
1. Noise immunity is not very high; so it cannot be used in areas where large noise voltages prevail.
2. Power dissipation is much higher than MOS gates.
ECL gates
Advantages
1. Since transistors operate in the active region, highest speed among all logic families
Disadvantages
1. Very low noise-margin.
2. Highest power dissipation among all logic gates.
3. Capacitive loading limits fan-out.
NMOS gates
Advantage
1. Very low power dissipation (nW).
2. Large fan-out capability (20 gates).
3. Very high noise-margin. Suitable for use in industrial atmosphere.
Disadvantage
1. Large propagation delay per gate.
2. Higher power dissipation than CMOS gates.
CMOS gates
Advantages
1. Extremely large fan-out capability (> 50).
2. Lowest power dissipation of all gates (a few nano watt).
3. Very high noise-immunity and noise-margin (typically, VDD/2).
4. Lower propagation delay than NMOS.
5. Higher speed than NMOS. Currently computer chips operation at 1.5 GHz has been introduced into
open market.
Disadvantage
1. Delays are more compare to bipolar transistor logic families.
2. (b)
Excitation table of (S-R) Flip-Flop.
truth table
S R Qn +1 Q (n) Q (n + 1)
0
0 0 Qn 0

1
0 1
0 0

1
0
1 0
1

1
1 1
x 1

S
0
1
0
x

R
x
0
1
0

Design of mod-6 counter state diagram.

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Test 4 (Conventional) : Control Systems & Digital Electronics

State diagram
0
1

2
5
3
6

State transition table

Present state
0
2
3
6
5
1

Q2
0
0
0
1
1
0

Q1
0
1
1
1
0
0

next stage

Q0 Q2
0
0
0
0
1
1
0
1
1
0
1
0

Q1
1
1
1
0
0
0

Q0 S2 R2 S1 R1 S0 R0
0
0 x
1 0 0 x
1 0 x x 0 1 0
0
1 0 x 0 0
1
1 x
0 0 1 1 0
1 0
1 0 x x
0
0
0 x 0 x 0
1
R2

S2

Q1 Q0
00
Q2

01

11

10

Q1 Q0
00
Q2
x
0
1

S2 = Q1 Q0

11

10

R2 = Q1
R1

S1

Q1 Q0
00
Q2

01

11

10

Q1 Q0
00
Q2

01

11

10

S1 = Q1 Q0

R1 = Q2

S0
Q1 Q0
00
Q

R0
01

11

10

Q1 Q0
00
Q2

01

11

10

S0 = Q1 Q0

Copyright:

01

R0 = Q2 Q0

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Q0
S0 = Q1 Q0

S0

S2

S1
S-R

R0

Q2

Q1

S-R
Q0

S-R
Q1

R1

R2

Q2

CLK
Q2

Logic diagram

3. (a)

G(s)H(s) =

2(s + 0.2)
s 2 (s + 1)(s + 2)

put s = j

G(j)H(j) =

G(j )H(j ) =
and

2( j + 0.2)
2 ( j + 1)( j + 2)

2 2 + 0.22
2 2 + 12 2 + 22

tan1 tan1
0.2
1
2
= 180 + tan1 5 tan1 tan1 0.5

G(j)H(j) = 180 + tan1

= 180 + tan1

5
tan1 0.5
1 + 5.

4
2 0.5
= 180 + tan1 1+ 5
4
1+
0.5
1+ 52
1
= 180 + tan

(3.5 2.5 2 )
1 + 7 2

As 0

G(j )H(j )
and

G( j )H ( j ) 180

For the intersection of ve real axis of G(j) H(j) plane, at = 2, it is required that
G(j) H(j) = 180
(3.5 2.5 2 )
1 + 7 2
Therefore, the condition for intersection of the ve real axis is given by
G(j2) H(j2) = 180

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G(j) H(j) = 180 + tan1

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Test 4 (Conventional) : Control Systems & Digital Electronics

G(j) H(j) = 180 + tan1

tan1

2 (3.5 2.522 )
=0
1 + 7 22

(3.5 2.5 2 )
= 180
1 + 7 2

2(3.5 2.5 22) = 0

3.5
= 1.18 rad/sec.
2.5
At = 1.18 rad/sec., the magnitude is calculated below :

2 = 0, or 2 =

Hence,

G(j1.18)H(1.18) =
As

2 1.182 + 0.22
1.182 1.182 + 12 1.182 + 22

= 0.48

G(j )H(j ) 0 and G( j )H ( j ) 270

As per above calculations the shape of the Nyquist plot is shownin figure.
The given transfer function is of type 2, hence the Nyquist plot is completed from = 0 to = 0+ through
360 with radius
Imj

= 0

= +
=

= 0+
0.48

1 + j0

Re
G(j) H(j)-plane

As the critical point (1 + j0) is not encircled by the Nyquist plot and P+ (Poles at RHS) = nil, the system is
stable.
The system becomes marginally stable, if the gain is increased by a factor 1/0.48, therefore the gain
margin is
1
= 20log10 2.08 = 6.375 db
G.M. = 20log10
0.48

3. (b)
Reducing the inner loop

Gmot(s) =

10 / s
10
=
1 + 0.1 10 / s s + 1

from the forward path

10 k
(s) = s (s 1) E (s)
+

E(s) = Vr(s) (s)

10 k
E(s) = Vr (s)
E (s)
s (s + 1)

for unit ramp input

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Vr(s) =

1
s2

s (s + 1)
1
E(s) =
2
s (s + 1) + 10 k s

Steady-state error

ess = Lim s E (s) = Lim

s0

or

ess =

(s + 1)
s (s + 1) + 10 k

1
= 0.01
10k

k = 10
(s)
T (s) =
=
Vr (s)

s 0

T (s) =

10 k
s (s + 1)
10 k
1+
s (s + 1)

10k
s (s + 1) + 10 k

T
To find Sk

SkT =

T k

k T

T(s) =

10k
s (s + 1) + 10k

[{s (s + 1) + (10 k )}10 10 k (10)]

T
=
k
[s (s + 1) + 10 k ]2

s (s + 1)
T k
=

s (s + 1) + 10 k
k T
SkT =

s (s + 1)
s (s + 1) + 10 k

at k = 10
T
S10
=

s (s + 1)
s (s + 1) + 100

At low frequencies s = j, tending to zero

T = 0
S10

4. (a)
1
0
As the matrix A = 2 3 is in phase variable form, therefore,

Vandermonde matrix is used for transformation.

The eigen values of matrix A are determined below
1
s 0 0
(sI A) =
2 3 =
0
s

Copyright:

1
s
2 s + 3

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Test 4 (Conventional) : Control Systems & Digital Electronics

s

sI A = 2 s + 3 = s(s + 3) (1) (2) = s2 + 3s + 2

put
or

s2 + 3s + 2 = 0
(s + 1) (s + 2) = 0
Eigen values are 1 = 1 and 2 = 2

The Vandermonde matrix is

1 1
P=
=
1 2

1 1
1 2

The inverse of matrix P can be determined as

1 1
P1 =

1 2

2 1
=

1 1

The diagonal matrix ^ = P1 AP is determined below

1 1 1
2 1 0
1
^ = P AP = 1 1 2 3 1 2 =

e^t

e t
=
0

1 0
0 2

e 2t

The time response is given by

x(t) = L 1 (s) x(0) + L 1 (s) BU (s)
Applying convolution integral to second term of the R.H.S.
x(t) = (t) x(0) +

0 (t )Bu()dt

0
1
x(0) = 0 , B = 0 and u(t) = et


At
^
t
1
e = P e P = (t)
t
1 1 e

1 2 0

0 2 1

e 2t 1 1

2e t e 2t
=
t
2t
2e + 2e

e t e 2t

e t + 2e 2t

x(t) =

0 (t )Bu()d

2e (t ) e 2(t )
0 2e (t ) + 2e 2(t )

2e (t ) e 2(t )

0 2e (t ) + 2e 2(t ) e d =

2e t e 2t e
2e t e 2t e
d

0 2e t + 2e 2t e
2e t + 2e 2t e = 0

e (t ) e 2(t ) 1
e d
e (t ) + 2e 2(t ) 0
(2e (t ) e 2(t ) ) e
0 ( 2e (t ) + 2e 2(t ) )e d

=t

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10

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(2te t e 2t et ) (2 0 e t e 2t e 0 )

=
( 2te t + 2e 2t et ) ( 2 0 e t + 2e 2t e 0 )
2te t e t + e 2t

x(t) =
t
t
2t
2te + 2e 2e

or

4. (b)
Signal flow graph of the block diagram can be drawn easily by inspection is shown in figure.
G4

R(s)

G1

G2

H3

G3

C(s)

H2

H1

There are two forward paths having gains G1G2G3 and G4 respectively.
Loops
1. a b c d e a
G1G2G3 (H1) = G1G2G3H1
2. b c d b
G1G2 (H3) = G1G2H3
3. c d e c
G2G3 (H2) = G2G3H2
4. b e a b
G4(H1) = G4H1
5. c d b e c
G2(H3)G4 (H2) = G2G4H2H3
Non-touching Loops : Nil
Using Masons gain formula

G1G2G3 + G4
C(s)
=
1 + G1G2G3H1 + G1G2H 3 + G2G3H 2 + G4H1 G2G4H 2H 3
R(s)

we can write;

5. (a)

d 2c
dt

+8

dc
= 64 (r c)
dt

So

C(s)
64
R(s) = s2 + 8s + 64

also

n2
C(s)
= 2
R(s)
s + 2sn + n2

so

n = 8
= 0.5

%age MP = 100 e

= 100 e

Copyright:

12
0.5
1 0.52

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Test 4 (Conventional) : Control Systems & Digital Electronics

11

MP = 16.3%
d = n 1 2 = 8 1 0.25 = 8 0.75 = 6.93 rad/sec
5. (b)
Open loop transfer function G(s) H(s) =

K
s(s + 6)2

The open-loop poles are

s=0
s = 6, 6 (multiple)
The number of root locus branches N = P = 3.
The root locus branches start (k = 0) from open loop poles and terminates (k = ) at infinity (as there is no
open loop zeros).
Angle of asymptotes =

(2 k + 1) 180
, k = 0, 1, 2.
P Z

2 0 +1
180 = 60
3
2 1+ 1
180 = 180
(ii)
3
2 2 +1
(iii)
180 = 300 or 60
3

(i)

(0 6 6) (0)
Poles Zeros
=
= 4
3
P Z
The characteristic equation is 1 + G(s) = 0

Centroid =

K
=0
s(s + 6)2

K = (s3 + 12s2 + 36s)

Break away point is given by solving the equation
dK
=0
ds
dK
= (3s2 + 24s + 36)
ds

3s2 + 24s + 36 = 0

s1, s2 = 2, 6
The point s = 2 is selected as break away point as it is located between two open loop poles.
The characteristic equation is s3 + 12s2 + 36s + K = 0.
The Routh table
1+

s3
s

36

12
K

12
36
K
s1
12
s0
K
For marginal stability
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12

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12 36 K
=0
12

K = 432
The crossing point of the root locus branches on the imaginary axis is determined below:
12s2 + K = 0

12s2 + 432 = 0
s2 + 36 = 0

s = j 6
on the basis of above analysis, root-locus is drawn below
Imj

+j 6

K=0

K=0

4
2

Centroid

Re

0
Break away point
j 6

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