Limitations and Parallel-Port Interface Documentation of the HungChang DSO-2100 PC-Based Oscilloscope

A while ago I needed to do some automated data acquisition and happened to be in

possession of the DSO-2100 PC-based digital storage oscilloscope made by Hung Chang
(Seoul, Korea) and sold under brand names like Protek or Voltcraft. Unfortunately, Hung
Chang went bankrupt in 2001, and driver software that could be linked to user programs,
though advertised in the instrument brochure, had never been made available. At least
that's what I was told. I therefore had to analyze the Visual-Basic program that comes
with the instrument.
Along the way I found that the DSO 2100 differs in important respects from the
specifications stated in the instrument brochure and (until 2004) on the Hung-Chang
website, and also (until 2005) by Conrad Electronic, a German electronics chain store
where the instrument was on sale. Thus, you cannot acquire data from both inputs
simultaneously, and only 5000 data points per trigger event are made available for
uploading to the host! I felt quite annoyed when I realized this.
I also learned that, prior to the bankruptcy, a new Korean company called MITech, Inc.
had taken over the Test & Measurement Department of Hung Chang, but their engineers
preferred not to answer my technical questions. Since 2005, Hung Chang continues as
GSI Co., Inc. in Incheon, Korea, and the DSO 2100 (or Protek 2100) still receives
support on the website of their chinese subsidiary, HCQ Electronics Co., Ltd. in Qingdao.
I am herewith placing the results of my analysis on the Web. A simple test driver written
in Turbo Pascal that implements DSO-2100 control via the parallel port can be obtained
from the author and may serve as a starting point for programs of your own. Please direct
requests, as well as comments and notifications of mistakes to Clicliclic.
A friendly correspondent, Anton Zechner, from Austria has contributed an upgrade utility
(http://www.mikrocontroller.net/topic/56876) to make your DSO2100.EXE run under
Windows NT or 2K or XP. Be sure to have a German dictionary around. And don't ask
me for support on this!
Copyright 2002, 2004, 2006 by Clicliclic. All rights reserved.

0. Remarks on DSO-2100 Limitations

- the DSO 2100 must be operated on a bi-directional parallel port (with the host BIOS
configured accordingly!): only the eight data lines (pins 2-9) and the STROBE (pin 1),

(pin 14), INIT (pin 16), and SELECT-IN (pin 17) control lines are wired. Old
unidirectional ports won't do!
AUTO-FEED

- electromagnetic interference, such as electromagnetic pulses generated by switching on

the room lighting, may cause the communication between PC and DSO to hang up.
Briefly unplug the power supply of the DSO unit to recover from this.
- in contrast to what the accompanying brochure suggests ("Ch A: 100 MSa/s, Ch B: 100
MSa/s, Dual: 100 MSa/s"), the DSO unit has only one digitization channel which is
switched between the two analog input channels: capture of both inputs requires two
successive trigger events even for single-shot acquisition, resulting in non-corresponding
signals!
- data reloaded from previously stored *.dso files are vertically expanded relative to the
measured signal as originally displayed. On the other hand, data displayed during Scroll
Mode measurements are vertically contracted relative to signals measured otherwise. In
either case, the effect is dependent on the vertical offset setting!
- for each data acquisition completed, the on-board intelligence (an ADSP-2105 processor
with 8 kB OTP EPROM and a QL2003 FPGA) makes only 5000 samples available to the
host, although the digitization channel is equipped with 32+32 kB RAM. This falls far
short of a memory depth of 32 kB/Ch, as also stated in the instrument brochure!
- even though the DSO unit prepares only 5000 samples for uploading, their acquisition
takes twice as long as needed for 5000 consecutive data points. Consequently, the
maximum repetition rate of the DSO 2100 at low scan speeds is only half of what one
would expect. The inefficiency should be attributed to a bug in the DSO firmware.
- the Fourier transform for the spectrum display is based on 2^8 = 256 samples (and thus
generates only 2^7+1 = 129 data points in frequency), and there are no data windowing
options. Most unbelievably, of the 129 spectral points only 125 are actually displayed, the
21st, 64th, and 107th are skipped and the 128th is omitted! (Here, the spectral points are
numbered from zero.) You can easily uncover the frequency holes by means of a tunable
oscillator.
- digital data from the DSO unit always include 6 or 7 data points preceding the trigger
event - a pleasant surprise for a change! The trigger, however, is accepted only before
every other sample, causing a time jitter of two sampling intervals!
- at slew rates of about 3Div / 10ns, the ADC (actually two alternating HI5714s) begins to
show glitches: the lower five bits gradually fail (folding section of the converter) while
the upper three bits continue to function (subranging section of the converter). The
sparkle is easily seen when a suitable signal is heavily "undersampled", but remains
invisible in ordinary work. The behavior is in agreement with the "analog input
bandwidth" specification of the HI5714 (provided the Harris/Intersil datasheet is read
correctly - signal attenuation is comparatively unimportant here!).

- even for shorted inputs, at acquisition rates above 5 MSa/s (especially at 50 and 100
MSa/s) the data from my unit show a digital contamination of up to 0.3 Div p-p that may
at first sight be taken for analog noise. The contamination is influenced by the various
amplifier and trigger settings; obvious features are stronger isolated spikes (occasionally
up to ?0.6 Div) followed by a train of weaker equidistant (640 ns) peaks, this is
sometimes (at 50 MSa/s) accompanied by a constant signal at half the sampling
frequency.
- for open inputs there is a significant capacitive coupling from the EXT trigger signal
onto CH2 at 0.5 V/Div and 50 mV/Div, suggesting bad routing on the PCB.
- the DSO amplifiers stop drifting and recalibration becomes unnecessary only after
roughly one hour of warming-up and thermal equilibration!
- positive-slope triggering on fast signals (such as the 1 kHz calibration signal measured
with a 101 probe) is unreliable (frequent false release on negative slopes), in striking
contrast with negative-slope triggering: for rapid transitions the trigger comparator
(LM361) seems to suffer from some kind of ringing. For slow signals like a 50 Hz sine
wave, the distinction of slopes seems to be lost as well, and triggering to be bistable
without exception.
- the on-board analog calibration settings (stored in 1 F capacitors gated by an HC4051)
are not refreshed during acquisition, whence calibration drift results in a progressive (and
ultimately prohibitive) signal distortion for measurements from 50 ms/Div (10 kSa/s) to
0.5 s/Div (1 kSa/s), i.e. with acquisition times exceeding 0.5 s.
- the auto-calibration procedure quite frequently fails to terminate within reasonable time;
you may have to break and restart the process repeatedly.
- and finally, for daring fellow owners, I have prepared a description of what can be done
about some of the hardware problems (mainly trigger instability and calibration drift) of
the DSO 2100.
1. Control Sequences Employed by DSO2100.EXE
NORM-trigger acquisition without signal:
S04R0f..{R01} S02{R00}{R21} {S99{R21}}

NORM-trigger acquisition with signal:

S04R0f..{R01} S02{R00}{R21} {S99{R21}} S99{R00}{R03} {L}

AUTO-trigger acquisition:
S04R0f..{R01}
S04R0f..{R01}
S04R0f..{R01}
S04R0f..{R01}

S02{R00}{R21}
S02{R00}{R21}
S02{R00}{R21}
S02{R00}{R21}

S99{R00}{R03} {L}
S99{R21} S99{R00}{R03} {L}
S99{R21} S99{R21} S99{R00}{R03} {L}
S99{R21} S99{R21} S99{R21} Sfe{R21}

S99{R00}{R03} {L}

and so on repeating {S99.. S99.. S99.. Sfe.. S99..}

acquisition break:

.. {R21} Sff{R00}{R03} {L}

reselect readout:
S04R0f..{R01} S03{R00}{R03} {L}

scroll acquisition:

S04R0f..{R01} S04 {{R14}{L}}

scroll-acquisition break:
.. {L} Sff{R0f}..{R01} ..

Notes:
- Rxx, Sxx, and L stand for Receive Status Byte, Send Command Byte, and Load Data
Byte, respectively, where xx represents the transferred byte in hex; {} indicates
repetition. The corresponding parallel-port operations are detailed in sections 3.C, 3.D,
and 3.E, respectively.
- S02 starts a 5000-sample acquisition with selection of 500+500 readout points; S03
starts a reselection of 500+500 readout points from the previous data; S04 starts a scroll
acquisition / a new setup-parameter transfer; S99 leaves acquisition if complete; Sfe
supplies AUTO trigger; Sff breaks acquisition.
- R00 indicates On-board Processor Busy / Illegal Command; R03 indicates Acquisition
Complete / Data Ready; R14 indicates Scroll Acquisition Active (scroll acquisition timing
is determined by the host data requests!); R21 indicates Waiting for Trigger / Acquiring.
- the sequence R0f..R01 transfers setup parameters to the DSO; it is explicated in section
2.
- the LED indicator on top of the DSO unit lights up for any status but hex 03
(Acquisition Complete / Data Ready) after an acquisition; it stays on after a reselection.
- to my knowledge, the commands listed here exhaust those accepted by the DSO unit.
2. DSO-2100 Setup-Parameter Transfer
R0f
S01
R0f
S01
R05
S02
R05
S02
R08
S02
R08
S02

ready for transfer

select Acq CH1 (01,02 = CH1,CH2)
repeat
set 50 MSa/s (01,02,03,04,05 .. = 100,50,25,20,10 .. MSa/s)
repeat
readout2 step + 1 (02,03 ..,0b)
repeat

R09
S0b
R09
S0b
R06
S3b
V/Div)
R06
S3b
R07
S3b
R07
S3b
R0a
S01
R0a
S01
R0b
S02
R0b
S02
R0c
S66
R0c
S66
R0d
S5d
R0d
S5d
R0e
S80
R0e
S80
R10
Saa
R10
Saa
R11
S7c
R11
S7c
R12
S89
R12
S89
R13
Sba
R13
Sba
R01

readout1 step + 1 (02,03 ..,0b)

repeat
set CH1 AC, 5 V/Div, Trig CH1
(00,04,08 = DC,GND,AC)
(01,02,20,21,22,30,31,32,33 = 10m,20m,50m,0.1,0.2,0.5,1,2,5
(00,40,80 = Trig CH1,EXT,CH2)
repeat
set CH2 AC, 5 V/Div, Trig AC
(00,40,80 = Trig AC,TV-V,TV-H)
repeat
readout2 shift (01,02,03,04,05 .. = 0,5,10,15,20 ..)
repeat
set Trig Slope pos (01,02 = neg,pos)
repeat
Cal CH1 V-Offset + 1
repeat
Cal CH2 V-Offset + 1
repeat
Trig Level + 1
repeat
Cal CH1 Offset + 1
repeat
Cal CH1 Gain + 1
repeat
Cal CH2 Offset + 1
repeat
Cal CH2 Gain + 1
repeat
transfer done

Notes:
- the purpose of the readout1 step, readout2 step, and readout2 shift parameters is

explained in section 3.E.

- hex 03 and hex 23 are alternative codes for the 50 mV/Div and 0.5 V/Div settings; their
advantage is a reduced noise level. Change DSO2100.EXE at hex file offset 29782 from
hex 20 to hex 03 and at hex file offset 297c6 from hex 10 to hex 03 to see this.
- DSO2100.EXE seems to keep the trigger level fixed at 50% (hex 7f); the PCB is
apparently not equipped for a variable trigger level!
- the V-Offset, Offset, and Gain calibration constants are stored in the file DSO2100.INI.
- the new parameter settings become effective only with the subsequent command (S02,
S03, or S04).
3. DSO-2100 Parallel-Port Code from VKVXD.VXD
A. Initialize DSO port:
LEA
MOV
ADD
MOV
OUT
BPP

ESI, DWORD PTR [EBP+08]

EDX, DWORD PTR [ESI]
EDX, 00000402
EAX, 00000020
DX, AL

; port
; (+ 402 !)
; set ECP hardware to emulate a

B. Verify DSO connection:

LEA
MOV
ADD
MOV
OUT
OUT
OUT
OUT
OUT
OUT
MOV
OUT
LEA
MOV
IN
AND
LEA
MOV
MOV
ADD
MOV
OUT

ESI, DWORD PTR [EBP+08]

EDX, DWORD PTR [ESI]
EDX, 00000002
EAX, 00000020
DX, AL
DX, AL
DX, AL
DX, AL
DX, AL
DX, AL
EAX, 00000021
DX, AL
ESI, DWORD PTR [EBP+08]
EDX, DWORD PTR [ESI]
AL, DX
EAX, 000000FF
ESI, DWORD PTR [EBP+0C]
ESI, DWORD PTR [ESI]
DWORD PTR [ESI], EAX
EDX, 00000002
EAX, 00000020
DX, AL

; port

; STROBE+ AUTO+ INIT- SLCTIN+

;
;
;
;
;
; STROBE- AUTO+ INIT- SLCTIN+
; read status byte

; STROBE+ AUTO+ INIT- SLCTIN+

Note:
- a status of hex 55 is returned if the DSO is present.
C. Receive DSO status:

LEA
MOV
ADD
MOV
OUT
OUT
MOV
OUT
OUT
LEA
MOV
IN
AND
LEA
MOV
MOV
ADD
MOV
OUT
MOV
OUT
MOV
OUT

ESI, DWORD PTR [EBP+08]

EDX, DWORD PTR [ESI]
EDX, 00000002
EAX, 00000022
DX, AL
DX, AL
EAX, 00000023
DX, AL
DX, AL
ESI, DWORD PTR [EBP+08]
EDX, DWORD PTR [ESI]
AL, DX
EAX, 000000FF
ESI, DWORD PTR [EBP+0C]
ESI, DWORD PTR [ESI]
DWORD PTR [ESI], EAX
EDX, 00000002
EAX, 00000022
DX, AL
EAX, 00000022
DX, AL
EAX, 00000024
DX, AL

D. Send DSO command:

LEA
MOV
ADD
MOV
OUT
LEA
MOV
LEA
MOV
OUT
OUT
OUT
ADD
MOV
OUT
MOV
OUT
MOV
OUT
OUT
MOV
OUT
MOV
OUT

ESI, DWORD PTR

EDX, DWORD PTR
EDX, 00000002
EAX, 00000006
DX, AL
ESI, DWORD PTR
EDX, DWORD PTR
ESI, DWORD PTR
EAX, DWORD PTR
DX, AL
DX, AL
DX, AL
EDX, 00000002
EAX, 00000006
DX, AL
EAX, 00000007
DX, AL
EAX, 00000006
DX, AL
DX, AL
EAX, 00000026
DX, AL
EAX, 00000024
DX, AL

E. Load DSO data (CH1):

LEA
MOV
ADD
MOV
OUT

[EBP+08]
[ESI]

; port

; STROBE+ AUTO- INIT- SLCTIN+

;
; STROBE- AUTO- INIT- SLCTIN+
;
; read status byte

; STROBE+ AUTO- INIT- SLCTIN+

;
; STROBE+ AUTO+ INIT+ SLCTIN+

; port

; STROBE+ AUTO- INIT+ SLCTIN+

[EBP+08]
[ESI]
[EBP+0C]
[ESI]

ESI, DWORD PTR [EBP+08]

EDX, DWORD PTR [ESI]
EDX, 00000002
EAX, 0000002A
DX, AL

; write command byte

;
;
; STROBE+ AUTO- INIT+ SLCTIN+
; STROBE- AUTO- INIT+ SLCTIN+
; STROBE+ AUTO- INIT+ SLCTIN+
;
;
; STROBE+ AUTO+ INIT+ SLCTIN+

; port
; (28 = AUTO+ for CH2)
; STROBE+ AUTO- INIT- SLCTIN-

MOV
OUT
LEA
MOV
IN
AND
MOV
ADD
MOV
OUT
LEA
MOV
MOV

EAX, 0000002B
DX, AL
ESI, DWORD PTR [EBP+08]
EDX, DWORD PTR [ESI]
AL, DX
EAX, 000000FF
EBX, EAX
EDX, 00000002
EAX, 0000002A
DX, AL
ESI, DWORD PTR [EBP+0C]
ESI, DWORD PTR [ESI]
DWORD PTR [ESI], EBX

; (29 = AUTO+ for CH2)

; STROBE- AUTO- INIT- SLCTIN; read data byte

; (28 = AUTO+ for CH2)

; STROBE+ AUTO- INIT- SLCTIN-

Notes:
- to load CH2 data substitute hex 28/29 for hex 2a/2b.
- data after a 5000-sample acquisition for one input channel consist of 500 points selected
according to the readout1 step parameter, followed by 500 points selected according to
the readout2 step and shift parameters, followed by the bytes hex 01, hex fe, and hex 80,
followed by a repeat of points 301 through 400 from readout2.
- the original 5000 samples are available after hex 2000 bytes (8 kB); the intervening and
subsequent bytes are mostly set to a pattern of hex 00 and ff (presumably the power-on
state); the whole data repeat after hex 4000 bytes (16 kB).
- readout1 starts at the 1st point of the original data and proceeds in steps of readout1
step; readout2 starts at the original data point selected as the (n+1)th point of readout1
and proceeds in steps of readout2 step, where n is the value coded by the readout2 shift
parameter.
- data are retained in the acquisition RAM until overwritten: when acquisition /
reselection is on hold, Load Data delivers the previous data; after an acquisition break, it
delivers part new and part old data.
- during scroll acquisition, data points are loaded one at a time (scroll acquisition timing
is determined by the host data requests!); data in the acquisition RAM are not affected.
Copyright 2002, 2004, 2006 by Clicliclic. All rights reserved.

Hung-Chang DSO-2100 Hardware Faults and Remedies

In this description, electronic components of the DSO 2100 are referred to by their
designations on the oscilloscope schematic and board. You may obtain the schematic
from Conrad Electronic. (Conrad were selling the DSO 2100 across Europe, and they still
provide copies of the schematic for free - just ask them to mail you one.)
The description refers to the particulars of my board (labelled REV 2100 - 02) and the
components on it (or left out!); other boards may differ, but relevant deviations are
mentioned insofar as they were brought to my attention. In order to open the DSO-2100
unit, the "WARNING" sticker covering the fifth (the center) screw must be punched or
removed. Needless to say, the responsibility for any action regarding your DSO 2100 is
yours!
Once you have studied the description you will probably concur that the DSO-2100
hardware was insufficiently debugged, and not ready for sale. It's a shame the unit was
marketed at this immature stage. Comments and notifications of mistakes should be
directed to Clicliclic.
Copyright 2004, 2006 by Clicliclic. All rights reserved.

0. Amplifier Linearity, Rise Time, and Thermal Drift

The DSO amplifiers have the usual high-impedance FET input stage (a cascode of two
2SK161s, where the top FET operates as a source follower and the bottom FET as a
constant-current active load) followed by a HFA1130 (current-feedback amplifier) gain
block followed by a discrete differential stage where the screen offset is added (three
2N3904 jelly beans, with some massaging of the frequency response) followed by a PNP
level shifter (2N3906) and another HFA1130 gain block (unfortunately, the built-in
clipping function of the HFA1130s is not used). The amplifiers drive two parallel
HI5714/6 (=TDA8714/6) ADCs supplied with ping-pong clocking of up to 50MHz to
achieve acquisition rates of up to 100MSa/s. (The hardware would need to be modified if
you want to acquire the two channels in parallel.) Some resistors and capacitors in the
amplifiers are (?regularly) adjusted by hand soldering at the factory in order to trim the
offset (R110, R131) and gain (R12, R40) calibration ranges, as well as the frequency
response (C34, C88).
The linearity of the DSO amplifiers is good, but the gain of the differential stage depends
on the voltage level at its inverting input, which is controlled by the corresponding
vertical offset knob. This gain variation is corrected for in software: for the lowermost
knob position the full ADC data are displayed (range 0 to 255), for center setting the data
are expanded about 2.4% (displayed range 0 to 249), and for the uppermost position the
data are expanded twice as much (displayed range 0 to 243). The expansion appears to be
uniform, and the transformation therefore linear. The gain correction is taken into account

during auto-calibration, but it is omitted in Scroll Mode display; Scroll Mode signals are
therefore contracted relative to the screen markings! On the other hand, the correction is
applied to data reloaded from disk even though saved data are already transformed;
reloaded data are therefore expanded relative to the markings!
The DSO signal rise-time of the order of 10ns (10% to 90%) is primarily determined by
the discrete differential stage. It is also visibly influenced by the combined capacitance
(5+25)pF + (5+12)pF + (2*14)pF of a HC4051 trigger source selector plus a HC4052
acquisition channel selector plus the double HI5714 inputs, which are all driven by the
final HFA1130s via current-limiting resistors of 47 Ohm. As the effective capacitance
depends on the trigger source setting, the 1/e decay time of the associated exponential
tails varies noticeably, from about 4ns to about 5ns (these values assume on-resistances
around 40 Ohm for the selector switches). Without R-C damping of this order the digital
noise seen at high sampling rates (up to about 0.3 Div p-p at 100 MSa/s) would most
likely be worse; this kind of noise is strongest when the signal fluctuates across major
digital transitions, such as from binary 01111111 to 10000000 and back.
You will have noticed that the heat generated by the unit (of the order of 10W) makes the
amplifier offsets drift for an hour or so after switching on. The thermal drift is caused in
part by the FET cascodes (their contribution varies with the Volts/Div setting and may
also differ between channels) and in part by the 2N3906 level shifters (whose effect
doesn't vary and should dominate at the 5V/Div setting).
There is no simple remedy for this design weakness; the unit would have to be equipped
with drift-compensated amplifiers, or the heat kept away from them. In fact, at the
5V/Div setting, one may use the drift of the PNP level shifter to estimate the temperature
inside the unit, assuming a typical -2mV/K for the B-E junction at Ic = -2mA. (The signal
level at the shifter stage is about 40mV per screen division.) My unit reaches about 20C
above ambient temperature.
On-the-fly automatic recalibration of the offset by the DSO software (e.g. once every
minute) would be a practical way to deal with the thermal drift.
1. Trigger Comparator Instability
Almost every user must have noticed the shortcomings of the DSO trigger circuitry: in
the first place, for the typical environment with the SMPS of a PC and a CRT monitor
running nearby, it is often too sensitive to high-frequency interference spikes. (Although
one of the DAC channels used for calibration is reserved for a variable trigger level, on
my board some components necessary for this option are left out, and the Hung-Chang
operating software makes no provision for setting this channel.)
More disturbingly, the distinction between positive and negative signal slopes is
unsatisfactory even for the simple 1kHz calibration signal; it looks like the trigger

comparator U26 (LM361) suffers from internal ringing, as the unit often triggers on
negative edges when set for positive ones, and vice versa.
Watch out: the connection topology around C22, R30, R202, C87 is not properly
represented on the schematic (compare the sketch below)! The sensitivity of the trigger
comparator (i.e. its hysteresis) is about 80mV, where 200mV at the trigger stage
correspond to 1 division on the screen. Make absolutely sure your signal is free of highfrequency hidden spikes when looking into trigger stability!
..
+----------------------||-----> U36(2)
|
''C87
|
..
|
+-----||-----+
|
|
''C81 |
|
..
|
____
|
U43(3) >---|-----||-----+---|____|---+---< U26(11)
|
''C22 |
R159
|
____
|
+---|____|---+---> U26(3)
|
R30
||
| |
|_|R202
|
===
AGND

A. Fault:
The trigger stage is AC coupled, with 47nF (C94, C95) feeding 27kOhm (R202, the
schematic says 75kOhm). This high-pass with a corner frequency of 125Hz lowers the
trigger sensitivity at low frequencies (expected around 37% for a 50Hz sine wave,
measured near 25%) and introduces huge phase shifts (expected almost 70 at 50Hz).
This is intolerable as you cannot switch to a DC-coupled trigger mode.
Remedy:
Upgrade C94 and C95 to 1F 16V X7R capacitors, Murata makes them in 0805 size. (I
have also replaced C96 by a 22(?47)-Ohm resistor - the external trigger path doesn't need
two 47nF capacitors in series).
B. Fault:
C22 = 1.2 kOhm (!) introduces a kickback from the LM1881 video sync separator U36
(about 0.5mA clamping current in my case, the datasheet by National says 0.8mA typ).
Rapid negative signal transitions (as exhibited by the calibration signal measured with a
101 probe) are therefore regularly (after about 200ns delay) followed by false positive
ones whence triggering on positive slopes becomes bistable.
Remedy:
Replace C22 by a 0-Ohm connection. I have moved the free 1.2kOhm resistor to the R30

position - maybe the designer had thought about protecting the LM1881 input in this way
(note: the copper bridge between the R30 pads has to be cut for this!). I have also
changed C87 = 10n to 47n (the LM1881 datasheet recommends 100nF).
By the way, R159 = 680k supplies the input bias current (about 5A) during the
comparator-high state, thereby making the trigger level independent of the low-high ratio
(5A * 27kOhm = 135mV !).
C. Fault:
R226 = 39k was missing on my board. The trigger comparator then has only dynamic
hysteresis with tau = R201*C78 = 10s, and no static hysteresis, which prevents stable
triggering for slow signal transitions (e.g. for a 50Hz sine wave).
Remedy:
Put in R226 = 39k, as shown on the schematic. If you think about tinkering with the
trigger hysteresis, don't forget to adjust C78 too (keeping C78 / 220pF = R226 / 1kOhm)!
D. Fault:
There is no value of R158 that guarantees stable triggering on both positive and negative
signal slopes at all board temperatures. As I see it, this resistor in the positive supply line
of the trigger comparator utilizes the switching current spike boosted by C127 and C78
at output pin 9 to suppress spurious oscillations (about 25MHz) during the negative
transitions at output pin 11: sufficiently large resistor values stabilize the negative
transitions, but may also destabilize positive ones. As with the LM1881 kickback (see
under 1.B), comparator oscillation may trigger data acquisition on a wrong signal slope.
Remedy:
You have to live with unstable triggering on negative signal slopes while the unit warms
up! If the triggering on negative slopes doesn't stabilize at elevated board temperatures,
decrease R158. If triggering on positive signal slopes becomes unstable at elevated board
temperatures, increase R158 (my board has 39 Ohm dropping 460mV DC, which is
barely large enough). Moral: don't place a trigger comparator within 1cm of a supply
regulator heat sink, subjecting it to a temperature variation of about 40C.
It appears that only a small R158 = 10 Ohm was used on earlier boards labelled REV
2100 - 01, and the trigger stage stabilized instead by adding C81, in the form of two antiseries connected diodes tacked on by hand soldering and looking much like 1SS133 by
Rohm. This would make the removal of C22 = 1.2 kOhm seem unwise, but I am
informed that the diode stabilization works even with C22 shorted - regardless of board
temperature!
2. Sloping Background at Low Scan Speeds
At low acquisition rates from 10 kSa/s (50 ms/Div) down to 1 kSa/s (0.5 s/Div), i.e. for
acquisition times exceeding 0.5s, the DSO exhibits an increasingly severe downward

slope of the background without signal. I succeeded in getting rid of the slope by
replacing the quad sample-and-hold OpAmps U17 and U18 (KA324=LM324, the
schematic says MC3403, however) with CMOS types (I've used TLC27M4, the specs of
which closely resemble the LM324 specs). So, the slope is caused by the input bias
current of the KA324 (40nA typ) gradually increasing the charge of the 1F sample-andhold capacitors C99 to C106! (I had earlier suspected the HC4051 CMOS gate U23,
which is here clearly pushed beyond the specified leakage limit of 100nA at 25C,
1A at 85C - my board has a Harris chip.)
I think the ceramic chips used for the 1F capacitors are 16V types made of Y5V
material; X7R with a much smaller dC/dT should be preferred for this purpose in order to
minimize voltage fluctuations resulting from fluctuations in capacitor temperature.
The TLC274 or the TLC27L4 should also have done for U17 and U18 - it's just a tradeoff between power consumption and speed, and speed is of no importance here. The
TL064 (BiFET), the TS914 (CMOS rail-to-rail), and many more may be considered as
well.
3. Out-of-Tolerance Reference Voltage VRT
There is yet another blunder, and this one is in the VRB/VRT reference circuitry of the
DSO. These voltages are used by the two HI5714 ADCs (VRB is also used by the HI1171
DAC). According to the HI5714 datasheet, VRB must lie between 1.2V and 1.6V, and
VRT between 3.5V and 3.9V; recommended values are 1.3V and 3.6V, respectively. The
ADCs combined draw a substantial current of 20mA between VRT and VRB.
VRB = 1.3V is derived from a LM336-2.5 bandgap reference (D7) by 1.2k / 1.3k division
(R123 and R31) and OpAmp buffering. VRT = 3.9V is derived from VRB by 2k / 1k
multiplication (R178 and R124) in another OpAmp and buffering by a third. The
OpAmps used (U34) are a KA324 (=LM324) quad model, which simply isn't capable of
delivering 20mA at 3.9V from a 5V supply, nor does its input common-mode range
suffice! Indeed, I measured a VRT around 3.21V after switching on, which decreased to
about 3.16V as the unit warmed up.
Moreover, the LM336-2.5 is fed from the 5V supply via a 100-Ohm resistor (R122),
implying a bias current of 25mA. The National datasheet specifies an absolute maximum
rating of only 15mA!
The HI5714 datasheet has this statement: "VRT must be kept within the range of 3.5V to
3.9V and VRB within 1.2V to 1.6V. If the reference voltages go outside their respective
ranges, the input folding amplifiers may saturate giving erroneous digital data."
Although this doesn't really tell what the consequences of a (slightly drifting) VRT of
3.2V are, I would suggest to substitute MC33204 (bipolar rail-to-rail by ON) for U34. In
addition, R122 should be changed to 1k (2.5mA bias current), and R178 to 1.8k in order

to bring VRT down 3.64V (else there might be problems with the HFA1130 output upper
limit).
Because the buffer OpAmp U34C is not isolated from the capacitive load C175 plus
C176 (100n+100n) it is likely to oscillate when the output is no longer glued to the
positive rail; it should therefore be bypassed and VRT be taken directly from C25. The
gain calibration probably cannot absorb a change of VRT from 3.16V to 3.64V, so R12
and R40 (330 Ohm on my board) may need to be increased. Such ramifications make this
upgrade less than straightforward; its benefit is somewhat uncertain anyway.
I suspect the unreasonably high current through the LM336, the choice of a resistance
ratio corresponding to a rather high target voltage, and the extra OpAmp buffer are all the
result of an abortive attempt to raise VRT to an acceptable level.
The TS924 OpAmp (BiCMOS rail-to-rail by SGS-Thomson) might be an alternative
substitute for U34.
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