[INTERNATIONAL JOURNAL FOR RESEARCH &

DEVELOPMENT IN TECHNOLOGY]

Volume-4,Issue-2, Aug - 2015

ISSN (O) :- 2349-3585

Synthesizing of SET Based Indirect Logic Nano IC

for Pulse Train Generation
Dr. Jayanta Gope 1 , Sanjay Bhadra 2, Mahuya Panda3 ,
Tapanita Saha4 , Sreeja Mukherjee 5
145

Dept. of Electronics & Communication Engineering

23
Dept.of Electrical Engineering
Camellia School of Engineering & Technology

AbstractSETs owing to its excellent figure of merit has

the novelty of SET where a single electron or a very few

become the work horse of modern device research.

number of electron are capable enough to drive one bit of

Numerous research attempts have been made in this

information; this is not the case of existing traditional

sector. One such endeavor is being reported here in this

topologies. Eventually the same has motivated the device

short communication. The authors here have rendered its

engineers as well as the authors here to articulate the SET and

offerings in mobilizing SET to model the indirect logic

to incorporate the same in modelling the most complex Indirect

circuit and empirically studied its performance. The

Logic. The authors here would like to consider the previous

consequences are in better trade off and the effectual

works of Gope et.al [15-21].

linkage is categorically established for the post CMOS era.

The results have been obtained using SIMON2.0 simulation

tool. Lastly a comparative analysis is carried out to adjudicate

Index TermsSET, Hybrid CMOS SET, Indirect Logic, Pulse

Train Generator, SIMON 2.0

the novelty of SETs.

INDIRECT LOGIC
INTRODUCTION

Pulse trains or more conveniently repetitive series of

electronic pulses are of utmost importance in several

The pitfalls of the limitations of the downscaling of CMOS

occasions. The symbolic metaphor of pulse train has vivid

technology has been categorically studied since the last two

similarity with sequence generator which remains in

decades [1-5]. The outcome is the technological shift towards

synchronism with a clock. It is nothing but cordially prescribed

new novel nano technology. One such admiring aspirant is

sequence of logic bits. The application of such pulse train

single electron transistor technology (SET) [6-14]. It has

generators are not limited to open valves, closed gates, turn on

plentiful of offerings to the electronic industry. Incorporation of

lights, on/ off machines or obtain other controlled operations.

SET is somewhat magical in a sense that in very proximity the

These trains are generated based on either direct logic or

SET logic devices is anticipated to replace the age old

indirect logic. The discrepancy lies in the fact that in case of

conventional CMOS ICs. Straight forward comparison leads

indirect logic the output is derived directly from a Flip Flop

to unputdownable triumphs of SET; it includes robustness, high

(FF) whereas in indirect logic the same is obtained from a

integration density, low power consumption and dissipation,

decoder gate. Presently as the authors here have limited

simplicity and last but not least is sophistication. Presently,

themselves in the embracement of indirect logic milieu

SET is the driving force to build next generation ultra-dense

henceforth, the advantages of the indirect logic has been

nano digital ICs. Logical synthesis using SET is the new

catered in this short communication. One significant advantage

paradigm of device research. The fundamental lies in

in generating a pulse train using indirect logic is that any

www.ijrdt.org | copyright 2014, All Rights Reserved.

Volume-4,Issue-2, Aug-2015
ISSN (O) :- 2349-3585

Paper Title:- Synthesizing of SET Based Indirect Logic Nano IC for Pulse Train

Generation

counter (i.e. ripple/synchronous) with the correct number of

states can design the generator. Thus, it is always prevalent that
the number of FFs required if is n then it has to be always in
N 2n. These gates detect the proper states if only logic 1 is the
output. The same is largely included for multiple outputs as
well as multiple output minimization only to reduce the logic.
The conceptual ideology of the above said indirect logic based
pulse train generator is depicted in the block diagram as shown
in Fig.1. The authors here extend their capacity to design and
model the same pulse train generator using indirect logic by

CONCLUSION
The design parameters of the proposed SET indirect logic nano
IC mimics the outstanding novelty of electron tunneling in SET
device research. It is the ultimate form of device research as the
device engineers as depicted in this short communication is
able to manipulate electron in a confined metal granule as
shown in Fig.2. Thus the relevance of the proposed model is
noteworthy. Besides the author would like to enlighten the
other blooming effectual linkages in designing high speed nano
ICs using the same SET indirect logic nano IC.

incorporating SET only to replace its conventional counterpart.

The model has been enumerated in Fig.2.

TEST BENCH ANALYTICAL STUDY OF SET MADE

INDIRECT LOGIC NANO IC

ACKNOWLEDGMENT
Dr. Jayanta Gope thankfully acknowledges the financial
contribution provided by the Director of Camellia School of

The authors here sincerely attributed the electron tunneling

Engineering and Technology to undertake this research work in

phenomena in co designing all the essential elements of the

Nano Device Simulation Lab.

nano IC using SIMON 2.0. Then after the entire model was
simulated piecewise for 10 attempts. Then after the results

REFERENCES

were compared to find its best equivalent match with its

[1]. David J. Frank, Yuan Taur, Design considerations for

traditional counterpart. Later on the authors adhered in using

CMOS near the limits of scaling, Solid-State Electronics,

pulse in a given manner to testify the modus operandi of the

Volume 46, Issue 3, March 2002, Pages 315320.

new SET made indirect logic nano IC.

The pulse train to be generated was considered as i) 100111000
and ii)) 11111100 these are required to be fetched into the
inputs of the first section of Fig.2. Thus 8 unique states are
required to generate 2 pulse trains in the combination of 01 00
11 000 and 0 11 11 11 00 in situ to the earlier (i) and (ii).
Furthermore a mod 8 which is nothing but a SET 3 bit ripple
counter is used in connection to the two subsequent sections
besides the abovementioned (Fig.2) left most section of the
circuit. The F1 and F2 are the outputs of the modelled nano IC.
F1 and F2 is capable enough to produce the pulse trains 01 00

[2]. Y. Taur, CMOS design near the limit of scaling, IBM J.

RES. & DEV. VOL. 46 NO. 2/3 MARCH/MAY 2002.
[3]. "Report on Penryn Series Improvements." (PDF). Intel.
October 2006.
[4]. David J. Frank, The Limits of CMOS Scaling from a
Power-

Constrained

Technology

Optimization

Perspective," https://nanohub.org/resources/1883., 2006

[5]. W. HAENSCH ET AL, Silicon CMOS devices beyond
scaling, IBM J. RES. & DEV. VOL. 50 NO. 4/5
JULY/SEPTEMBER 2006.

11 000 and 0 11 11 11 00 as shown in Fig.3.Thus the authors

[6]. K. K. Likharev : IBM J. Res. Devel., vol 32 , 144 , 1988.

hereby propagate their previous propositions and empirically

[7]. P. Hadley, G. Lientschnig, and M. Lai, Single-Electron

demonstrate the satisfactory and successful implementation of

SET indirect logic nano IC.

Transistors, pp. 18.

[8]. Liu, R.S. ; Pettersson, H. ; Suyatin, D. ; Michalak, L. ;
Canali, C.M. ; Samuelson, L., Nanoscaled ferromagnetic
single-electron transistors, 7th IEEE Conference on
Nanotechnology, 2007. IEEE-NANO 2007.

www.ijrdt.org | copyright 2014, All Rights Reserved.

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Volume-4,Issue-2, Aug-2015
ISSN (O) :- 2349-3585

Paper Title:- Synthesizing of SET Based Indirect Logic Nano IC for Pulse Train

Generation

[9]. Daw Don Cheam ; Karre, P.S.K. ; Palard, M. ; Bergstrom

[18].

J. Gope et.al., Single Electron Transistor Technology

P.L., Mass Production of Room Temperature Single

Based On-Chip Implementation Of Smoke Detection

Electron Transistors using Step & Flash Imprint

Alarm For Residential Security Application, IJRET:

Lithography

International Journal of Research in Engineering and

and

Lift-Off

Technique,

8th

IEEE

Conference on nanotechnology,2008. NANO '08.

[10].

Technology, Volume: 03 Issue: 04 , Apr-2014, pp- 205-

Degawa, K. ; Aoki, T. ; Higuchi, T. ; Inokawa, H. ;

Takahashi, Yasuo, A single-electron-transistor logic gate

209.
[19].

J. Gope et.al., Advanced and Secured Rijndael

family and its application - Part I: basic components for

Hardware Realization Using Single Electron Transistor

binary, multiple-valued and mixed-mode logic, 34th

Technology, International Journal of Emerging Research

International Symposium on Multiple-Valued Logic,

in Management & Technology, Volume-3, Issue-5, MAY-

2004.

2014, pp -182-188.

[11].

Casper Lageweg et al Single-electron encoded

[20].

J. Gope, Single Electron Transistor based Hardware

latches and flip-flops IEEE trans. On nanotechnology,

designing of Linear Block Coding Technique for Error

vol.3, no.2, June 2004

Correction

in

Digital

Communication

System,

B. H. Lee and Y. H. Jeong, A Novel SET/MOSFET

INTERNATIONAL JOURNAL OF ENGINEERING

Hybrid Static Memory Cell Design, IEEE Trans. On Nano

SCIENCES & RESEARCH TECHNOLOGY, vol: 3(6):

technol.,vol. 3, no. 3, pp. 377-382, 2004.

June, 2014, pp-382-388.

[12].

[13].

K. Navi, M. J. Sharifi, D. Bahrepour and M.

[21].

J. Gope, A Novel Designing of Controlled Buffer

Yaghoubi, High Speed Saturating Counter based on

Register using Single Electron Transistor Modelling,

Single Electron Device,12th Computer Society of Iran

International Journal of Advanced Research in Computer

(CSI) Computer Conference, March, 2007.

Science & Technology (IJARCST 2014), Vol. 2, Issue 2,

[14].

G. L. Bilbro, W. E. Snyder, S. J. Garnier, J. W. Gautt:

Ver. 2 (April - June 2014), pp-312-316.

IEEE Trans. Neural Networks 3(1), 131 (1992)

[15].

Jayanta

Gope,

et.al.,

Logic

Synthesis

of

Contemporary European Model Traffic Control Signaling

System Using Novel Nano Scaled Single Electron
Tunneling Technology The International Journal Of
Science & Technoledge, Vol 2 Issue 4, 2014.
[16].

Jayanta Gopeet.al., Single Electron Transistor Based

IC Architecture Design for Car Intrusion Prevention: A

Case

Study

RESEARCH

INTERNATIONL

JOURNAL

FOR

IN

SCIENCE

AND

APPLIED

ENGINEERING TECHNOLOGY (I J R A S E T), Vol. 2

Issue IV, April 2014.
[17].

J.

Gope

et.al.,

Single

Electron

Tunneling

Technology based Level Sensitive SR Latch Circuit for

Next Generation Novel Bios Architecture IRACST
Engineering Science and Technology: An International
Journal (ESTIJ), Vol.4, No. 2, April 2014, pp-83-88.

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Volume-4,Issue-2, Aug-2015
ISSN (O) :- 2349-3585

Paper Title:- Synthesizing of SET Based Indirect Logic Nano IC for Pulse Train

Generation

Fig.1: Block diagram of Indirect Logic based Pulse Train Generator

Fig.2: SET based architecture of Indirect Logic nano IC

Fig.3: Simulated results obtained from SET Indirect Logic nano IC

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