Digital Design

Lecture 11

Latches and Flip Flop

Dr. PO Kimtho
Department of Computer Sciences
Norton University (NU)

Topic Outlines
Latches & Flip-Flops

Differences between Latches and FlipFlops

Types of Latches and Flip-Flops
Edge-Triggered Flip-Flops
Flip-Flop Operating Characteristics

Introduction
Latches and flip-flops are the basic single-bit memory
elements used to build sequential circuit with one or
two inputs/outputs, designed using individual logic
gates and feedback loops.

Latches & Flip-Flops

Differences between Latches and Flip-Flops
Latches
The output of a latch depends on its current inputs and on its
previous output and its change of state can happen at any time
when its inputs change.

Flip-Flops
The output of a flip-flop also depends on current inputs and its
previous output but the change of state occurs at specific times
determined by a clock input.

Latches & Flip-Flops

Types of Latches and Flip-Flops
Latches

S-R (SET-RESET) Latch

Gated S-R Latch
Gated D-Latch

Flip-Flops

Edge-Triggered S-R Flip-Flop

Edge-Triggered D Flip-Flop
Edge-Triggered J-K Flip-Flop

Latches
Type of temporary storage device that has 2 stable (bistable) states
Similar to flip-flop the outputs are connected back to
opposite inputs
Main difference from flip-flop is the method used for
changing their state
Types:
S-R latch, Gated/Enabled S-R latch and Gated D latch

Latches
S-R (SET-RESET) Latch

Active-HIGH input S-R Latch

Active-LOW input S-R Latch

Latches
S-R Latch
Logic symbols

Latches
S-R Latch

Negative-OR equivalent of the NAND gate S-R latch

Latches
S-R Latch

Truth table for an active-LOW input S-R latch

Question:

What is the truth table for an active-HIGH input S-R latch?

S-R Latch
The three
modes of
basic latch
operation
SET
RESET
no-change
&
the invalid
condition

Latches
S-R Latch Waveforms
Assume that Q is initially LOW

Latches
Gated S-R Latch
A gate input is added to the S-R latch to make
the latch synchronous.
In order for the set and reset inputs to change
the latch, the gate input must be active
(HIGH/Enable).
When the gate input is low, the latch remains in
the hold condition.

Latches
Gated S-R Latch

Latches
Gated S-R Latch Truth-table
S

Comment

Hold

Hold

Hold

Hold

Hold

Set

Reset

Not allowed

Latches
Gated S-R Latch Waveform

Latches
Gated S-R Latch Waveform

set

reset

set

reset

set

Latches
Gated S-R Latch Application

S-R latch is used to eliminate switch contact bounce

Latches
Gated D Latch (74LS75)

The D (data) latch has a single input that is used to set and
to reset the flip-flop.
When the gate is high, the Q output will follow the D input.
When the gate is low, the Q output will hold.

Latches
Gated D Latch (74LS75)

Latches
Gated D Latch (74LS75) Waveform

The output follows the input when the gate is high but is in a
hold when the gate is low.

Flip-Flops
Flip-flops are synchronous devices
Synchronous means that the output changes state only
at a specified point on the triggering input called the
clock (CLK)
An edge-triggered flip-flop changes state either at the
positive edge (rising edge) or at the negative edge
(falling edge)
Three types of edge-triggered flip-flops:
S-R Flip-Flops
D Flip-Flops
J-K Flip-Flops

Flip-Flops
Edge-triggered flip-flop logic

Positive
edgetriggered

Negative
edgetriggered
(bubble at C
input)

Flip-Flops
Clock signals and synchronous sequential circuits
1

Clock signal
0

Clock Cycle
Time
Rising edges of
the clock

(Positive-edge
triggered)

Falling edges
of the clock
(Negative-edge
triggered)

A clock signal is a periodic square wave that indefinitely

switches values from 0 to 1 and 1 to 0 at fixed intervals.

Flip-Flops
Edge-triggered S-R Flip-Flop

The basic of S-R flip-flop consist of 2 NOR gates

with the outputs cross-coupled to the inputs

Cross-NOR S-R Flip-Flop

Flip-Flops

Edge-triggered
S-R Flip-Flop
Note: Flip-flop cannot change
state except on the triggering
edge of a clock pulse.
When S=R=1, invalid condition
exists

Flip-Flops
Edge-triggered S-R Flip-Flop (+ve edge)
INPUTS
S

OUTPUTS
CLK

COMMENTS

Q0

Q0

No change
(Hold
condition)

RESET

SET

Invalid

= clock transition LOW to HIGH

X = irrelevant (dont care)
Q0 = output level prior to clock transition

-ve edge?

Flip-Flops
Edge-triggered D Flip-Flop
Addition of an inverter to an S-R flip-flop creates a basic
D flip-flop

QUESTION:
What is the
condition of
this S-R flipflop?

A positive-edge triggered D
flip-flop

Flip-Flops
Edge-triggered D Flip-Flop (Function of +ve e-t)

SET
If there is a HIGH on the D input when a clock pulse is
applied, the flip-flop will SET and the HIGH on the D input
is stored by the flip-flop on the positive-going edge of the
clock pulse (In the SET state, flip-flop is storing 1)
RESET
If there is a LOW on the D input when a clock pulse is
applied, the flip-flop will RESET and the LOW on the D
input is stored by the flip-flop on the positive-going edge
of the clock pulse (In the RESET state, flip-flop is storing
0)

Flip-Flops
Edge-triggered D Flip-Flop (+ve e-t)
Truth Table
INPUTS

OUTPUTS

COMMENTS

CLK

SET
(stores a 1)

RESET
(stores a 0)

= clock transition LOW to HIGH

Flip-Flops
Edge-triggered J-K Flip-Flop
Function of J-K Flip Flop is identical to that of the S-R
flip flop in the SET, RESET and no-change conditions of
operation
The difference is that the J-K flip-flop has no invalid
states as does the S-R flip-flop

On each successive clock spike, the flip-flop changes to

the opposite state. This mode is called toggle operation

Flip-Flops
Edge-triggered J-K Flip-Flop

Simplified logic diagram for a positive edge-triggered J-K

flip flop

Flip-Flops
Edge-triggered J-K Flip-Flop
Truth Table for positive edge-triggered J-K flip-flop

INPUTS

OUTPUTS

COMMENTS

CLK

Q0

Q0

No change

RESET

SET

Q0

Toggle
(Opposite
state)

Q0

= clock transition LOW to HIGH

Q0 = output level prior to clock transition

Flip-Flops Operating Characteristics

Propagation delay time

Define as the interval of time required after an input

signal has been applied for the resulting output change
to occur

tPLH
Propagation delay tPLH as measured from the triggering edge
of the clock pulse to the LOW-to-HIGH transition of the output

Flip-Flops Operating Characteristics

Propagation delay time

tPHL
Propagation delay tPHL as measured from the triggering edge
of the clock pulse to the HIGH-to-LOW transition of the output

Flip-Flops Operating Characteristics

Set-up time (ts)
Define as the minimum interval required for the logic
levels to be maintained constantly on the inputs (J and K,
or S and R, or D) prior to the triggering edge of the clock
pulse in order for the levels to be reliably clocked into the
flip-flop

Flip-Flops Operating Characteristics

Hold time (th)
Define as the minimum interval required for the logic
levels to remain on the inputs after the triggering edge of
the clock pulse in order for the levels to be reliably
clocked into the flip-flop

Flip-Flops Operating Characteristics

Maximum Clock Frequency (fmax)

The highest rate at which a flip-flop can be
reliably triggered.
At clock frequencies above the maximum, the
flip-flop would be unable to respond quickly
enough, and its operation would be impaired
Power dissipation
P = Vcc x Icc