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DATA SHEET
74AHC125; 74AHCT125
Quad buffer/line driver; 3-state
Product specification
Supersedes data of 1999 Jan 11
File under Integrated Circuits, IC06
1999 Sep 27
Philips Semiconductors
Product specification
74AHC125; 74AHCT125
PARAMETER
CONDITIONS
UNIT
AHC
AHCT
tPHL/tPLH
propagation delay
nA to nY
CL = 15 pF;
VCC = 5 V
3.0
3.0
ns
VI = VCC or GND
3.0
3.0
pF
4.0
4.0
pF
10
12
pF
CI
input capacitance
CO
output capacitance
CPD
power dissipation
capacitance
CL = 50 pF;
f = 1 MHz;
notes 1 and 2
Notes
1. CPD is used to determine the dynamic power dissipation (PD in W).
PD = CPD VCC2 fi + (CL VCC2 fo) where:
fi = input frequency in MHz;
fo = output frequency in MHz;
(CL VCC2 fo) = sum of outputs;
CL = output load capacitance in pF;
DESCRIPTION
The 74AHC/AHCT125 are
high-speed Si-gate CMOS devices
and are pin compatible with low
power Schottky TTL (LSTTL). They
are specified in compliance with
JEDEC standard No. 7A.
The 74AHC/AHCT125 are four
non-inverting buffer/line drivers with
3-state outputs. The 3-state outputs
(nY) are controlled by the output
enable input (nOE). A HIGH at n
causes the outputs to assume a
HIGH-impedance OFF-state.
The 125 is identical to the 126 but
has active LOW enable inputs.
nA
nY
Note
1. H = HIGH voltage level;
L = LOW voltage level;
X = dont care;
Z = high-impedance OFF-state.
1999 Sep 27
OUTPUT
Philips Semiconductors
Product specification
74AHC125; 74AHCT125
ORDERING INFORMATION
OUTSIDE NORTH
AMERICA
PACKAGES
NORTH AMERICA
PINS
PACKAGE
MATERIAL
CODE
74AHC125D
74AHC125D
14
SO
plastic
SOT108-1
74AHC125PW
74AHC125PW DH
14
TSSOP
plastic
SOT402-1
74AHCT125D
74AHCT125D
14
SO
plastic
SOT108-1
74AHCT125PW
7AHCT125PW DH
14
TSSOP
plastic
SOT402-1
PINNING
PIN
SYMBOL
DESCRIPTION
1, 4, 10 and 13
1OE to 4OE
2, 5, 9 and 12
1A to 4A
data inputs
3, 6, 8 and 11
1Y to 4A
data outputs
GND
ground (0 V)
14
VCC
DC supply voltage
1999 Sep 27
Philips Semiconductors
Product specification
1OE
14 VCC
1A
13 4OE
1Y
12 4A
2OE
11 4Y
2A
10 3OE
2Y
GND
8 3Y
74AHC125; 74AHCT125
handbook, halfpage
nY
nA
125
nOE
MNA227
3A
MNA226
handbook, halfpage
1A
1Y
3
handbook, halfpage
1OE
2A
2OE
3A
2
1
2Y
EN1
5
6
4
3Y
9
8
10
3OE
12
4A
13
4OE
10
4Y
12
11
11
13
MNA229
MNA228
1999 Sep 27
Philips Semiconductors
Product specification
74AHC125; 74AHCT125
PARAMETER
74AHCT
CONDITIONS
UNIT
MIN.
TYP. MAX.
4.5
5.0
5.5
VCC
DC supply voltage
2.0
5.0
5.5
VI
input voltage
5.5
5.5
VO
output voltage
VCC
VCC
Tamb
40
+25
+85
40
+25
+85
40
+25
+125 40
+25
+125 C
see DC and AC
characteristics per
device
100
VCC = 5 V 0.5 V
20
20
ns/V
LIMITING VALUES
In accordance with the Absolute Maximum Rating System (IEC 134); voltages are referenced to GND (ground = 0 V).
SYMBOL
PARAMETER
CONDITIONS
VCC
DC supply voltage
0.5
+7.0
VI
0.5
+7.0
IIK
20
mA
IOK
20
mA
IO
25
mA
ICC
75
mA
Tstg
PD
65
+150 C
500
Notes
1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. For SO packages: above 70 C the value of PD derates linearly with 8 mW/K.
For TSSOP packages: above 60 C the value of PD derates linearly with 5.5 mW/K.
1999 Sep 27
mW
Philips Semiconductors
Product specification
74AHC125; 74AHCT125
DC CHARACTERISTICS
74AHC family
Over recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Tamb (C)
TEST CONDITIONS
SYMBOL
OTHER
VIH
VIL
VOH
VOL
40 to +85
25
PARAMETER
HIGH-level input
voltage
LOW-level input
voltage
VCC (V)
40 to +125 UNIT
MIN.
TYP.
2.0
1.5
1.5
1.5
3.0
2.1
2.1
2.1
5.5
3.85
3.85
3.85
2.0
0.5
0.5
0.5
3.0
0.9
0.9
0.9
5.5
1.65
1.65
1.65
2.0
1.9
2.0
1.9
1.9
3.0
2.9
3.0
2.9
2.9
4.5
4.4
4.5
4.4
4.4
HIGH-level output
voltage; all
outputs
VI = VIH or VIL;
IO = 50 A
HIGH-level output
voltage
VI = VIH or VIL;
IO = 4.0 mA
3.0
2.58
2.48
2.40
VI = VIH or VIL;
IO = 8.0 mA
4.5
3.94
3.8
3.70
LOW-level output
voltage; all
outputs
VI = VIH or VIL;
IO = 50 A
2.0
0.1
0.1
0.1
3.0
0.1
0.1
0.1
4.5
0.1
0.1
0.1
LOW-level output
voltage
VI = VIH or VIL;
IO = 4 mA
3.0
0.36
0.44
0.55
VI = VIH or VIL;
IO = 8 mA
4.5
0.36
0.44
0.55
1.0
2.0
2.5
10.0 A
II
input leakage
current
VI = VCC or GND
5.5
0.1
IOZ
3-state output
OFF current
VI = VIH or VIL;
5.5
VO = VCC or GND
0.25
ICC
quiescent supply
current
VI = VCC or GND;
IO = 0
5.5
2.0
20
40
CI
input capacitance
10
10
10
pF
1999 Sep 27
Philips Semiconductors
Product specification
74AHC125; 74AHCT125
74AHCT family
Over recommended operating conditions; voltages are referenced to GND (ground = 0 V).
TEST CONDITIONS
SYMBOL
Tamb (C)
PARAMETER
40 to +85
25
OTHER
VCC (V)
40 to +125 UNIT
VIH
HIGH-level input
voltage
2.0
2.0
VIL
LOW-level input
voltage
4.5 to 5.5
0.8
0.8
0.8
VOH
4.5
4.4
4.5
4.4
4.4
HIGH-level output
voltage
VI = VIH or VIL;
IO = 8.0 mA
4.5
3.94
3.8
3.70
4.5
0.1
0.1
0.1
LOW-level output
voltage
VI = VIH or VIL;
IO = 8 mA
4.5
0.36
0.44
0.55
II
input leakage
current
VI = VIH or VIL
5.5
0.1
1.0
2.0
IOZ
3-state output
OFF current
VI = VIH or VIL;
5.5
VO = VCC or GND
per input pin;
other inputs at
VCC or GND;
IO = 0
0.25
2.5
10.0 A
ICC
quiescent supply
current
2.0
20
40
ICC
additional
quiescent supply
current per input
pin
VI = VCC 2.1 V
other inputs at
VCC or GND;
IO = 0
4.5 to 5.5
1.35
1.5
1.5
mA
CI
input capacitance
10
10
10
pF
VOL
1999 Sep 27
Philips Semiconductors
Product specification
74AHC125; 74AHCT125
AC CHARACTERISTICS
Type 74AHC125
GND = 0 V; tr = tf 3.0 ns.
TEST CONDITIONS
SYMBOL
Tamb (C)
PARAMETER
40 to +85
25
WAVEFORMS
CL
MIN.
40 to +125
TYP.
MIN.
MAX.
UNIT
propagation delay
nA to nY
4.4
8.0
1.0
9.5
1.0
11.5
ns
tPZH/tPZL
propagation delay
nOE to nY
4.7
8.0
1.0
9.5
1.0
11.5
ns
tPHZ/tPLZ
propagation delay
nOE to nY
6.7
9.7
1.0
11.5
1.0
12.5
ns
tPHL/tPLH
propagation delay
nA to nY
6.2
11.5
1.0
13.0
1.0
14.5
ns
tPZH/tPZL
propagation delay
nOE to nY
6.8
11.5
1.0
13.0
1.0
14.5
ns
tPHZ/tPLZ
propagation delay
nOE to nY
9.6
13.2
1.0
15.0
1.0
16.5
ns
propagation delay
nA to nY
3.0
5.5
1.0
6.5
1.0
7.0
ns
tPZH/tPZL
propagation delay
nOE to nY
3.3
5.1
1.0
6.0
1.0
6.5
ns
tPHZ/tPLZ
propagation delay
nOE to nY
4.8
6.8
1.0
8.0
1.0
8.5
ns
tPHL/tPLH
propagation delay
nA to nY
4.3
7.5
1.0
8.5
1.0
9.5
ns
tPZH/tPZL
propagation delay
nOE to nY
4.7
7.1
1.0
8.0
1.0
9.0
ns
tPHZ/tPLZ
propagation delay
nOE to nY
6.8
8.8
1.0
10.0
1.0
11.0
ns
Notes
1. Typical values at VCC = 3.3 V.
2. Typical values at VCC = 5.0 V.
1999 Sep 27
Philips Semiconductors
Product specification
74AHC125; 74AHCT125
Type 74AHCT125
GND = 0 V; tr = tf 3.0 ns.
Tamb (C)
TEST CONDITIONS
SYMBOL
40 to +85
25
PARAMETER
WAVEFORMS
CL
MIN.
40 to +125
TYP.
MIN.
MAX.
UNIT
propagation delay
nA to nY
3.0
5.5
1.0
6.5
1.0
7.0
ns
tPZH/tPZL
propagation delay
nOE to nY
3.4
5.1
1.0
6.0
1.0
6.5
ns
tPHZ/tPLZ
propagation delay
nOE to nY
4.5
6.8
1.0
8.0
1.0
8.5
ns
tPHL/tPLH
propagation delay
nA to nY
4.3
7.5
1.0
8.5
1.0
9.5
ns
tPZH/tPZL
propagation delay
nOE to nY
4.9
7.3
1.0
8.3
1.0
9.5
ns
tPHZ/tPLZ
propagation delay
nOE to nY
6.5
8.8
1.0
10.0
1.0
11.0
ns
Note
1. Typical values at VCC = 5.0 V.
AC WAVEFORMS
VI
handbook, halfpage
VM(1)
nA INPUT
GND
tPHL
tPLH
VOH
VM(1)
nY OUTPUT
VOL
FAMILY
VI INPUT
REQUIREMENTS
VM(1)
INPUT
MNA230
VM(1)
OUTPUT
AHC
GND to VCC
50% VCC
50% VCC
AHCT
GND to 3.0 V
1.5 V
50% VCC
1999 Sep 27
Philips Semiconductors
Product specification
74AHC125; 74AHCT125
VI
VM(1)
nOE INPUT
GND
tPLZ
OUTPUT
LOW-to-OFF
OFF-to-LOW
tPZL
VCC
VM(1)
VOL +0.3 V
VOL
tPHZ
tPZH
VOH
VOH 0.3 V
OUTPUT
HIGH-to-OFF
OFF-to-HIGH
VM(1)
GND
outputs
enabled
outputs
enabled
outputs
disabled
MNA231
VI INPUT
REQUIREMENTS
FAMILY
VM(1)
INPUT
VM(1)
OUTPUT
AHC
GND to VCC
50% VCC
50% VCC
AHCT
GND to 3.0 V
1.5 V
50% VCC
S1
VCC
PULSE
GENERATOR
VI
RL =
1000
VO
D.U.T.
CL
RT
MNA232
TEST
S1
tPLH/tPHL
open
tPLZ/tPZL
VCC
tPHZ/tPZH
GND
Fig.7 Load circuitry for switching times.
1999 Sep 27
10
VCC
open
GND
Philips Semiconductors
Product specification
74AHC125; 74AHCT125
PACKAGE OUTLINES
SO14: plastic small outline package; 14 leads; body width 3.9 mm
SOT108-1
A
X
c
y
HE
v M A
Z
8
14
Q
A2
(A 3)
A1
pin 1 index
Lp
1
7
e
detail X
w M
bp
2.5
5 mm
scale
DIMENSIONS (inch dimensions are derived from the original mm dimensions)
UNIT
A
max.
A1
A2
A3
bp
D (1)
E (1)
HE
Lp
Z (1)
mm
1.75
0.25
0.10
1.45
1.25
0.25
0.49
0.36
0.25
0.19
8.75
8.55
4.0
3.8
1.27
6.2
5.8
1.05
1.0
0.4
0.7
0.6
0.25
0.25
0.1
0.7
0.3
0.010 0.057
0.004 0.049
0.01
0.16
0.15
0.050
0.028
0.024
0.01
0.01
0.004
0.028
0.012
inches 0.069
0.244
0.039
0.041
0.228
0.016
Note
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
REFERENCES
OUTLINE
VERSION
IEC
JEDEC
SOT108-1
076E06S
MS-012AB
1999 Sep 27
EIAJ
EUROPEAN
PROJECTION
ISSUE DATE
95-01-23
97-05-22
11
8
0o
Philips Semiconductors
Product specification
74AHC125; 74AHCT125
TSSOP14: plastic thin shrink small outline package; 14 leads; body width 4.4 mm
SOT402-1
c
y
HE
v M A
14
Q
(A 3)
A2
A1
pin 1 index
Lp
L
7
e
detail X
w M
bp
2.5
5 mm
scale
DIMENSIONS (mm are the original dimensions)
UNIT
A
max.
A1
A2
A3
bp
D (1)
E (2)
HE
Lp
Z (1)
mm
1.10
0.15
0.05
0.95
0.80
0.25
0.30
0.19
0.2
0.1
5.1
4.9
4.5
4.3
0.65
6.6
6.2
1.0
0.75
0.50
0.4
0.3
0.2
0.13
0.1
0.72
0.38
8
0o
Notes
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
2. Plastic interlead protrusions of 0.25 mm maximum per side are not included.
OUTLINE
VERSION
SOT402-1
1999 Sep 27
REFERENCES
IEC
JEDEC
EIAJ
EUROPEAN
PROJECTION
ISSUE DATE
94-07-12
95-04-04
MO-153
12
Philips Semiconductors
Product specification
74AHC125; 74AHCT125
Use a double-wave soldering method comprising a
turbulent wave with high upward pressure followed by a
smooth laminar wave.
SOLDERING
Introduction to soldering surface mount packages
This text gives a very brief insight to a complex technology.
A more in-depth account of soldering ICs can be found in
our Data Handbook IC26; Integrated Circuit Packages
(document order number 9398 652 90011).
Reflow soldering
Reflow soldering requires solder paste (a suspension of
fine solder particles, flux and binding agent) to be applied
to the printed-circuit board by screen printing, stencilling or
pressure-syringe dispensing before package placement.
Manual soldering
Fix the component by first soldering two
diagonally-opposite end leads. Use a low voltage (24 V or
less) soldering iron applied to the flat part of the lead.
Contact time must be limited to 10 seconds at up to
300 C.
Wave soldering
Conventional single wave soldering is not recommended
for surface mount devices (SMDs) or printed-circuit boards
with a high component density, as solder bridging and
non-wetting can present major problems.
1999 Sep 27
13
Philips Semiconductors
Product specification
74AHC125; 74AHCT125
Suitability of surface mount IC packages for wave and reflow soldering methods
SOLDERING METHOD
PACKAGE
REFLOW(1)
WAVE
BGA, LFBGA, SQFP, TFBGA
not suitable
suitable(2)
not
suitable
suitable
suitable
suitable
not
recommended(3)(4)
suitable
not
recommended(5)
suitable
Notes
1. All surface mount (SMD) packages are moisture sensitive. Depending upon the moisture content, the maximum
temperature (with respect to time) and body size of the package, there is a risk that internal or external package
cracks may occur due to vaporization of the moisture in them (the so called popcorn effect). For details, refer to the
Drypack information in the Data Handbook IC26; Integrated Circuit Packages; Section: Packing Methods.
2. These packages are not suitable for wave soldering as a solder joint between the printed-circuit board and heatsink
(at bottom version) can not be achieved, and as solder may stick to the heatsink (on top version).
3. If wave soldering is considered, then the package must be placed at a 45 angle to the solder wave direction.
The package footprint must incorporate solder thieves downstream and at the side corners.
4. Wave soldering is only suitable for LQFP, TQFP and QFP packages with a pitch (e) equal to or larger than 0.8 mm;
it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.65 mm.
5. Wave soldering is only suitable for SSOP and TSSOP packages with a pitch (e) equal to or larger than 0.65 mm; it is
definitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm.
DEFINITIONS
Data sheet status
Objective specification
This data sheet contains target or goal specifications for product development.
Preliminary specification
This data sheet contains preliminary data; supplementary data may be published later.
Product specification
Limiting values
Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or
more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation
of the device at these or at any other conditions above those given in the Characteristics sections of the specification
is not implied. Exposure to limiting values for extended periods may affect device reliability.
Application information
Where application information is given, it is advisory and does not form part of the specification.
LIFE SUPPORT APPLICATIONS
These products are not designed for use in life support appliances, devices, or systems where malfunction of these
products can reasonably be expected to result in personal injury. Philips customers using or selling these products for
use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such
improper use or sale.
1999 Sep 27
14
Philips Semiconductors
Product specification
74AHC125; 74AHCT125
NOTES
1999 Sep 27
15
Internet: http://www.semiconductors.philips.com
SCA 68
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The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed
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245002/02/pp16
Sep 27