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AD/ DA Measurement
2006/ 4/ 14
Page 1
Agenda
1. DAC Algorithm introduction & Testing
2. ADC Algorithm introduction & Testing
3. Instrument Solution Overview
AD/ DA Measurement
2006/ 4/ 14
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AD/ DA Measurement
2006/ 4/ 14
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Page 4
DAC Testing
Static Parameters
Dynamic Parameters
Gain Error
Offset Error
Gain Mismatch
Dynamic Deviation
Conversion Rate
AD/ DA Measurement
2006/ 4/ 14
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AD/ DA Measurement
2006/ 4/ 14
DNL
Page 6
AD/ DA Measurement
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AD/ DA Measurement
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AD/ DA Measurement
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AD/ DA Measurement
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AD/ DA Measurement
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AD/ DA Measurement
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AD/ DA Measurement
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AD/ DA Measurement
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AD/ DA Measurement
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AD/ DA Measurement
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AD/ DA Measurement
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Agenda
1. DAC Algorithm introduction & Testing
2. ADC Algorithm introduction & Testing
3. Instrument Solution Overview
AD/ DA Measurement
2006/ 4/ 14
Page 19
AD/ DA Measurement
2006/ 4/ 14
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10
AD/ DA Measurement
2006/ 4/ 14
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ADC Testing
Static Parameters
Dynamic Parameters
Gain Error
Offset Error
Missing Code
Quantization Error
AD/ DA Measurement
2006/ 4/ 14
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AD/ DA Measurement
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AD/ DA Measurement
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AD/ DA Measurement
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AD/ DA Measurement
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AD/ DA Measurement
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ADC Summary
AD/ DA Measurement
2006/ 4/ 14
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14
Agenda
1. DAC Algorithm introduction & Testing
2. ADC Algorithm introduction & Testing
3. Instrument Solution Overview
AD/ DA Measurement
2006/ 4/ 14
Page 29
PG
Sampling
Clock
Sampling Clock
For UUT DAC
16903A
16720A
Logic Analyzer
DA
Converter
Analog Signal
3458A
E4401B
N bits data
(Digital in)
LAN
Agilent VEE
GP-IB
PC(GP-IB)
AD/ DA Measurement
2006/ 4/ 14
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15
AD/ DA Measurement
2006/ 4/ 14
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AD/ DA Measurement
2006/ 4/ 14
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16
PG
Sine Wave
(to Analog input)
SG
Sampling
Clock
For ADC
Sampling
Clock
For LA
16903A
16911A
Logic Analyzer
AD
Converter
Filter
N bits data
(Digital out)
E4400B
Agilent VEE
LAN
GP-IB
PC(GP-IB)
AD/ DA Measurement
2006/ 4/ 14
Page 33
AD/ DA Measurement
2006/ 4/ 14
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17
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AD/ DA Measurement
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20
Requirements of Stimulus
Multiple synchronous stimulus channels
Different data formats and lengths
Different amplitude levels
Independent multiple clock phases
Multiple frequencies
ADDAConverter Testing
812xx Modular HW
Selected Front-Ends
determine
- type (out/in)
- speed / # of channels
Mainframe determines
- computer platform/interface
- total # of channels
ADDAConverter Testing
E4847A
330 Msa/s
Dual Channel
-2.1 to 5.1V
200 mV sensitivity
350 MHz BW
50 / 10k Ohm
max 500 kbit / ch *)
E4846A
200 Mbits/s
Dual single-ended channels
.3 .. 3.50 Vpp @ 50 ohm
-1.75 to +3.5 V window.
Constant slew rate < 750ps
NRZ/DNRZ
Max memory 500k / channel
ADDAConverter Testing
New products:
Product #
Description
E4862A
E4863A
E4864A
E4865A
E4835A
E4832A
E4861A
E4805B
E4874A
E4835A
E4843A
E4838A
E4861A
E4862A
E4863A
E4864A
E4865A
ADDAConverter Testing
Modules
E4805B/08A
Standard/
High
Performance
Clock
Module
E4832A
675 Mb/s
Module
E4861A
2.7 Gb/s
Module
E4861B
3.35 Gb/s
Module
E4810A
3.35 Gb/s
Electrical/Optical
Generator Module
E4811A
3.35 Gb/s
Optical/Electrical
Analyzer Module
N4872A
13.5 Gb/s
Generator
Module
N4873A
13.5 Gb/s
Analyzer
Module
Front Ends
E4838A
675 Mb/s
Generator
E4835A
675 Mb/s
Analyzer
675 Mb/s
E4862A/64A/63A/65A
2.7/1.6 Gb/s
Generator/Analyzer
2.7/1.6 Gb/s
E4862B/63B
3.35 Gb/s
Generator/Analyzer
13.5 Gb/s
45 Gb/s
ADDAConverter Testing
Data formats
Pattern format: NRZ, DNRZ, RZ, R1
up to 1 Mbit pattern memory per channel
Sequencing with 5 looping levels
PRBS 2^n -1, n=7,..15
Logical EXOR addition of two or four channels
ADDAConverter Testing
Data Formats
1 bit period
clock
NRZ
DNRZ
RZ
R1
ADDAConverter Testing
Frequency
Frequency 1 kHz to 200/330/660/ 2.7/3.35GHz
ADDAConverter Testing
ADDAConverter Testing
Voltages
independent control of each channel
Generator - output levels
Analyzer - input thresholds
Timing
ADDAConverter Testing
Stimulus
Data
Clock
Timing,
Formats
Clock
DUT
Digital Out
Errors
Error / no Error
Error / no Error
Sampling
Timing
Sampling
Data
Timing
Digital Out
Sequence
Errors
Data
Expected
Data
Clock
Sequence
Stimulus
Analysis
ADDAConverter Testing
TTL/CMOS
Icc (mA)
GTL
LVDS
10
3V
100
MHz
Single ended
2V
3V
Differential
2V
1V
1V
0V
ADDAConverter Testing
0.3V
LVDS
Speed
or n times
infinite, or stop on error
Branch on Event/Error
ADDAConverter Testing
Measurement Modules
for data analysis
to
import/export
any data the
content is
specified by
using an
ASCII editor
like Notepad.
the given
example
defines a
segment:
Cntrl 3 bit
wide.
ADDAConverter Testing
ADDAConverter Testing
10
Digital Solution
Reference Site:
Katholic University Leuven
16 Bit @ 13Gb/s ADDAC
Combine analysis
with Logic Analyser
AD/DA Converter
Stimulus/Analysis
capture
ADC
send
11111111
11110000
11001100
01010101
11111111
11110000
11001100
01010101
Parallel Digital
data stream
Parallel Digital
data stream
Analysis
Capture Data stream
Post processing
DAC
Much cleaner Eye performance with low Jitter (80ps typ @675MHZ)
More flexible with different modules of different speedclass
Sequence editor to setup complex data stream
Nested looplevels
BER measurement capability
Speedrates of 675M and 2.7G can be upgraded to the 81250
Covering very low frequency range down to 1Khz
We are real parallel and can control channels individually
Channel add function (XOR/Analog add)
All speedclasses operate with internal high precision clock
Hugh memory depth per channel
Semiautomatic deskew for precise timealignment
Mulitple clockdivider and multiply
Data import and export functionality
Covering LVDS standards
ADDAConverter Testing
11
ADDAConverter Testing
Amplitude @ 1.7 V
ADDAConverter Testing
12
Receiver Performance
Generator Source
ADDAConverter Testing
Jitter Control
ADDAConverter Testing
13
Crossover Control
Crossover @ 70%
Crossover @ 50%
Crossover @ 30%
ADDAConverter Testing
ADDAConverter Testing
14
ADDAConverter Testing
ADDAConverter Testing
15
Amplifier
Output
Delay(U)
Levels
Inverted
Output
'U/ ' t
ADDAConverter Testing
16
Output Timing
Measurement
Measurement Results Provided:
x Clock out to data out (setup & hold time)
x Skew between outputs
x Delay at optimum sample point
x Phase margin
x Pass/fail results
x Jitter (rms, p-p)
ADDAConverter Testing
ADDAConverter Testing
17
BER
Time
High Rj
Low Rj
Rj + Dj
ADDAConverter Testing
ADDAConverter Testing
18
ADDAConverter Testing
ADDAConverter Testing
19
BER vs Threshold
Level
Noise
Q-values
High Level
Low Level
Amplitude
Threshold
margin
S/N
ration for
p-p, rms
PP noise
Q- factor
Q-level
Q- opti.
sampling
point
dBER vs Threshold
20
Deskew Procedure
How to Deskew Channels
ADDAConverter Testing
21
Auto Delay Calibration can be used with data modules E4861A, E4861B,
E4866A and E4867A.
Auto Delay Calibration must be performed prior to deskew of individual
channels.
Auto Delay Calibration will define the internal analog delay/timing values.
These values are necessary to define the most accurate delay value over
frequency for the user and is temperature and time dependent.
Timing values are stored in the EEPROM
Calibration window can be found at:
System Auto Delay Calibration
The system will start automatically to update the timing values. There
are no additional task to do.
ADDAConverter Testing
Deskew possibilities
Zero Deskew will align all parallel data outputs/inputs at the SMA
connector
Cable Deskew will align all parallel data outputs/inputs at the end of
the connected cable
Active Probe Deskew will align all parallel data outputs/inputs on the
DUT board.
Manual Deskew can be done with a Oscilloscope. It can measure
the misplacement of each parallel channel. The measured delay
value can be inserted into the DESKEW table.
ADDAConverter Testing
22
Deskew possibilities
IC
Front-end
Cable adjustment
Zero adjustment
Board adjustment
with Active Probe
2nd.
1st.
Deskew Procedure I
New front-ends must be deskewed after swapping or exchanging
Deskew of generator or analyzer channels are performed to align
the timing system and compensate delay times at the output or
input of each individual channel.
the Agilent 812xx Application Software provides a semiautomatic tool to perform the task
The deskew value for zero adjust is saved within the front-end,
the cable/active probe value is saved within the setting.
Deskew editor can be found at
Go -> Deskew
ADDAConverter Testing
23
ADDAConverter Testing
Deskew Procedure I
available front-ends
for deskew.
System name: DSRA
ADDAConverter Testing
24
Deskew Procedure II
Choose the right Clock system DSRxy:
If more than one module were exchanged, try to find a
clock system that includes as many of the related
instruments as possible, otherwise you need to
reconnect until all modules front-ends were deskewed
Choose the right front-end:
The front-end description is labeled as e.g. C1M1C2.
C1 - clock group one
M1 - data module one after clock module
C2 - front-end channel 2 in the particular data module
ADDAConverter Testing
ADDAConverter Testing
25
Deskew Procedure IV
How to connect the application to a system:
After select (1) and (2) the started clock system can be
deskewed!
ADDAConverter Testing
Zero Adjustment I
Generator Front-End Zero Adjust:
1.) select front-end(s)
2.) start measurement
ADDAConverter Testing
26
Zero Adjustment II
Analyzer Front-End Zero Adjust:
1.) select front-end(s)
2.) start measurement
ADDAConverter Testing
53
Zero Adjustment II
Analyzer Front-End Zero Adjust: (if no reference gen. is available in this
clock group)
1.) select front-end(s)
3.) enter master cable delay and connect
2.) start measurement
cable as prompted
4.) repeat 3.) for every selected front-end
ADDAConverter Testing
54
27
ADDAConverter Testing
ADDAConverter Testing
28
ADDAConverter Testing
29
30
Page 1
or
DSP
INPUT
MCU
Processing
Output
Power
Page 2
Page 3
CH1
CH2
Page 5
Page 6
5 ns/div
5 ns/div
CH2 = A4
CH2 = D4
A4
D4
Page 7
Page 9
Differentiated:
Most, Highest, Fastest
4th Dimension Ensures Seeing ALL
100,000 waveforms/sec update
rate
See jitter, noise, infrequency
glitch
With deep memory
Acquisition Time
Dead-time
Acquisition Time
Jitter
Noise
Dead-time
Glitch
Page 10
Non-Sampled-based?
Page 11
Page 12
Optional with
Infiniium MSO
Virtex-4
Virtex-II Pro
Virtex-II
Spartan-3
FPGA
Control access
to new signals
via JTAG
ATC2
Parallel or USB
LAN
USB
GPIB
JTAG
Page 13
Page 15
Standard Capability
No Special Modes--Standard
Operating Condition
Maintains Fast Waveform Update Rate
and Responsiveness
Analog
channels see
isolated clock
coupling
Digital channels
provide state
trigger on first
address phase after
a bus turnaround
Page 17
Infiniium MSO!
Bus Display
Hex Readout Directly on Waveform
Infiniium Segment
Segmented Memory Acq Mode
Efficiently Utilize Memory to Capture
Bursting or Packetized Signals
Only Captures Period of Signal Activity,
Not Dead-Time Between Packets
Captures both Analog and Digital
Channels
Capture up to 32,000 Segments Over
Seconds, or Even Days of Time At Full
Sample Rate!
Overlay Segments with
Persistence or Color Grading
Full Analysis on Each Segment
Build Up Measurement Stats and
Histograms Across All Segments
Navigation Controls to Step or Play
Through Segments
Page 19
Automatic Clickand-Zoom
Listing
Window
Search
Index
Search Navigation
Controls
Page 20
10
FPGA
Control access
to new signals
via JTAG
ATC2
Parallel
Virtex-4
Virtex-II Pro
Virtex-II
Spartan-3
JTAG
Page 22
11
Analog:
Digital:
Serial:
Page 23
Thank you
Page 24
12
Backup slides
Page 25
Positioning
Statements
Target
Customers
- R&D engineers
- Value oriented customers
- R&D engineers
- Performance oriented customers
Primary
Application
Design
philosophy
13
Agilent N5423A
Agilent N5393A
6000 Series
Yes
Yes
Content Search
No
Yes
Lister Window
No
Yes
Page 27
Page 28
14
13 GHz
Infiniium DSO80000
Series
Infiniium 8000
Series
6000 Series
300 MHz
Page 29
Page 30
15
Page 31
First
Logic Analyzer
1973
3M 40-pin
Single-Ended
17 Channels
Mictor
Single-Ended
34 Channels
3pf loading
600Mb/s
Samtec
Single-Ended
Differential
34 Channels
1.5pf loading
1500Mb/s
1985
1996
2000
2003
2004
Page 32
16
Page 33
Page 34
17
Page 35
Page 36
18
Setup
setup
Automate setup/hold and
threshold settings to obtain
accurate and reliable
measurements
Scan all channels
simultaneously or just a few
View as composite display or as
individual signals
Signal Quality
Quickly find problem channels &
see skew between channels
Measure data valid windows
Identify signal integrity
problems related to rise times,
fall times, eye width,
Page 37
19
www.agilent.com.tw
www.agilent.com.tw/find/handouts
104 2 8
(02) 8772-5888
324 20
(03) 492-9666
552 12 C
(04) 2310-6914
8026251
(07) 535-5035
2005
Issued date : 04/2006
Updated data : 04/2006
Printed in Taiwan
04/2006
5989-5000ZHA