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2006 4 14

13:00~13:20

13:20~13:30

13:30~14:40

14:40~15:00

15:00~15:40

15:40~16:40

16:40~17:00

The Standard Testing Challenge


for A to D&D to A Chipset Design
Brian Chi
Senior Project Manager
Electronic Measurements Group
Agilent Technologies Taiwan
Brian-tn_chi@agilent.com
03-4959054

AD/ DA Measurement
2006/ 4/ 14

Page 1

Agilent EMG Taiwan

Agenda
1. DAC Algorithm introduction & Testing
2. ADC Algorithm introduction & Testing
3. Instrument Solution Overview

AD/ DA Measurement
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Agilent EMG Taiwan

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DAC Block Diagram

AD/ DA Measurement
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DAC Block Diagram

Usually use reconstruct filter to compensate sinx/x droop


AD/ DA Measurement
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DAC Testing
Static Parameters

Dynamic Parameters

DNL (Differential Non- Linearity)

THD (Total Harmonic Distortion)

INL (Integral Non Linearity)

SINAD (Signal-to-Noise + Distortion


Ratio)

Gain Error

SFDR (Spurious Free Dynamic Range)

Offset Error

ENOB (Effective Number of Bits)

Gain Mismatch

Dynamic Deviation

Conversion Rate

AD/ DA Measurement
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Agilent EMG Taiwan

DAC Testing Static Para.


INL

AD/ DA Measurement
2006/ 4/ 14

DNL

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DAC Testing Static Para.


End Point method (INL/ DNL)

AD/ DA Measurement
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DAC Testing Static Para.


Regression method (INL/ DNL)

AD/ DA Measurement
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DAC Testing Static Para.


Gain Error (Proportional Displacement)

AD/ DA Measurement
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DAC Testing Static Para.


Offset Error (Linear Displacement)

AD/ DA Measurement
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DAC Testing Static Para.


Gain Mismatch

AD/ DA Measurement
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DAC Testing Static Para.


Conversion Rate
Run code from 0 - 2^n-1 -0
Find the maximum DAC operation Frequency

AD/ DA Measurement
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DAC Testing Static Para.


Settling time
Input Code from 0 to Full Scale.
Settling time T1- T2, within Settling band +/- 0.5 LSB
DAC Speed = (Settling Time)^-1

AD/ DA Measurement
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Agilent EMG Taiwan

Page 13

DAC Testing Static Para.


Rising/ Falling time
Run code from 0 to FS (Full Scale) than back to 0

AD/ DA Measurement
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DAC Testing Static Para.


PSRR (Power Supply Rejection Ratio)
Run Code to FS, measure DAC IC to Power noise

AD/ DA Measurement
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DAC Testing Dynamic Para.

AD/ DA Measurement
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DAC Testing Dynamic Para.

AD/ DA Measurement
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Agilent EMG Taiwan

DAC Testing Example

From TCSFT VLSI course


AD/ DA Measurement
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Agenda
1. DAC Algorithm introduction & Testing
2. ADC Algorithm introduction & Testing
3. Instrument Solution Overview

AD/ DA Measurement
2006/ 4/ 14

Agilent EMG Taiwan

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ADC Block Diagram

AD/ DA Measurement
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ADC Block Diagram

AD/ DA Measurement
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Agilent EMG Taiwan

ADC Testing
Static Parameters

Dynamic Parameters

DNL (Differential Non- Linearity)

THD (Total Harmonic Distortion)

INL (Integral Non Linearity)

SINAD (Signal-to-Noise + Distortion


Ratio)

Gain Error

SFDR (Spurious Free Dynamic Range)

Offset Error
Missing Code
Quantization Error

AD/ DA Measurement
2006/ 4/ 14

Agilent EMG Taiwan

ENOB (Effective Number of Bits)


Dynamic Deviation

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ADC Static Para.


Ideal 3-bit ADC

AD/ DA Measurement
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Agilent EMG Taiwan

ADC Static Para.


Ideal & Real ADC

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ADC Static Para.


ADC DNL Algorithm

AD/ DA Measurement
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Agilent EMG Taiwan

ADC Static Para.


ADC INL Algorithm

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ADC Static Para.


Quantization Error

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Agilent EMG Taiwan

ADC Summary

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Agenda
1. DAC Algorithm introduction & Testing
2. ADC Algorithm introduction & Testing
3. Instrument Solution Overview

AD/ DA Measurement
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Agilent EMG Taiwan

DAC Measurement Solution


81130A
81131A

PG

Sampling
Clock
Sampling Clock
For UUT DAC

16903A
16720A
Logic Analyzer

DA
Converter

Analog Signal

3458A
E4401B

N bits data
(Digital in)

LAN

Agilent VEE

GP-IB

PC(GP-IB)
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DAC Solution Results DNL/INL

AD/ DA Measurement
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DAC Solution ResultsSpectrum

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ADC Measurement Solution


81130A
81131A
10MHz Reference

PG

Sine Wave
(to Analog input)

SG

Sampling
Clock
For ADC

Sampling
Clock
For LA

16903A
16911A
Logic Analyzer

AD
Converter

Filter

N bits data
(Digital out)

E4400B

Agilent VEE

LAN

GP-IB
PC(GP-IB)

AD/ DA Measurement
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ADC Solution Result DNL/INL

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ADC Solution Result Spectrum

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Appendix: FFT Requirement

FFT data point should be 2^n, with Coherence sampling


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Appendix: FFT Requirement

UTP: Unit Test Period one complete signal cycle


N as sampling data.
M as number of whole signal cycles
N sampling data MUST contain M signal cycles
AD/ DA Measurement
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Appendix: FFT Requirement

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How to Use 81250 ParBERT


to Implement A to D&D to A
Testing
Francis Liu
Junior Project Manager
Electronic Measurements Group
Agilent Technologies Taiwan
Francis-tc_liu@agilent.com
03-4959340
ADDAConverter Testing

Requirements of Stimulus
Multiple synchronous stimulus channels
Different data formats and lengths
Different amplitude levels
Independent multiple clock phases
Multiple frequencies

ADDAConverter Testing

812xx Modular HW
Selected Front-Ends
determine
- type (out/in)
- speed / # of channels

Data Modules determine


- signal generation/
analysis capabilities
- speed / # of channels

Mainframe determines
- computer platform/interface
- total # of channels

ADDAConverter Testing

Generator / Analyzer Modules


E4841A
4 slots for generator or
analyzer
front-ends 4 / 8 channels

E4847A
330 Msa/s
Dual Channel
-2.1 to 5.1V
200 mV sensitivity
350 MHz BW
50 / 10k Ohm
max 500 kbit / ch *)

E4846A
200 Mbits/s
Dual single-ended channels
.3 .. 3.50 Vpp @ 50 ohm
-1.75 to +3.5 V window.
Constant slew rate < 750ps
NRZ/DNRZ
Max memory 500k / channel

ADDAConverter Testing

Generator / Analyzer Modules


E4832A

New products:
Product #

Description

E4862A

2.6 Gbit generator front-end

E4863A

2.6 Gbit analyzer front-end

E4864A

1.3 Gbit generator front-end

E4865A

1.3 Gbit analyzer front-end

E4835A
E4832A

Dual 660 MHz differential


analyzer front-end
660 MHz module

E4861A

2.6 Gbit module

E4805B

Central clock module

E4874A

Software revision 3.0

E4835A
E4843A
E4838A

E4861A

E4862A
E4863A
E4864A
E4865A

ADDAConverter Testing

ParBERT 81250 Platform Product offering


Software

E4875A ParBERT Software Suite

Modules

E4805B/08A
Standard/
High
Performance
Clock
Module

E4832A
675 Mb/s
Module

E4861A
2.7 Gb/s
Module

E4861B
3.35 Gb/s
Module

E4810A
3.35 Gb/s
Electrical/Optical
Generator Module
E4811A
3.35 Gb/s
Optical/Electrical
Analyzer Module

N4872A
13.5 Gb/s
Generator
Module
N4873A
13.5 Gb/s
Analyzer
Module

E4896A 45 Gb/s Pattern Generator Bundle


E4867A 45 Gb/s Error Detector Bundle
E4883A Lightwave Transmitter Module
E4882A Lightwave Receiver Module
E4884A High Performance Lightwave Option

Front Ends
E4838A
675 Mb/s
Generator

E4835A
675 Mb/s
Analyzer

675 Mb/s

E4862A/64A/63A/65A
2.7/1.6 Gb/s
Generator/Analyzer

2.7/1.6 Gb/s

E4862B/63B
3.35 Gb/s
Generator/Analyzer

3.35 Gb/s E/O

13.5 Gb/s

45 Gb/s

ADDAConverter Testing

Key Features of The Generator (I)


Multiple channels
2 to 120 RZ channels (doubles for NRZ channels
up to 200 Mbit/s)

Data formats
Pattern format: NRZ, DNRZ, RZ, R1
up to 1 Mbit pattern memory per channel
Sequencing with 5 looping levels
PRBS 2^n -1, n=7,..15
Logical EXOR addition of two or four channels

ADDAConverter Testing

Data Formats
1 bit period

clock
NRZ
DNRZ

width is multiple of clock period


signal can be delayed as required

RZ

width and delay can be set as required

R1

width and delay can be set as required

ADDAConverter Testing

Key Features of The Generator (II)


Amplitude
Variable output levels (max. 3.5 Vpp),
10 mV resolution
Clock
Variable delay (0 to 3 us) and width
2 ps timing resolution, 50 ps edge
placement accuracy

Frequency
Frequency 1 kHz to 200/330/660/ 2.7/3.35GHz

ADDAConverter Testing

Key Features of The Analyzer


At run time, the data analyzer compares
data from the device against expected data.
Expected data can be:
captured data from a golden device
data generated on a simulator.
As a result immediate PASS/FAIL information
is available instead of post-processing tons of data.
In case of failures, tools like the error state list or
BER help to get insight on the device under test.

ADDAConverter Testing

Key Features: Generators and Analyzers


Required for deskewing to device pins and making parametric
measurements such as - setup and hold time

Voltages
independent control of each channel
Generator - output levels
Analyzer - input thresholds

Timing

independent control of each channel


Clocking
Variable delay
1 ps timing resolution, 50 ps edge placement accuracy

ADDAConverter Testing

Full parallel test resources in


real time
Simplified Block Diagram
to: oscilloscope, spectrum analyzer,
frequency counter, etc.
Analog out
Expected

Stimulus
Data

Clock

Timing,
Formats
Clock

DUT

Digital Out

Errors

Error / no Error
Error / no Error

Sampling
Timing
Sampling

Data

Timing

Digital Out
Sequence

Errors

Data
Expected
Data

Clock

Sequence

Clock Generation, Central Start / Stop, Sequence

Stimulus

Analysis
ADDAConverter Testing

The Benefits of CMOS Serial Devices


Why Measure Differential for BER analysis?
Low Voltage Differential Signals (LVDS) are a key technology for
enabeling state-of-the-art high-speed designs.
Icc vs freq.

TTL/CMOS

Icc (mA)

Major advantages of using differential signals:


enables high speed operation
reduced power consumption
reduces noise, cross talk and EMI

GTL

=>>Differential Connection is important to


reduce Common Mode Noise specifically for
low voltage levels

LVDS
10

3V

100

MHz

Single ended

2V

3V

Differential

2V
1V

1V
0V

ADDAConverter Testing

0.3V
LVDS

Speed

Test Flow and Data Analysis


Test Flow:
Single

or n times
infinite, or stop on error
Branch on Event/Error

Real Time Compare:


CAPTURE
ERROR STATE LIST
Bit Error Rate Display

ADDAConverter Testing

Sequence Editor for enhanced data


processing

5 nested loop levels


Multiple blocks with different block length
Jump on Event (CMD, Trigger Pod, VXI Backplane, by Error)
ADDAConverter Testing

Sequence Editor including Jump on


event

Possible events to react on:


CMD at the GUI
Trigger Pod
VXI trigger lines on the VXI back plane
On Errors
ADDAConverter Testing

Measurement Modules
for data analysis

Capture data into memory


BER measurement
Acquire and compare incoming data stream
with expect data until error is detected
ADDAConverter Testing

Waveform viewer for detailed data


analysis

Waveform viewer allows analysing memory based data content


Shows errored bit information
ADDAConverter Testing

Data Import/Export (1)

to
import/export
any data the
content is
specified by
using an
ASCII editor
like Notepad.
the given
example
defines a
segment:
Cntrl 3 bit
wide.

ADDAConverter Testing

Data Import/Export (2)


The 81200 format
allows to deal with
binary, hexadecimal
and decimal base.
For masking the
states high, low
and dont care are
available. Instead
of plain vectors,
also segments with
pseudo random
data (PRBS) up to
2^15-1 can be
defined.

ADDAConverter Testing

10

Digital Solution
Reference Site:
Katholic University Leuven
16 Bit @ 13Gb/s ADDAC

Combine analysis
with Logic Analyser

AD/DA Converter
Stimulus/Analysis

capture
ADC

send

11111111
11110000
11001100
01010101

11111111
11110000
11001100
01010101

Parallel Digital
data stream

Parallel Digital
data stream

Analysis
Capture Data stream
Post processing

DAC

Provide digital parallel


data stream to DAC and
generate analog signal
Capture digital parallel
data stream from ADC and
do post processing
Free parallel configurable
system with different
speed classes
ADDAConverter Testing

Key Values: Parallel Data stimulus, sequencing, capture, import/export

Why are we better than


competition?!

Much cleaner Eye performance with low Jitter (80ps typ @675MHZ)
More flexible with different modules of different speedclass
Sequence editor to setup complex data stream
Nested looplevels
BER measurement capability
Speedrates of 675M and 2.7G can be upgraded to the 81250
Covering very low frequency range down to 1Khz
We are real parallel and can control channels individually
Channel add function (XOR/Analog add)
All speedclasses operate with internal high precision clock
Hugh memory depth per channel
Semiautomatic deskew for precise timealignment
Mulitple clockdivider and multiply
Data import and export functionality
Covering LVDS standards

ADDAConverter Testing

11

ParBERT 81250 Big Systems


26 Channels mix of 7 / 13.5Gb/s
for KU Leuven ( ADDAC)

ADDAConverter Testing

3.35Gb/s Generator Output


Signal
Amplitude @ 40mV

Amplitude @ 1.7 V

ADDAConverter Testing

12

Receiver Performance
Generator Source

Receiver Eye Detect

ADDAConverter Testing

Jitter Control

Clean Eye @ 3.3Gbit/s

Jitter modulated with Rectangle-Wave

Jitter modulated with Sine-Wave

Jitter modulated with Triangle-Wave

ADDAConverter Testing

13

Crossover Control
Crossover @ 70%

Crossover @ 50%

Crossover @ 30%

ADDAConverter Testing

Software Screens (1)


Connection
4 Generator
& 4 Analyzer

ADDAConverter Testing

14

Software Screens (2)


Segment Resolution 128
Memory Depth 16MBit
Max Frequency 3.35GHz

ADDAConverter Testing

Software Screens (3)


Change Generator Delay value
without restarting the System!!

Change Crossing point


between 30% and 70%

ADDAConverter Testing

15

Software Screens (4)


Delay Control IN at the Generator front-end:
Delay variation with 50ps when '1V is applied
Delay variation of 500ps when '1V is applied

Amplifier
Output

Delay(U)
Levels

Inverted
Output

'U/ ' t
ADDAConverter Testing

ParBERT 81250 Parallel


measurements
Measurements:
Extended BER
Output timing
Jitter (RJ,DJ,TTJ)
Output level
Eye opening
Fast eye mask
Q-factor
Setup/hold time
Spectral Jitter
Advantage:
Real world stress
Saves time & money
ADDAConverter Testing

16

Output Timing
Measurement
Measurement Results Provided:
x Clock out to data out (setup & hold time)
x Skew between outputs
x Delay at optimum sample point
x Phase margin
x Pass/fail results
x Jitter (rms, p-p)

ADDAConverter Testing

Bath Tub Measurement


with Rj / Dj
Low Rj
High Rj
Rj + Dj

ADDAConverter Testing

17

Bath Tub Measurement


with Rj / Dj
BER Threshold
Rj, random jitter, rms
Range
for Extrapolation
Min. BER

Dj, deterministic jitter


Extraplolated Total Jitter (for
BER 10^-6 to 10^-15)
Quality of Fit

BER
Time

High Rj
Low Rj
Rj + Dj
ADDAConverter Testing

Eye Opening Measurement


Measurement Results Provided:

Characterize the following:

x Graphical Iso BER

x Eye Opening (voltage and timing)

x Cursors for waveform analysis

x Optimum sample point

ADDAConverter Testing

18

Fast Eye Mask


Measurement
x BER at pre-defined
points (1 to 32) relative
to starting point
x Fast: 1-2 sec.
x Pass/fail results

ADDAConverter Testing

Fast Eye Mask catches the errors


12 channel, 2.5G parallel optical
receiver
Power Supply 3.3 volts

Power Supply 2.5 volts

ADDAConverter Testing

19

Output Level measurement


Q-factor

BER vs Threshold

Level

Noise

Q-values

High Level
Low Level
Amplitude
Threshold
margin

S/N
ration for
p-p, rms
PP noise

Q- factor
Q-level
Q- opti.
sampling
point

dBER vs Threshold

Q from BER vs Threshold


ADDAConverter Testing

Bit error ratio measurement

BER for all bits


# of total errors
BER for zero bits
BER for one bits
# of zero errors
# of one errors
PPass / Fail Information
ADDAConverter Testing

20

Spectral Jitter measurement


Noise Threshold Plot

By capturing error information at the


crossing point and post processing
(involving FFT), the Measurement Analysis
Suite is able to display a power spectrum of
the Jitter frequency.
ADDAConverter Testing

Deskew Procedure
How to Deskew Channels

ADDAConverter Testing

21

Auto Delay Calibration

Auto Delay Calibration can be used with data modules E4861A, E4861B,
E4866A and E4867A.
Auto Delay Calibration must be performed prior to deskew of individual
channels.
Auto Delay Calibration will define the internal analog delay/timing values.
These values are necessary to define the most accurate delay value over
frequency for the user and is temperature and time dependent.
Timing values are stored in the EEPROM
Calibration window can be found at:
System Auto Delay Calibration
The system will start automatically to update the timing values. There
are no additional task to do.

ADDAConverter Testing

Deskew possibilities

Zero Deskew will align all parallel data outputs/inputs at the SMA
connector
Cable Deskew will align all parallel data outputs/inputs at the end of
the connected cable
Active Probe Deskew will align all parallel data outputs/inputs on the
DUT board.
Manual Deskew can be done with a Oscilloscope. It can measure
the misplacement of each parallel channel. The measured delay
value can be inserted into the DESKEW table.

ADDAConverter Testing

22

Deskew possibilities
IC
Front-end

Cable adjustment

Zero adjustment

Board adjustment
with Active Probe

Sum Delay value = zero adjust + cable adjust / board adjust


3rd.

2nd.

1st.

Deskew will align a misplacement of


the data stream in order to output/sample all
data at the right point in time.
ADDAConverter Testing

Deskew Procedure I
New front-ends must be deskewed after swapping or exchanging
Deskew of generator or analyzer channels are performed to align
the timing system and compensate delay times at the output or
input of each individual channel.
the Agilent 812xx Application Software provides a semiautomatic tool to perform the task
The deskew value for zero adjust is saved within the front-end,
the cable/active probe value is saved within the setting.
Deskew editor can be found at
Go -> Deskew

ADDAConverter Testing

23

Logic process of Deskew


1)Set the typically frequency of your application and warm up the
system at least hour.
2)Start with Auto Delay Calibration to compensate any temp. and timing
effects to the frequency versus delay relation.
3)Perform the Zero Adjustment for all/individual front-ends to align all
outputs/inputs at the right point in time.
4)Perform Cable/Active Probe Adjustment to align the data on the
cable-end or DUT board. Delay values are based on the Zero
Adjustment!

ADDAConverter Testing

Deskew Procedure I

available front-ends
for deskew.
System name: DSRA
ADDAConverter Testing

24

Deskew Procedure II
Choose the right Clock system DSRxy:
If more than one module were exchanged, try to find a
clock system that includes as many of the related
instruments as possible, otherwise you need to
reconnect until all modules front-ends were deskewed
Choose the right front-end:
The front-end description is labeled as e.g. C1M1C2.
C1 - clock group one
M1 - data module one after clock module
C2 - front-end channel 2 in the particular data module

ADDAConverter Testing

Deskew Procedure III


How to connect the application to a system:

ADDAConverter Testing

25

Deskew Procedure IV
How to connect the application to a system:

(1) choose the noted system name


(2) press OK

After select (1) and (2) the started clock system can be
deskewed!
ADDAConverter Testing

Zero Adjustment I
Generator Front-End Zero Adjust:
1.) select front-end(s)
2.) start measurement

3.) enter master cable delay and connect


cable as prompted
4.) repeat 3.) for every selected front-end

ADDAConverter Testing

26

Zero Adjustment II
Analyzer Front-End Zero Adjust:
1.) select front-end(s)
2.) start measurement

3.) enter master cable delay and reference


generator front-end and connect
cable as prompted
4.) repeat 3.) for every selected front-end

ADDAConverter Testing

53

Zero Adjustment II
Analyzer Front-End Zero Adjust: (if no reference gen. is available in this
clock group)
1.) select front-end(s)
3.) enter master cable delay and connect
2.) start measurement
cable as prompted
4.) repeat 3.) for every selected front-end

ADDAConverter Testing

54

27

Cable Adjustment - Generator front-end


1
2

Connect the cable of the given


Generator front-end to the Probe Input
(Clock Module Probe SMA input)

ADDAConverter Testing

Cable Adjustment - Analyzer front-end


1

Select Analyzers and Cable


Adjust

Connect the cable of the given


Analzyer front-end to the selected
Generator front-end (C1M3C1)

ADDAConverter Testing

28

Cable Adjustment - Analyzer front-end


(if no reference gen. is available in this clock group)
1

Select Analyzers and Cable


Adjust

Connect the cable of the given


Analzyer front-end to the Clock Module
trigger output as Reference channel.

ADDAConverter Testing

Active probe deskew - Generator front-end


Probe Attenuation: 10
Probe Delay value: ~8.5ns
Probe Delay value not known??
If you don t know the probe delay,
you can make a first measurement
by connecting the probe directly to
the first generator output.
Start the measurement by clicking
OK. The result is the probes
propagation delay. Close the
Automated Deskew window. Click
Measure again. Enter
the resulting value as the probe
delay and repeat the measurement.
Now the resulting value for this
output should be 0 ns.
ADDAConverter Testing

29

Active probe deskew - Analyzer front-end


1) - Instead of using the active probe,
a normal 50Ohm cable (passive probe) with
a known length must be used.
2) - Connect the known 50 Ohm probe
to the selected Generator front-end.
3) - Use this 50 Ohm Probe and select
the measure point on the DUT board
where the Analyzer front-end is connected to.
Exercise example:
Connect a cable with a know length to
the Generator front-end C1M2C1 and
connect this to a second cable which is
applied to the Analzyer front-end C1M3C1.
As a result you will get the delay length
of the Analyzer cable.
ADDAConverter Testing

30

Leverage Embedded System


Design Testing to ADDA
Application
Agilent Application Engineer:
Name: Ryan Lu
Mail: ryan_lu@agilent.com

Page 1

Typical Mixed-Signal Embedded Design

or
DSP

INPUT

MCU
Processing

Output

Power

Page 2

Challenge of digital circuit board debugging


Glitch

Analog signals are controlled by


digital control lines
Need to observe analog behavior
of high speed digital signals
In the figures left , you see the
signal behavior with deep memory
scope while you do not know when
it happens .

Page 3

MCU-based Chirp Design Block Diagram

Mixed-signal embedded design that generates


analog chirp outputs based on analog,
digital, and serial I/O.
Product designed by Solutions-Cube of
Chico, CA
Page 4

View Multiple Signals in an MCU-based Design


Challenge: Validate DAC design by viewing and measuring timealigned input and output signals
D0 D7

CH1

CH2

Pattern trigger to achieve stable trigger at 100%


point of channel 1

Verify the digital input signals of the


DAC are time-aligned with the
analog output
Pattern trigger across analog and digital channels
to achieve stable trigger at 50% point of channel 1

Use pattern/state trigger across the


digital inputs and analog outputs .

Page 5

Why is Synchronized Pattern Triggering


Important?
User-specified Trigger Condition: LHLL (0100)

Where should the scope trigger?

Page 6

Stable Triggering Requires Non


Sample-based Triggering
Trigger Condition: Trigger on rising edge of D4 (A4) during specified pattern

5 ns/div
5 ns/div

CH2 = A4

CH2 = D4

A4

D4

Sample-based pattern triggering


induces Trigger Jitter
(+/- sample period of p-p jitter)

Analog/real-time pattern triggering


minimizes Trigger Jitter
(10 ps RMS typical for 1-GHz scope)

Page 7

300MHz, 500MHz and 1 GHz bandwidth


2, 4, and 2 + 16, 4+16 channel models
Up to 8 MB MegaZoom III deep memory
High-Definition XGA Color Display with 100,000 waveforms/sec
Powerful triggering Serial bus and new HDTV triggering
Standard USB, LAN and GPIB Interface
Page 8

Uncovering Signal Anomalies


Challenge: See a signal anomaly embedded in every other AM
packet, then zoom in for detailed analysis
High definition display and
256 levels of color intensity
show anomalies
See signal details
Zoom in for analysis

Page 9

Differentiated:
Most, Highest, Fastest
4th Dimension Ensures Seeing ALL
100,000 waveforms/sec update
rate
See jitter, noise, infrequency
glitch
With deep memory

Acquisition Time

Dead-time

Acquisition Time

I. Most Responsive Deep Memory


II. Highest Definition Color Display

III. Fastest Waveform Update Rate,


Uncompromised

Jitter
Noise

Dead-time

Glitch

Page 10

What Type of Triggering is Required?

Simple Pattern Triggering


Analog AND Digital?
Synchronized?
Time-Qualified?

Advanced Digital Triggering


Pattern Duration?
Pattern Sequencing?
Serial (I2C, SPI, LIN, etc.)?

Non-Sampled-based?
Page 11

N5423A I2C and SPI serial decode

Page 12

FPGA Dynamic Probe for Agilent MSOs


FPGA Dynamic Probe SW
running on Infiniium MSO
or on PC, licensed either
to MSO or PC

Move FPGA designs quickly through


debug and validation
Increased visibilitymeasure up to 64 internal FPGA
signals for each debug pin, max 1024 internal signals
Faster probing changesmove internal FPGA probe
points in less than a second, no design recompiles
Automatic setup of MSOautomatically turn on
channels and/or busses and map designs signal
names to channel labels

Optional with
Infiniium MSO

Virtex-4
Virtex-II Pro
Virtex-II
Spartan-3

Probe core output


on variety of logic
probe connectors to
MSO cable

FPGA

Control access
to new signals
via JTAG

ATC2

Insert ATC2 core


with ChipScope
Pro Core Inserter

Parallel or USB

LAN
USB
GPIB

JTAG
Page 13

Achieve 1 GHz System Bandwidth


With 1 GHz MSO and DSO Models
(6102/4A) and
1130A InfiniiMax 1.5 GHz differential
active probe or
1156A 1.5 GHz single-ended active
probe
Achieve
Faithful reproduction of signal
Flat frequency response
Wide dynamic range
1130A modular probe architecture
Automatic probe sense and probe power
enabled by AutoProbe interface
Page 14

Infiniium 8000 Series Oscilloscopes


New Capabilities
Next-Generation MegaZoom Technology
Highest Resolution XGA Resolution Display
3rd Dimensional Viewing with 256 Levels of Waveform
Intensity Grading
Standard Touch Screen for Mouse-Free Operation
Added Features to I2C, SPI and CAN Serial Data Analysis
Software Options
Front Panel USB 2.0 Host Port for Easy File Saving to USB
Thumb Drive
2.9 GHz CPU Processor with 1GB CPU Memory

Page 15

Infiniium 8000 Series Next-Generation


Next-Generation MegaZoom
Technology
Highest Resolution XGA Display
Only 256 Levels of Intensity Grading
for 3rd Dimensional Viewing

Standard Capability
No Special Modes--Standard
Operating Condition
Maintains Fast Waveform Update Rate
and Responsiveness

Spot Problems Easily,


Then Quickly Zoom In for
More Detailed Analysis
Page 16

MSO Finds Root Cause

Analog
channels see
isolated clock
coupling
Digital channels
provide state
trigger on first
address phase after
a bus turnaround

Page 17

Infiniium MSO!
Bus Display
Hex Readout Directly on Waveform

State Bus Mode Display


Choose a Clock Source and Bus
Waveform Values Update Only on Clock
Transition

Bus Display of Easy Viewing of Parallel Busses


Page 18

Infiniium Segment
Segmented Memory Acq Mode
Efficiently Utilize Memory to Capture
Bursting or Packetized Signals
Only Captures Period of Signal Activity,
Not Dead-Time Between Packets
Captures both Analog and Digital
Channels
Capture up to 32,000 Segments Over
Seconds, or Even Days of Time At Full
Sample Rate!
Overlay Segments with
Persistence or Color Grading
Full Analysis on Each Segment
Build Up Measurement Stats and
Histograms Across All Segments
Navigation Controls to Step or Play
Through Segments
Page 19

N5391A Low-Speed SDA for SPI and


Column
On-Screen
I 2C
Sort
Serial Decode

Automatic Clickand-Zoom
Listing
Window

Search
Index

Search Navigation
Controls
Page 20

10

New Serial Data Analysis Capabilities

Real-time eye using


clock recovery
Eye mask unfold
on failures
8b/10b decode,
search, & triggering
Page 21

N5397A FPGA Dynamic Probe for Infiniium MSOs


Block Diagram of Solution

FPGA

Control access
to new signals
via JTAG

ATC2

Insert ATC2 core


with ChipScope
Pro Core Inserter

Probe core output


on variety of logic
probe connectors
to MSO cable

Parallel

Virtex-4
Virtex-II Pro
Virtex-II
Spartan-3

FPGA Dynamic Probe SW


application licensed to a
PC or Infiniium MSO scope

JTAG

Page 22

11

Integrated Analog, Digital & Serial test


for superior insight.

Analog:

Portable 6000 series

Infiniium 8000 series

2-4ch, 100MHz-1GHz Bandwidth

4ch, 600MHz-1GHz Bandwidth

Industries highest resolution displays: XGA with 256 intensity levels


Fast waveform update rate: 100k
Extensive applications suite including
waveforms/s
jitter analysis software.

Digital:

Serial:

16 Digital timing channels time correlated with analog channels:


Mixed Signal Oscilloscope (MSO)
Pattern and mixed signal triggering
FPGA Dynamic Probe application
Built in I2C, SPI, CAN, LIN, USB
I2C, SPI, CAN analysis, GBE, USB
hardware trigger.
compliance testing
Up to 8Mpts of Megazoom deep memory. Up to 128Mpts of Megazoom deep
memory.

Page 23

Thank you

Page 24

12

Backup slides

Page 25

Positioning for 6000 series and 8000 series

Agilent 6000 Series

Agilent Infiniium 8000 Series

Positioning
Statements

Optimized for general purpose


R&D bench-top testing where basic
measurement functions with analog
scope-like display, responsiveness,
portability and affordability are
important.

Optimized for R&D environment


where high performance, advanced
signal analysis and measurement
features are critical.

Target
Customers

- R&D engineers
- Value oriented customers

- R&D engineers
- Performance oriented customers

Primary
Application

Optimized for general purpose


bench testing

Optimized for R&D design


verification

Design
philosophy

Fixed architecture for simple and


compact design

PC based open architecture for


flexibility and upgradeability
Page 26

13

Comparison of Agilent Low Speed Serial


(LSS) Analysis
For use with
I2C /SPI trigger

Agilent N5423A

Agilent N5393A

6000 Series

Infiniium 8000 and


80000 series

Yes (standard HW No (software trigger)


accelerated trigger)

I2C /SPI on-screen decode

Yes

Yes

Content Search

No

Yes

Lister Window

No

Yes

Page 27

Agilent Logic Analyzer

Page 28

14

Integrate Agilent Oscilloscopes


and Logic Analyzers

16900 Series Modular


Logic Analysis Systems

Efficiently track down problems


across the analog and digital
portions of your design

13 GHz

Infiniium DSO80000
Series

1680 Series Standalone


Logic Analyzers

Infiniium 8000
Series

1690 Series PC-Hosted


Logic Analyzers

6000 Series

300 MHz
Page 29

Logic Analysis Modules

Page 30

15

16720A Pattern Generator


Module
Up to 300 MHz clock rate
Up to 16 M vectors deep
48 channels/module
Logic levels supported:
3 state TTL, ECL, 3 state CMOS, LVDS, 3 state 1.8V, 3
state 2.5V, 3 state 3.3V, 3.3V LVPECL, 5V PECL
Initialize block, step, repeat and break macros
Simulate missing components and stimulate your target

Page 31

The Probing Challenge:


Performance, Accuracy, Connectivity
Consistent Leadership in Logic Analyzer
Probing

First
Logic Analyzer

1973

3M 40-pin
Single-Ended
17 Channels

Mictor
Single-Ended
34 Channels
3pf loading
600Mb/s

Samtec
Single-Ended
Differential
34 Channels
1.5pf loading
1500Mb/s

1985

1996

2000

Soft Touch Pro


Connectorless
Single-Ended
Soft Touch
Connectorless Flying Leads Size Soft Touch Differential
34 Channels
Connectorless
Single-Ended Single-Ended
<0.7pf loading
Differential
Single-Ended
Differential
>2500Mb/s
17 Channels
34 Channels Accessories
<0.7pf loading Industry Standard
<0.7pf loading 0.9pf loading
Footprint
1500Mb/s
>2500Mb/s
>2500Mb/s

2003

2004
Page 32

16

Soft Touch Connectorless Probes


Reliable & Robust
Extremely low Loading:
<0.7pf
High Performance:
> 2.5 Gb/s data rates
Connectorless:
retention module
for mechanical
retention and
alignment
Easy Flow-thru
routing

Page 33

Agilent Logic Analyzer Probes


Unmatched Connectivity.
Soft Touch

Page 34

17

Filter Tool and Distribution Display


I dont want to dig for answers. I need answers to jump out at me.
Identify event frequency with color

Distribution of bus values over time

Page 35

Eye Finder Whats Changing


Taking Logic Analyzer Setup to the Next
Dimension
Scans at user threshold setting
Finds signal activity
Sets the sample position for each
channel

New display has intensity grading


Select if want to include voltage
scan

Page 36

18

Eye Diagrams on Every Channel


Simultaneously
Save time during measurement

Setup

setup
Automate setup/hold and
threshold settings to obtain
accurate and reliable
measurements
Scan all channels
simultaneously or just a few
View as composite display or as
individual signals
Signal Quality
Quickly find problem channels &
see skew between channels
Measure data valid windows
Identify signal integrity
problems related to rise times,
fall times, eye width,
Page 37

19

www.agilent.com.tw

www.agilent.com.tw/find/handouts

104 2 8
(02) 8772-5888
324 20
(03) 492-9666
552 12 C
(04) 2310-6914
8026251
(07) 535-5035

2005
Issued date : 04/2006
Updated data : 04/2006
Printed in Taiwan
04/2006
5989-5000ZHA