CHNG 1

Tng quan v ngn ng lp trnh

VHDL
1. Cng c pht trin VHDL
VHDL (VHSIC Hardware Description Language) l mt ngn
ng c dng m t cc h thng in t s. N c chng
trnh quc gia v cc mch tch hp tc rt cao VHSIC
(Very Hight Speed Intergated Circuit) do chnh ph M khi xng
vo u nhng nm 1980. Cc cng ty tham gia chng trnh
VHSIC nhn thy rng h cn phi c mt cng c no
thit k cc gin u vo cho cc IC chuyn dng c ln, v
h xut vic lp ra mt ngn ng m t phn cng dng
m t cu trc v chc nng ca cc mch tch hp (cn c
gi l IC- Intergated Circuit).
1.1. Gii thiu v lc s cc tiu chun VHDL
1.1.1 Chun IEEE 1076.
u nm 1980, mt nhm k s t ba cng ty IBM, Texas
Instruments v Intermetrics tp hp li hon thin cc
c im k thut ca mt ngn ng mi - phng php m t
thit k c s. Phin bn c sn dng chung ca VHDL l 7.2,
n c a ra nm 1982. Nm 1986, hip hi cc k s in
v in t, vit tt l IEEE a ra xut chun ho ngn
ng, n c thc hin nm 1987 sau ci tin v sa
i thc hin bi mt nhm i din ca cc cng ty qung

co chnh ph v cc trng i hc. Kt qu chun ho, IEEE

1076-1987, l c s cho hu ht mi m phng VHDL v sn
phm tng hp ngy nay. S ci tin v cp nht phin bn ca
ngn ng, IEEE 1076-1993, c pht hnh nm 1994, v cc
nh cung cp cng c hng ng bng cch thm cc c trng ngn ng mi ny cho cc sn phm ca h.
1.1.2 Tiu chun IEEE 1164
Tiu chun IEEE 1076 ch r ngn ng VHDL hon thin,
l mt b phn ca ngn ng m thc hin n kh khn
cho vit m t thit k linh hot. Vn chnh t s vic m
cc phn h tr ca VHDL l nhiu kiu d liu tru tng, nhng
n khng ch ra cc trc trc n gin ca chui cc tn hiu
phc tp hay cc iu kin m phng s dng ph bin, nh cc
n s v tr khng cao.
Ngay sau khi tiu chun IEEE 1076-1987 c thng qua, cc
nhm m phng bt u ci tin VHDL vi cc kiu tn hiu
mi, cho php cc khch hng ca h m phng chnh xc cc
mch in phc tp.
Nguyn do ca cc vn ny bi v cc m t thit k s
dng nhp mt m phng trong nhiu trng hp khng tng
thch vi cc iu kin m phng khc. VHDL nhanh chng
khng c chun ho. tm ra hng gii quyt vn ca
cc kiu d liu khng chun ha, cc chun khc, s 1164,
c to ra hip hi IEEE . N nh r cc ng gi chun bao
gom cc nh ngha cho mt chun kiu d liu nine-valued.

Chun d liu ny c gi l std_logic, v ng gi IEEE 1164

c s dng thng xuyn nh ng gi logic chun, hay MVL9.
Chun IEEE 1076-1987 v IEEE 1164 trong dng chun ca
VHDL c s dng rng ri ngy nay.
1.1.2.1 Tiu chun IEEE 1076.3 (tiu chun numeric)
Chun 1076.3 (thng c gi l chun Numeric hay chun
Synthesis) ch r tiu chun ng gi v s th hin cho d
liu chun VHDL ging nh cc chun lin quan ti cc phn cng
c thc. Chun ny c dng thay th cc th tc ng
gi m cc nh cung cp cng c tng hp to v phn phi
cc sn phm ca h.
Tiu chun IEEE 1076.3 khng cho ngi s dng tng hp m
chun IEEE 1164 cho ngi s dng m phng:
Tng thm kh nng ca chun IEEE 1076, trong khi thi
gian bo m tng thch gia cc cng c ca cc nh cung
cp sn phm khc nhau. Tiu chun 1076.3 bao gm nhng
ni dung c thm:
Mt ti liu gii thch phn cng ca cc gi tr lin quan
ti kiu bt v boolean c ch r bi tiu chun IEEE
1076, ging nh m t ca std_logic nh r bi tiu chun
IEEE 1164.
Mt chc nng m cung cp dont care hay will card
kim tra gi tr c s ca kiu std_logic. Tnh cht c
bit ny s dng cho s tng hp, khi ny n rt c li cho
biu din logic trong cc iu kin ca gi tr dont care.

 nh r kiu d liu s hc c du v khng c du, cng

vi kiu s hc,

dch chuyn, v kiu qu trnh hot

ng chuyn i ca cc kiu ny.

1.1.2.2 Tiu chun IEEE 1076.4 (VITAL).
S ch gii thng tin thi gian cho mt m hnh m phng
l mt v tr quan trng ca s m phng s chnh xc. Chun
IEEE 1076 m t s a dng ca cc c trng ngn ng m
c th s dng m t thi gian, tuy nhin n khng m t
mt phng php chun cho s biu din gi tr thi gian cho
thi gian ca chnh m hnh .
Kh nng chia nh cc hot ng m t ca mt s

phng m hnh t thi gian nh l quan trng cho nhiu

lp lun. Mt trong nhng chuyn ngnh mnh ca Verilog HDL
l c s lp lun m n bao gm mt c trng nh r
dng cho s ch gii thi gian.
Chun nh dng gi chm (SDF), cho php s la chn
ng lc d liu biu din trong tabular form v bao gm
trong m hnh thi gian Verilog trong thi gian m phng.
Tiu chun IEEE 1076.4, c cng b bi hip hi cc k s
in t nm 1995, thm kh nng cho VHDL nh l mt chun
ng gi. S thc y u tin sau tiu chun ny l s n lc
c thc hin mt cch d dng cho cc nh cung cp ASIC
v nhng nh cung cp cc sn phm khc to ra cc m
hnh thi gian ng dng cho c VHDL v Verilog HDL. Vi l do

ny, c s nh dng d liu ca chun IEEE 1076.4 v

Verilogs SDF l hon ton nh nhau.
1. 2. Cc cu trc c bn ca ngn ng VHDL.
Cc thnh phn chnh xy dng trong ngn ng VHDL c
chia ra thnh nm nhm c bn nh sau:
- Entity
- Architecture
- Package- Configuration
- Library
Entity: Trong mt h thng s, thng thng c thit k theo
mt s xp chng cc modul, m mi modul ny tng ng vi
mt thc th thit k (c gi l Entity) trong VHDL. Mi mt
Entity bao gm hai phn :
- Khai bo thc th ( Entity).
- Thn kin trc ( Architecture Bodies )
Mt khai bo Entity c dng m t giao tip bn ngoi
ca mt phn t (component), n bao gm cc khai bo cc
cng u vo, cc cng u ra ca phn t . Phn thn
ca kin trc c dng m t s thc hin bn trong ca
thc th .
Packages: Cc ng gi ch ra thng tin dng chung, m
cc thng tin ny c s dng bi mt vi Entity no .
Configuration: nh cu hnh, n cho php gn kt cc
th hin ca phn t no cn dng ca mt thit k no

 c dng mt cu trc v a cc th hin ny vo trong cp

Entity v Architecture.
N cho php ngi thit k c th th nghim thay i
cc s thc thi khc nhau trong mt thit k. Mi mt thit k
dng VHDL bao gm mt vi n v th vin, m mt trong cc
th vin ny c dch sn v ct trong mt th vin thit k.
1.2.1 Khai bo Entity:
Nh trn cp, phn khai bo Entity ch a ra mt ci
nhn pha bn ngoi cu mt phn t m khng cung cp
thng tin v s thc hin ca phn t nh th no. C php
khai bo ca mt Entity nh sau:
Entity entity_name is
[generic (generic_declaration);]
[port (port_declaration);]
{entity_declarative_item {constants, types, signals};}
end [entity_name];
[] : Du ngoc vung ch ra cc tham s c th la chn.
| : Du gch ng hin th mt s la chn trong s cc la
chn khc.
{}: Khai bo mt hoc nhiu cc i tng, m cc i tng ny
c th c nh ngha bi ngi dng.
a. Khai bo Generic dng khai bo cc hng m chng c
th c dng iu khin cu trc v s hot ng ca
Entity. C php ca khai bo ny nh sau:
generic ( constant_name : type [:=init_value];

{constant_name: type [:=init_value]});

y tn hng constant_name ch ra tn ca mt hng
dng generic (hng dng chung).
Kiu (Type) c dng ch ra kiu d liu ca hng.
init_value : ch ra gi tr khi to cho hng.
b. Khai bo cng ( Port ): c dng khai bo cc cng vo,
ra ca Entity.

C php ca khai bo ny nh sau:

Port ( port_name : [mode] type [:= init_value];

{ port_name: [mode] type [:=init_value]});
port_name c dng ch ra tn ca mt cng, mode
ch ra hng vo ra ca tn hiu ti cng . Type ch ra kiu
d liu ca mt cng v init_value ch ra gi tr khi to cho
cng .
Ch ! VHDL khng phn bit ch hoa v ch thng,
chng hn nh : xyz = xYz = XYZ.
* C bn mode c s dng trong khai bo cng :
- in : Ch c th c c, n ch c dng cho cc tn hiu
u vo ( ch c php nm bn phi php gn )
- out : Ch c dng gn gi tr, n ch c dng cho cc
cng u ra ( N ch c nm bn tri ca php gn ).
- inout : C th c dng c v gn gi tr. N c th c
nhiu hn mt hng iu khin ( C th nm bn tri hoc
bn phi php gn ).
- Buffer : C th c dng c v gn gi tr. ( C th nm
bn tri hoc bn phi php gn ).

inout l mt cng hai hng, cn Buffer l mt cng khng c

hng.
c. entity_declarative_item : c dng khai bo cc hng, kiu
d liu, hoc tn hiu m n c th c s dng trong khi
thc hin ca mt Entity.
d. V d :
* V d v khai bo cc cng vo ra:
entity xxx is
port ( A : in integer ;
B : in integer ;
C : out integer ;
D : inout integer ;
E : buffer integer) ;
end xxx;
architecture bhv of xxx is
begin
process (A,B)
begin
C <= A ; -- ( Cu lnh ng: A c gn cho C ).
A <= B ; -- ( Cu lnh sai: A l mt u vo ).
E <= D + 1; -- ( Cu lnh ng: D mode inout v vy n c
th c gn v c )
D <= C + 1; -- ( Cu lnh sai : C l cng u ra nn khng
th c c cho u vo ).
end process;

end bhv;
* V d v khai bo Entity:
A

COUT

FULL_ADDER

CIN

SUM

Hnh trn ch ra mt giao din ca mt b cng mt bit. Tn

Entity ca phn t ny l FULL_ADDER. N bao gm cc cng
u vo A, B v CIN. Cc cng ny c kiu d liu l kiu Bit,
cn cc cng u ra SUM v COUT cng mang kiu d liu l
kiu BIT. Ngn ng VHDL dng din t giao din ny nh
sau:
Entity FULL_ADDER is
port ( A, B, CIN : in BIT;
SUM, COUT : out BIT );
End FULL_ADDER ;
Chng ta c th iu khin cu trc cng nh thi gian ca
mt Entity bi vic s dng cc hng generic. V d sau s ch
ra vic iu khin ny, trong v d ny hng N c dng
ch ra s bt ca mt b cng. Trong qu trnh m phng

hoc qu trnh tng hp, gi tr thc t cho mi hng dng

chung generic c th b thay i.
entity ADDER is
generic (N : INTEGER := 4);
M : TIME := 10ns);
port ( A, B : in BIT_VECTOR (N -1 downto 0 );
CIN : in BIT;
SUM : out BIT_VECTOR (N-1 downto 0);
COUT : out BIT );
end ADDER;
Giao din m t b cng ny nh sau:
A (3)

B (3)

COUT

A (2)

B (2)

A (1)

B (1)

A (0)

B (0)

CIN

FULL _ ADDER

SUM (3)

SUM (2)

SUM (1)

SUM (0)

1.2.2. Cc kiu kin trc ( ARCHITECTURES ):

Mt kin trc a ra kt cu bn trong ca mt Entity. Mt
Entity c th c nhiu hn mt kin trc, n ch ra quan h

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gia cc u vo v u ra ca mt Entity m quan h ny

c din t theo cc thut ng sau :
- Kiu hnh vi hot ng ( Behavioural ).
- Kiu hot ng ca cc lung d liu ( Dataflow ).
- Kiu cu trc ( Structure ).
Mt kin trc xc nh chc nng ca mt Entity. N bao
gm phn khai bo ( Khai bo cc cc tn hiu, hng, khai bo
cc kiu, cc phn t, tip theo l cc pht biu ng thi ).
Khai bo mt kin trc s dng c php sau:
architecture architecture_name of entity_name is
{ architecture_declarative_part }
Begin
{concurrent_statement}
end [ architecture_name ];
1.2.2.1. Kin trc theo kiu hnh vi hot ng
( Behavioural ):
Mt kin trc kiu hnh vi hot ng ch ra cc hot ng
m mt h thng ring bit no phi thc hin trong mt
chng trnh, n ging nh vic din t cc qu trnh hot
ng, nhng khng cung cp chi tit m thit k c thc thi
nh th no. Thnh phn ch yu ca vic din t theo kiu
hnh vi trong VHDL l process. Di y l v d ch ra kiu
din t theo kiu hnh vi ca mt b cng vi tn l
FULL_ADDER.

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architecture BEHAVIOURAL of FULL_ADDER is

begin
process (A,B,CIN)
begin
if ( A ='0' and B ='0' and CIN='0' ) then
SUM <= '0'

COUT <= '0' ;

elsif
(A='0' and B='0' and CIN='1') or
(A='0' and B='1' and CIN='0') or
(A='1' and B='0' and CIN='1') then
SUM <= '1';
COUT <= '0' ;
elsif (A='0' and B='1' and CIN='1') or
(A='1' and B='0' and CIN='1') or
(A='1' and B='1' and CIN='0') then
SUM <= '0';
COUT <= '1';
elsif (A='1' and B='1' and CIN='1') then
SUM <='1';
COUT <='1';
end if;
end process;
end BEHAVIOURAL;

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1.2.2.2 Kin trc theo kiu hot ng ca cc lung

d liu:
Mt kin trc kiu lung d liu ch ra mt h thng di
dng m t ng thi ca cc lung iu khin v dch
chuyn ca d liu. N s dng theo mu thng tin hoc mu
hot ng ca lung d liu , hoc mu thi gian ca cc
chc nng logic t hp. Chng hn nh cc b cng, b so snh,
b gii m, v cc cng logic nguyn thu.
V d :
architecture DATAFLOW of FULL_ADDER is
signal S : BIT;
begin
S <= A xor B ;
SUM <= S xor CIN after 10 ns;
COUT <= (A and B ) or (S and CIN) after 5ns;
end DATAFLOW;

1.2.2.3. Kin trc kiu cu trc:

Mt kin trc kiu cu trc ch ra s thc thi cu trc theo
dng s dng cc khai bo phn t v cc th hin ca phn t
. V d di y ch ra s din t cu trc ca mt b cng
FULL_ADDER nh trn gii thiu. Hai kiu phn t c s dng
trong v d ny l HALF_ADDER v OR_GATE.

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architecture STRUCTURE of FULL_ADDER is

component HALF_ADDER
port (L1, L2 : in BIT;
CARRY, SUM : out BIT);
end component;
component OR_GATE
port (L1, L2 : in BIT;
O: out BIT);
end component;
begin
HA1: HALF_ADDER port map (A,B,N1,N2);
HA2: HALF_ADDER port map (N2,CIN,N3,SUM);
OR1 : OR_GATE port map (N1, N3,COUT);
end STRUCTURE;
v d ny Entity mc cao nht s cha hai th hin ca
HALF_ADDER v mt th hin ca OR_GATE. Th hin
HALF_ADDER c th b rng buc vi mt Entity khc, m Entity
ny bao gm mt cng XOR v mt cng AND. Giao tip ca
mt b cng HALF_ADDER c dng nh sau:
L1

L2

X1

SUM

A1

CARRY

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B cng ny gm c hai u vo L1 v L2 , u ra l SUM

v CARRY. Kiu BIT l kiu tin nh ngha ca ngn ng
VHDL, n c kiu lit k dng ch k t nh '0' v '1'.
1.3. Cc kiu ng gi ( Packages ):
Mc ch chnh ca Package l tp hp cc phn t c th
b chia s bi hai hay nhiu n v thit k ( hay cc phn t
c th dng chung c). N c cha cc kiu d liu, cc hng,
cc chng trnh con c th dng chung gia cc thit k. Mt
Package c cha hai phn chnh:
- Phn khai bo Package.
- Phn thn Package.
1.3.1. Phn khai bo Package
Mt khai bo Package c dng ct gi hng lot cc khai
bo dng chung, chng hn nh cc phn t, cc kiu, cc th
tc, cc hm. Cc khai bo ny c th nhp vo cc n v
thit k khc bi vic s dng mt mnh use.
V d :
package EXAMPLE_PACK is
type SUMMER is ( MAY, JUN, JUL, AUG, SEP);
component D_FLIP_FLOP
port (D, CK: in BIT;
Q, QBAR: out BIT)
end component;
constant PIN2PIN_DELAY:TIME:=125ns;
function IN2BIT_VEC(INT_VALUE:INTEGER)

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return BIT_VECTOR;
end EXAMPLE_PACK;
v d ny tn ca package c khai bo l EXAMPLE_PACK.
N c cha cc khai bo kiu, phn t, hng v hm. Lu rng
hot ng ca hm INT2BIT_VEC khng xut hin trong khai
bo gi, m ch c giao tip ca hm xut hin. Vic nh
ngha, hay thn ca hm ch xut hin trong thn ca ng
gi ( Body Package ).
Gi s rng ng gi ny c dch v to thnh mt th
vin thit k v c gi l DESIGN _LIB . Xem xt vic dng
mnh use s dng chng di y:
library DESIGN_LIB;
use DESIGN_LIB.EXAMPLE_PACK.all
Entity RX is.........
Mnh library DESIGN_LIB cho php th vin thit k
DESIGN_LIB c php dng trong phn m t ny, iu c
ngha l tn DESIGN_LIB c th c s dng. Mnh use
tip theo s ly tt c cc khai bo c trong Package
EXAMPLE_PACK vo trong khai bo Entity ca RX. C ngha l ta
c th chn la cc khai bo t trong mt cc khai bo ca mt
ng gi vo trong mt n v thit k khc. V d :
library DESIGN_LIB;
use DESIGN_LIB.EXAMPLE_PACK.D_FLIP_FLOP;
use DESIGN_LIB.EXAMPLE_PACK.PIN2PIN_DELAY;

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architecture RX_STRUCTURE of RX is.........

Hai mnh use v d ny nhm to ra khai bo cho
D_FLIP_FLOP v khai bo hng cho PIN2PIN_DELAY c php s
dng trong thn kin trc.
1.3.2. Phn khai bo thn Package.
S khc bit gia khai bo Package v thn Package cng
ging nh s khc bit gia khai bo ca mt Entity v phn
thn kin trc Architecture ca chng. C php khai bo ca
Package nh sau:
package package_name is
{package_declarative_item}
end [package_name ];
package body package_name is
{package_declarative_item}
end [package_name]
Mt thn package c dng lu cc nh ngha ca mt
hm v th tc, m cc hm v th tc ny chng c khai
bo trong phn khai bo package tng ng. V vy phn thn
package lun c kt hp vi phn khai bo ca chng, hn na
mt phn khai bo package lun c t nht mt phn thn
package kt hp vi chng.
V d : package EX_PKG is
subtype INT8 is integer range 0 to 255;

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constant zero : INT8:=0;

procedure Incrementer (variable Count : inout
INT8);
end EX_PKG;
package body EX_PKG is
procedure Incrementer (variable Data : inout INT8)
is
begin
if (Count >= MAX ) then
Count:=ZERO;
else Count:= Count +1;
end if;
end Incrementer;
end EX_PKG;
1.4. nh cu hnh ( Configurations )
Mi mt Entity bao gm nhiu kin trc khc nhau. Trong qu
trnh thit k, ngi thit k c th mun th nghim vi cc
s bin i khc nhau ca thit k bng vic chn la cc
kiu kin trc khc nhau. Configuration c th c s dng
cung cp mt s thay th nhanh cc th hin ca cc phn t
( Component ) trong mt thit k dng cu trc. C php khai
bo ca Configuration ny nh sau:
Configuration configuration_name of entity_name is
{configuration_decalarative_part}
For block_specification

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{use_cluse}
{configuration_item}
end for;
Vi mt Entity ca b cng FULL_ADDER nh gii thiu
phn trn, v d ny ta c th s dng chng trong php
nh cu hnh nh sau:
configuration FADD_CONFIG of FULL_ADDER is
For STRUCTURE
for HA1, HA2 : HALF_ADDER use entity
burcin.HALF_ADDER(structure);
for OR1: OR_GATE use entity
burcin.OR_GATE;
end for;
end FADD_CONFIG;
y tn ca php nh cu hnh l tu , v d ny ta
ly tn l FADD_CONFIG, cn vi dng lnh For STRUCTURE
ch ra kin trc c nh cu hnh v c s dng vi thc
th Entity FULL_ADDER. Gi s rng chng ta dch hai thc
th HALF_ADDER v OR_GATE thnh th vin vi tn l burcin v
s dng chng trong v d trn.
1.5. Cc th vin thit k
Kt qu ca vic bin dch VHDL l chng c ct gi bn
trong cc th vin dng cho bc m phng tip theo, iu
ny ging nh vic s dng mt phn t c khai bo trong

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mt thit k khc. Mt th vin thit k c th cha cc n v

th vin nh sau:
- Cc ng gi Packages
- Cc thc th Entity
- Cc kiu kin trc Architectures
- Cc php nh cu hnh Configurations.
Ch ! VHDL khng h tr cc th vin theo th bc.
Bn c th c nhiu th vin nh theo mun nhng khng
c khai bo lng nhau!
m mt th vin v truy cp chng nh mt Entity c
bin dch trong mt thit k VHDL mi, iu u tin cn lm
l phi khai bo tn th vin. C php ca chng nh sau:
Library library_name : [path/directory_name];
Bn c th truy cp cc n v c bin dch t mt th
vin VHDL ti ba mc nh sau:
library_name.Package_name.item_name
V d: Gi s chng ta to mt ng gi ct mt hng
m hng ny c s dng trong nhiu thit k, sau dch n
v ct vo trong th vin vi tn l burcin .
Package my_pkg is
constant delay: time:=10ns;
end my_pkg;
Tip n chng ta gi my_pkg s dng chng trong
thit k di y:
architecture DATAFLOW of FULL_ADDER is

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signal S : BIT;
begin
S <= A xor B;
SUM <= S xor CIN after burcin.my_pkg.delay;
COUT <= (A and B ) or (S and CIN) after 5ns;
end DATAFLOW;
1.6. Cc i tng d liu :
Mt i tng d liu gi mt gi tr ca mt kiu nht
nh. Trong VHDL c ba lp i tng d liu :
- Cc hng ( Constants ).
- Cc bin ( Variables ).
- Cc tn hiu ( Signals ).
Lp cu mt i tng c ch ra bi mt t kho v n c
ch ra im bt u ca mt khai bo.
1.6.1. Cc hng ( Constant )
Mt hng n l mt i tng m n c khi to ch ra
mt gi tr c nh v n khng b thay i. Khai bo hng
c php khai bo trong cc ng gi, cc Entity, cc kin trc,
cc chng trnh con, cc khi v trong pht biu ca cc qu
trnh processes.
C php khai bo chng nh sau :
Constant constant_name {constant_name}: type [:= value];
V d :
constant YES : BOOLEAN:= TRUE;
constant CHAR7: BIT_VECTOR (4 downto

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0 ):="00111";
constant MSB: INTEGER:=5;
1.6.2. Cc bin
Cc bin c dng lu d liu tm thi, chng ch c
php khai bo trong pht biu Process hoc cc chng trnh
con.
V d :
variable X,Y : BIT;
variable TEMP: BIT_VECTOR (8 downto 0) ;
variable DELAY : INTERGER range 0 to 15:=5;
1.6.3. Cc kiu tn hiu ( Signal ):
Tn hiu c dng kt ni cc Entity ca thit k li vi
nhau v trao i cc gi tr bin i trong pht biu
process. Chng c th c xem nh cc dy dn hay cc bus ni
trong mch thc t. Tn hiu c th c khai bo trong cc
ng gi ( Package ), trong cc khai bo Entity, trong khai bo
kin trc (Architecture), trong cc khi ( Block ). Vi cc tn
hiu c khai bo trong cc package th tn hiu ny c gi
l tn hiu ton cc ( Cc thit k c th s dng chng ), cc
tn hiu c khai bo trong Entity l tn hiu ton cc trong
mt Entity, tng t vi tn hiu c khai bo trong mt kin
trc, n l tn hiu dng chung trong mt kin trc .
C php ca chng c dng nh sau :
Signal Signal_name {,signal_name}: type [:=value];
V d :

22

signal BEEP : BIT:= '0';

signal TEMP: STD_LOGIC_VECTOR (8 downto 0);
signal COUNT: INTEGER range 0 to 100 :=5;
1.7. Cc kiu d liu
Tt c cc i tng d liu trong VHDL cn phi c nh
ngha vi mt kiu d liu. Mt khai bo kiu phi ch ra tn
v di ca kiu . Khai bo kiu d liu chng c php khai
bo trong phn khai bo cc ng gi, trong phn khai bo
Entity, trong phn khai bo kin trc, trong phn khai bo cc
chng trnh con v trong phn khai bo cc Process. Cc kiu
d liu bao gm cc kiu sau:
- Kiu lit k
- Kiu nguyn.
- Cc kiu d liu tin nh ngha.
- Kiu mng.
- Kiu bn ghi.
- Kiu d liu chun logic.
- Kiu d liu c du v khng du.
- Cc kiu ph.
1.7.1. Cc kiu lit k ( ENUMERATION )
Mt kiu lit k c ch ra bi vic lit k cc gi tr cho
php ca kiu . Tt c cc gi tr c nh ngha bi ngi
dng c th l cc tn nh danh, hoc cc cc kiu ch k t .
Tn nh danh thc cht l mt tn do ngi dng t ra,

23

chng hn nh blue, ball, monday. Kiu ch k t l kiu ca

cc k t c km theo du ngoc n, chng hn nh 'x', ' 0'...
C php khai bo cu chng nh sau:
Type type_name is (enumerattion_literal {,
enumeration_literal});
Vi type_name l mt tn nh danh v mi
enumerattion_literal hoc l mt tn nh danh hoc l mt
ch k t.
V d :
type COLOR is (RED, ORANGE, YELLOW, GREEN, BLUE,
PURPLE);
type DAY is (MONDAY,
TUESDAY,WEDNESDAY,THURDAY,FRIDAY);
type STD_LOGIC is ('U','X','0','1','Z','W','L','H','_');
Mi mt nh danh trong mt kiu u c mt v tr nht
nh trong kiu, chng c xc nh bi th t xut hin cu
chng trong kiu . Trong v d trn, mc nh RED c v
tr 0, ORANGE s c v tr 1 ..... Nu chng ta khai bo mt i
tng d liu vi kiu l COLOR v khng nh ngha gi tr
khi to th i tng d liu s c khi to mc nh v tr
u tin ca kiu lit k ( V tr khng ), trong trng hp ny
COLOR s nhn gi tr RED.
1.7.2. Kiu nguyn

24

Kiu nguyn l cc kiu s nguyn, chng c dng cho cc

php tnh, cc ch s, cc iu khin s vng lp. Trong hu
ht cc kiu thc thi trong VHDL c di t - 2,147,483,647
n + 2, 147, 483,647. C php ca chng c khai bo nh
sau:
type type_name is range - 2,147,483,647 to + 2, 147,
483,647;
V d :
type INTEGER is range - 2,147,483,647 to + 2, 147, 483,647;
type COUNT is range 0 to 10;
1.7.3. Cc kiu d liu tin nh ngha trong VHDL
IEEE nh ngha hai gi d liu STANDART v TEXTIO trong
th vin STD. Mi mt gi d liu ny c cha mt lot cc kiu
v cc php tnh chun . Di y l cc kiu d liu c nh
ngha trong gi STANDARD:
- BOOLEAN: Mt kiu lit k vi hai gi tr true v False, cc thao
tc Logic v cc php ton quan h s tr v gi tr Boolean.
- BIT : Mt kiu lit k vi hai gi tr '0' v '1' , cc php tnh
logic c th ly v tr v gi tr kiu BIT.
- CHARACTER: Kiu lit k ca cc m ASCII.
- INTEGER : c dng miu t cc s m v dng. Di hot
ng ca chng c n nh t - 2.147.438.647 n
2.147.438.647. Cc hm ton hc nh cng, tr, nhn, chia c
h tr kiu nguyn.

25

- NATURE: Cc kiu con ca kiu nguyn c dng miu t

cc s kiu t nhin ( khng m ).
- POSITIVE: Cc kiu con ca kiu nguyn c dng miu t
cc s dng.
- BIT_VECTOR : c dng miu t mt mng cc gi tr kiu
BIT.
- STRING : Mt mng cc k t, mt gi tr kiu chui c i
km bi du ngoc kp.
- REAL: c dng m t cc kiu s thc, di hot ng t1.0E+38 n +1.0E+38.
- Kiu thi gian vt l : M t cc gi tr thi gian c dng trong
m phng.
C mt vi kiu d liu c nh ngha trong gi
STANDARD nh sau:
Type BOOLEAN is ( fase, true);
Type BIT is

( '0', '1' );

Type SEVERITY_LEVEL is (note, warning, error, failure

);
Type INTEGER is range -2147483648 to 2147483648;
Type REAL is Range -1.0E38 to 1.0E38;
Type CHARACTER is (nul, soh, stx, eot, enq, ack,
bel,............);
1.7.4. Kiu mng
Kiu mng l kiu ca nhm cc phn t c cng kiu ging
nhau. C hai kiu mng nh sau:

26

- Kiu mng c gn kiu .

- Kiu mng khng b gn kiu.
Kiu mng b gn kiu l kiu m cc ch s mng ca
chng c nh ngha tng minh. C php ca chng nh sau:
type array_type_name is array (discrete_range) of
subtype_indication;
y array_type_name l tn ca kiu mng c p kiu,
discrete_range kiu ph ca kiu nguyn khc hoc kiu lit
k, subtype_indication chnh l kiu ca mi phn t ca mng.
Kiu mng khng b gn kiu l kiu m ch s mng ca
chng khng b ch ra, nhng cc kiu ch s ca chng phi
c ch ra. C php ca chng c ch ra nh sau:
type array_type_name is array (type_name range <>) of
subtype_indication;
V d :
type A1 is array ( 0 to 31) of INTEGER;
type Bit_Vector is arrray (NATURAL range <>) of BIT;
type STRING is array (POSITIVE range <>) of CHARACTER;
A1 l mt mng gm ba hai phn t m trong mi phn
t l mt kiu nguyn. Mt v d khc ch ra kiu Bit_vector v
kiu String c to ra trong chun cc gi STANDARD.
V d : subtype B1 is BIT_VECTOR (3 downto 0);
variable B2 : BIT_VECTOR (0 to 10);
Di ch s xc nh s phn t trong mng v hng ca
chng ( low to high | high to low ).

27

VHDL cho php khai bo cc mng nhiu chiu c th

dng khai bo cc mu RAM v ROM. Xem v d di y:
type Mat is array (0 to 7, 0 to 3) of BIT;
constant ROM : MAT : = (( '0', '1', '0', '1'),
('1', '1', '0', '1' ),
('0', '1', '1', '1' ),
('0', '1' , '0', '0' ),
('0', '0' ,'0' , '0'),
('1', '1' , '0', '0' ),
('1', '1' , '1', '1' ),
('1', '1' , '0', '0' );
X := ROM (4,3);
Bin X s ly gi tr '0' c t m.
1.7.5. Kiu Record
Kiu record l mt nhm c nhiu hn mt phn t c cc
kiu khc nhau. Phn t ca Record bao gm cc phn t ca
bt c kiu no, n c th l cc kiu mng hoc kiu Record.
V d :
type DATE_TYPE is ( SUN, MON, TUE , WED , THR , FRI , SAT) ;
type HOLIDAY is
record
YEAR : INTEGER range 1900 to 1999;
MONTH : INTEGER range 1 to 12 ;
DAY : INTEGER range 1 to 31;
DATE : DATE_TYPE;

28

end record ;
signal S : HOLIDAY;
variable T1: integer range 1900 to 1999;
variable T2 : DATE_TYPE;
T1: = S .YEAR;
T2:= S . DATE;
S . DAY <= 30;
1.3.6. Cc kiu STD_LOGIC :
to mu cc ng tn hiu c nhiu hn hai gi tr ( '0' ,
'1' ), VHDL nh ngha chn khong trong gi chun. Chn gi
tr bao gm :
type STD_LOGIC is

( 'U' -- khng khi to gi tr

'X' -- Khng xc nh
'0' -- Kiu mc thp
'1' -- Kiu mc cao
'Z' -- Kiu tr khng cao
'W' -- Khng xc nh mc yu
'L' -- Mc thp yu
'H' -- Mc cao yu
'_' -- Khng quan tm n gi tr .);

Tng t nh kiu BIT v kiu BIT_VECTOR, VHDL cung cp

mt kiu khc gi l STD_LOGIC_VECTOR.
s dng cc nh ngha v cc hm trong gi chun
logic, cc pht biu sau y cn c phi khai bo nh km
theo chng trnh .

29

Library IEEE;
USE IEEE.STD_LOGIC_1164.all;

1.3.7. Cc kiu d liu khng du v c du

Cc kiu d liu c du v khng du chng c ch ra
trong cc gi chun NUMERIC_BIT v NUMERIC_STD. Cc i tng vi kiu c du v khng du chng c hiu nh l cc s
nguyn binary khng du v cc i tng vi kiu c du v
chng c dch nh cc nguyn b hai .
Vic nh ngha ca cc kiu d liu c ch ra nh sau:
type signed is array (NATURAL range <>) of
BIT/STD_LOGIC;
Cc pht biu di y bao gm cc khai bo vic s dng
ca cc kiu d kiu c du v khng du.
Library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_BIT.all;
use IEEE.NUMERIC_STD.all;
1.7.8. Cc kiu con
VHDL cung cp cc cc kiu con m cc kiu con ny chng
c nh ngha trong cc nh cc tp ph trong mt kiu khc.
Bt c u c mt khai bo kiu th c th xut hin
mt nh ngha kiu con. Kiu NATURAL v kiu POSITIVE l

30

mt kiu ph hay kiu con ca kiu nguyn v chng c th c dng vi bt k mt hm nguyn no.
V d :
subtype INT4 is INTEGER range 0 to 15;
subtype BIT_VECTOR6 is BIT_VECTOR (5 downto
0);
1.8. Cc ton t
VHDL cung cp 6 lp ton t , mi mt ton t c mt mc u
tin nht nh. Tt c cc ton t trong cng mt lp th c cng
mt mc u tin.
Mc
u
tin
thp

Cc ton t

Cc ton hng

nht
.

Logical_operator

and

or

Cng kiu

nand

Cng kiu

Cng kiu

31

nor

Cng kiu

xor

Cng kiu

Cng kiu

Relational _

/=

Cng kiu

operator

<

Cng kiu

<=

Cng kiu

>

Cng kiu
Cng kiu

concatenation_op

>=
&

erator

Cng kiu

arithmetic_operat

Cng kiu

or
arithmetic_operat

Bt k kiu s no

or
arithmetic_operat

Bt k kiu s no
Cng kiu

or

Cng kiu

mod

integer
integer
Kiu m integer

Mc

arithmetic_operat

rem
**

or

abs

Bt k kiu s no

not

Cng kiu

tin
cao

Logical_operator

nht
1.8.1. Cc ton t logical
Kiu ton t logic khng chp nhn cc ton hng l cc kiu
tin nh ngha nh kiu BIT, BOOLEAN v cc kiu mng cc
bit, cc ton hng cn phi l cng kiu v cng di.

32

V d :
signal A,B : BIT_VECTOR (6 downto 0);
signal C,D,E,F,G: BIT;
A<= B and C ; -- Khng xy ra v cc ton hng
khng cng kiu.
D <= (E xor F) and (C xor G);
1.4.2. Cc ton t quan h
Cc ton t quan h cho ta kt qu c kiu Boolean, cc ton
hng cn phi c cng kiu v cng di.
V d :
signal A,B : BIT_VECTOR (6 downto 0);
signal C: BOOLEAN;
C <= B <= A; ( Tng ng nh C <= (B<=A));
1.4.3. Cc ton t cng
Cc ton t cng bao gm "+", "-" , v "&" , trong ton t
"&" l ton t kt ni chui v cc i tng l mng cc thanh
ghi. Vi s c du v khng du c th c dng vi cc s
nguyn v cc kiu BIT_VECTOR.
V d :
signal W: BIT_VECTOR (3 downto 0);
signal X: INTEGER range 0 to15;
signal Y,Z : UNSIGED (3 downto 0);
Z <= X + Y + Z;
Y <= Z (2 downto 0) & W(1);

33

"ABC" & "xyz" cho kt qu l : "ABCxyz"

"1010" & "1" cho kt qu l : "10101"
1.5. Cc kiu ton hng
Trong mt biu thc cc ton t s dng cc ton hng
tnh ton cc gi tr ca chng. Cc ton hng trong mt biu
thc bao gm :
- Kiu ch
- Kiu nh danh
- Cc tn c nh theo ch s
- Tn cc Slice
- Tn cc c tnh
- Cc biu thc iu kin
- Cc li gi hm
- Cc biu thc chuyn i
1.9.1. Kiu ch
Cc kiu ch c th chia ra thnh hai nhm chnh :
- Kiu v hng
. Kiu k t
. Kiu BIT
. Kiu chun STD_LOGIC
. Kiu Boolean
. Kiu s thc
. Kiu nguyn
. Kiu thi gian
- Kiu mng

34

. Kiu chui
. Kiu BIT_VECTOR
. STD_LOGIC_VECTOR
1.9.1.1. Kiu ch k t
Kiu ch k t ch ra mt gi tr bng vic s dng mt k
t n v km theo mt du ngoc n. Nhn chung VHDL
khng quan tm n cc trng hp ch thng v ch hoa, tuy
nhin vi kiu ch k t cn phi phn bit ch thng v ch
hoa. V d : 'a' hon ton khc vi kiu 'A' trong kiu ch k t.
Kiu ch k t c th c dng nh ngha bt c kiu
no trong cc ng gi chun v gi tr mc nh ca chng
l Null.
V d : 'A' , 'a' , ......'1' .
Kiu ch k t khng phi l kiu bit k t nh '1' hoc kiu
nguyn 1, v vy kiu ch l t cn phi c cung cp mt tn
kiu no .
1.9.1.2. Kiu chui
Mt kiu chui k t thc cht l mt mng cc k t. Mt
chui cc k t c nh ngha trong mt du ngoc kp .
V d : "A" , " hold time error ", " x " ....
1.9.2. Kiu BIT
Kiu bit l kiu m t hai gi tr ri rc bng vic s dng cc
ch k t '0' v '1'. i khi cc kiu Bit ny c dng to ra

35

kiu ch bit mt cch tng minh dng phn bit chng vi

cc kiu k t.
V d : '1' , ' 0 ' , bit' ('1')
1.9.3. Kiu BIT_VECTOR
Kiu bit_vector l mt mng cc bit m chng c t trong
du ngoc kp.
V d : "01001111000" , x"00FFF0" , b"100010101" ,
o"277756"...
Trong v d trn ch 'x' c dng din t cc gi tr s
hexa, cn 'b' c dng m t kiu binary, cn 'o' c dng
cho h m c s 8.
1.9.4. Kiu ch trong ng gi chun STD_LOGIC
Kiu ch logic chun l mt trong 9 gi tr c nh ngha
trong ng gi chun v c a ra di dng cc ch in hoa v
t trong du ngoc n .
V d : ' U ' khng trng vi
'X','0','1','Z','W','L','H','_'
1.9.5. Kiu ch STD_LOGIC_VECTOR
Mt kiu ch STD_LOGIC_VECTOR thc cht l mt mng bao
gm cc phn t ca kiu std_logic v c t trong du
ngoc kp.
V d : " 10_1Z" , " UUUUU " , signed("1011 ").....
1.9.6. Kiu Boolean
Kiu Boolean c dng m t hai gi tr ri rc, l
kiu true v false.

36

V d : true , false , True , TRUE, FALSE ...

1.9.7. Kiu s thc
Kiu s thc l kiu c dng din t cc s thc nm
trong khong t -1.0E+38 n +1.0E+38.
Mt kiu s hc c th l kiu dng hoc m nhng chng
phi c du chm thp phn .
V d : + 1.0 khng c vit '1' hoc 1 hoc ' 1.0 '
0.0 khng c vit 0
-1.0 , -1.0E+10.
1.9.8. Kiu nguyn
Mt kiu nguyn c dng din t cc s nguyn nm
trong khong t - 2,147,438,647 n + 2,147,438,647.
V d : +1 , 862 862.0 , - 257 , + 123_456 , 16 # 00FF #.
Trong cc k hiu c dng nh ngha kiu nh sau:
" C s_n # s din t trong c s n ", y n nm trong
h 2 n 16.
1.9.9. Kiu TIME
Mt kiu vt l duy nht c nh ngha trc trong ng gi
chun, l thi gian time.
V d : 10 ns , 100 us , 6.3 ns ..... Ch phn s phi c vit
cch phn n v o bi mt khong trng.

37

38