Professional Documents
Culture Documents
Volume: 3 Issue: 5
ISSN: 2321-8169
2685 - 2689
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I.
INTRODUCTION
Logic Value
0
Vdd
0
1
Vdd
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IJRITCC | May 2015, Available @ http://www.ijritcc.org
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ISSN: 2321-8169
2685 - 2689
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TABLE II
TRUTH TABLE OF TERNARY INVERTERS
Input X
STI
PTI
NTI
A. Ternary Inverter
A general ternary inverter is an operator (gate) with one input
x, and three outputs (denoted by y0, y1 , and y2 ) such that
(5)
(2)
(4)
Input X2
YNAND
YNOR
(7)
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IJRITCC | May 2015, Available @ http://www.ijritcc.org
_______________________________________________________________________________________
ISSN: 2321-8169
2685 - 2689
_______________________________________________________________________________________________
B
A
Decoder
Decoder
A<B
A=B
A>B
A2 A1 A0
B2 B 1 B 0
A
0
0
0
1
1
1
2
2
2
B
0
1
2
0
1
2
0
1
2
SUM
0
1
2
1
2
0
2
0
1
CARRY
0
0
0
0
0
1
0
1
1
B
Decoder
(8)
TABLE IV
TRUTH TABLE OF TERNARY 1BIT-COMPARATOR
A
0
0
0
1
1
1
2
2
2
B
0
1
2
0
1
2
0
1
2
A<B
0
2
2
0
0
2
0
0
0
A=B
2
0
0
0
2
0
0
0
2
A>B
0
0
0
2
0
0
2
2
0
SUM
CARRY
A2 A1 A0
B2 B 1 B 0
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ISSN: 2321-8169
2685 - 2689
_______________________________________________________________________________________________
III.
Full Adder
A 1-bit ternary full adder adds two ternary numbers and
previously calculated carry which here denoted as Cin. This
circuit produces a 2-bit output sum represented by the
signals Cout and SUM. A ternary full adder can be
implemented by cascading two ternary half adder circuits.
Fig.4 shows the ternary full adder block diagram using two
ternary half adders block. Here the first half adder adds 2
input bits A and B. The following half adder adds the sum
output of A and B inputs with past carry (Cin) and generates
sum bit and one carry bit in its output. The final carry bit
(Cout) is generated by the OR operation between the two
carry bits generated from the two stages (first half adder and
the second half adder). Fig. (7) shows the waveforms of the
designed ternary full adder circuit. Table VI shows the truth
table of the Ternary full-adder.
2
2
2
2
2
2
2
2
0
0
1
1
1
2
2
2
1
2
0
1
2
0
1
2
0
1
0
1
2
1
2
0
1
1
1
1
1
1
1
2
V.SIMULATION RESULTS
B
0
0
0
1
1
1
2
2
2
0
0
0
1
1
1
2
2
2
0
CIN
0
1
2
0
1
2
0
1
2
0
1
2
0
1
2
0
1
2
0
SUM
0
1
2
1
2
0
2
0
1
1
2
0
2
0
1
0
1
2
2
COUT
0
0
0
0
0
1
0
1
1
0
0
1
0
1
1
1
1
1
0
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ISSN: 2321-8169
2685 - 2689
_______________________________________________________________________________________________
VI.CONCLUTION
This paper presented the design of ternary logic arithmetic
circuits based on Carbon Nano-tube Field Effect Transistor
(CNTFET). This is the future technology to the predominant
CMOS Technology, the major drawback of traditional CMOS
technology is scaling of its size. Less power dissipation was
observed in the CNTFET-based ternary logic circuits than the
CMOS technology. The threshold voltage of CNTFET is
depends on its diameter, so we can easily control on threshold
voltage rather than CMOS. By the above points we conclude
that, CNTFET based ternary circuit design is a promising
circuit element in MVL circuits in the near future.
REFERENCES
[1] S. Lin,Y. B. Kim, and F. Lombardi, The CNTFETbased design of ternary logic gates and arithmetic
circuits, IEEE Trans. Nanotechnol., vol.10, no. 2,
pp.217-225, Mar.2011.
[2] T. Araki, H. Tatsumi, M. Mukaidono, and F.
Yamamoto, Minimization of incompletely specified
regular ternary logic functions and its application to
fuzzy switching functions, in Proc. IEEE Int. Symp.
Multiple-Valued Logic, May, 1998, pp. 289296.
[3] P. C. Balla and A. Antoniou, Low power dissipation
MOS ternary logic family, IEEE J. Solid-State
Circuits, vol. 19, no. 5, pp. 739749, Oct.1984.
[4] Y. Yasuda, Y. Tokuda, S. Taima, K. Pak, T.
Nakamura, and A. Yoshida, Realization of
quaternary logic circuits by n-channel MOS devices,
IEEE J. Solid-State Circuits, vol. 21, no. 1, pp. 162
168, Feb. 1986.
[5] J. Appenzeller, Carbon nanotubes for highperformance electronics Progress and prospect,
Proc. IEEE, vol. 96, no. 2, pp. 201211, Feb. 2008.
[6] A. Akturk, G. Pennington, N. Goldsman, and A.
Wickenden, Electron transport and velocity
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