2014 Fifth International Symposium on Electronic System Design

A Resolution Independent 2 bits-per-cycle SAR

ADC
Anish Morakhia , Sridhar Gunnam , Preejit Prakash , Sneha Kudli , Tonse Laxminidhi
Department of Electronics and Communication Engineering
National Institute of Technology Karnataka
Surathkal, India-575025
Email: amorakhia@gmail.com, sridhargunnam@gmail.com, preejit.prakash@gmail.com, sneha.kudli@gmail.com,
laxminidhi t@yahoo.com
AbstractThis paper proposes a resolution independent architecture for SAR ADCs. The proposed architecture uses 2 bits
per cycle conversion and is made independent of number of ADC
bits. A 2-bit ash ADC is used to compute 2-bits in each iteration.
The reference voltage across the resistor divider of the 2-bit ash
ADC is changed in each iteration based on the 2-bits resolved in
the previous iteration. The reference voltages for each iteration
are generated using a pair of modied switched capacitor-based
DACs. The new DAC architecture used in the proposed ADC
can use the thermometric code output of the 2-bit ash ADC
directly, avoiding the need for complex control circuitry. The
dependency of DAC architecture on the ADC resolution, observed
in conventional SAR ADCs, has been absorbed into the digital
logic which is easy to design. The proposed architecture is
validated using a 8 bit ADC designed in 0.25 m CMOS process.
Fig. 1.

I.

I NTRODUCTION

bit ash ADC is used to compute the two bits in every

cycle/iteration. The reference voltage of the 2-bit ash ADC
is switched in every iteration depending on the the bits
obtained in the previous iteration. A simple switched-capacitor
DAC is used to generate the desired reference voltages. The
comparators of the ash ADC are realized using a CMOS
inverter based architecture [6].

SAR ADCs are very popular for high resolution and low
to medium speed ADCs. They use the binary search algorithm
producing only 1 bit in every iteration and are slow but their
output can be tapped serially saving pins on the integrated
circuit. But the conventional SAR ADCs have bulky capacitor
arrays [1]. For an N-bit SAR ADC, 2n unit capacitors are
needed in the DAC as shown in Fig. 1.

The analog circuit of the ADC architecture is independent of ADC resolution. Also, this resolution independent
architecture has the advantage of the ability to trade speed
for resolution i.e. a 12-bit ADC designed for operation at
1 MSPS could operated as a 6-bit ADC at 2 MSPS with only
some clocking changes. [3] does have a resolution independent
architecture but it is slower than the proposed ADC and, as
mentioned earlier, it has very complex control circuitry.

Two bits per cycle conversion almost doubles the speed of

the ADC but at the cost of power and area. They typically
use three comparators instead of the single comparator of a
conventional SAR ADC. The three comparators enable a two
bit decision in every iteration, i.e. to nd in which quarter of
the reference range the input lies in. Few such designs can
be found in [2], [3] and [4]. The ADC presented in [2]
uses resistive dividers and switching techniques to achieve
the 2 bits-per-step. The number of resistors and switches
involved make this an area-inefcient architecture. Designs
have been proposed to reduce the area of the DAC. In [5],
a DAC architecture is presented that uses 4 minimum sized
unit capacitors and 2 buffers. The ADC presented in [3],
adapts this architecture to a 2 bits-per-cycle case leading to
a DAC that uses 7 minimum capacitors and 4 buffers but at
the expense of increased complexity of control circuitry. A 2
bits-per-cycle ADC, presented in [4], uses split capacitor and
dual sampling techniques but the capacitor array can still be
quite bulky. The complex control logic is another impediment
in using this technique.

To validate the proposed architecture, an 8-bit ADC is

designed in 0.25m CMOS process. A dual power supply
has been used to simplify the design since the ADC here is
designed only as a proof of concept. The rest of the paper is
organized as follows. Section II presents the ADC architecture,
section III presents the simulation results and section IV
concludes the paper.
II.

ADC A RCHITECTURE

The overall block diagram of the proposed ADC is shown

in Fig. 2. The 2-bit Flash ADC resolves the voltage difference
Vup -Vdown into four equal levels and outputs a thermometer
code corresponding to the analog input. The reference voltages

In this paper, we present a 2-bits-per-cycle ADC. A two

978-1-4799-6965-4/14 $31.00 2014 IEEE
DOI 10.1109/ISED.2014.37

The conventional SAR ADC Architecture

145

Fig. 2.

Overall ADC design

Fig. 3.

Working of the 2 bit-per-cycle ADC, an example

Vup and Vdown are generated by two DACs (shown as a single

block in Fig. 2) by using Vup /Vdown and the Flash thermometer
code of the previous iteration. Fig. 3 shows the conversion
process involved for an input close to the mid-code. It also
shows Vup and Vdown for each iteration.
A. DAC

Fig. 4.
ash

Switched capacitor DACs are used to generate the reference

voltages Vup and Vdown required for the 2-bit ash. Fig. 4
shows the schematic of the same. It can be clearly observed
from the gure that the DAC uses Vup , Vdown and the
thermometer code (t2 t1 t0 ) of the 2-bit ash of one iteration to
generate Vup and Vdown for the next iteration.

Schematic of the DAC generating reference voltages for the 2-bit

capacitors C0 C2 sample either Vup [n 1] or Vdown [n 1]

based on the values of t0 , t1 and t2 (Vup [n 1] if high and
Vdown [n 1] if low). The capacitor C3 samples Vup [n 1]
irrespective of the thermometer code. During the phase , the
capacitor C4 will be connected to across the opamp and C4
will be discharged to zero. The total charge stored in C0 C3
will be transferred to C4 . At the end of nth iteration Vup will
be ready for the next iteration. Vup [n] can be computed using
charge conservation and is given in (1).


t0 C0 + t1 C1 + t2 C2 + C3
Vup [n 1]
Vup [n] =
C4


t 0 C 0 + t 1 C 1 + t2 C 2
Vdown [n 1] (1)
+
C4

The generation of Vup and Vdown can be explained as

follows.
1) Vup Generation: The capacitors C0 C3 are all equal,
say C. C4 and C4 are chosen to be 4C and their switching
scheme is shown in Fig. 4. We denote Vup [n] as the Vup during
phase of the nth iteration. It can now be written, Vup [n] =
f (Vup [n1], Vdown [n1], t0 [n1], t1 [n1], t2 [n1]) where
f is a function.
Consider the nth iteration. During the phase , as per the
timing diagram shown in Fig. 4, the opamp along with the
capacitor C4 is in action during this iteration. The charge stored
in C4 during the last iteration will decide the voltage Vup . The

Note that the thermometer code bits ti  s correspond to the

iteration [n 1] and take values of either 0 or 1. Therefore

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ti can be written as ti = 1 ti . Using this identity and

substituting for capacitor values, (1) can be re-written in the
form,
2

Vup [n] = Vup [n 1]

Vupdown [n 1] 
(1 ti )
4
i=0

(2)

where, Vupdown = Vup Vdown .

For the example shown in Fig. 3, in the rst iteration, the
thermometer code (t2 t1 t0 ) is 011 (since the input belongs to
the third quarter). This corresponds to a binary code of 10.
Using this in (2), for the second iteration, Vup [2] = Vup [1]
0.25Vupdown [1] as desired.

Fig. 5.

2) Vdown Generation: The circuit generating Vdown is

identical to that generating Vup . Here, C5 C8 are equal to
C and C9 = C9 = 4C. A similar analysis can be done for
nding Vdown [n] in the nth iteration and can be written in the
form,


t0 C5 + t1 C6 + t2 C7
Vdown [n] =
Vup [n 1]
C9


t0 C 5 + t 1 C 6 + t 2 C 7 + C 8
Vdown [n 1]
+
C9
2
Vupdown [n 1] 
ti
Vdown [n] = Vdown [n 1] +
4
i=0

Schematic of the op-amp used for generating Vdown

Fig. 6.

Frequency response of the op-amp used for generating Vdown

Fig. 7.

Schematic of the inverter based comparator

(3)

Here, the capacitor C8 samples Vdown [n 1] irrespective of

the thermometer code.
In the example shown in Fig. 3, for the second iteration,
Vdown [2] = Vdown [1] + 0.5Vupdown [1] as can be seen in the
Fig. 3 .
As one can see from (2) and (3), this DAC architecture is
independent of the ADC resolution. For the ADC designed in
this work, the reference voltages are taken as 1 V (Vref p and
Vref m ) since a bipolar ADC is targeted, giving a range of 2 V
for the ADC.

cascode differential amplier with current mirror load. The

second stage is a common source stage. The rst stage carries
a typical current of 200 A and the second stage provides
the current for the resistor ladder in the 2-bit ash. Since the
voltage difference at the ends of the resistor ladder decreases
by 4 in every iteration, the current carried in the second
stage will take on values of 500 A, 125 A, 31.25 A and
7.8125 A in successive iterations. This means each op-amp
consumes on an average 915 W power operating on 1.25 V
. Each op-amp has an open loop gain of 97 dB and a Unity
Gain Bandwidth (UGB) of 33 MHz. It has to be ensured that
the error build-up due to nite gain of the op-amp at the end
of four iterations doesnt exceed the LSB of the ADC. Hence,
a high gain op-amp is used.

Every iteration has roughly three segments- First, the

capacitors C0 -C3 and C5 -C8 are connected to either Vup or
Vdown respectively based on the thermometer code of the
previous iteration or in case of the rst iteration, C0 -C3
connect to Vref p (1 V here) and C5 -C8 connect to Vref m (1 V here). Next, C0 -C3 and C5 -C8 transfer their charge to C4
(C4 ) and C9 (C9 ) respectively to generate Vup and Vdown . Last,
Vup and Vdown generate the required references for the three
comparators which produce a 3-bit thermometer code. This
thermometer code is converted to a 2-bit binary code using
simple NAND-NOR logic. The comparator has been described
in part B of this section.
The input sampling is accomplished during the rst iteration until the comparator comes into action. In case of 8
bits, this gives the sampling a little less than 250 ns. The rst
iteration operation of the DAC and the input sampling havent
been shown in the Fig. 4 for simplicity.

B. Comparator
Fig. 7 shows the schematic of the comparator designed
for the the ADC. A CMOS inverter based switched capacitor
comparator has been used. In addition, a differential operation
along with a latch (formed by Inv3, Inv4, M1 , M2 and switches
s3 s5) increases the speed and resolution of the comparator.
The working of the comparator can be described with the help
of the clocking scheme shown in Fig. 8.

Fig. 5 shows the schematic of the op-amp used for generating Vdown and Fig. 6 shows the frequency response for the
same. The op-amp used for generating Vup has an indentical
architecture but with a PMOS input pair instead of an NMOS
one. Each op-amp has two stages. The rst stage is a folded

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Fig. 8.

Clocking scheme of the comparator

Fig. 9.

Histogram of the ADC output showing no missing codes

During clock s1, the capacitor C1 is charged to

Vx1 Vi1 = Vin Vmid
where Vmid is the input/output voltage of Inv1 when Vi1 and
Vo1 are shorted (since s2 is high).
During clock s2, Vx1 is the voltage from resistor divider of 2bit ash and we denote it as Vref . Due to charge conservation,
we can write
Vi1 = Vmid Vin + Vref
(4)
Similarly at the other end of the comparator,
Vi2 = Vmid + Vin Vref

(5)

Fig. 10.

The INL plot of the ADC

Fig. 11.

The DNL plot of the ADC

From the inverter action of Inv1 and Inv2, we can write,

for Vin > Vref , Vo1 VDD and Vo2 VSS

(6)

for Vin < Vref , Vo1 VSS and Vo2 VDD

(7)

Since the gain of inverters is low, to accelerate the decision

making, the voltages Vo1 and Vo2 are fed to a latch. The
transistors M1 and M2 prevent the kick-back current from
the latch to the resistor divider of the 2-bit ash when latch
switches. With the help of the switch s4, the back-to-back
inverters are maintained at meta-stable state (Vmid ). When s4
is opened, s3 is closed for a very short duration to create
imbalance in the latch. The latch then makes a decision based
on the values of Vin and Vref .
In a more complete implementation, one would have to
take care of the offset of the comparator. This could be done
by having offset correction techniques like the one used in [7].
Once there is a budget for the comparator offset, one would
need more conversions to provide some redundancy. Note that
the emphasis of this paper is on the architecture and, therefore,
offset cancellation schemes are not discussed.
III.

respectively. It is to be noted that, no attempt has been made

to compensate for any non-idealities such as channel charge
injection, effect of parasitics, etc. The average power consumed
by the ADC for an input sine wave of 300kHz is 7.98 mW.
The simulated SNDR for a frequency of 20 kHz is 48.08 dB
giving an Effective Number of Bits (ENOB) of 7.69 and for
a frequency of 496.09375 kHz is 47.82 dB giving an Effective
Number of Bits (ENOB) of 7.65.

S IMULATION R ESULTS

The proposed ADC has been designed in 0.25 m technology with a resolution of 8 bits and is operated on a dual
power supply of 1.25 V. The ADC is designed to operate
in the input range of 1 V. The ADC can operate at a clock
speed of 4 MHz giving a conversion speed of 1 MSPS. The
histogram of the simulated ADC is shown in Fig. 9 for a ramp
input applied in such a way that each code occurs ten times.
It can be seen that there are no missing codes.

IV.

C ONCLUSIONS

A 2-bits-per-cycle SAR ADC was proposed which has

an architecture independent of ADC resolution. Since the
architecture is resolution independent, the designers attention
is only required to optimize the blocks for the desired accuracy
depending on the ADC resolution. Two bits are computed
in each clock (iteration) using a 2-bit ash ADC. The use
of switched reference concept for the ADC made the DAC
required for the SAR ADC operation simple and resolution
independent. The working of the reference generation using the
DAC was explained in detail. The DAC proposed in this work

The INL and DNL of the ADC are plotted in Fig. 10

and Fig. 11 respectively. INL and DNL, with values of
1.4 VLSB and 0.8 VLSB , are well within 2 VLSB and 1 VLSB ,

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avoids complex control circuitry and is easy to understand and

implement. The proposed architecture was validated with a 8bit SAR ADC designed in 0.25 m. A dual power supply was
used for the design in order to keep the common-mode at zero
volts since the emphasis was on the architecture. However,
the design can be extended to single supply operation with
some modications. The designed ADC did not show any
missing code and the INL and DNL were within the tolerable
limits. It is important to note that the focus here is not on the
implementation but on the architecture. The proposed ADC is
just a proof of concept and a lot more simulations including
impact of noise and op-amp offset need to be done as part of
future works.
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