AIP Introduction

Chapter 10
Operational Amplifier Circuits
10.1
The Two-Stage CMOS Op Amp

!
The circuit consists of two stages:
Analog Integrated Circuit Lab
"
"
The first stage is formed by the differential pair Q1 Q2 .

The second stage consists of the commonsource Q6 and its current-source
load Q7.
Figure 10.1

!
!
The differential pair is biased by current source Q5 , which is one of

the two output transistors of the current mirror formed by Q5 , Q7 , Q8 .
The current mirror is fed by reference current I REF .
Figure 10.1

is Miller-multiplied by the gain of the second stage, and the resulting capacitance at the input of the second stage interacts with the
total resistance there to provide the required dominant pole.
! Cc
Figure 10.1

The systematic output dc offset voltage can be eliminated by sizing
the transistors so as to satisfy the following constraint:
(W )6
(W )7
L =2
L
W
W
(
)
(
)
L4
L5
Figure 10.1
Input Common-Mode Range

The lowest value of VICM has to

be sufficiently large to keep Q1
and Q2 in saturation.
VICM should not be lower than
the voltage at the drain of Q1
by more than Vtp .
Thus,
VICM (min)
VICM VSS + VGS 3 Vtp
or
VICM VSS + Vtn + VOV 3 Vtp

!
!
The highest value of VICM should ensure that Q5 remains in

saturation.
VSD 5 should not decrease below VOV 5
So,
VICM VDD VOV 5 VSG1
VICM (max)
or equivalently
VICM VDD VOV 5 Vtp VOV 1
!
Thus, the range of VICM is

VSS + Vtn + VOV 3 Vtp VICM VDD VOV 5 Vtp VOV 1
8
Output Swing
The signal swing allowed at

the output of the op amp is
limited at the lower end by
keeping Q6 saturated and at the
upper end by keeping Q7
saturated.
Thus,
vO (max)
VSS + VOV 6 vO VDD VOV 7
vO (min)
Voltage Gain
Each of the two stages is modeled as a transconductance amplifier.
Figure 10.2
10
Voltage Gain
The input resistance is infinite:
Rin =
!
The first-stage transconductance Gm1 is equal to Q1 and Q2 :

Gm1 = g m1 = g m 2
Q1 and Q2 are operated at equal bias current and overdrive voltage:
2( I )
2 = I
Gm1 =
VOV 1 VOV 1
R1 represents the output resistance of the first stage:
VA 2 ,
VA 4
,
r =
r =
R =r !r
1
o2
o2
o4
11
o4
Voltage Gain
The dc gain of the first stage is

A1 = Gm1 R1
= g m1 (ro 2 ! r04 )
1
1
=
+
VOV 1 VA2 VA 4
! The second-stage transconductance Gm 2 is
2
Gm 2 = g m 6 =
!
2I D6
VOV 6
R2 represents the output resistance of the second stage:

R2 = ro 6 ! ro 7 , ro 6 =
V
V
VA 6
, ro 7 = A7 = A7
I D6
ID7
I D6
12
Voltage Gain
The voltage gain of the second stage is

A2 = Gm 2 R2
= g m 6 (ro 6 ! ro 7 )
1
1
+
VOV 6 VA6 VA7

! The overall dc voltage gain is the product A1 A2 :
=
Av = A1 A2
= Gm1 R1Gm 2 R2
= g m1 (ro 2 ! ro 4 ) g m 6 (ro 6 ! ro 7 )
!
The output resistance of the op amp is equal to R2 :

Ro = R2 = (ro 6 ! ro 7 )
13
Common-Mode Rejection Ratio (CMRR)

The CMRR of the two stage op amp is determined by the first stage,
so the CMRR is
CMRR = [ g m1 (r02 ! r04 )][ 2 g m3 RSS ]
RSS is the output resistance of the bias current source Q5 .
Since g m ro is proportional to VA VOV = VA L VOV ,the CMRR is increased

if long channels are used, and the transistors are operated at low
overdrive voltage.
'
14
Frequency Response
!
!
Consider the equivalent circuit in Fig.10.2.

C1 : total capacitance at the output node of the first stage
C1 = C gd 2 + Cdb 2 + C gd 4 + Cdb 4 + Cgs 6
C2 : total capacitance at the output node of the op amp, including CL

C2 = Cdb 6 + Cdb 7 + C gd 7 + CL
CC + C gd 6 CC
15
Frequency Response
The circuit has two poles and a positive real-axis zero:

f P1
1
2 R1Gm 2 R2CC
fP2
Gm 2
2 C2
fZ
Gm 2
2 CC
(1 + Gm 2 R2 )CC Gm 2 R2CC
f P1 is the dominant pole formed by the Miller-multiplied CC and R1

! The unity-gain frequency f t is
!
f t = Av f P1
Gm1
2 CC
16
Frequency Response
ft must lower than f P 2 and f Z ,so the design must satisfy the two conditions:
Gm1 Gm 2
<
, Gm1 < Gm 2
CC
C2
! The uniform -20-db/decade gain rolloff obtained at frequencies f f P1
the op amp can be represented by the simplified equivalent circuit in

Fig.10.3.
Figure 10.3
17
Phase Margin
!
!
The frequency compensation is the pole-splitting type.

It provides a dominant lowfrequency pole f P1 and shifts
the second pole beyond ft .
uniform -20db/decade
phase lag exceeds 90
Figure 10.4 Typical frequency response of the two stage op amp.
18
Phase Margin
The excess phase shift caused

by f P 2 is
f
P 2 = tan 1 ( t )
fP2
By the right-half-plane zero is

Z = tan 1 (
ft
)
fZ
The phase lag at f = ft will be

total = 90$ + tan 1 ( f t f P 2 ) + tan 1 ( f t f Z )
The phase margin will be

Phase margin
= 180$ total
= 90$ tan 1 ( f t f P 2 ) tan 1 ( ft f Z )
19
Frequency Response
!
!
!
The CC will produce a right-half-plane zero and cause the additional

phase lag.
The solution is to include a resistance R in series with CC .
Set Vo = 0, the current through CC and R will be Vi 2 ( R + 1 sCC ) , and a
Vi 2
node equation at the output is
= Gm 2Vi 2
1
R+
sCC
1
R)
! Thus, the new zero is at sZ = 1 CC (
Gm 2
make the right-half-plane zero locating at negative real-axis
20
Slew Rate
!
!
Consider the unity-gain follower with a step 1V.

Because of the amplifier dynamics, the output will not change in zero time.
Such a large signal will turn off
Q2, and switch the bias current
I to Q1 .
Q4 will pull a current I from CC .
3
21
Slew Rate
The output voltage will be a ramp with a slope of I CC :

vo (t ) =
Thus the slew rate SR is

SR =
I
CC
A relationship exists between ft and SR :

noting that ft =
I
t
CC
Gm1
and Gm = g m1 = I VOV 1 , so SR = 2 ftVOV ,or SR = tVOV
2 CC
Thus, for a given t , SR is determined by the overdrive voltage at

which the first-stage transistors are operated.
22
Power-Supply Rejection Ratio(PSRR)

!
!
The PSRR is defined as the ratio of the amplifier differential gain to

the gain experienced by a change in the power-supply voltage (vdd and vss )
Define
v
+
Ad
A+
A
PSRR = d
A
A =
PSRR + =
!
!
vdd
v
A = o
vss
The circuit is remarkably insensitive to variations in VDD , so PSRR + is

very high.
The portion of vss that appears at the op-amp output is determined by
the voltage divider formed by the output resistances of Q6 and Q7
vo = vss
ro 7
ro 6 + ro 7
23
Power-Supply Rejection Ratio(PSRR)

!
Thus,
A
!
Now utilizing Ad gives

PSRR
vo
ro 7
=
vss ro 6 + ro 7
Ad
= g m1 (ro 2 ! ro 4 ) g m 6 ro 6
A
2
So, PSRR is of the form ( g m ro ) and is maximized by selecting long

channels L (to increase VA ), and operating at low VOV .
24
Design Trade-offs
!
!
!
!
The performance of the two-stage CMOS op-amp are primarily determined by two design parameters:
1. The length L used for the channel of each MOSFET.
2. The overdrive voltage VOV at which each transistor is operated.
A large L and correspondingly larger VA increases the gain, CMRR and PSRR.
Operating at a lower VOV can also increase these three parameters and the range ofVICM
and output swing.
Also, the offset is minimized by operating at a lower VOV .
However, the transition frequency fT requires the selection of a larger VOV , which
determines the high-frequency performance of the MOSFET,
fT =
gm
2 (C gs + C gd )
25
Design Trade-offs
!
For an n-channel MOSFET, we can show that

1.5nVOV
fT
2 L2
To increase fT and improve the high-frequency response, we need

to use a larger overdrive voltage and shorter channels.
A larger VOV also results in a higher SR, and for the same bias current, in a smaller W L, which can lead to smaller devices and intrinsic
capacitances.
So, the selection of VOV presents the designer with a trade-off between the low-frequency performance and high-frequency performance.
For modern submicron technologies, which require from power supplies of 1V to 1.5V, VOV between 0.1V and 0.3V are typically utilized.
26
Example 10.1
Let it be required to design the circuit to obtain a dc gain of 4000 V V .
Assume that the available fabrication technology is of the 0.5 m type for
which Vtn = Vtp = 0.5V , kn ' = 200 A V 2 , k p ' = 80 A V 2 , VAn ' = VAp ' = 20 V m 2
, and VDD = VSS = 1.65V. Use L = 1 m for all devices. Operate all devices at
the same VOV , in the range of 0.2V to 0.4V. Use I = 200 A, I D 6 = 0.5mA.
Specify the W L for all transistors. Also give the values realized for the
range of VICM , the maximum possible output swing, Rin and Ro .
Also determine the CMRR and PSRR. If C1 = 0.2pF and C2 = 0.8pF, find
the required values of CC and the series resistance R to place the transmission zero at s = and to obtain the highest possible ft consistent with
a phase margin of 75$. Evaluate the values obtained for ft and SR.
27
Solution
(a) W L ratio:
Av = g m1 (ro 2 ! ro 4 ) g m 6 (ro 6 ! ro 7 )
=
2I
2( I 2) 1 VA
1 V

D6 A
VOV
2 ( I 2) VOV 2 I D 6
VA 2
)
VOV
To obtain AV = 4000, given VA = 20V
400
4000 =
, VOV = 0.316V
2
VOV
To obtain the required ratio of Q1 and Q2 ,
=(
I D1 =
1 ' W
k p VOV 2
2 L 1
1
W
100 = 80 0.3162
2
L 1
25 m
W 25 m W
Thus, =
, =
L 1 1 m L 2 1 m
28
Solution
(a) W L ratio:
For Q3 and Q4 ,
1
W
100 = 200 0.3162
2
L 3
To obtain
W W 10 m
= =
L 3 L 4 1 m
For Q5 ,
1
W
200 = 80 0.3162
2
L 3
W 50 m
Thus, =
L 5 1 m
29
Solution
(a) W L ratio:
Since Q7 is required to conduct 500 A,its
(W L )
ratio should be 2.5 times that of Q5 ,
W
W 125 m
=
2.5

=
1 m
L 7
L 5
For Q6 ,
1
W
500 = 200 0.3162
2
L 6
W 50 m
Thus, =
L 6 1 m
Let's select I REF = 20 A,
W
W 5 m
Thus, = 0.1 =
L 8
L 5 1 m
30
Solution
(b) Use the following equation:

VSS + Vtn + VOV 3 Vtp VICM VDD VOV 5 Vtp VOV 1
the range of VICM is
1.33V VICM 0.52V

Use the following expression:
VSS + VOV 6 vO VDD VOV 7
So, the output swing is:

1.33V vO 1.33V
The Rin is infinite, and Ro is
1 20
Ro = ro 6 ! ro 7 =
= 20k
2 0.5
31
Solution
(b) The CMRR is determined using

CMRR = [ g m1 (r02 ! r04 ) ][ 2 g m3 RSS ] ,
where R SS = r05 = VA I .
Thus,
2( I 2) 1 VA
2( I 2) VA
CMRR =

2
VOV
2 ( I 2)
VOV
I
= 2(
VA 2
20 2
) = 2(
) = 8000
VOV
0.316
Expressed in decibels, we have
CMRR=20 log8000 = 78dB
32
Solution
(c) PSRR = g m1 (ro 2 ! ro 4 ) g m 6 ro 6

=
2I
2( I 2) 1 VA
V

D6 A
VOV
2 ( I 2) VOV I D 6
= 2(
VA 2
20 2
) = 2(
) = 8000
VOV
0.316
Expressed in decibels,
PSRR=20 log8000 = 78dB
33
Solution
(d) We use the following Eq. and substituge for Gm 2 :

Gm 2 = g m 6 =
Thus, f P 2
2 I D 6 2 0.5
=
= 3.2 mA V
VOV 6 0.316
3.2 103
=
= 637MHz
12
2 0.8 10
To move the transmission zero to s = , we select the value of R as

R=
1
1
=
= 316
Gm 2 3.2 103
34
Solution
(e) For a phase margin of 75$ , the phase shift due to the second pole at f = ft
must be 15$ ,
That is , tan 1
ft
= 15 Thus, f t = 637 tan15 = 171MHz

fP2
The value of CC can be found using CC =
Gm1 = g m1 =
Thus,
The value of SR is
Gm1
, where
2 f t
2 100A
= 0.63mA V
0.316V
0.63 103
CC1 =
= 0.6pF
2 171103
SR = 2 171106 0.316
= 340 V s
35
10.2
The Folded-Cascode CMOS Op Amp
36

!
!
!
Figure 10.8 shows the structure of the CMOS folded-cascode op amp.

Q1 and Q2 form the input differential pair.
Q3 and Q4 are the cascode transistors.
Figure 10.8
37

!
Q5 to Q8 is the cascode current mirror to get the high output-resistance.
CL denotes the total capacitance at the output node (including internal transi
-stor capacitances).
Figure 10.8
38

!
Figure 10.9 is a more complete circuit for the CMOS folded-cascode op amp.
Q9 and Q10 provide the constant bias currents I B .
Q11 provides the constant current I utilized of biasing the differntial pair.
Figure 10.9
39

VICM (max) should keep Q1 and Q2 opera-
VDD VOV 9
ting in saturation at all time.

! Because V
BIAS 1
must allow Q9 and Q10
operating in saturation, VICM (max) will be

! VBIAS 2
VICM (max) = VDD VOV 9 + Vtn

should be selected to the required
value of I B while operating Q9 and Q10

at a small value of VOV .
! So, VICM (min) is
VICM (min) = VSS + VOV 11 + VOV 1 + Vtn
40
VICM
VICM (min)
Output Swing
The vO (max) is determined by the need to
maintain Q10 and Q4 in saturation.

! We should select VBIAS 1 so that Q10 operates at the edge of saturation:
VBIAS 1 = VDD VOV 10 VSG 4
!
So, vO (max) = VDD VOV 10 VOV 4
The vO (min) is obtained when Q6 reaches

the edge of saturation,
Thus, vO (min) = VSS + VOV 7 + VOV 5 + Vtn
41
Voltage Gain
! The
folded-cascode op amp is simply a transconductance amplifier with an infinite
input resistance, a transconductance Gm and an output resistance Ro .

2( I 2)
I
Gm = g m1 = g m 2 , Gm =
=
VOV 1
VOV 1
!
Ro is the parallel equivalent of the output resistance of the cascode amplifier and the
output resistance of the cascode mirror, thus
Ro = Ro 4 ! Ro 6
Ro 4 ( g m 4 ro 4 )(ro 2 ! ro10 )
Ro 6 g m 6 ro 6 ro8
So, Ro = [ ( g m 4 ro 4 )(ro 2 ! ro10 )] ! ( g m 6 ro 6 ro8 )
42
Figure 10.10
Voltage Gain
! The
dc open-loop gain can be found using Gm and Ro :

Av = Gm Ro
= g m1 {[ ( g m 4 ro 4 )(ro 2 ! ro10 ) ] ! ( g m 6 ro 6 ro8 )}

! Consider a unity-gain follower formed by cinnecting the output terminal of the
circuit of Fig. 10.9 back to the negative input terminal.

! This
feedback is of the voltage sampling type, so it reduces the output resistance
by the factor (1 + A ) , where A = Av , = 1, so

Rof =
Substituting for Av , Rof
1
Gm
Ro
R
o
1 + Av Av
Thus,
Rof = 1 g m1
43
Frequency Response
!
This circuit has poles at the input, at the connection between the CS and CG
transistors, and at the output terminal.
Normally, the first two poles are at very high frequencies. CL is usually large,
and the pole at the output becomes dominant
From Fig. 10.10, we can write

Vo
Gm Ro
=
Vid 1 + sCL Ro
The dominant pole f p is
fp =
1
2 CL Ro
The unity-gain frequency f t will be
f t = Gm Ro f p =
44
Gm
2 CL
Frequency Response
!
When CL is increased, ft decreases, but the phase margin increases.
In other words, a heavier capacitive load decreases the bandwidth of the foldedcascode amplifier but does not impair its response.
45
Slew Rate
Refer to Fig. 10.8 and consider a large

signal Vid applied so that Q2 cuts off and
Q3 will now carry a current I B I ,
and Q4 will conduct a current I B .

! Q5 and Q7 will carry the same current
with Q3 , and the current mirror Q6 and

Q8 will produce the same current whi-
5
3
IB I
ch is I B I .
!
IB
IB I
Q1 conducts the entire bias current I .
IB I
So, the current flowing CL is I 4 I 6 = I .
46
Slew Rate
Thus, the output vO will be a ramp with a slope I CL , and the SR is

SR =
I
CL
The reason for selecting I B > I is to avoid turning off the current mirror completely;
if the current mirror turns off, the output distortion increases.
! Finally,
the relationship between SR and ft is

SR = 2 ftVOV 1
47
Example 10.2
Consider a design of the folded-cascode op amp of Fig. 10.9 for which I = 200 A,
I B = 250 A, and VOV for all transistors is 0.25V. Assume that the fabrication process provides kn ' = 100 A V 2 , k p ' = 40 A V 2 , VA' = 20 V m. VDD = VSS = 2.5V,
and Vt = 0.75V. Let all transistors have L = 1m, and assume that CL = 5pF.
Find I D , g m , ro , W L for all transistors, the allowable range of VICM and output swing.
Determine the values of Av , ft , f P and SR.
What is the power dissipation of the op amp?
48
Solution
The transconductance of each device is

2I
2I
found using g m = D = D
VOV 0.25
ro =
VA
ID
20
,
ID
2 I Di
W
=

'
2
L i k VOV
The result are as follows:

Q1
I D ( A)
g m (mA V)
ro (k)
W L
Q2
Q3
Q4
Q5
Q6
Q7
Q8
Q9
Q10
Q11
100 100 150 150 150 150 150 150 250 250 200
0.8
2.0
2.0
1.6
200 200 133 133 133 133 133 133 80
80
100
32
0.8
32
1.2
1.2
1.2
120 120 48
1.2
49
48
1.2
48
1.2
48
200 200 64
Solution
!
For all transistors, g m ro = 160 V V , VGS = 1.0V
The range of VICM is 1.25V VICM 3V
The output swing is 1.25V vO 2V

! Ro 4 = 160(200 ! 80) = 9.14M
Ro 6 = 21.28M
Ro = Ro 4 ! Ro 6 = 6.4M
!
Av = Gm Ro = 0.8 103 6.4 106

= 5120 V V
0.8 103
! ft =
= 25.5MHz
12
2 5 10
!
fp =
f t 25.5MHz
=
= 5kHz
Av
5120
50
Solution
The slew rate is
I
200 106
SR =
=
= 40 V s
CL
5 1012
The total current is 500A=0.5mA, and the total supply voltage is 5V,thus
PD = 5 0.5 = 2.5mW
51
Increasing the Input Common-Mode Range:

Rail-to-Rail Input Operation
We have found that the upper limit on the input common-mode range exceeds the
supply voltage VDD , the magnitude of lower limit is significantly lower than VSS .
The opposite situation occurs if the input differential amplifier is made up of PMOS.
It follows that an NMOS and a PMOS differential pair placed in parallel would
provide an input stage with a common-mode range that exceeds the power supply
voltage in both directions.
Figure. 10.11 is the circuit which is known as rail-to-rail input operation.
52
Increasing the Input Common-Mode Range:

Rail-to-Rail Input Operation
! Each
of the current increments indica-
ted is equal to Gm (Vid 2 ) , where

Gm = g m1 = g m 2 = g m3 = g m 4.
! Thus, the total current feeding each of
the two ouput nodes will be GmVid .
! So,
Vo = 2Gm RoVid
The voltage gain will be

Av = 2Gm Ro
Figure 10.11
53
Increasing the Output Voltage Range: The

Wide-Swing Current Mirror
The cascode current mirror limits the negative swing to 2 VOV + Vt above VSS .
The cascode mirror reduces the voltage swing by Vt volts.
This point is further illustrated in Figure 10.12(a).
Figure 10.12
54
Increasing the Output Voltage Range: The

Wide-Swing Current Mirror
! To
permit the output voltage at the drain of Q3 to swing as low as 2VOV , we must
lower the voltage at the gate of Q3 from 2Vt + 2VOV to Vt + 2VOV .

! Fig.
10.12(b) is the modified mirror circuit, which is known as the wide-swing current mirror.
! The
gate of Q3 is now connected to a bias voltage VBIAS =Vt + 2VOV .
Thus the output voltage can go down to 2VOV with Q3 still in saturation.
! Also,
the voltage at the drain of Q1 is now VOV and thus Q1 is operating at the edge
of saturation.
55
10.3
The741 Op-Amp Circuit
56
The 741 Op-Amp Circuit

Stage 3
Stage 1
Stage 2
57
Bias Circuit
The bias current I REF is generated by
Q11 , Q12 , and R5 .

! Using a Widlar current source formed
by Q11 , Q10 , and R4 , Q10 generates the
bias current of the first stage.
!
Q12 and Q13 form a two-output current

mirror:
1.
Q13 B provides bias current and acts
2.
as a current-source load for Q17 .

Q13 A provides bias current for the
output stage of the op-amp.
The purpose of Q18 and Q19 is to

establish two VBE drops between
the bases of Q14 and Q20 .
58
The Input Stage

The input stage consists of Q1 through Q7 ,

with biasing performed by Q8 , Q9 , and Q10 .
Q5 , Q6 , and Q7 and R1 , R2 , and R3 form

the load circuit of the input stage.
Level shifting is done in the first stage

using the pnp Q3 and Q4 .
The pnp transistors Q3 and Q4 can

protect the input-stage transistors
Q1 and Q2 against emitter-base junction breakdown.
59
The Second Stage

The second stage is composed of Q16 ,

Q17 , Q13 B , R8 , and R9 .
The emitter follower Q16 can give the

second stage a high input resistance,
and can also minimize the loading on the
input stage and avoid loss of gain.
Q17 acts as a CE amplifier with a 100

resistor in the emitter. Its load is composed of the high output resistance Q13 B .
The output of the second stage is taken at the collector of Q17 .

CC is connected in the feedback path of the second stage to provide frequency
compesation using the Miller-cmpensation technique.
60
The Output Stage

!
The purpose of the output stage is to

provide the amplifier with a low ouput
resistance.
The output stage of the 741 consists of the

complementary pair Q14 and Q20 .
Q18 and Q19 are fed by current source

Q13 A and bias the Q14 and Q20 .
Q23 acts as an emitter follower, thus

minimizing the loading effect of the
output stage on the second stage.
61
Device Parameters
For the standard npn and pnp, the following parameters will be used:
npn : I S = 1014 A, = 200, VA = 125V

pnp : I S = 1014 A, = 50, VA = 50V
!
Q13 will be assume to be equivalent to two transistors, Q13 A and Q13 B , with parallel
base-emitter junctions and haveing following saturation currents:
I SA = 0.25 1014 A, I SB = 0.75 1014 A
Q14 and Q20 will be assumed to each have an area three times that of a standard device.
62
10.4
DC Analysis of the741
63
Reference Bias Current

With reference to Fig. 10.13, we can write
I REF =
VCC VEB12 VBE11 (VEE )

R5
For VCC = VEE = 15V and VBE11 = VEB12 0.7V,

we have I REF = 0.73mA.
64
Input-Stage Bias
Fig. 10.14 is the Widlar current source that biases the input stage.
Assume 10 to be large, we have
VBE11 VBE10 = I C10 R4
I REF
= I C10 R4
I C10
= I S 11 , we can get I C10 = 19A.
VT ln
Assumed that I S 10
Figure 10.14
65
Input-Stage Bias
! From symmetry,
I C1 = I C 2
IE3 = IE4 I
2I
IC 9 =
1+ 2 P
2 I I C10
I C10 = 19A, thus I 9.5A

So, I C1 = I C 2 I C 3 = I C 4 = 9.5A
!
Q1 through Q4 , Q8 , and Q9 from a

negative-feedback loop, which works
to stabilize the value of I at approximately I C10 2.
66
Input-Stage Bias
This part is fed by I C 3 = I C 4 I

IC 5 = IC 6
IC 5 IC 3 I
neglect I B 7 and I B16
IC 6 IC 4 I
!
The bias current of Q7 can be determined from

IC 7 I E 7 =
2I
VBE 6 + IR2
R3
I
IS
Substituing I S = 1014 A and I = 9.5A results in VBE 6 = 517mV.
VBE 6 = VT ln
Thus, I B 7 at approximately 0.05A is negligible.

67
Input Bias and Offset Currents

The input bias current of an op amp is defined as

I +I
I B = B1 B 2
2
For 741,
I
IB =
Using N = 200, yields I B = 47.5nA
This value is reasonably small and is typical of general-purpose op amps that

use BJTs in the input stage.
Given the value of the mismatch, the input offset current is defined as
I OS = I B1 I B 2
68
Second-Stage Bias
If we neglect the I B 23 , the I C17 is approximately equal to the current supplied by

current source Q13 B .
I C13 B 0.75I REF
Thus, I C13 B = 550A and I C17 = 550A.
VBE17 = VT ln
So, I C16 I E16 = I B17 +
I C17
= 618mV
IS
I E17 R8 + VBE17
R9
This caculation yields I C16 =16.2A.
69
assume that P 1
Output-Stage Bias
! I C 23 I E 23 = 0.25I REF = 180A
I B 23 = 180 50 = 3.6A, which is negligible.

Assume that VBE18 is 0.6V, we can determine the current in R10 as 15A.
So, I E18 = 180 15 = 165A
I C18 I E18 = 165A

I C19 I E19 = 15.8A
I C19
= 530mV
IS
= VBE18 + VBE19 = 588 + 530 = 1.118V
VBE19 = VT ln
VBB
VBB = VT ln
I C14
I
+ VT ln C 20
I S 14
I S 20
Substituing I S 14 = I S 20 = 3 1014 A, so that I C14 = I C 20 = 154A.

70
10.5
Small-Signal Analysis of the 741
71
The Input Stage

vi
4re
V
25mV
re = T =
= 2.63k
I
9.5A
Rid = 4 ( N + 1) re
ie =
= 4 ( 200 + 1) 2.63
= 2.1M
!
Figure 10.18
io = 2 ie
Gm1
io
=
vi 2re
Substituing re = 2.63k and 1

yields Gm1 = 1 5.26 mA V.
72
Figure 10.19
The Input Stage

Using the equation :

Ro = ro 1 + g m ( Re ! r )
Substituing Re = re = 2.63k and

ro = VA I , where VA = 50Vand
I = 9.5A, and neglecting r , results
in Ro 4 = 10.5M.
!
Figure 10.20
Ro 6 can be determine with Re = R2 .

Thus Ro 6 18.2M.
Combine Ro 4 and Ro 6 in parallel,
the output resistance of input stage
Figure 10.21
is Ro1 = 6.7M.
Figure 10.21 shows the equivalent circuit of the input stage.
73
Example10.3
We wish to find the input offset voltage resulting from a 2% mismatch between the
resistances R1 and R2 in Fig. 10.13.
74
Solution
VBE 5 + IR = VBE 6 + ( I I )( R + R )
VBE 5 VBE 6 = I R I ( R + R )
VBE 5 VBE 6 Ire
I
R
=
I
R + R + re
Substituing R = 1k and re = 2.63k
shows that I = 5.5 103 I .
So, VOS
I 5.5 103 I
=
=
Gm1
Gm1
Substituting I =9.5A and Gm1 =1 5.26 mA V ,

VOS 0.3mV
75
Example10.4
It is required to find the CMRR of the 741 input stage. Assume tha the circuit is balancde
except for mismatches in the current-mirror load that result in an error m in the mirror's
current-transfer ratio; that is, the ratio becomes(1- m ).
76
Solution
Ro = Ro 9 ! Ro10
2i +
2i
vicm
Ro
vicm
2 Ro
io = mi
Gmcm
assume P 1
io
i
= m
vicm vicm
=
CMRR=
m
2 Ro
Gm1
= 2 g m1 Ro m
Gmcm
So, CMRR= 2g m1 ( Ro 9 ! Ro10 ) m

77
The Second Stage

Input Resistance
Ri 2 = ( 16 + 1) re16 + R9 ! ( 17 + 1)( re17 + R8 )

Transconductance
Shortcircuiting the output terminal

of the second stage to ground.
vb17
ic17 =
re17 + R8
( R9 ! Ri17 )
vb17 = vi 2
( R9 ! Ri17 ) + re16
Figure 10.24
Ri17 = ( 17 + 1)( re17 + R8 )

Gm 2
ic17
vi 2
For the 741 parameter values, Gm 2 = 6.5 mA V.

78
Figure 10.25?
The Second Stage

Output Resistance
Ro 2 = ( Ro13 B ! Ro17 )
Ro13 B = ro13 B
For the 741 component value we obtain Ro13 B = 90.9k.
Since the base resistance of Q17 is

relatively small, we can assume
that the base is grounded.
For our case, the result is Ro17 787k.
Figure 10.26
Combining Ro13 B and Ro17 in parallel yields Ro 2 = 81k.

79
Thvenin Equivalent Circuit

The second-stage equivalent circuit can be converted to the Thvenin form,
as Figure 10.27.
The stage open-circuit voltage gain is -Gm 2 Ro 2 .
Figure 10.27
80
The Output Stage

Output Voltage Limits

vO (max) = VCC VCEsat VBE14
limited by the saturation of Q13 A
vO (min) = VEE + VCEsat + VEB 23 + VEB 20
limited by the saturation of Q17
Figure 10.28
81
The Output Stage

Small-Signal Model
vo 2 = Gm 2 Ro 2 vi 2
A2
vi 3
Rin 3
= Gm 2 Ro 2
vi 2
Rin 3 + Ro 2
Figure 10.29
The total resistance in the emitter of

Q23 is 100k ! 280k or 74k.
So, Rin 3 23 74k
For 23 = 50, Rin 3 3.7M.

v
Gvo 3 = o
( RL = )
vo 2
With RL = , the gain of Q14 or Q20 will be nearly unity. Also, the emitter resistance
of Q23 will be very large. We thus conclude that Gvo 3 1.
82
The Output Stage

! Ro 23 =
Ro 2
+ re 23
23 + 1
Substituting Ro 2 = 81k, 23 = 50, and

re 23 = 25 0.18 = 139 yields Ro 23 = 1.73k
Since ro13 A alone is much larger than Ro 23 ,
the effective resistance at the base of Q20
is equal to Ro 23 .
Now we can find Rout as
Rout =
Ro 23
+r
20 + 1 e 20
Figure 10.30
For 20 = 50, Rout = 34
The output resistance of the 741 is typically 75.

83
The Output Stage

Output Short- Circuit Protection

R6 and Q15 limits the current that would flow out of Q14 in the event of s short circuit.
If the current in the emitter of Q14 exceeds about 20mA, the voltage drop across R6
exceeds 540mV, which turns Q15 on.
As Q15 turns on, its collector robs some of the current supplied by Q13 A , thus reducing
the base current of Q14 .
This mechanism thus limits the maximum current that the op amp can source to about
20mA.
84
10.6
Gain, Frequency Response, and Slew
Rate of the 741
85
Small-Signal Gain
vo vi 2 vo 2 vo
=
vi vi vi 2 vo 2
= Gm1 ( Ro1 ! Ri 2 )( Gm 2 Ro 2 ) Gvo 3
Thus,
Ao
RL
RL + Rout
vo
= 476.1 (526.5) 0.97
vi
= 243147 V V
107.7dB
86
Figure 10.31
Frequency Response
!
From Miller's theorem, the effective
capacitance due to CC at the base of

Q16 is Cin = CC (1 + A2
A2 = 515, results in Cin = 15480pF.
Rt = Ro1 ! Ri 2
= 6.7M ! 4M = 2.5M
Thus, the dominant pole f P is
1
fP =
= 4.1Hz
2 Cin Rt
f t = A0 f3dB
Figure 10.32
assume that all the other poles are at very high frequency.
= 243147 4.1 1MHz

87
A Simplified Model
A( s )
Vo ( s ) Gm1
=
Vi ( s ) sCC
A( j ) =
Gm1
jCC
The magnitude of gain becomes unity at =t ,

where
t =
Gm1
CC
Sustituting Gm1 = 1 5.26 mA V and CC = 30pF yields

ft =
t
1MHz
2
88
Figure 10.33
Slew Rate
! Consider the unity-gain follower of Fig. 10.34

with a step of 10V applied at the input.
This large signal causes the input stage
to be overdriven.
Rather, half the stage cuts off and the other
half conducts all the current
Figure 10.34
Thus, we can see that the output voltage

will be a ramp with a slope of 2 I CC :
vO (t ) =
2I
t
CC
So, the SR is given by

SR =
2I
CC
For the 741, I = 9.5A and CC =30pF,

resulting in SR = 0.63V s
Figure 10.35
89
Relationship Between ft and SR

2I
t
Gm1
4I
SR =
t
g m1
I
g m1 =
VT
SR = 4VT t
SR =
For the 741,
SR = 4 25 103 2 106 = 0.63V s

There is a relationship between SR and t , which is
SR = t a
where a is the constant of proportionality relating the transconductance of the first

stage Gm1 , to the total bias current of the input differential stage.
90
10.7
Modern Techniques for the Design of
BJT Op Amps
91
Special Performance Requirements

! Many modern BJT op amps are required to operate from a single power supply of only
2V to 3V.
This is done for the following reasons:
1. Modern small-feature-size IC fabrication technologies require low power-supply voltages.
2. Compatibility must be achieved with other parts of the system that use low-voltage supplies.
3. Power dissipation must be minimized, especially for battery-operated equipment.
Figure 10.36
92
Special Performance Requirements

! Consider first the inverting op-amp.
Since the positive input terminal is connected to ground, ground voltage has to be within
the allowable input common-mode range.
The input common-mode range should extend below the negative-supply rail.
Consider the unity-gain voltage follower.
The input common-mode voltage is equal to the signal vI .
Thus, the input common-mode range shoulde include also the positive supply rail.
Therefore, the input common-mode range is more than rail-to-rail operation.
93
Figure 10.37
Bias Design
Figure 10.38 shows a self-biased currentreference source.

I
VBE1 = VT ln
I S1
I
VBE 2 = VT ln
I
S2
IS 2
VBE1 VBE 2 = VT ln
I
S1
But,
VBE1 VBE 2 = IR2

Thus,
I
V
I = T ln S 2
R2 I S 1
Figure 10.38
94
Bias Design
The circuit in Fig 10.38 provides a bias

line VBIAS 1 with a voltage equal to VBE1.
This bias line can be used to bias other
transistors and thus generate constant
currents proportional to I by appropriately scaling emitter areas and emitterdegeneration resistances.
These ideas are illustraged in Fig. 10.39.
Figure 10.39
95
Design of the Input Stage to Obtain Rail-toRail V

ICM
Consider the Fig. 10.40(a).
VICM is limited by keeping Q1 in active

mode, so VICM (min) is 0.1V, and the input
common-mode range does not include
ground voltage as required.
The minimum allowed value of VICM in
Fig. 10.40(b) is
VICM (min) = VRC 0.6V
Figure 10.40
If VRC is selected to be 0.2 to 0.3V,

VICM (min) will be -0.4V to -0.3V, which is exactly what we need.
96

ICM
The differential gain is
vo
= g m1,2 RC
vid
=
VR
I 2
RC = C
VT
VT
For VRC = 0.3V, the gain realized is only 12 V V.

This problem can be solved by cascoding.
97

ICM
! Consider the
upper end of the input

common-mode range.
In Fig. 10.40(b), VICM (max) has to keep Q5

in active mode.
So, VICM (max) is
VICM (max) = VCC 0.1 0.7 = VCC 0.8
That is, the upper end of the input

common-mode range is at least 0.8V
below VCC .
0.3 VICM VCC 0.8
98

ICM
To extend the upper end of VICM , we

adopt a solution similar to that used in
the CMOS case.
The Fig. 10.41 is the npn version of
the circuit of Fig. 10.40(b), and has a
common-input range of
0.8 VICM VCC + 0.3
Thus, the high end is above the positive
supply rail by 0.3V.
There is a range of VICM in which both
the pnp and the npn circuits will be
active and properly operating.
0.8 VICM VCC 0.8
99

ICM
Figure 10.42
100

ICM
! Figure 10.42
shows an input stage that achieves more than rail-to-rail input common-
mode range by utilizing a pnp differential pair (Q1 and Q2 ) and an npn differential
pair (Q3 and Q4 ) connected in parallel.
The dependence of the differential gain on the input common-mode VICM is usually
undesirable and can be reduced considerably by arranging that on of the two differential
pairs is turned off when the other one is active.
101
Example 10.5
It is required to find the input resistance and the voltage gain of the input stage shown
in Fig. 10.42. Let VICM 0.8V so that the Q3 Q4 pair is off. Assume that Q5 supplies
10 A, that each of Q7 to Q10 is biased at 10A, and that all four cascode transistors
are operating in the active mode. The iuput resistance of the second stage of the op amp
(not shown) is RL = 2M. The emitter-degeneration resistances are R7 = R8 = 20K,
and R9 = R10 = 30K. Recall that the device parameters are N = 40, P = 10, VAn = 30V,
VAp = 20V.
102
Solution
Rid = 2r 1 = 2 P g m1
I C1 5 106
g m1 =
=
= 0.2 mA V
VT 25 103
2 10
Rid =
= 100k
0.2
i
Gm1 = c 7
vid 2
ro1 =
VAp
I C1
R7 = 20k
20V
= 4M
5A
ro 7 =
VAn 30V
=
= 3M
I C 7 10A
re 7
1
V
25mV
= T =
= 2.5k
g m 7 I C 7 10A
103
Solution
v R7
ie 7 g m1 id
2
R
+
r
7
e7
v 20
v
= g m1 id
= 0.89 g m1 id
2 20 + 2.5
2
v
io ie 7 = 0.89 g m1 id
2
i
Gm1 o = 0.89 g m1 = 0.89 0.2 = 0.18 mA V
vid 2
R = Ro 9 ! Ro 7 ! ( RL 2 )
Ro 9 = ro 9 + ( Ro 9 ! r 9 )(1 + g m9 ro 9 )
ro 9 =
g m9
VAp
IC 9
20V
= 2M
10A
I C 9 10 106
=
=
= 0.4 mA V
VT 25 103
104
Solution
! r 9 =
P
g m9
10
= 25k
0.4 mA V
Ro 9 = 2 + ( 30 ! 25 ) 103 (1 + 0.4 2 103 )
= 0.18 0.89 103 = 160 V V
= 12.9M
Ro 7 = ro 7 + ( R7 ! r 7 )(1 + g m 7 ro 7 )
gm7
I C 7 10 106
=
=
= 0.4 mA V
3
VT
25 10
r 7 =
N
gm7
R = 12.9 ! 23 ! 1 = 0.89M
v 2
Ad = od = Gm1 R1
vid 2
40
= 100k
0.4 mA V
Ro 7 = 3 + ( 20 ! 100 ) 103 (1 + 0.4 3 103 )

= 23M
RL 2M
=
= 1M
2
2
105
Common-Mode Feedback to Control the dc

Voltage at the Output of the Input Stage
For the cascode circuit in Fig. 10.42, the cascode transistors Q7 through Q10 must
operate in the active mode at all time.
However, the currents supplied by Q9 and Q10 will not be exactly equal to the
currents supplied by Q7 and Q8.
These changes in turn can cause one set of the current sources to saturate.
Thus, we need a circuit that detects the change in the dc or VCM of vO1 and vO 2 , and
adjusts the bias voltage on the bases of Q7 and Q8. , VB to restore current equality.
Therefore, we use a feedback loop to provide common-mode feedback (CMF).
106

Figure 10.44 shows the cascode circuit
with the CMF circuit shown as a black box.

The CMF circuit has the transfer characteristic:
VB = VCM + 0.4
By keeping VB higher than VCM by
only 0.4V, the CMF ensures that Q7
and Q8 remain active.
Figure 10.44
107

Figure 10.45 shows the second stage of an op-amp circuit.

vO1 = VCM + vd 2
vO 2 = VCM vd 2
VB = VCM + 0.4
VE = VCM + VEB11,12 VBE13,14
Thus, VE VCM .
The voltage VB is simply equal to VE
plus the voltage drop of diode D1.
Figure 10.45
So, VB = VE + VD = VCM + 0.4
108
Example 10.6
Consider the operation of the circuit in Fig. 10.44. Assume that VICM 0.8V and thus
the npn input pair (Fig. 10.42) is off. Hence I 3 = I 4 = 0. Also assume that only dc voltages are present and thus I1 = I 2 = 5A. Each of Q7 to Q10 is biased at 10A, VCC = 3V,
VBIAS 3 = VCC 1, R7 = R8 = 20k, R9 = R10 = 30k. Neglect base currents and neglect
the loading edffect of the CMF circuit on the ouput nodes of the cascode circuit. The
CMF circuit provides VB = VCM + 0.4.
(a) Determine the nominal values of VB and VCM . Does the value of VCM ensure
operation in the active mode for Q7 through Q10 ?
(b) If the CMF circuit were not present, what would be the change in vO1 and vO 2
as a result of a current mismatch I =0.3A between Q7 Q8 and Q9 Q10?
Use the output resistance values found in Example 10.5.
(c) Now, if the CMF circuit is connected, what change will it cause in VB to eliminate
the current mismatch I ? What is the corresponding change in VCM from its
nominal value?
109
Solution
(a) VB = VBE 7 + ( I E 7 + I1 ) R7 0.7 + (10 + 5) 103 20 = 1V

VCM = VB 0.4 = 1 0.4 = 0.6V
VCM > VB 7,8 0.6
for Q7 Q8 to be active
That is,
VCM > 0.4V
VCM < VBIAS 3 + 0.6
for Q9 Q10 to be active
VCM < VCC 1 + 0.6

VCM < 2.6V
Thus, for all four cascode transistors to operate in the active mode,
0.4V <VCM < 2.6V

Thus the nominal value of 0.6V ensures active mode operation.
110
Solution
(b) For I C 9 I C 7 = I C10 I C 8 = I
VCM = IRo1
Ro1 = Ro 7 ! Ro 9 = 23 ! 12.9 = 8.3M
Thus,
VCM = 0.3 8.3 2.5V
If VCM is positive,
VCM = 0.6 + 2.5 = 3.1V
which exceeds the 2.6V maximum allowed value before Q9 Q10 saturate.
If VCM is negative,
VCM = 0.6 2.5 = 1.9V
which is far below the +0.4V keeping Q7 Q8 in the active mode.

Thus, a current mismatch of 0.3A would cause one set of the cascode transistors
to saturate.
111
Solution
(c)
I C 7 = I C 8 =
I =
VB
re 7 + R7
VB
re 7 + R7
VB = I ( re 7 + R7 )
Correspondingly
25mV
= 0.3A
+ 20k
10A
= 0.3 22.5 = 6.75mV

VCM = VB = 6.75mV
Thus, to restore the current equality, the change required in VB and VCM is only 6.75mV.
112
Output-Stage Design for Near Rail-to-Rail

Output Swing
! Modern
low-voltage bipolar op amps

cannot afford to use the classical emitter
-follower-based class AB output stage;

it would consume too much power.
! A complementary pair of common-
emitter transistors are utilized as

shown in Figure 10.46 .
!
We can see that vO can swing to within

0.1V of each of the supply rails.
! Its
disadvantage is the relatively high output resistance.
! However,
we can use with a negative-feedback loop to reduce the output resitance.

113
Output-Stage Design for Near Rail-to-Rail

Output Swing
! The
output transistors can be called on to

supply large current, but such the large
current cannot be usually supplied by the
amplifier stage preceding the output stage.
! Rather a
buffer/driver stage is usually
needed, as shown in Figure 10.47.

! Q3
is used to drive QN .Q1 and Q2 are used
to drive Q p .
! Because of
the low P , QP has to use two
emitter-follower to drive it.
114
Establishing IQ and Maintaining a Minimum

Current in the Inactive
Figure 10.48
115

Figure 10.48 shows a fuller version of the output stage.

i
iC 6 = I N
iP + iN
i
iC 7 = I P
iP + iN
I SN and I S 7
iN iP
I
vE = VT ln
iN + iP I SN I S 7
are the saturation currents of QN and Q7 .
For iP iN , iC 6 0, iC 7 I . Thus Q6 turns off and Q7 conducts all of I .
iN
vE VT ln
I SN
I
+ VT ln
S7
i
vE = VT ln N
I SN
116
+ VEB 7

In the other extreme case of iN iP , iC 6 I , iC 7 0.

Thus Q7 turns off and Q6 conducts all of I .
iP
vE = VT ln
+ VEB 6
I
SN
We can obtain a relationship between iN and iP :
I
vE = VREF = VT ln REF
I S 10
I REF
+
V
ln
T
S 11
2
I REF
I SN I S 7
iN iP
=
iN + iP I I S 10 I S 11
In the quiescent case, iN = iO = I Q , the above equation yields

2
I REF
I SN I S 7
IQ = 2
I
I
I
S 10 S 11
117

! Thus,
So,
the constant on the right-hand side is I Q 2.

iN iP
1
= IQ
iN + iP 2
The above equation shows that for iN iP , iP
1
1
I Q , and that for iP iN , iN I Q .
2
2
Thus the circuit not only establishes the quiescent current I Q but also sets the
minimum current in the inactive output transistor at
118
1
IQ .
2
Chapter 11
Filters and Tuned Amplifiers
11.1
Filter Transmission, Types, and
Specification
Filter Transmission
!
!
The filters studied in this chapter are linear circuits

represented by the general two-port network shown.
The filter transfer function T ( s) is the ratio of the output Vo ( s )
voltage to the input voltage Vi ( s)
T ( s)
Figure 11.1
Vo ( s)
Vi ( s)
Filter Transmission
The filter transmission is found by evaluating T(s) for

physical frequencies, s = j and can be expressed in terms
of magnitude and phase as
T ( j ) = T ( j ) e j ( )
!
The magnitude of transmission is often expressed in

decibels in terms of the gain function
G ( ) 20 log T ( j ) , dB
or, alternatively, in terms of the attenuation function.
A( ) 20 log T ( j ) , dB
Vo ( j ) = T ( j ) Vi ( j )
Ideal transmission characteristics of the four major filter

types:
Figure 11.2
Specification of the transmission characteristics of a lowpass filter
!
!
!
The maximum allowed variation in passband

transmission Amax is also called passband ripple
The minimum required stopband attenuation Amin
This transition band extends from the passband edge p
to the stopband edge s
s
The selectivity factor:
p
Figure 11.3
6
Transmission specifications for a bandpass filter
Notice that this filter monotonically decreasing

transmission in the passband on both sides of the
peak frequency.
The passband edge p1 , p 2 and the stop band edges1 , s 2
Figure 11.4
7
11.2
The Filter Transfer Function
The Filter Transfer Function

Transform function T ( s) can be

written
as the ratio of
M
M 1
two polynomials as T ( s) = aMNs + aM N1s1 + a0 , N is the filter
s + bN 1s + + b0
order
where a0 , a1 , , aM and b0 , b1 ,, bN 1are real numbers
For filter circuit to be stable M N
T (s) =
aM ( s z1 )( s z2 ) ( s zM )
( s p1 )( s p2 ) ( s pN )
The orther form is

, z1 , z2 ,, zM
are the transfer function zeros ,or transmission zeros;
p1 , p2 ,, pN are the transfer function poles, or the
natural modes
5th Order Low Pass Filter

!
Transfer function: T ( s) =
Transmission zeros at s = jl1 , s = , s = jl 2

For a filter circuit to be stable, all poles must lies in
the left half of the s plane
a4 ( s 2 + l21 )( s 2 + l22 )
s 5 + b4 s 4 + b3 s 3 + b2 s 2 + b1s + b0
Figure 11.4
10
6th Order Band Pass Filter

!
Transfer function:
Transmission zeros at s = jl1 s =, jl 2 s = ,
a5 s ( s 2 + l21 )( s 2 + l22 )
T (s) =
s 6 + b5 s 5 + b0
s=0
11
5th all-pole Low Pass Filter(no finite

zeroes)
An all-pole filter T ( s) =
a0
sN + bN 1s N 1 + + b0
12
11.3
Butterworth and Chebyshev
Filters
13
Butterworth and Chebyshev Filters

Two functions that are frequently used in

approximating the transmission characteristics of
lowpass filter
14
The Butterworth Filter

!
!
Monotonically decreasing transmission with all the

transmission zero at =
The magnitude function for an Nth-order Butterworth
filter with a passband edge p is given by
1
T ( j ) =
1+ 2 (
!
At = p ,
T ( j p ) =
2N
)
p
1
1+ 2
15
The Butterworth Filter

The parameter determines the maximum variation

in passband transmission, Amax , according to
Amax = 20log 1 + 2
Conversely, given Amax , can be determined from

= 10 A
max
/10
At the edge of the stopband = s

A(s ) = 20 log[1/ 1 + 2 (s / p ) 2 N ] = 10 log[1 + 2 (s / p ) 2 N ]
This equation can be used to determine the filter

order required, which is the lowest integer value of n
that yields A(s ) Amin
16
Magnitude response for Butterworth filters
!
!
Increasing the order N makes response very flat near

. = 0 .and gives the response the name maximally flat
response
Converges to brick wall
= p at the edge of stopband
17
The poles of a Butterworth filter can be determined from the

graphical construction below
18
!
!
The poles lie on a circle of radius p (1/ )1/ N and are

spaced by equal angles of / N
Since all poles have equal radial distance from the
origin, they all have the same frequency
0 = p (1/ )1/ N
Once the N natural modes p1 , p2 , pN have been found,

the transfer function can be written as
K 0N
T ( s) =
( s p1 )( s p2 ) ( s pN )
where K is a constant equal to the required DC gain of the filter
19
Example 11.1
Find the Butterworth trsanfer function that meets the

following low-pass filter specification:f p = 10kKz , Amax = 1dB
, f s = 15kHz , Amin = 25dB , dcgain = 1
Solution
1.Determine from = 10 A /10 1 and substitute Amax = 1dB
max
= 0.588
2.Determine the filter order as the lowest integer value of N

that result A(s ) Amin ,
if N = 8 A( ) = 22.3dB ,if N = 9 A( ) = 25.8dB
select N = 9
s
20
Solution
3.find 0 from 0 = p (1/ )
1/ N
0 = 2 10 103 (1/ 0.5088)1/9 = 6.773 104 (rad / s)
4.find poles
p1 = 0 ( cos80! + j sin 80! ) = 0 (0.1736 + j 0.9848)
combine its conjugate p9 yields the factor

( s 2 + s0.34720 + 02 ) in the denominator of T(s )
the same way can be done for other complex poles
K 0N
5. T ( s ) =
( s p1 )( s p2 ) ( s pN )
09
T ( s) =
( s + 0 )( s 2 + s1.87940 + 02 )( s 2 + s1.53210 + 02 )( s 2 + s0 + 02 )( s 2 + s0.34720 + 02 )
21
The Chebyshev Filter

The Chebyshev exhibits an equiripple response in the

passband and a monotonically decreasing in the
stopband
Figure 11.12 Sketches of the transmission characteristics of representative (a) even-order and (b) odd-order Chebyshev
filters.
22

!
!
!
The total number of passband maxima and minima equals

the order of the filter
All the transmission zeros of the Chebyshev filter are at =
making it an all pole filter
The magnitude of the transfer function of an Nth-order
Chebyshev filter with p is given by
1
1. T ( j ) =
for p
2
2
1
1 + cos [ N cos ( / p )]
2. T ( j )
1
2
1 + cosh [ N cosh ( / p )]
23
for p

!
At the passband edge, = p ,the magnitude function is given

by
1
T ( j p ) =
1+ 2
Thus,the parameter determines the passband ripple

according to
2
Amax = 10log(1 + )
Conversely,given Amax ,the value of is determined from
= 10 A
max
24
/10

The attenuation at stopband edge( = s ) is found as

A(s ) = 10 log[1 + 2 cosh 2 ( N cosh 1 (s / p ))]
Increasing the order N of the Chebyshev filter causes

its magnitude function to approach the ideal brick-wall
low-pass response
The poles of the Chebyshev filter are given by
pk = p sin(
2k 1
1
1
2k 1
1
1
) sinh( sinh 1 ) + j p cos(
) cosh( sinh 1 )
N 2
N
N 2
N
k = 1, 2,3, N
!
Transfer function of the Chebyshev filter can be

K p2
written as
T (s) =
2 N 1 ( s p1 )( s p2 ) ( s pN )
where K is a constant equal to the required DC gain of the filter
25
Example 11.2
Find the chebyshev transfer function that meets the

same low-pass filter specifications given in
Example11.1 f p = 10kKz Amax = 1dB f s = 15kHz Amin = 25dB dcgain = 1
1.Determine from = 10 A
max
/10
and substitute Amax = 1dB
= 0.588
2.Determine the filter order as the lowest integer

value of N that result A(s ) Amin ,if N = 4 A( ) = 21.6dB
, if N = 5 A( ) = 29.9dB select N = 5
3.find poles
s
pk = p sin(
2k 1
1
1
2k 1
1
1
) sinh( sinh 1 ) + j p cos(
) cosh( sinh 1 )
N 2
N
N 2
N
26
Solution
p1 , p5 = p (0.0895 j 0.9901)
p2 , p4 = p (0.2342 j 0.6119)
p5 = p (0.2895)
5. T ( s) =
T (s) =
K p2
2 N 1 ( s p1 )( s p2 ) ( s pN )
5p
8.1408( s + 0.2895 p )( s 2 + s 0.4684 p + 0.4293 p2 )( s 2 + s 0.1789 p + 0.9883 p2 )
where
p = 2 104 (rad / s)
27
11.4
First-Order and Second-Order
Filter Function
28
First-Order And Second-Order

Filter Functions
!
The simplest filter functions
!
!
!
!
First order
Second order
First-and second-order filters can be cascaded to

realize a high order filter
Cascade design is in fact one of the most popular
methods for the design of active filters
29
First-Order Filter
The general first order transfer function is given by
a1s + a0
T ( s) =
s + 0
!
This bilinear transfer function characterizes a firstorder filter with

! A natural mode at s = 0
!
a1
The numerator coefficients, a0 and a1 , determine the
type of filter (e.g., LP, HP, etc.)
!
A transmission zero at s = a0 / a1
The high frequency gain that approaches
30
First-Order Filter
The active realizations provide considerably more

versatility then their passive counterparts; gain, and
transfer-function parameters adjust
The op amp limits the high frequency operation of the
active circuits.
31
Figure 11.13 First-order

filters.
32
All-Pass Filter
!
!
The transmission zero and the natural mode are

symmetrically located relative to the j axis
All pass Filter are used as phase shifters (phase
shaping)
33
Second-Order Filter Functions

The general second order (biquadratic) filter transfer

function is usually expressed by
T (s) =
a2 s 2 + a1s + a0
0 ) s + 2
0
Q
s2 + (
!
Where 0and Q determine the natural modes(poles ) according

to
p1 , p2 = 0 j0 1 1 2
4Q
2Q
pole frequency 0
pole quality factor
The higher the value of Q the closer the poles
are to the j axis
! Q = ,yield sustained oscillation
!
34

!
!
!
A negative value of Q implies that the poles are in the right

half of the s plane, which certainly produces oscillations.
The transmission zeros of the second-order filter are

determined by the numerator coefficients,a0 ,a1 and a2 .
The numerator coefficients determine the type of
second-order filter function (i.e., LP, HP, etc.)
Seven special cases of interest are illustrated in
Fig.12.16.
35
36
37
All seven special second-order filters have a pair of

complex-conjugate natural modes characterized by a
frequency 0 and a quality factor Q
38

!
!
!
In the low-pass (LP) case, the two transmission zeros

1
are at s = ,the magnitude response shows a peak for Q > 2
In the high-pass (HP) case, both transmission zeros are
1
at s = 0 ,the magnitude response shows a peak for Q > 2
In the band-pass (BP) case, one transmission zeros is
at s = 0,and the other is s = , the magnitude response
peaks at = 0 also called center frequency of BP filter.
The second-order BP filter is measured by its 3-dB
bandwidth.
bandwidth is the difference between the two frequencies
1 and 2
1 , 2 = 0 1 + (1/ 4Q 2 ) 0 Thus, BW 2 1 = 0
Q
2Q
39

The transmission zeros are located on the j axis, then

the magnitude response exhibits zero transmission at
= n ,which is called notch frequency.
Three cases of the second-order notch filter
!
!
!
!
!
Regular notch, = 0
Low-pass notch, > n
High-pass notch, < n
All notch cases, there are no transmission zeros at

either s = 0 or s =
All-pass filter
!
!
Two transmission zeros are in the right side half of the s plane
The magnitude response is constant over all frequencies , called
flat gain
40
11.5
The Second-Order LCR Resonator
41
The Resonator Natural Modes

The use of this resonator to derive circuit realizations
for the various second-order filter
Figure 16.17 (a) The second-order parallel LCR resonator. (b, c) Two ways of exciting the resonator of (a) without changing its natural structure:
Figure 11.17
resonator poles are those poles of Vo/I and Vo/Vi.
42
The Resonator Natural Modes

V0 1
Z=
= =
I Y (1
1
) + sC + ( 1 )
sL
R
s
C
= 2
s + s( 1 ) + ( 1 )
CR
LC
Equating the denominator to the standard from [ s 2 + s(0 Q) + 02 ]

leads to
02 = 1 LC and 0 / Q = 1/ RC
Thus,
0 = 1/ LC
Q = 0CR
43
Realization of transmission zeros
The transform function is
The transmission zeros are the values of s at which Z 2 ( s) = 0

,provided Z1 ( s) 0 ,and the values of s at which Z1 ( s) =
,provided Z 2 ( s)
T ( s) =
44
V0 ( s )
Z 2 (s)
=
Vi ( s ) Z1 ( s ) + Z 2 ( s )
Realization of transmission zero

!
Realization of the Low-Pass Function

Transfer function
T ( s)
V0 ( s )
Z 2 (s)
Y1
=
=
Vi ( s ) Z1 ( s ) + Z 2 ( s ) Y1 + Y2
1/ sL
1/ LC
= 2
(1/ sL) + sC + (1/ R ) s + s (1/ CR ) + (1/ LC )
Transmission zeros occur

Impedance sL = at s = ,and 1 / [ sC + (1 / R)] = 0 at s =
Realization of the High-Pass Function
V0 ( s)
Z 2 (s)
Y1
=
=
Vi ( s) Z1 ( s ) + Z 2 ( s) Y1 + Y2
sC
s2
=
=
(1 / sL) + sC + (1 / R) s 2 + s (1 / CR ) + (1 / LC )
T ( s)
Transmission zeros occur s = 0

45
Realization of transmission zero

!
Realization of the Band-Pass Function
Transfer function
T ( s)
V0 ( s)
Z 2 (s)
Y1
=
=
Vi ( s) Z1 ( s ) + Z 2 ( s) Y1 + Y2
1/ R
s(1 / RC )
= 2
(1 / sL) + sC + (1 / R ) s + s(1 / CR) + (1 / LC )
Transmission zeros occur

s = 0, s =
Realization of the Notch Functions
!
Transfer function
s 2 + 02
T ( s) a2 2
s + s (0 / Q) + 02
46

! L1 , C1 are
selected so that
L1C1 = 1/ n2
ensure that the natural modes

have not been altered; thus
C1 + C2 = C
!
L1 || L2 = L
For the LPN n > 0 ,thus L1C1 < ( L1 || L2 )(C1 + C2 )

!
The transfer function
s 2 + n2
T ( s ) a2 2
s + s(0 / Q) + 02
where n2 = 1 / LC1 , 02 = 1/ L(C1 + C2 )

0 / Q = 1/ CR
47

! s
V0
C1
=
Vi C1 + C2
,thus
a2 =
C1
C1 + C2
For the HPN n < 0,thus L1C1 > ( L1 || L2 )(C1 + C2 )

!
The transfer function can expressed as

V0
Z2
Y1
(1 / sL) + sC
=
=
=
Vi Z1 + Z 2 Y1 + Y2 (1/sL)+sC+(1/R)
s 2 + (1 / L1C )
= 2
s + s (1 / CR ) + [1 / ( L1 || L2 )C ]
T(s )
48
Realization of All-Pass Function

The transfer function can expressed as
s 2 s(0 / Q) + 02
T ( s) = 2
s + s(0 / Q) + 02
s 2(0 / Q)
s 2 + s(0 / Q) + 02
s (0 / Q)
= 0.5 2
s + s (0 / Q) + 02
T ( s) = 1
49
11.6
The Second-Order Active Filters Based on
Inductor Replacement
50
The Antoniou Inductance-Simulation Circuit
Z in V1 / I1 = sC4 R1R3 R5 / R2
L = C4 R1R3 R5 / R2
51
The Antoniou Inductance-Simulation Circuit
52
The Op Amp-RC Resonator

0 = 1/ LC6 = 1/ C4C6 R1 R3 R5 / R2
Q = 0C6 R6 = R6
!
C6 R2
C4 R1 R3 R5
Select C4 = C6 = C,R1 = R2 = R3 = R5 = R
0 = 1/ CR Q = R6 / R
Figure 11.21 (a) An LCR resonator. (b) An op ampRC resonator obtained by replacing the inductor L in the LCR
resonator of (a) with a simulated inductance realized by the Antoniou circuit of Fig. 11.20(a). (c) Implementation of the
buffer amplifier K.
53
Realization of the Various Filter Types
KR2 / C4C6 R1R3 R5

T (s) =
1
R2
s2 + s
+
C6 R6 C4C6 R1R3 R5
Ks 2
T ( s) =
s2 + s
K = DC gain
1
R2
+
C6 R6 C4C6 R1R3 R5
K = High-frequency gain
54
T (s) =
Ks / C6 R6
1
R2
s2 + s
+
C6 R6 C4C6 R1R3 R5
K [ s 2 + ( R2 / C4C6 R1R3 R5 )]
T ( s) =
1
R2
s2 + s
+
C6 R6 C4C6 R1R3 R5
K = Center-frequency gain
K = Low-and high frequency gain
55
C61
T ( s) = K
C61 + C62 s 2 + s
s 2 + ( R2 / C4C61 R1 R3 R5 )
1
R2
+
(C61 + C62 ) R6 C4 (C61 + C62 ) R1 R3 R5
n = 1/ C4C61R1 R3 R5 / R2
C61 + C62 = C6 + C
C61 = C (0 / n )2
0 = 1/ C4 (C61 + C62 ) R1 R3 R5 / R2
Q = R6
K = DC gain
C62 = C C61
C61 + C62 R2
C4
R1 R3 R5
56
s 2 + ( R 2 / C 4 C 6 R1 R 3 R 5 1 )
T (s) = K
R2
1
1
1
s2 + s
+
(
+
)
C 6 R 6 C 4 C 6 R1 R 3 R 5 1 R 52
n = 1 /
0 =
Q = R6
C 4 C 6 R1 R 3 R 5 1 / R 2
R2
1
1
(
+
)
C 4 C 6 R1 R 3 R 5 1 R 5 2
C 6 R2
1
1
(
+
)
C 4 R1 R 3 R 5 1 R 5 2
K = High-frequency gain
1
1
1
+
=
= 0C
R51 R52 R5
R51 = R5 (0 / n ) 2
R52 = R5 / [1 (n / 0 ) 2 ]
57
1 r2
R2
+
C6 R6 r1 C4C6 R1R3 R5
T (s) =
1
R2
s2 + s
+
C6 R6 C4C6 R1R3 R5
s2 s
z = 0 , Qz = Q (r1 / r2 ), Flat gain =1

58
r1 = r2 = r (arbitary)
Adjust r2 to make Qz = Q
11.7
Second-Order Active Filters Based on the
Two-Integrator-Loop Topology
59
Derivation of the Two-Integrator-Loop Biquad

!
The second-order high-pass transfer function

Ks 2
= 2
Vi
s + s (0 / Q) + 02
Vhp
02
1 0
Vhp + ( Vhp ) + ( 2 Vhp ) = KVi
Q s
s
02
1 0
Vhp = KVi ( Vhp ) ( 2 Vhp )
Q s
s
!
Use of the inverting op-amp Miller

integrator arrangement
60
Derivation of the Two-Integrator-Loop

Biquad
Thp Vhp / Vi
(0 / s)Vhp
Vi
(02 / s 2 )Vhp
Vi
K 0 s
= Tbp ( s)
2
2
s + s(0 / Q) + 0
K 02
= 2
= Tlp ( s)
2
s + s(0 / Q) + 0
61
Circuit Implementation
Vhp = Vi
!
R
R
R
R3
R2
(1 + f ) + Vbp
(1 + f ) V1 p f
R2 + R3
R1
R2 + R3
R1
R1
Substituting Vbp = (0 / s)Vhp , V1 p = (02 / s 2 )Vhp
Rf
Rf
R f 02
R3
0
R2
Vhp =
(1 + )Vi +
(1 + )( Vhp )
( Vhp )
R2 + R3
R1
R2 + R3
R1
s
R1 s 2
2
1
0
0
! Equating Vhp = KVi ( Vhp ) ( Vhp )
Q s
s2
! R / R =1
f
1
! R3 / R2 = 2Q 1
! K = 2 (1 / Q )
62
Circuit Implementation
Vo = (
!
RF
R
R
R
R
R
Vhp + F Vbp + F V1 p ) = Vi ( F Thp + F Tbp + F Tlp )
RH
RB
RL
RH
RB
RL
Substituting for Thp ,T1 p , Tbp

Vo
( RF / RH ) s 2 s ( RF / RB )0 + ( RF / RL )02
= K
Vi
s 2 + s (0 / Q) + 02

R
selecting RB = and H = n
RL 0
63
An Alternative Two-Integrator-Loop
Biquad Circuit
!
Use in a single-ended mode can be developed:
!
!
!
add and additional inverter

The coefficients of summer have the same sign
Dispense with the summing amplifier altogether, perform the
summation at the virtual-ground input of the first integrator
The circuit is call Two-Thomas biquad
64
The TowThomas biquad with

feedforward
Vo = (
V
V
V
rV 1
1
1
+ sC1 )( i ) + (
)Vo + [( 0 i ) i ](
)
R
sC
sQCR
sCR sCR2
R3 sCR
= p
= Vi ( s 2
Vo
=
Vi
s2 (
C1 s 1
r
1
+ (
)+ 2
)
C C R1 RR3 C R2 R
C1
1 1
r
1
)+s (
)+ 2
C
C R1 RR3 C RR2
1
1
s2 + s
+ 2 2
QCR C R
Figure 11.26 The TowThomas biquad with feed forward. The transfer function of Eq. (11.68) is realized by feeding
the input signal through appropriate components to the inputs of the three op amps. This circuit can realize all special
second-order functions. The design equations are given in Table 11.2.
65
The TowThomas biquad with

feedforward
!
Design data for the Circuit in fig. 11.26
!
!
!
!
All case C = arbitary R = 1/ 0C r = arbitary

C1 = 0 R1 = R2 = R / dc _ gain R3 =
LP
Positive BP C1 = 0 R1 = R2 = R3 = Qr / center frequency _ gain
Negative BP C1 = 0 R1 = QR / center frequency _ gain R2 = R3 =
HP
! Notch
(all types)
! AP
!
C1 = C high frequency _ gain R1 = R2 =
R3 =
C1 = C high frequency _ gain R1 =

R2 = R(0 / n ) 2 / high frequency _ gain R3 =
C1 = C flat _ gain R1 = R2 = R / gain R3 = Qr / gain
66
11.8
Single-Amplifier Biquadratic Active Filters
67
Single-Amplifier Biquadratic Active

Filters
!
!
!
Require only one opamp per biquad (second order)

Single-op amp is more sensitive to tolerances in the values of
capacitors and resistors than the multiple-op amp.
Limited to pole Q factor less than 10
11.8.1 Synthesis of the Feedback Loop
68
Synthesis of the Feedback Loop
!
!
!
!
Poles of the filter are the same as the zeros of

the RC feedback network
General form of the transfer function for
feedback network is t ( s) = Va = N ( s)
Vb D ( s )
N ( s)
Loop gain for feedback amplifier is L( s) = t ( s) A = A
D(s)
Poles of feedback amplifier (filter) are found from
setting 1 + L( S ) = 0 or t ( sP ) = 1 N ( s p ) = 0 since A =
A
69
Bridged-T networks
70
Bridged T network
General form of filters transfer function

a
Vo ( s ) a2 s 2 + a1s + ao
T ( s) =
=
Vi ( s ) s 2 + 0 s + 2
0
Q
1
1 1
1
s2 + s + +
V
C1 C2 R3 C1C2 R3 R4
T (s) = a =
Vb
1
1
1
1
s2 + s
+
+
+
C1 R3 C2 R3 C1 R4 C1C2 R3 R4
1
C1C2 R3 R4
0 =
s2 + s
Q =[
+ 02 = s 2 + s (
C1C2 R3 R4
R3
71
1
1 1
1
+ ) +
C1 C2 R3 C1C2 R3 R4
1
1
+ )]1
C1 C 2
Analysis of t(s) for Bridged-T

Network
t ( s) =
I3 = (Vb-Va)/R3
Ia = 0
Va
I2 = I 3
I1
Begin by finding I 2 and I 3 in terms of Va and Vb

I3 =
(Vb Va )
R3
and
I2 = I3 =
(Vb Va )
R3
Now find I1 and I 4 in terms of Va and Vb .
V12
I4
Va
Vb
V12 = Va I 2 Z C 2 = Va
(Vb Va )
R3
Vb
1
1
= Va 1 +
sC2
sR3C2 sR3C2
1
Vb
1 +
sR3C2 sR3 R4C2

V
Vb
(V V )
1
I1 = I 4 I 2 = a 1 +
b a
R4 sR3C2 sR3 R4C2

R3
I4 =
Vb
1
1 1
1
+
s 2 + s +
V
C1 C2 R3 C1C2 R3 R4
t (s) = a =
Vb
1
1
1
1
+
s 2 + s
+
+
C1R3 C2 R3 C1R4 C1C2 R3 R4
72
V12 Va
=
R4 R4
1
1
1 1
1
+ Vb +
= Va 1 +
R3 sR3 R4C2
R4 sR3C2 R3
Vb = I1Z C1 + V12
=
Va 1
1 1 Vb 1
1
+
1
+

+
sC1 R4 sR3C2 R3 sC1 R3 sR3 R4C2
1
Vb
+Va 1 +
sR3C2 sR3C2
Rearranging we get the final result for t(s)
Injecting the input Signal
Vo
s ( / C1 R4 )
=
1
Vi s 2 + s ( 1 + 1 ) 1 +
C1 C2 R3 C1C1 R3 R4
73
Generation of Equivalent Feedback

Loops
!
!
One method to generate more SABs is to use the

complementary transformation
The complementary transformation for op amp
circuits will result in circuit with the same poles as
illustrated in Fig.32 This transformation is performed
in two steps:
!
!
1. Interchange the op amp output and ground

2. Interchange the two input terminals of the op amp
74
Generation of Equivalent Feedback

Loops
The poles of the closed loop circuit of Fig. 32(a) can

be obtained by solving the characteristic equation:
1 + L( s ) = 0
The circuit of Fig. 32(b) uses the op amp as unity-gain

buffer. It cab be shown that the buffer has a gain of
A/(A+1). Thus, the characteristic equation of the
circuit of Fig. 32(b) is given by:
1
A
(1 t ) = 0
A +1
Can be manipulated to the form

1 + At = 0
75
Feedback Loops
Feedback loop obtained by applying
the complementary transformation
to the loop
Injecting the input signal through C1

realizes the high-pass function.
This is one of the Sallen-and-Key family of
circuits.
Namely, the design of circuit
R3 = R R4 = R / 4Q 2
CR = 2Q / 0 C1 = C2 = C
76
Feedback Generated by placing twoport RC network
Figure 11.34 (a) Feedback loop obtained by placing the bridged-T network of Fig. 11.28(b) in the negative feedback
path of an op amp.
(b) Equivalent feedback loop generated by applying the complementary transformation to the loop in (a). (c) A low-pass
filter obtained by injecting Vi through R1 into the loop in (b).
We can write for the active-filter poles

0 =
1
C3C4 R1 R2
Q =[
C3C4 R1 R2
C4
1
1
+ )]1
R1 R2
2
! R1 = R2 = R, C4 = C , and C3 = C / m yield m = 4Q
77
CR = 2Q / 0
11.9
Sensitivity
78
Sensitivity
Because of the tolerances in component values and

the finite op-amp gain, the response of actual
assembled filter will deviate from the ideal response.
For predicting such deviations, the filter designer
employs the concept of sensitivity
classical sensitivity function Sxy ,defined as
y / y
y x x denotes the value of a component and
y
y
S x = lim
, Sx =
x 0 x / x
x y y denotes a circuit parameter of interest(say,0 or Q)
y / y
For small changes S xy
x / x
thus we can use the value of S xy to determine the per-unit change in y
due to a given per-unit change in x
79
Example 11.3
For the feedback loop of Fig. 11.29, find the sensitivities of 0 and Q relative to all
the passive components and the op-amp gain.Evalate these sensitivities for the design
considered in the preceding section for which C1 = C2
Solution
1
1
0 =
,to obtain SC10 = SC20 = S R30 = S R40 =
2
C1C2 R3 R4
1
1 1
For Q we have Q = [ C1C2 R3 R4 ( + ) ]1
C1 C2 R3
C1 C2
C1
1 C2
Q
apply the sensitivity definition to obtain SC1 =
C + C
2 C1
C2
1
2
For the design C1 = C2 SQC1 = 0 SCQ2 = 0 S RQ3 =
80
1 Q
1
SR 4 =
2
2
Solution
we assume the op amp to have a finite gain A, the characteristic equation
for the loop becomes 1 + At ( s) = 0
using the design values C1 = C2 = C , R3 = R, R4 = R / 4Q 2 , and CR=2Q /0
s 2 + s (0 / Q) + 02
we get t ( s) = 2
s + s (0 / Q )(2Q 2 + 1) + 02
where the 0 and Q have the nominal or design values of the pole frequency and Q factor
the actual values are obtained by substituting for t ( s ) in 1 + A ( s ) = 0
s2 + s
2Q
(
Q
+ 1 + 02 + A( s 2 + s
+ 02 ) = 0
Q
assumeing the gain A to be real and dividing both sides by A + 1, we get
0 2Q 2
2
2
s + s 1 +
+ 0 = 0
Q
A +1
we see the actual pole frequency,0 a , and the pole Q, Qa , are
0 a = 0 , Qa =
Q
1 + 2Q 2 / ( A + 1)
81
Solution
Thus SwA0 a = 0
S
Qa
A
A
2Q 2 / ( A + 1)
=
A + 1 1 + 2Q 2 / ( A + 1)
For A 2Q 2 and A 1 we obtain

2Q 2
S
A
Is usual to drop the subscript a in this expression and write
2Q 2
Q
SA
A
Notice that if Q is high ( Q 5 ) ,its sensitivity relative to the amplifer gain can be quite high
Qa
A
82
11.10
Switched-Capacitor Filter
83
Switched-Capacitor Filter
The active RC filter circuits presented above have two

properties that make their production in monolithic IC
form difficult, if not practically impossible; these are the
need for large-valued capacitors and the requirement of
accurate RC time constants
84
The Basic Principle

The switched-capacitor filter technique is on the realization

that a capacitor switched between two circuit nodes at a
sufficiently high rate is equivalent to a resistor connecting
these two nodes.
85
The Basic Principle

The two MOS switches are driven by nonoverlapping

two-phase clock
Assume clock frequency f c ( f c = 1/ T ) is much

higher than the frequency of the input signal vi
During clock phase 1 ,capacitor C1 charges
up to the voltage vi
qC1 = C1vi
During clock phase 2 , C1 is connected to the
virtual-ground input of the op amp
86
The Basic Principle

The average current flowing between the input

node(IN) and the virtual-ground node(VG) is
iav =
CiVi
Tc
Define an equivalent resistance Req that is in effect

present between node IN and VG
Req vi / iav
thus,
Req Tc / C1
we obtain an equivalent time constant for the integrator: Time constant =C2 Req = Tc
!
The accuracy of capacitor ratios in MOS technology

can be controlled to within 0.1%
87
C2
C1
Practical Circuit
Figure 11.36 A pair of complementary stray-insensitive, switched-capacitor integrators. (a) Noninverting switchedcapacitor integrator.
(b) Inverting switched-capacitor integrator.
88
Realization of a complete biquad circuit
Figure 11.37 (a) A two-integrator-loop, active-RC biquad (b) its switched-capacitor counterpart.
89
Realization of a complete biquad circuit

Fig.11.37(a) yields
0 =
1
, replace R2 and R4 with their switched-capacitor equivalent values,that is
C1C2 R3 R4
R3 = Tc / C3 and R4 = Tc / C4
givs 0 =
1
Tc
C3 C4
select the C1 = C2 = C then C3 = C4 = KC
C2 C1
select the C1 = C2 = C then C3 = C4 = KC so K =0Tc

the Q factor of the corresponding switched-capacitor circuit is given by
Tc / C5
C
KC
C
, thus C5 should be selected from C5 = 4 =
= 0Tc
Tc / C4
Q
Q
Q
Center-frequency gain of the bandpass function is given by
C
C6
Center-frequency gain = 6 = Q
C5
0Tc C
Q=
90
11.11
Tuned Amplifiers
91
Tuned Amplifiers
Application in the radio-frequency and intermediatefrequency sections
The response is characterized by the center frequency 0 ,the 3-dB bandwidth B, and the skirt
selectivity, which is usually measured as the ratio of 30-dB bandwidth to the 3-dB bandwidth
The 3-dB bandwidth is less than 5% of 0 , this narrow-band property makes possible centain
approximations that can simplify the design process
92
The Basic Principle
Figure 11.39 The basic principle of tuned amplifiers is illustrated using a MOSFET with a tuned-circuit load. Bias
details are not shown.
93
Figure 11.39
V0 =
g mVi
g mVi
=
YL
sC + 1/ R + 1/ sL
Thus the voltage gain can be expressed as
V0
g
s
= m 2
Vi
C s + s (1/ CR) + 1/ LC
0 = 1/ LC
a 3-dB bandwidth of B=
1
CR
a Q factor of Q 0 / B = 0CR
and a center-frequency gain of
V0 ( j0 )
Vi ( j0 )
= gm R
94
Example 11.4
It is required to design a tuned amplifier of the type show in Fig.11.39,having f 0 = 1

MHz ,3-dB bandwidth = 10kHz , and center-frequency gain= 10 V / V .The FET available has at the bias point g m = 5 mA / V and r0 = 10k .
The output capacitance is negligibly small.Determine the value of RL ,CL , and L
Solution
Center-frequency gain = 10 = 5 R.Thus R = 2 k .Since R = RL ! r0 then R = 2.5k
B = 2 104 =
1
CR
Thus
1
= 7958 pF
2 104 2 103
Since 0 = 2 106 = 1/ LC , we obtain
C=
L=
1
= 3.18 H
4 2 1012 7958 1012
95
Inductor Losses
The power loss in the inductor is usually
represented by a series resistance rs
L
Q0 0
rs
Typically, Q0 is in the range of 50 to 200
1
1
1
1 1 + j (1/ Q0 )
=
=
rs + j0 L j0 L 1 j (1/ Q0 ) j0 L 1 + 1/ Q02
1
1
For Q0 1 Y ( j0 ) =
1
+
j
j0 L
Q0
Y ( j0 ) =
Q0 =
Rp
0 L
R p = 0 LQ0
96
Use of Transformers
Figure 11.41 A tapped inductor is used as an impedance transformer to allow using a higher inductance, L, and a
smaller capacitance, C.
Figure 11.42 (a) The output of a tuned amplifier is coupled to the input of another amplifier via a tapped coil. (b) An
equivalent circuit.
Note that the use of a tapped coil increases the effective input impedance of the second amplifier stage.
97
Amplifiers with Multiple Tuned Circuit
Figure 11.43 A BJT amplifier with tuned circuits at the input and the output.
To avoid the loading effect of the bias resistors RB1 and RB 2 on the
input tuned circuit, a radio frequency choke(RFC) is inserted in series
with each resistor
The analysis and design is complicated by the Miller effect
due to capacitance C
98
The Cascode and the CC-CB Cascade

! Two amplifier configurations do not suffer from the Miller effect
! The CC-CB cascade is usually preferred in IC implementations
99
Synchronous Tuning
! In the design of tuned with multiple tuned circuit, the question of the
frequency to which each circuit should be tuned arise for the overall
response to exhibit high passband flatness and skirt selectivity
B=
0
Q
21/ N 1
The factor 21/ N 1 is known as the

bandwidth-shrinkage factor
100
Stagger-Tuning
Stagger-tuned amplifiers are usually designed so that the overall

response exhibits maximal flatness around the center frequency f 0
a1s
0
0
1
1
j0 1
s+
+ j0 1
s+
2
2
2
Q
4
Q
2
Q
4
Q
For narrow-band filter,Q 1

a1 / 2
a1 / 2
T (s)
=
s + 0 / 2Q j0 ( s j0 ) + 0 / 2Q
T (s) =
This is known as the narrow-band approximation

A first-order low-pass network with a single pole at p = 0 / 2Q
K
, we can know p = s j0 so s = p + j0
p + 0 / 2Q
The result implies that the response of second-oder bandpass filter in the neighborhood of
Transfer function is T ( p ) =
its center fequency s = j0 is identical to the response of a first-order low-pass filter with
a pole at ( -0 / 2Q ) in the neighborhood of p = 0
Called a lowpass-to-bandpass transformation for narrow band filters

101
Stagger-Tuning
102
Stagger-Tuning
Figure 11.48 Obtaining the poles and the frequency response of a fourth-order stagger-tuned, narrow-band bandpass
amplifier
by transforming a second-order low-pass, maximally flat response.
Stagger-Tuning
01 = 0 +
B
2 2
, B1 =
B
, Q1
2
20
B
20
B
B
, B2 =
, Q2 =
B
2 2
2
Note that for the overall response to have a normalized center-frequency gain of unity,
02 = 0
the individual responses have to have equal center-frequency gain of 2
104
Chapter 12
Signal Generators and
Waveform-Shaping Circuits
Introduction
Linear
oscillators
Signal
Generators
RC frequency-selective network
(operation in 10~100K Hz)
- Wien-Bridge Oscillator
- Phase-Shift Oscillator
- Quadrature Oscillator
- Active-Filter Tuned Oscillator
LC frequency-selective network
(operation in 100K~hundreds MHz)
-LC-Tuned Oscillators
-Crystal Oscillators
Nonlinear
oscillators
Bistable multivibrators
Astable multivibrators
Monostable multivibrators
2
Oscillator Feedback Loop

The basic structure of sinusoidal oscillator consists of an amplifier and a

frequency selective network connected in a positive- feedback loop.
A( s )
1 A( s) ( s )
Loop gain : L(s) A(s) ( s)
Af (s) =
characteristic equation :
1-A(s) ( s) = 0
For the curcuit to produce sustained oscillations at a frequency 0
the characteristic equation has to have roots at s = j 0 .
Thus 1-A(s) (s) should have a factor of the form s 2 + o 2 .
3
Oscillation Criterion
Barkhausen criterion : at 0 the phase of the loop gain should be zero and
the magnitude of the loop gain should be unity.

L( j ) A( j ) ( j ) = 1
0
0
0
For this loop to produce and sustain

an output x o with no input(x s =0)
x f = xo
Ax f = xo
A xo = x0
A = 1
Oscillation Criterion
The stability of the frequency of oscillation will determined by the

manner in which the phase () of the feedback loop varies with frequency.
d
is large,
d
the resulting change in
If
0 will be small.
Nonlinear Amplitude Control

Because of the Barkhausen criterion, we need a mechanism for forcing A

to remain equal to unity at the desired value of output amplitude.
It is accomplished by providing a nonlinear circuit for gain control.
The function of gain-control mechanism :
(1)To ensure oscillation will start.
A is slightly greater than unity
(2)When the amplitude reaches the desired level.
A is reduced to exactly unity
Two basic approaches to the implementation:
(1) Limiter circuit
(2) Controlled-resistance element. (e.g. diodes, or JFET operated in the triode region)
6
Limiter Circuit for Amplitude Control

(i) vI very small and small output,
so vA is positive and vB is negative (D1 ,D 2 : off)
vO = R f R1 vI
vA = V
R3
R2
+ vO
R2 + R3
R2 + R3
vB = V
R5
R4
+ vO
R4 + R5
R4 + R5

(ii) vI goes positive and vO goes negative,

when v A becomes -VD (D1:on ,D 2 : off)
vO = L - = -V
R3
R
- VD 1 + 3
R2
R2
(ii) vI goes negative (D1:off ,D 2 : on)
vO = L + = V
R4
R
+ VD 1 + 4
R5
R5

(a) The transfer characteristic of the limiter circuit (R f , gain )

(b) When R f is removed, the limiter turns into a comparator
Wien-Bridge Oscillator
R2 Z p
L ( s ) = 1 +
R1 Z p + Z s
1 + R2 R1
L (s) =
3 + sCR + 1 sCR
s = j
L ( j ) =
1 + R2 R1
3 + j (CR 1 CR)
To sustained oscillations:
(1) the phase will be zero
w0 =
1
CR
(2) the loop gain to unity

R2
=2
R1
(To ensure that oscillation will start, one chooses R2 R1 slightly greater than 2)
10
Wien-bridge oscillator with a limiter circuit
To obtain a symmetrical output waveform,
R 3 = R 6 , and R 4 = R 5 .
11
Wien-bridge oscillator with an

alternative method
(1)Potentiometer P is adjusted until

oscillations just start to grow, so
the output can be varied by adjusting
potentiometer P.
(2)The output is taken at point b, because
the signal at b has lower distortion than
that at a.
(3)Point b is a high-impedance node, and a
buffer will be needed if a load is to be
connected.
12
Phase-Shift Oscillator
(1) It consists of a negative-gain amplifier(-K) with a three-section
(thrid-order) RC ladder network in the feedback.
(2) The circuit will oscillate at the frequency for which the phase shift
of the RC network is 180 .
(3) For oscillations to be sustained, the value of K should be equal to
the inverse of the magnitude of the RC network transfer function at
the frequency of oscillation.
13
Phase-shift oscillator with a limiter for

amplitude stabilization
(1) To start osicillations, R f has to
made slightly greater than the

minimum require value.
(2) The circuit stabilizes more rapidly,

and provides sine waves with more
stable amplitude.
(3) If R f is made much larger than this

minimum, the paid is an increased
output distortion.
14
Quadrature Oscillator
The quadrature oscillator is based on the two-intergrator loop.
Amplifier 1 is connented as an inverting as an inverting Miller intergrator
with a limiter in the feedback for amplitude control.
Amplifier 2 is connected as a noninverting integrator.
Norton
equivalent
15
Quadrature Oscillator
For R f = 2 R :
The circuit will be a perfect noninverting integrator.
vO 2 =
1 t
vO1dt
0
CR
loop gain:
L (s)
Vo 2
1
= 2 2 2
Vx
sC R
oscillation frequency:
0 =
1
CR
The name quadrature oscillator is used because the circuit provides

two sinusiods with 90 phase difference.
16
Active-Filter Tuned Oscillator

The circuit consists of a high-Q bandpass filiter connected
in a positive-feedback loop with a hard limiter.
Bandpass
filter
Limiter
17
Implementation of active-filter-tuned oscillator
This circuit uses a variation on the bandpass circuit based on the Antoniou
inductance-simulation circuit.
Limiter
18
LC-Tuned Oscillators
Two commonly used configurations of LC-tunned oscillators .

Colpitts oscillator:
0 = 1
Hartley oscillator:
CC
L 1 2
C1 + C2
0 = 1
19
( L1 + L2 ) C
The oscillation condition for Colpitts

Equivalent circuit of the Colpitts oscillator. C and r are neglected,
and the resistance R includes ro of the transistor.
At node C:
sC2V + g mV + + sC1 (1 + s 2 LC2 ) V = 0

R
since V 0 :
s 3 LC1C2 + s 2 ( LC2 R ) + s ( C1 + C2 ) + g m + = 0
R
20
The oscillation condition for Colpitts
1 2 LC2
3
g m + R R + j ( C1 + C2 ) LC1C2 = 0
s j :
For oscillations to start, both real and imaginary parts must be zero.
0 = 1
CC
L 1 2
C1 + C2
C2 C1 =g m R
for oscillations to start :
g mR > C2 C1
21
Complete circuit for a Colpitts oscillator
(1) Here the radio-frequency choke (RFC)

provides a high reatance at 0
but a low dc resistance.
(2) LC-tuned oscillators utilize the nonlinear
ic vBE characteristics of the BJT for
amplitude control.
Thus these LC-tuned oscillators are
know as self - limiting oscillators.
22
Crystal Oscillators
A piezoelectric crystal, such as quartz, exhibits electromechanical-resonance
characteristics that are very stable(with time and temperature) and highly
selective(having very high Q factors).
Since the Q factor is very high, we may neglect the resistance r.
s 2 + (1 LC s )
1
1
Z ( s ) = 1 sC p +
= sC 2
sL
+
1
sC
s
p s + ( C p + Cs ) LCs C p
a series resonance at s
Cp Cs
s = 1
s j ,
LCs
a parallel resonance at p
p = 1
1 2 s2
Z ( j ) = j
C p 2 p2
23
CsC p
L
Cs + C p
Crystal Oscillators
CsC p
p = 1 L
> s = 1
C
+
C
p
s
But C p Cs p s
LCs
Expressing Z(j )=jX( )
Use the crystal to replace L in the Colpitts.

The circuit will oscillate at the resonance
frequency of the crystal inductance L with
the series equivalent of Cs and (C p +C1C2 /(C1 +C2 )).
Since C s in much smaller than the others.
0 1/ LCs = s
24
Pierce crystal oscillator

(1) The Pierce oscillator utilizes a CMOS

inverter as an amplifier.
(2) Resistor R f determines a dc operating
point in the high-gain region of the
CMOS inverter.
(3) Resistor R 1 together with capacitor C1
provides a low-pass filiter that discourages
the circuit from oscillating at a higher
harmonic of the crystal frequency.
25
Bistable Multivibrator
The bistable multivibrator has two stable stables. The circuit can remain in
either stable state indefinitely and moves to the other stable state only
when appropriately triggered.
R1 ( R1 + R 2 )
v + = vo
26
Transfer Characteristics of the

vI is a trigger signal
R1 ( R1 + R2 )
Assume that vo is L+ , and thus v+ = L+
(1) vI is increase from 0
vI > v + (i.e L+ ), vo goes negative.
op amp saturating in the negative direction
v o = L- , v + = L - and VTH = L +
(2) vI is decreased
vI < v + (i.e L ), vo goes positive.
op amp go to its positive-saturation state
v o = L + , v + = L + and VTL = L
27
Transfer Characteristics of the

This bistable circuit switchs from the positive to negative state

as vI is increased, so it is said to be inverting.
The bistable multivibrator is basic memory element of digital system.

(when VTL <vI <VTH , the output will depend on the state that the circuit is already in)
The bistable is also known as a Schmitt trigger.
28
A Bistable Circuit With Noninverting Transfer

Characteristics
vO = L+ , v+ = 0 and vI = VTL
VTL = L+ ( R1 R2 )
Superposition:
R2
R1
v+ = vI
+ vO
R1 + R2
R1 + R2
vO = L , v+ = 0 and vI = VTH
VTH = L ( R1 R2 )
29
Bistable Circuit as a Comparator

Alough one normally thinks of the comparators as having a single

threshold value (Fig a), it is useful in many applications to add
hysteresis to the comparator characteristics (Fig b).
30
Hysteresis in the Comparator characteristics

as a means of Rejecting Interference
If the input signal is increasing in magnitude, the comparator with hysteresis

will remain in the low state until the input level exceeds VTH .
31
Making the Output Levels More Precise

The output levels of the bistable circuit can be made more precise than the
saturation voltages of the op amp are by cascading the op amp with a limiter circuit.
L + = VZ1 + VD
L + = VZ + VD1 + VD2
L - = - ( VZ2 + VD )
L - = - VZ + VD3 + VD4
32
Astable Multivibrator
A square waveform can be generated by arranging for a bistable multivibrator

to switch states periodically. This can be done by connecting the bistable
multivibrator with an RC circuit in a feedback loop.
Astable
Multivibrator
33
Operation of the Astable Multivibrator

For T1 :
For T2 :
v = L+ ( L+ L ) e t
v = L ( L L+ ) e t
= CR and v = L+ at t = T1
v = L at t = T2
T1 = ln
1 ( L L+ )
1
T2 = ln
1 ( L+ L )
1
For T1 = T2 , L+ = L
T = 2ln
34
1+
1-
Generation of Triangular and Square

Waveforms
The exponential waveforms generated in the astable circuit can be changed to
triangular by replacing the low pass RC circuit
with an integrator. The integrator causes linear
charging and discharging of the capacitor, thus
providing a triangular waveform.
35
Generation of Triangular and Square

Waveforms
For T1 :
VTH VTL L+
=
T1
CR
T1 = CR
VTH VTL
L+
T2 = CR
VTH VTL
L
For T2 :
VTH VTL L
=
T2
CR
For symmetrical square waves :

L+ = L , T = T1 + T2
T = 2CR
36
VTH VTL
L+
Monostable Multivibrator
In some applications the need arises for a pulse of known height and width
generated in response to a trigger signal. The monostable multivibrator has
one stable stage in whcih it can remain indefinitely, and a quasi-stable stage
to which it can be triggered and in which it stays for a predetermined interval.
vB ( t ) = L ( L VD1 ) e t C1R3
and vB (T ) = L :
L = L ( L VD1 ) e T C1R3
Trigger
circuit
V L
T = C1 R3 ln D1
L L
For VD1 << L
recovery
period
37
1
T C1 R 3 ln
1-
Integrated-Circuit Timers 555 timer

The circuit consist of two comparators, an SR flip-flop, a resistive voltage divider,

and a transistor Q1 that operates as a switch.
For comparator 1:
2
VTH = VCC
3
For comparator 2 :
1
VTL = VCC
3
38
Implementing a Monostable Multivibrator

Using the 555 IC
2
vc = VTH = Vcc at t = T :
3
T = CRln3 1.1CR
vc = Vcc (1 et RC )
39
An Astable Multivibrator Using the 555 IC
40
An Astable Multivibrator Using the 555 IC

In interval TL :
In interval TH :
vC = VTH e t CRB
vC = VCC (VCC VTL )e t C ( RA + RB )
at t = TL , vC = VTL = VCC 3,VTH = 2VCC / 3
at t = TH , vC = VTH = 2VCC 3,VTL = VCC / 3

TH = C ( RA + RB ) ln 2 0.69C(R A + R B )
TL = CRB ln 2 0.69CR B
Period T of the square wave:
T = TH + TL = 0.69C ( RA + 2 RB )
Duty cycle of the square wave:
Duty cycle
TH
R + RB
= A
TH + TL R A + 2R B
The duty cycle will always be greater

than 0.5 ; it approaches 0.5 if R A RB
41
Nonlinear Waveform-Shaping Circuits

Diodes or transistors can be combined with resistors to synthesize two-port
networks having arbitrary nonlinear transfer characteristics. Such two-port
networks can be employed in waveform shaping.
42
The Breakpoint Method

(1) vI < V1 , all diodes(ideal) :Off ,
zero current flows through R 4

output voltage at B = input voltage
(2) vI > V1 D2 : On
vO = V1 + ( vI V1 )
(3) VB = V2 , D1 : On
vO = V2
43
R5
R4 + R5
The Nonlinear-Amplification Method

It is based on feeding the triangular wave to the input of an amplifier having
a nonlinear transfer characteristic that approximates the sine function.

One such amplifier circuit consists of a differential pair with a resistance
connected between the two emitters.
vI is small:
Transfer characteristic : almost linear
(as a sine waveform is near its zero crossings)
vI is large:
Transfer characteristic : bend
(as a sine waveform approaches its peak)
44
Precision Half-Wave RectifierThe

Superdiode
vI > 0 : Diode : On
vO = vI
The straight-line transfer characteristic
vo -v I almost pass through the origin.
suitable for small input signal.
vI < 0 : Diode : Off
vO = 0
The op amp will be operating in an open-loop
fashion and its output will be at the
negative saturation level.
it requires some time to back into its
linear region (limit the operation frequency)
45
An Alternative Circuit
Catching
diode
vI > 0 : D2 : On D1 : Off
vO = 0
vI 0 : D2 : Off D1 : On
vO = vI ( R1 = R2 )
(1) The slope of the characteristic

can be set by R 1 and R 2
(2) The feedback loop around the
op amp remains closed all times.
(op amp remains in linear region)
46
Measuring AC Voltages
For sinusoid with VP :

1
min
CR4
vI : Half sine wave having a peak of Vp R2 / R1
(To reduce the amplitudes of all these

harmonics to negligible level.)
v2 : mostly DC ; V2 =
VP R2 R4
R1 R3
First-order
low-pass filter
47
Precision Full-Wave Rectifier

The principle of full-wave rectification:
Now replacing diodes D A with a superdiode, and replacing diode D B and

the inverting amplifier with the inverting precision halfwave rectifier but
without the catching diode, we obtain the precision full-wave-rectifier circuit.
48
Precision Full-Wave Rectifier

(absolute-value circuits)
49
vI > 0 :
vI < 0 :
D2 : On ; D1 : Off
D1 : On ; D2 : Off
vO = v I
when R1 = R2
(virtual short )
vO = v I
Precision Bridge Rectifier for

Instrumentation Applications
This circuit causes a current equal to |VA | / R
to flow through the moving-coil meter M.

Thus the meter provides a reading that is
proportional to the average of the absolute
value of the input voltage vA .
vA > 0 :
current flows from the op-amp output
through D1 , M , D3 , R
vA < 0 :
current flows into the op-amp output
through R, D2 , M , D4
feedback loop remains closed(virtual short)
50
Precision Peak Rectifiers
vI > vO :
vI reaches its positive peak : beyond that ,
Diode : On op amp act as a follower.
Diode : Off
vO follow vI
the capacitor will retain a voltage equal

to the positive peak of the input.
51
A Buffered Precision Peak Detector

When the peak detector is required to hold the value of the peak for a long time,
the capacitor should be buffered.

During the holding state :
High Rin,
low input bias current
Follower A2 supplies D2 with a small

current through R.
The output voltage of A1 = (vI VD )
When vI > the value stored on C :

D2 : Off , D1 : On
Capacitor C is charged to the
new positive peak of the input.
52
A Precision Clamping Circuit

By replacing the diode in the clamping circuit with a "superdiode",

the precision clamp is obtained.
53
Chapter 13
Output Stages and
Power Amplifiers
13.1 Classification of Output Stages
Figure 13.1 Collector current waveforms for transistors operating in (a) class A,
(b) class B, (c) class AB, and (d) class C amplifier stages.
2
13.2 Class A Output Stage
The transfer characteristic of

the emitter follower is :
vO =vI vBE1
The transfer characteristic of the emitter follower

The positive limit of the linear region is determined by the saturation of Q1.
vOmax =VCC VCE 1sat
The negative limit of the linear region is determined by Q1 turn off.
vO min = -IR L
Signal waveforms
Input a sine-wave to the

emitter-follower circuit
VCEsat
of Fig.13.2
Figure 13.4 Maximum signal waveforms in the class A output stage of Fig. 13.2 under the condition
I = VCC /RL or, equivalently, RL = VCC /I. Note that the transistor saturation voltages have been neglected.
Example13.1
Consider he emitter follower in Fig13.2 with VC C = 10V,I = 100mA,and RL
= 100.
( a ) Find the power dissipated in Q1 and Q2 under quiescent conditions ( vo = 0 ) .

( b ) For a sinusoidal output voltage of maximum possible amplitude ( neglecting VCEsat ) , find the average power dissipation in Q1 and Q2 . Also find the load power.
Sol:
( a ) Under quiescent condition v0 = 0, and each of Q1 and Q2
conducts a current I = 100mA=0.1A
and has a voltage VCE = VC C = 10V, thus

PD1 = PD 2 = VC C I = 10 0.1 = 1W
( b ) For a sinusoidal output voltage of maximum possible amplitude ( i.e.,10-V peak ) , the instantaneous
power dissipation in Q1 will be as shown in Fig.13.4 ( d ) .Thus the average power dissipation in Q1
will be
1
1
PD1 = VC C I = 10 0.1 = 0.5W
2
2
For Q2 , the current is constant at I = 0.1A and the voltage at the collector will have an average value of
0V. Thus the average voltage across Q2 will be VC C and the average dissipation will be
PD 2 = I vCE
= I VC C = 10 0.1 = 1W
average
Finally, the power delivered to the load can be found from
PL =
2
orms
V
=
RL
10 / 2
100
= 0.5W
Power-conversion efficiency
The power-conversion efficiency of an output stage is defined as
Load power(PL )
Supply power(PS )
Assuming that the output voltage of Fig13.2 is a sinusoid with the peak value V!o , the
average load power will be
(
P =
V"o / 2
RL
2
"
1 VO
=
2 RL
The total average supply power is
PS = 2VC C I
Thus
2
!
1 VO
1 V!o V!o
=
=
4 IRLVC C 4 IRL VC C
Since V! O VC C and V! O IRL , maximum efficiency is obtained when
V! O = VC C = IRL
13.3 Class B Output Stage
In class B stage of Fig13.5 are biased at zero current and
conduct only when the input signal is present. The circuit

operates in a "push-pull" fasion: Q N pushes ( sources )
current into load when vI is positive, and QP pulls ( sinks )
current from the load when vI is negative.
Figure 13.5 A class B output stage.
10
There exists a range of vI centered around

zero where both transistors are cut off and
vO is zero.
Figure 13.6 Transfer characteristic for the class B output stage in Fig. 13.5.
11
This "dead band" results in the crossover

distortion illustrated in Fig.13.7 for the
case of an input sine wave.
Figure 13.7 Illustrating how the dead band in the

class B transfer characteristic results in crossover
distortion.
12
Power-Conversion Efficiency
The average load power of class B stage is
2
1 V!o
PL =
2 RL
The average power drawn from each of the two power supplies is
And the total supply power will be
1 V!o
PS + = PS =
V
RL C C
2 V!o
PS =
VC C
RL
1 V! 2
Thus the efficiency will be given by = o
2 RL
2 V!o
V!o
VC C =
RL
4 VC C
The maximum efficiency is limited by the saturation of QN and QP to VC C VCEsat VC C

Thus max =
= 78.5% This value is larger than that obtained in the class A stage (25%)
2
1 VCC
The maximum average power available from a class B output stage is PL =
2 RL
13
Power Dissipation
2 V!o
1 V!
The average power dissipated in the class B stage is given by PD = PS PL =
V
RL C C 2 RL
When V!o
P D max
= VCC , PD max
2Vcc2
Vcc2
= 2
Thus, PDN max = PDP max = 2
RL
RL
14
Example13.2
It is required to designe a class B output stage to deliver an average power of 20W to an 8- load.
The power supply is to be selected such that VCC is about 5V greater than the peak output voltage.
This avoids transistor saturation and the associated nonlinear distortion, and allows for including
short-circuit protection circuitry. ( The latter will be discussed in Section13.8 ) Determine the supply
voltage required, the peak current grawn from each supply, the total supply power, and the powerconversion efficiency. Also determine the maximum power that each transistor must be able to dissipate safely.
Sol:
2
1 V!o
Since PL =
then V!o = 2 PL RL = 17.9V Therefore we select VCC = 23V.
2 RL
V!
The peak current drawn from each supply is I!o = o = 2.24A
Rl
1
Thus the average power drawn from each supply is PS + = PS = 2.24 23 = 16.4W
P
20
The power-conversion efficiency is = L =
= 61%
PS 32.8
The maximum power dissipated in each transistor is PDN max = PDP max
15
Vcc2
=
= 6.7W
RL
Reducing Crossover Distortion

The crossover distortion of a class B output stage can be reduced substantially by employing a
high-gain op amp and overall negative feedback.
The original dead band 0.7V is reduced to 0.7 Ao volt, where Ao is the dc gain of the op amp.
Figure 13.9 Class B circuit with an op amp connected in a negative-feedback

loop to reduce crossover distortion.
16
Single-Supply Operation
The class B stage can be operated from a

singal power supply, in which case the load
is capacitively coupled.
Figure 13.10 Class B output stage operated with a single power supply.
17
Class AB Output Stage
Crossover distortion can be virtually eliminated

by biasing the complementary output transistors
at a small nonzero current as Fig13.11 shown.
Assuming matched devices,
iN = iP = IQ = I S eVBB /2VT
The value of VBB is selected to yield the
required quiescent current IQ.
18
Circuit Operation
When vI goes positive, VB of QN increases by the same amount and vo = vI +
Positive vo causes iL to flow through RL iN that is, iN = iP + iL

iN vBEN and vBEN + vBEP = vBB thus vBEN vBEP and i p
iQ
iN
iP
The relationship between iN and iP : VT ln + VT ln = 2VT ln
, iN iP = I Q2
IS
IS
IS
For a given iL we can find iN by iN2 iLiN + IQ2 = 0
19
VBB
vBEN
2
For small vI , both transistor conduct, and

as vI is increased or decreased, one of the
two transistors take over the operation. Since
the transition is a smooth one, crossover
distortion will be almost totally eliminated.
Figure 13.12 Transfer characteristic of the class AB stage in

Fig. 13.11.
20
Output Resistance
Rout
VT
VT
= reN ! reP and reN = , reP =
iN
iP
Thus,
Rout =
VT VT
V
= T
iN i p iP + iN
Figure 13.13 Determining the small-signal output resistance of the class

AB circuit of Fig. 13.11.
21
Example13.3
In this example we explore the details of the transfer characteristic, vo versus vI , of class AB
circuit in Fig.13.11. For this purpose let VCC =15V,I Q =2mA, and RL = 100. Assume that QN
and QP are matched and have I S = 1013 A. First, determine the required value of the bias voltage
VBB . Then, find the transfer characteristic for vO in the range-10V to +10V.
Sol:
To determine the required value of VBB we use iN = iP = I Q = I S eVBB /2VT
with I Q
= 2mA and
I S = 1013 A. Thus, VBB = 2VT ln ( I Q I S ) = 1.186V

The easiest way to determine the transfer characteristic is to work backward; that is, for a
given vO we determine the corresponding value of vI . We shall outline the process for positive vO :
1. Assume a value for vO .
2. Determine the load current i L , i L = vO RL
3. Use iN2 iL iN I Q2 = 0 to determine the current conducted by QN , iN .
4. Determine vBEN from vBEN = VT ln ( iN I S )
5. Determine vI from vI = vO + vBEN VBB 2
22
Example13.3
It is also useful to find iP and vEBP as follows: iP = iN iL , vEBP = VT ln ( iP iS )
A similar process can be employed for negative vO . However, symmetry can be utilized, obviating
the need to repeat the calculations. The resualts obtained are displayed in the following table:
The table also provides value for the dc gain vO vI as well as the increemental gain vO vi at the
various values of vO . The incremental gain is computed as follows
vo
RL
=
vi
RL + Rout
where Rout is the small-signal output resistance of the amplifier, given by Rout
23
VT V
VT
T =
iN i
iP + iN
P
Example13.3
The incremental gain is the slope of the voltage transfer characteristic, and the magnitude of its
variation over the range of vO is an indication of the linearity of output stage. Observe that for
0 vo 10V, the incremental gain changes from 0.94 to 1.00, about 6%. Also observe as vO
becomes positive, QN supplies more and more of iL and QP is correspondingly reduced. The
opposite happens for negative vO .
24
13.5 Biasing the Class AB Circuit
A class AB output stage utilizing diodes for biasing.

If the junction area of the output devices, Qn and Q p ,
is n times that of the biasing devices D1 and D2 , a
quiescent current I Q = nI BIAS flows in the output devices.
Figure 13.14
25
Example13.4
Consider the class AB output stage under the conditions that VCC = 15V, RL = 100, and the
output is sinusoidal with a maximum amplitude of 10V. Let Q N and Q P be matched with
I S = 10 13 A and =50. Assume that the biasing diodes have one-third the junction area of the
output devices. Find the value of I BIAS that quarantees a minimum of 1mA through the diodes
at all times. Determine the quiescent current and the quiescent power dissipation in the output
transistors ( i.e.,at vO = 0 ) . Also find VBB for vO = 0, +10V, and-10V.
Sol:
The maximum current through QN is approximately equal to iL max = 10 V 0.1k =100mA. Thus
the maximum base current in QN is approximately 2mA. To maintain a minimum of 1mA through
the diodes, we select I BIAS =3mA. The area ratio of 3 yields a quiescent current of 9 mA through Q N
and QP . The quiscent power dissipation is PDQ = 2 15 9 = 270mW
For vo = 0, the base current of QN is 9/51 0.18mA, leaving a current of 3-0.18=2.82mA to flow
1
through the diodes. Since the diodes have I S = 10 13 A, the voltage VBB will be
3
VBB = 2V
2.82mA
ln
I
= 1.26V
26
At vO = +10V, the current through the diodes will decrease to 1mA, resulting in VBB 1.21V.
At the other extreme of vO = 10V, QN will be conducting a very small current; thus its base
current will be negligibly small and all of I BIAS ( 3mA ) flows through the diodes, resulting in
VBB 1.26V
27
Biasing Using the VBE Multiplier

Neglecting the base current of
Q1 , the R1 and R2 will carry the
same current I R , given by
IR =
BE 1
R1
R2
R1
VBB = I R ( R1 + R2 ) = VBE1 1 +
And VBE1 = VT ln
I C1
; I C1 = I BIAS I R
I S1
Figure 13.15 A class AB output stage utilizing a

VBE multiplier for biasing.
28
We can use a potentiometer to yield

the desired value of quiscent current
in QN and QP as shown in the figure.
29
Example 13.5
It is required to redesign the output stage of Example 13.4 utilizing a VBE multiplier
for biasing. Use a small-geometry transistor for Q1 with I S = 1014 A and design for a quiescent current I Q = 2mA.
Sol:
Since the peak positive current is100mA,the base current of QN can be as high as 2mA. we
shall therefore select I BIAS = 3mA, thus providing the multiplier with a minimum current of
1mA. Under quiescent conditions ( vO = 0 and i L = 0 ) the base current of QN can be neglected and all of I BIAS flows through the multiplier. We now must decide on how this current
( 3mA ) is to be divided between I C1 and I R . If we select I R
greater than 1mA, the transistor
will be almost cut off at the positive peak of vO . Therefore, we shall select I R = 0.5mA, leaving2.5mA for I C1. To obtain a quiescent current of 2mA in the output transistors,
VBB
2 1013
2.5 103
VBB = 2VT ln 13 = 1.19V and R1 + R2 =
= 2.38k . At IC1 = 2.5mA VBE1 = VT ln
= 0.66V
IR
10
1014
Thus R1 =
VBE1
= 1.32k R 2 = 2.38 1.32 = 1.06k
IR
30
13.6 CMOS Class AB Output Stages
31
The Classical Configuration

The quiescent current IQ in QN and QP can be determined by utilizing the iD vGS equations
for the four MOS transistor for the case vO = 0.
1
1
2
For Q1 : I D1 =I BIAS = kn ' (W L )1 (VGS 1 Vtn ) ; For Q2 : I D 2 =I BIAS = k p ' (W L ) 2 VSG 2 Vtp
2
2
Thus, VGG = VGS 1 + VSG 2 = Vtn + Vtp + 2 I BIAS
Likewise, VGG = VGSN + VSGP
1
k n ' (W L )1
= Vtn + Vtp + 2 I Q
Combined the two equations above: I Q = I BIAS
1
k n ' (W L ) n
1
k P ' (W
L)
2
1
k P ' (W
L)p
L)
k n ' (W L )1 + 1
k P ' (W L )2
k n ' (W L ) n + 1
k P ' (W
For the (W L ) ratios of Q1 , Q2 and QN , QP are matched mutually : I Q = I BIAS
32
(W L )n
(W L )1
The resreicted range of output voltage swing of Fig13.17:
The maximum allowed value of vO :

vO max = VDD VOV
BIAS
vGSN = VDD VOV
BIAS
Vtn vOVN
where vOVN is the overdrive voltage of QN when it is supplying iL max .

The minimum allowed value of vO :
vO min = VSS + VOV I + Vtp + vOVP where vOVP is the overdrive voltage of QP when sinking
the maximum negative value of iL .
(W L ) N ,P
vOVN , vOVP vO max and vO min
33
An Alternative Circuit Utilizing CommonSource Transistors

When vO is positive
vO max = VDD vOVP > VDD VOV
BIAS
Vtn vOVN
When vO is negative
vO min = VSS + vOVN < VSS + VOV I + Vtp + vOVP
The allowable range of vO has been increased.
Disadvantage :
The output resistance
(R
out
= ron rop
is very high.
Figure 13.18 An alternative CMOS output stage

utilizing a pair of complementary MOSFETs connected
in the common-source configuration. The driving
circuit is not shown.
34
Inserting an amplifier in the negative

feedback path of each of QN and QP
reduces the output resistance and makes
vO vI ;both are desirable properties
for output stage.
Fig.13.19
35
Output Resistance
feedback factor : =1
v
open-loop gain : A o = g mp ( rop RL )
vi
open-loop output resistance : Ro =RL rop
output resistance with feedback :
Rof =
Ro
1 + A
(R
rop )
1 + g mp ( rop RL )
output resistance :
Routp
1
1
1
1
1
=1
rop
; Routn
=
g mp
g mn
Rof RL g mp
Rout 1 ( g mp + g mn )
36
The Voltage Transfer Characteristic
Figure 13.21
37

At vO =vI = 0V, illustrated in Fig13.21(a):
1
for Q P : I DP = I Q = k p ' (W L ) p VSGP Vtp
2
1
Similarly, for Q N : I Q = k n ' (W L )n VOV2
2
and VSGP = Vtp + VOV I Q =
1
2
Usually the Q P and Q N are matched : kn ' (W L )n =k p ' (W L ) p =k I Q =
k p ' (W L ) p VOV2
1 2
kVOV
2
When vI is applied, illustrated in Fig13.21(b):
vSGP decreases by ( vO vI ) , vGSN increases by ( vO vI )

2
v v
v v
1
1
2
iDP = k [VOV ( vO vI )] = kVOV 2 1 O I = I Q 1 O I ,
2
2
VOV
VOV
v v v
v v
iDN = I Q 1 + O I iL = iDP iDN = 4 IQ O I = O
VOV
VOV
RL
VOV
VOV
VOV
vO = vI 1 +
,
usually
v
=
v
1
O
I
4 I R
4 I R
4 I Q RL
Q
L
Q
L
38

Gain error vO vI =
VOV
4 I Q RL
At the quiescent point, g mp = g m =
2IQ
vOV
gain error =
1
2 g m RL
Thus , gain error , Rout ;

I Q crossover distortion , Rout , gain error , quiescet power dissipation
39
Example 13.6
In this example we explore the design and operation of a class AB common-source
output stage of the type shown in Fig.13.19, required to opertae from a 2.5V power
supply to feed a load resistance RL = 100. The transistors available have Vtn = Vtp = 0.5V
and kn '=2.5k p '=250 A V 2 . The gain error is required to be less than 2.5% and I Q = 1mA.
Sol:
Gain error:
VOV
4 I Q RL
We are given the required maximum gain error of -0.025, I Q = 1mA, and RL = 100. In order
to keep low and also obtain as high a g m as possible [g m =2I Q /VOV ], we select VOV to be as
low as possible. Practically speaking, VOV is usually 0.1V to 0.2V. Selecting VOV = 0.1V results in which yields = 10 which is within the typically recommened range.
Fig13.22(a)shows the circuit in the quiescent state with the various dc voltages and currents indicated. The required(W/L)ratios of QN and QP can be found as follows:
40
Example 13.6
IQ =
(W L ) P
1
2
k p ' (W L ) P VOV
(W L ) P = 2000; (W L ) n =
= 800
2
kn ' k p '
Thus QN and QP are very large transisitors, not an unusual situation in a high-power output stage.
To obtain the out put resistance at the quiescent point, we use Rout = 1 ( g mp + g mn ) where
g mp = g mn =
2IQ
VOV
= 20mA/V Rout = 2.5
Next we wish to determine the maximum and minimum allowed value of vO . Since the circuit is symmetrical, we need to consider only either the positive-output or negative-output case. For vO positive, QP conducts more of the output current iL . Evemtually, QN turns off and QP conducts all of iL .
To find the value of vO at which this occurs, note that QN turns off when the voltage at its gate drops
from the quiescent value of -1.9V to-2V, at which point vGSN = Vtn . An equal change of -0.1V appears
at the output of the top amplifier, as showns in Fig13.22(b). Analysis of the circuit in Fig.13.22(b) show
that: iL = iDP = 4mA; vO = iL RL = 0.4V
For vO > 0.4V, QP must conduct all the current iL . The situation at vO = vO max is illustrated in Fig.13.22(c).
Analysis of this circuit resulat after some straightforward but tedious manipulations, in
vO max 2.05V ; iL max = 20.5mA
41
13.7 Power BJTs

Junction Temperature:
for silicon devices, TJ max is in the range of 150C to 200C.
Thermal Resistance:
TJ TA = JA PD ;
JA (C / watt)is the thermal resistance between junction and ambience
42
Power Dissipation Versus Temoerature

The thermal resistance:
T
T
JA = J max A
PD max
The maximum allowable power
dissipation:
T
TA
PD max = J max
JA
Figure 13.24 Maximum allowable power dissipation versus ambient

temperature for a BJT operated in free air. This is known as a powerderating curve.
43
Example 13.7
A BJT is specified to have a maximum power dissipation PD 0 of 2W at an ambient temperature TA0

of 25C, and a maximum junction temperature TJ max of 150C. Find the following:
(a) The thermal resistance JA .
(b) The maximum power that can be safely dissipated at an ambient temperature of 50C.
(c) The junction temperature if the device is operation at TA = 25C and is dissipating 1W.
SOL:
(a) JA =
TJ max TA0
= 62.5 C W
PD 0
(b) PD max =
TJ max TA
JA
= 1.6w
(c) TJ = TA + JA PD = 87.5C
44
Transistor Case and Heat Sink
Figure 13.25 The popular TO3 package for power transistors. The case is metal with a
diameter of about 2.2 cm; the outside dimension of the seating plane is about 4 cm. The
seating plane has two holes for screws to bolt it to a heat sink. The collector is electrically
connected to the case. Therefore an electrically insulating but thermally conducting spacer
is used between the transistor case and the heat sink.
45
JA = JC +CA
JA : thermeal resistance between junction and ambience.
JC : thermeal resistance between junction and case(package).
CA : thermeal resistance between case and ambience.
If a heat sink is ultilized CA = CS + SA
CS : thermeal resistance between case and sink.
SA : thermeal resistance between ambience and sink.
TJ TA = ( JC +CS + SA ) PD
Figure 13.26 Electrical analog of the thermal conduction

process when a heat sink is utilized.
46
PD max =
TJ max TC
JC
Figure 13.27 Maximum allowable power dissipation

versus transistor-case temperature.
47
Example 13.8
A BJT is specified to have TJ max = 150C and to be capable of dissipation maximum
power as follows: 40W at TC = 25C; 2W at TA = 25C

Above 25C, the maximum power dissipation is to be derated linearly with
JC = 3.12C / W and JA = 62.5C / W. Find the following:
(a) The maximum power that can be dissipated safely by this transistor when operated
in free air at TA = 50C.
(b) The maximum power that can be dissipated safely by this transistor when operated
at an ambient temperature of 50C, but with a heat sink for which CS = 0.5C / W and
SA = 4C / W. Find the temperature of the case and of the heat sink.

(c) The maximum power that can be dissipated safely if an infinite heat sink is used and
TA = 50C.
SOL:
(a) PD max =
TJ max TA
JA
= 1.6W
48
(b) JA = JC + CS + SA = 7.62C / W PD max = 13.1W

(c) The infinite heat sink has CA = 0 ; TC = TA
PD max =
TJ max TA
JC
= 32W
Figure 13.28 Thermal equivalent circuit for Example 13.8.
49
The BJT Safe Operaying Area
1. The maximum allowable current I C max

2. The maximum power dissipation hyperbola : locus of the points for which
vCE iC = PD max (atTC 0 )
3. The second-breakdown limit
4. The collector-to-emitter breakdown
voltage, BVCEO
Figure 13.29 Safe operating area (SOA) of a BJT.

50
Parameter Value of Power Transistors

1. At high current: n=2 iC = IS evBE 2VT

2. is low, typically 30 to 80, but can be as low as 5. And Temperature
3. At high current, r becomes very small and rx becomes important.
4. fT is low, C is large, and C is even laeger.
5. ICBO is large and, as usual, double for every 10C rise in temperature.
6. BVCE0 is typically 50 to 100V but can be as high as 500V.
7 IC max is typically in the ampere range but can be as high as 100A
51
Use of Input Emitter Followers

Fig.13.30 shows a class AB circuit biased using
transistors Q1 and Q2 , which also function as emitter folowers, thus providing the circuit with
a high input resistance.
Resisitors R3 and R4 are included to compensate
for possible mismatches between Q3 and Q 4 and
to guard against the possibility of thermal runaway
due to temperature differences between the inputand output-stage transistors.
Figure 13.30
52
Use of Compound Devices

To increase the current gain of the output-stage
transistors, and reduce the required base current
drive, the Darlington configuration is frequently
used to replace the npn transistor of class AB stage.
The Darlington configuration is equivalent to a
singale npn transistor having 1 2 , but twice the value of VBE .
Figure 13.31 The Darlington configuration.
53
The Darlington configuration for pnp

transistors
Figure 13.32 The compound-pnp configuration.
54
Figure 13.33 A class AB output stage utilizing a Darlington npn and a compound pnp.
Biasing is obtained using a VBE multiplier.
55
Short-Circuit Protection
Figure 13.34
56
Thermal Shutdown
Figure 13.35 Thermal-shutdown circuit.
57
A Fixed-Gain IC Power Amplifiers
Figure 13.36 The simplified internal circuit of the LM380 IC power amplifier. (Courtesy National Semiconductor
Corporation.)
58
A Fixed-Gain IC Power Amplifiers (LM380)

For emitter current of Q3 : I 3
VS VEB10 VEB 3 VEB1

R1
Assuming all the VEB to be equal I 3

For the emitter current of Q4 : I 4 =
VS 3VEB
R1
VO VEB 4 VEB 2 VO 2VEB
R2
R2
1
1
Let I 3 = I 4 , and R1 = 2 R2 VO = VS + VEB
2
2
The DC feedback from the output to the emitter of Q4 , through R2 acting to stabilize
the debias voltage at approximately half the power-supply.
59
Small-siganl Analysing
By writing a node equation

at the collector of Q6:
vi vO vi
+
+
=0
R3 R2 R3
vO
2R
= 2 50 V V
vi
R3
Figure 13.37 Small-signal analysis of the circuit in Fig. 13.36. The

circled numbers indicate the order of the analysis steps.
60
Figure 13.38 Power dissipation (PD) versus output power (PL) for the LM380 with RL = 8. (Courtesy
National Semiconductor Corporation.)
61
Power Op Amps
62
The Bridge Amplifier

The voltage swing of the output of bridge amplifier is twice the input.
Figure 13.40 The bridge-amplifier configuration.

63
Structure of the Power MOSFET
Figure 13.41 Double-diffused vertical MOS transistor (DMOS).
64
Characteristics of Power MOSFET
Figure 13.42
65
Temperature Effects
66
Comparsion with BJTs

The power MOSFET does ot suffer from second breakdown.
Power MOSFETs do not require the large dc base-drive
current of power BJTs.
Power MOSFETs have a higher speed of operation than the
power BJT.
67
A Class AB Output Stage Utilizing Power

MOSFETs
Figure 13.44 A class AB amplifier with MOS output transistors and BJT drivers. Resistor
R3 is adjusted to provide temperature compensation while R1 is adjusted to yield the
desired value of quiescent current in the output transistors. Resistors RG are used to
suppress parasitic oscillations at high frequencies. Typically, RG = 100.
68
Transistor Q6 is placed in direct thermal contact with the output transistors.By appropriate
choice of the VBE multiplication factor of Q6 , the bias voltage VGG (between the gates of the
output transistors) can be made to decrease with temperature at the same rate as that of the
sum of the threshold voltages(VtN + VtP ) of the output MOSFETs.
VGG = (1 +
R3
R
)VBE 6 + (1 + 1 )VBE 5 4VBE
R4
R2
VBE 6 is thermally coupled to output devices
VGG
R V
= (1 + 3 ) BE 6
T
R4 T
VGG (VtN + VtP )

=
T
T
multiplier is then adjusted to yield the value of VGG
Choosing R3 R4
The other VBE
required for the desired quiescent current in

69
and

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Chapter 10

Operational Amplifier Circuits

The Two-Stage CMOS Op Amp

The circuit consists of two stages:

Analog Integrated Circuit Lab

The first stage is formed by the differential pair Q1 Q2 .

The Two-Stage CMOS Op Amp

The differential pair is biased by current source Q5 , which is one of

The Two-Stage CMOS Op Amp

Analog Integrated Circuit Lab

The Two-Stage CMOS Op Amp

Analog Integrated Circuit Lab

Input Common-Mode Range

The lowest value of VICM has to

VICM VSS + VGS 3 Vtp

Input Common-Mode Range

The highest value of VICM should ensure that Q5 remains in

Thus, the range of VICM is

The signal swing allowed at

VSS + VOV 6 vO VDD VOV 7

Each of the two stages is modeled as a transconductance amplifier.

The input resistance is infinite:

The first-stage transconductance Gm1 is equal to Q1 and Q2 :

The dc gain of the first stage is

R2 represents the output resistance of the second stage:

The voltage gain of the second stage is

VOV 6 VA6 VA7

The output resistance of the op amp is equal to R2 :

Common-Mode Rejection Ratio (CMRR)

RSS is the output resistance of the bias current source Q5 .

Since g m ro is proportional to VA VOV = VA L VOV ,the CMRR is increased

Consider the equivalent circuit in Fig.10.2.

C2 : total capacitance at the output node of the op amp, including CL

The circuit has two poles and a positive real-axis zero:

f P1 is the dominant pole formed by the Miller-multiplied CC and R1

Analog Integrated Circuit Lab

the op amp can be represented by the simplified equivalent circuit in

The frequency compensation is the pole-splitting type.

phase lag exceeds 90

Figure 10.4 Typical frequency response of the two stage op amp.

The excess phase shift caused

By the right-half-plane zero is

The phase lag at f = ft will be

The phase margin will be

The CC will produce a right-half-plane zero and cause the additional

make the right-half-plane zero locating at negative real-axis

Consider the unity-gain follower with a step 1V.

The output voltage will be a ramp with a slope of I CC :

Thus the slew rate SR is

A relationship exists between ft and SR :

Thus, for a given t , SR is determined by the overdrive voltage at

Power-Supply Rejection Ratio(PSRR)

The PSRR is defined as the ratio of the amplifier differential gain to

The circuit is remarkably insensitive to variations in VDD , so PSRR + is

Power-Supply Rejection Ratio(PSRR)

Analog Integrated Circuit Lab

Now utilizing Ad gives

So, PSRR is of the form ( g m ro ) and is maximized by selecting long

Analog Integrated Circuit Lab

For an n-channel MOSFET, we can show that

To increase fT and improve the high-frequency response, we need

Analog Integrated Circuit Lab

Analog Integrated Circuit Lab