A CMOS Integrated Linear

Voltage-to-Pulse-Delay-Time Converter for Time

Based Analog-to-Digital Converters
Holly Pekau, Abdel Yousif, James W. Haslett
Department of Electrical and Computer Engineering, University of Calgary, Calgary, Canada, T2N 1N4
TRLabs, Calgary, Canada, T2L 2K7 (haslett@enel.ucalgary.ca)

Abstract A novel 0.13m CMOS integrated linear voltage

to pulse delay time converter (VTC) is proposed. The VTC
architecture uses current starved inverters where the inverter
delay versus input voltage characteristic is linearized by using
several parallel current starving devices with different gate bias
voltages and different amounts of source degeneration. The VTC
operates at a clock frequency of up to 500 MHz. Input voltage
signals of up to 2 GHz can be converted to pulse time delays
by using several VTCs in parallel. Since the voltage to time
conversion is essentially done with a single inverter stage no
sample-and-hold is needed for the input voltage. The VTC can
be used in combination with a time-to-digital converter (TDC) to
build a simple high speed, low power, time based analog-to-digital
converter (ADC) that consumes very little chip area.

I. I NTRODUCTION
The need for high-speed low-power ADCs for software
radio receivers has led to the development of a new type of
time-based ADCs where the input voltage is first converted
to a pulse delay time using a voltage-to-time converter (VTC),
and then the pulse delay time is converted to the digital domain
by a time-to-digital converter (TDC) consisting of digital
logic and counter circuits [1]. This type of time based ADC
can operate at very high clock and input frequencies while
consuming less power and die area than other high frequency
ADC architectures. Time based ADC architectures can also be
made reconfigurable for use in multi-standard software radio
receivers.
Several high speed VTCs for various applications have been
proposed by previous authors. Most of these VTCs are based
on the simple current starved inverter shown in Fig. 1 where
the input voltage vin controls the delay of the falling edge
of the clock signal (vclk ) through the inverter by changing
the equivalent resistance between the source of the inverter
NMOS device and ground. In [2] Djemouai et al propose a
basic current starved differential delay cell and add weak cross
coupled inverters to the cell to shorten the transition times of
the inverters in [3]. Dudek et al propose a similar VTC but add
a weak nfet with its gate tied to the supply to ensure the VTC
operates at very low input voltages [4]. Watanabe et al propose
a delay unit consisting of a series of inverters with the PMOS
sources tied to the input voltage [1]. Gray et al propose inverter
delay units where the clock drives the gates of the NMOS
devices and the delay is controlled via the bias voltages of the

0-7803-9390-2/06/$20.00 2006 IEEE

M1
Vclk-delayed

Vclk

M2
Vin

Fig. 1.

M3

Basic current starved inverter schematic

PMOS gates resulting in higher current consumption but lower

switching noise [5]. These previously published VTCs were
designed for various applications but are not suitable for use
in a high speed high resolution time based ADC with minimal
digital post processing because they are not sufficiently linear
and the voltage to time conversion is not sufficiently sensitive.
In this work we present a VTC with a novel linearization
scheme that results in improved linearity and higher voltage
sensitivity for time based ADC applications.

II. C IRCUIT D ESIGN

A simplified schematic of the VTC circuit designed in a
0.13m CMOS process is shown in Fig. 2. Current starving
of the inverter transistors M1, M2, M3, and M4 is done using
transistors M5, M6, and M9-M14. The gates of M11-M14 are
AC coupled to the input signal (not shown) to allow them to be
biased at different voltages than the gates of M5 and M6. M7
and M8 are used for source degeneration of current starving
devices M5 and M6. M9 and M10 are weak devices with small
aspect ratios and low gm s used to ensure the inverter operates
at very low input voltages. Weak cross coupled inverters with
small aspect ratios are connected between the output inverters
to allow for faster pulse transition times. Additional inverters
are used as output buffers to allow the VTC to drive the
capacitive load of the output pads. The layout of the VTC
in a 0.13m CMOS process is shown in Fig. 3.

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ISCAS 2006

M1

M3

vclk

vclk
M2

M4
vclkdelay
vclkdelay
M5
M6

vin
M9

M11
VDG

M13

Fig. 2.

M7

M8

vin
M12
VDG

M14

M10

Simplified VTC schematic (gate biasing not shown)

sensitivity of the VTC.

IV. S IMULATED R ESULTS
A. Voltage Sensitivity and Linearity

Fig. 3.

VTC layout in a 0.13m CMOS technology (150m by 80m)

III. L INEARIZATION M ETHOD

A novel linearization approach was implemented to allow
the VTC to be used in a high resolution ADC. Several
current starving devices with different gate bias voltages were
used in parallel. For simplicity, the half circuit consisting
of M1, M2, M5, M7, M9, M11, and M13 is discussed. The
main current starving device, M5, is biased in saturation
when the inverter consisting of M1 and M2 begins to make
the transition from a logic high output to logic low. M5 is
linearized by using source degeneration implemented with
M7. Additional current starving devices M11 and M13 are
used in parallel with M5. These additional current starving
devices are biased in the subthreshold region and enter
the moderate or heavy inversion regions when the input
signal is sufficiently large. This mitigates the compression
of the pulse delay time versus input voltage characteristic at
high input voltages. The additional parallel current starving
devices also increase the voltage sensitivity of the VTC. The
enhanced linearization scheme of the proposed VTC allows
it to achieve over 200 mV of dynamic range where the slope
is linear within 2% accuracy whereas previously published
VTCs are highly non-linear over a similar range of input
voltages. Simulated results in the following section show that
the proposed linearization scheme improves the linearity and

The voltage sensitivity and linearity of the VTC were simulated by sweeping the DC input of the VTC and measuring
the clock pulse delay time using a transient analysis with
BSIM3v3.2 device models of a commercial 0.13m CMOS
process in a commercial RF simulator. The results are shown
in Fig. 4 where the input voltage controls the delay of the
rising edges of the clock pulses rather than the falling edges
because the delayed pulses are measured at the output of a
buffer consisting of a single inverter. For comparison, the same
simulation was repeated for a standard non-linearized VTC
using the same devices and bias voltages and for a standard
VTC linearized using only source degeneration. The results are
shown in Fig. 5 and Fig. 6. It can be seen that the combination
of degeneration and staggered bias parallel current starving
devices allows the VTC to achieve highly linear performance
(within 2% of a perfectly linear slope) over an input range of
200 mV at a sensitivity of 2.5 ps/mV, and moderately linear
performance (within 25% of a perfectly linear slope) over an
input range of 250mV. The linear range is significantly lower
for the VTC with no linearization. Although the linearity of
the VTC linearized with degeneration only is comparable to
that of the VTC with the enhanced linearization scheme, the
voltage sensitivity of the VTC with the enhanced linearization
scheme is much higher (2.5ps/mV versus 1.2ps/mV). Using
only source degeneration for linearization and increasing the
width of the main current starving devices, M5 and M6, does
not result in a VTC as sensitive to the input voltage as the VTC
with the enhanced linearization scheme as demonstrated by
the simulated transient results for this case (Fig. 7). The pulse
edge delay times for VTCs with each of the four linearization
methods considered is shown in Fig. 8 where it is evident that
the VTC with the enhanced linearization scheme has improved
linearity and significantly higher input voltage sensitivity than
the other VTCs considered.

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Fig. 4. Simulated transient clock pulse delay for various DC input voltages
for the VTC using the enhanced linearization method

Fig. 6. Simulated transient clock pulse delay for various DC input voltages
for the VTC using only source degeneration for linearization

Fig. 5. Simulated transient clock pulse delay for various DC input voltages
for the VTC without linearization

Fig. 7. Simulated transient clock pulse delay for various DC input voltages
for the VTC using only source degeneration for linearization with the widths
of M5 and M6 increased by a factor of three

B. Maximum Input Frequency

x 10

1.2

Clock Pulse Edge Delay Time s

If the VTC is used without a sample-and-hold at the

input the maximum input frequency that can be used without
incurring a significant amount of error due to the input
signal changing during the VTC delay time is an important
consideration. The maximum input frequency of the VTC was
simulated by using sinusoidal input signals at multiples of
the clock frequency at quarter period, half period, and three
quarter period delays with respect to the clock. This allowed
the delay at sampling instants where the input signal was at a
minimum, and at a maximum, and where the input signal was
at its maximum rate of change to be simulated. The simulated
results are shown in Fig. 9 where the delay error is plotted
versus input frequency at the three different sampling instants.
The delay error was calculated as the difference in the output
pulse delay of the VTC compared to the output delay with a
DC input voltage equal to the sinusoidal input voltage at the
sampling instant. The maximum tolerable delay error due to
an input signal changing rapidly during the time when that
signal is effectively being sampled is the delay equal to one
least significant bit (LSB) of the ADC resolution. For example,
for 6 bit ADC resolution with an input dynamic range of 250
mV and a sensitivity of 2.5 ps/mV, one LSB corresponds to
3.9mV or a 9.76ps delay, so the maximum tolerable VTC
sampling error is 9.76ps. Several lines indicating the maximum
delay error for 5 bit, 6 bit, and 7 bit ADC resolution with are
shown in Fig. 9. From Fig. 9 it can be seen that for 6 bit
resolution signals at frequencies up to about 1.8 GHz can be
applied directly to the VTC input for conversion to the time

Enhanced Linearization
Degeneration Only
Degeneration Only, 3X Wider M5, M6
No Linearization

0.8

0.6

0.4

0.2

0
0

0.05

0.1
0.15
0.2
Input Voltage V

0.25

0.3

Fig. 8. Simulated transient clock pulse edge delay versus input voltage for
the VTCs with different linearization methods

domain. If a resolution higher than 6 bits is required for input

frequencies higher than 1.8 GHz then a sample-and-hold must
be used to sample the input signal before it is applied to the
VTC input. The input frequencies considered here are higher
than half the maximum clock frequency of (500MHz/2) so
time interleaving of several VTCs in parallel could be used
to avoid sub-sampling the input frequencies (time interleaving
is a technique commonly used in flash ADCs to increase the

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30
Min Peak
25

x 10

20

20 5 Bit Resolution

Input Referred Spot Noise at 750MHz

V 2 /Hz

Delay Error Compared to DC Input ps

35

15

10

Zero Crossing

6 Bit Resolution

7 Bit Resolution
Max Peak

0
0

0.5

1.5
2
2.5
3
Input Frequency Hz

3.5

4.5
9

x 10

Fig. 9. Simulated VTC delay error versus input frequency at various sampling
instants (at the maximum, minimum, and zero crossing of the input sinusoid)

3.5

2.5

1.5

1
0

effective sampling frequency [6]).

Fig. 10.

0.05

0.1
0.15
VTC Input Voltage
V

0.2

0.25

Simulated VTC input referred noise versus input voltage

C. Noise
A nonlinear periodic noise simulation was performed to
determine the noise performance of the VTC at various input
voltages. A DC input signal was used and the input referred
noise across a 50 source resistance was simulated. The simulated input referred VTC spot noise at 750MHz versus input
signal voltage is shown in Fig. 10. This input referred noise
is relatively constant over the input bandwidth of the VTC
except in very narrow bandwidths centered around the clock
frequency and the second harmonic of the clock frequency. At
these specific frequencies there is a significant increase in input
referred noise due to transient currents during the switching
time of the inverter (the noise is on the order of 105 V 2 /Hz
at the switching frequency). The VTC noise over most of
the input bandwidth is low (on the order of 1020 V 2 /Hz
as shown in Fig. 10) and would not limit the resolution of
an ADC using the VTC. However, VTC switching noise at
the clock frequency and its second harmonic may limit the
ADC resolution. The switching noise could be mitigated by
using notch filtering at the VTC input or by using switches
to disconnect the input source after the VTC has started
switching. It should be noted that the problem of switching
noise is common to other VTCs using the current starved
inverter topology [5].
V. C ONCLUSION
A VTC with a novel linearization scheme for high speed
time-based ADC applications was designed in a 0.13m
CMOS process. The slope of the delay versus voltage characteristic of the VTC is within 2% of a perfectly linear slope of
2.5ps/mV over an input range of 200 mV. The performance
improvements realized by using the linearization scheme are
demonstrated by comparing the linearity and voltage sensitivity of the proposed VTC to similar VTCs with no linearization
and linearization by source degeneration. Previously published

VTCs have not used linearization schemes and linearity and

sensitivity results have not been published so a direct linearity
comparison with other works is not feasible. Input signals at
frequencies up to 1 GHz can be applied to the VTC without
using a sample-and-hold and input signals at frequencies
higher than 1 GHz can be used if the VTC is preceded by
a sample-and-hold.
VI. ACKNOWLEDGEMENT
This work was supported by the Natural Sciences and
Engineering Research Council of Canada, TRLabs, the Alberta
Informatics Circle of Research Excellence, the University of
Calgary, and by CMC Microsystems.
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