Getting the best out of your precision design

with Zero-Drift amplifiers, Part 2

Stephan Baier, Staff Architect and Applications Engineer Analog and Interface Products
Division Microchip Technology Inc. - December 09, 2014

Editors note: Previously we published Part 1. And now we finish up with Part 2.

Up to now, we have focused on what is usually the main contributor to the total noisethe voltage
noise. But a comprehensive system-level evaluation will also need to include other noise sources,
and for op amps that includes the current-noise contributions. Standard CMOS amplifiers have very
low input-bias currents; typically it is just the DC gate leakage current. Tied into this is an extremely
low current noise density, often on the order of single femtoamps per root Hz (fA/Hz). Current
noise is analogous to voltage noise in that it has a 1/f and a flat noise region. The good news is that
the 1/f-current noise is also reduced by the self-correcting architecture; just like the voltage 1/fnoise. On the other hand, this architecture tends to have a higher level of current noise; on the
average of about 10x to 100x, compared to the standard CMOS amplifier. The reason for this could
be explained by considering that, for Zero-Drift architectures, the input bias current is dominated by
the charge injection, and that the increased time-averaged bias current also causes the current noise
to rise.

Especially for applications with high source impedances, the current noise multiplied by the source
impedance could reach or even exceed the level of the op amps voltage noise, and should therefore
be taken into consideration. For example, a Zero-Drift amplifier features a very low noise voltage of
6nV/Hz, but the specifications also list a current noise of 0.6pA/Hz. Consequently, if this amplifier
sees a source resistance of 10k, the resulting current-noise contribution will be as high as its inputreferred voltage noise.

Another characteristic of self-correcting amplifiers is that they exhibit intermodulation distortion

(IMD). Because the inputs are switched, it produces small transients at the chopping frequency that
can mix with the input signal frequency and result in intermodulation distortion detectable at the op
amps output. To address this artifact of self-correcting op amp architectures, some designs
implement a spread-spectrum clocking scheme. Instead of a fixed chopping frequency, the clock is
being randomized and any resulting IMD products are spread over a wider frequency range. While
this is effective in reducing clock-related noise peaks and IMD products, it can cause the average
noise floor to rise. IMD products appear at the sum and difference frequencies of the input and the

clock frequency (and its odd harmonics).

The magnitude of the IMD that is observable at the output of the op amp depends on the closed-loop
gain; i.e., higher gains will proportionally amplify the IMD frequencies. Auto-zero amplifiers with a
clock frequency in the range of 1 to 10 kHz will be more likely to have IMD frequencies appear
within the bandwidth of interest, hence it may be more difficult to apply filtering to attenuate IMD
products.

Chopper-stabilized amplifiers run with higher clock frequencies (typically 25 kHz to 250 kHz),
placing the IMD products higher up in the spectrum and, therefore, allowing for easier filtering.
However, in both cases a simple first-order filter can be accomplished by placing a capacitor in
parallel with the feedback resistor. Figure 3 shows an example circuit; here, the MCP6V31 operates
in a gain of +201V/V, which allows for about 2 kHz of closed-loop bandwidth. Adding capacitor (CF)
in the feedback reduces the signal bandwidth to about 200 Hz, effectively limiting the Noise-Power
Bandwidth (NPBW), and attenuating the noise and IMD. Alternatively, higher-order, low-pass
filtering can be placed after the Zero-Drift amplifier, which may also be needed for anti-aliasing
purposes.

Figure 3: Example of a simple noise filter, by adding capacitor CF in the feedback.

Virtually Zero-Drift

Virtually Zero-Drift
Typically, the drift of an amplifier refers to the behavior of the offset voltage as a function of
temperature, also known as the temperature coefficient. In addition, an amplifiers offset voltage
also tends to change over time. For traditional op amps, this drift over time (also referred to as
aging) typically isnt specified in the datasheet, but it can create significant errors over the life of
the device. What makes the offset drift a particular problem for precision applications is that it
cannot be accounted for by a one-time calibration.

Some precision op amps employ on-chip trimming schemes to improve the offset voltage drift, with
the best featuring a drift less than 1V/C. The self-correcting architectures inherently minimize
both the drift over temperature and time by continually calibrating the offset voltage. This technique
is so effective that the offset-drift specification on Zero-Drift amplifiers is specified in nanovolt per
degree Celsius (nV/C), almost three orders of magnitude lower than traditional op amps and,
therefore, virtually Zero-Drift.

Measuring and specifying such low voltage levels represents a significant challengehow to
separate the drift of the amplifier from all the other external thermal effects. Historically, the
maximum drift specification for Zero-Drift amplifiers leveled off at 50nV/C, which may have been a
restriction set by measurement methodology rather than the IC itself. But, progress is being made,
as one can now find Zero-Drift amplifiers specifying a maximum drift as low as 15nV/C.

PCB Layout Considerations for Low-Drift Designs

With such ultra-low offset voltage drift numbers, error sources that previously were only of limited
importance are now taking on the dominant role: e.g., the thermocouple junctions and the PCB
layout of the external components around the operational amplifier. This Thermocouple Effect
occurs wherever two dissimilar metals are joined together and a temperature-dependent voltage
appears across the junction to form a thermocouple (also known as the Seebeck Effect). This effect
can generate potentials of several microvolts per degree Celsius (V/C), quickly dominating the
accuracy of precision circuitry. In order to minimize thermocouple-induced errors, the PCB layout
designer should consider three basic steps: a) minimize thermal gradient, b) cancel thermo-junction
voltages, and c) minimize differences in thermal potential between metals.

Microchip Technology offers an excellent application note (AN1258) on this subject that includes a
number of examples. One of those examples is given in Figure 4, showing a recommended PCB
layout for a difference amplifier using a Zero-Drift op amp (the MCP6V01) and four external
resistors. While the relative matching of the resistors determines the Common-Mode Rejection
(CMR) of this circuit, the physical placement of the resistors plays a major role in drift-ove-temperature performance. All four resistors in this example layout are placed next to each other, in
order to match the thermal gradient across them. In addition, each pair (R1, R3 and R2, R4) is
positioned such that their individual thermo-junction voltages will cancel out.

Figure 4: Example of an optimized PCB layout for a difference amplifier configuration

(MCP6V01)

In more complex system assemblies, it may be difficult to follow such ideal PCB layout
recommendations. In this case, paying close attention to minimizing thermal gradients may already
be sufficient. Measures include the reduction of airflow by placing the precision circuitry away from
areas that need forced cooling, or by encapsulating this portion altogether. This assumes that the
encapsulated circuit doesnt include its own hot spot (i.e., there is minimal to no self-heating
effect). As mentioned earlier, low-power, Zero-Drift amplifiers requiring only microamps of quiescent
current are readily available and well suited for full encapsulation. However, the system designer
must consider the load that the amplifiers are expected to drive, as it may create a thermal problem.
Loads and Sources
Loads and Sources

When it comes to optimizing the load drive to the amplifiers capability, Zero-Drift models are very
similar to their time-continuous precision counterparts. For low-drift designs, the total loading,
which is the combination of the load resistor and the feedback resistor, should be minimized in order
to avoid high currents flowing through the op amps output stage. Otherwise, this could lead to a
thermal gradient inside the IC.

Datasheets typically provide information on recommended loading resistors, as well as information

on how to isolate higher-capacitive loading by using an isolation resistor in series with the
amplifiers output. A related aspect of load driving is maintaining the amplifiers stability. While the
known tools (e.g., isolation resistors) for ensuring op amp stability also apply to the Zero-Drift
amplifiers, it is important to point out that their output impedance often includes multiple poles and
zeroes.

Going back to Figure 1, consider that the chopper-stabilized amplifier consists of two signal paths
that are re-combined at the main amplifier, which in itself comprises several amplifier stages. To
achieve overall amplifier stability with manageable on-chip capacitance values, the internal amplifier
compensation is often distributed (known as pole-splitting), which results in this more complex
output impedance. Therefore, users of Zero-Drift amplifiers should take a moment to examine the
amplifiers open-loop gain curve and determine whether the desired closed-loop gain will result in
stable operation.

The relationship between the input-bias currents of an amplifier and the source impedances
connected to those inputs is well known. Any bias current, either from the inverting input (Ibias-) or
non-inverting input (Ibias+) will flow through any resistance on that input, and will result in an
offset voltage on the op amps input. Its important to recall that there is typically only one input bias
current specification given in datasheets, which is the average of Ibias- and Ibias+.

While, for time-continuous amplifiers, the input bias current is very much a DC component, it is
quite different for any self-correcting amplifier architecture. As discussed earlier, this is due to the
use of switches at the amplifiers input that are part of the offset correction. Usually implemented as
CMOS transmission gate switches, this dynamic operation creates a charge injection current on
each of the amplifiers input terminals. This charge injection current, effectively a result of finite
device matching, is directly proportional to the chopping frequency.

Auto-zero architectures, with their lower clock frequencies, tend to have relatively low input bias
currents. Newer models of the chopper-stabilized architecture show significantly lower input-bias
currents down in the single picoampere (pA) range, compared to older models that had 10x or 100x
higher currents. The MCP6V31, for example, features a typical input bias current of only 5 pA at
room temperature.

In general, up to about +85C the input bias current of Zero-Drift amplifiers is dominated by the
charge injection current; whereas, at higher temperatures, the input ESD diode leakage current
starts to dominate. In order to minimize the effects of the bias current, it is recommended to keep
the source resistance low and, if possible, of equal value for each of the amplifiers input terminals.
In some cases, it may be advisable to add resistors in series with the inputs to achieve the desired
improvements.

Time Domain Aspects

Time Domain Aspects

Considering that Zero-Drift amplifiers provide superior precision performance, it is understandable

that they also have a weaker sidetheir time-domain performance. Events that involve driving the
amplifier into an overload condition or a fast, large-scale signal step on the amplifiers input are
difficult situations for self-correcting architectures. As discussed earlier, the higher-bandwidth
signal path within the Zero-Drift amplifier is responsible for the overall speed (Gain Bandwidth and
Slew-rate). However, once the new value of a step response is reached, the output has to settle
accurately to within the same low offset limits. This involves the bandwidth-limited, chopperstabilization path and, therefore, is largely a function of the chopping frequency.

The use of higher clock frequencies has enabled relatively fast recovery and settling times; still, for
Zero-Drift amplifiers, those are typically in the tens of microseconds or higher. As usual, there are
design tradeoffs. Opting for faster settling times can lead to an increase in the corrected offset
value, which typically has higher priority in precision designs. Over-drive recovery is a similar
scenario, except that the amplifier has to first return to within its linear range of operation, which
usually takes some additional time. The total overload recovery time can therefore reach into the
hundreds of microseconds.

Because Zero-Drift amplifiers incorporate a fair amount of logic, it is not surprising that they also
include some means of ensuring a defined behavior during startup and power glitches (brownouts).
When first powering up a self-correcting amplifier, there is a small period of time during which the
output will reflect the uncorrected offset. Once the supply voltage reaches a defined trip-point, set
by the Power-On Reset (POR) circuit, the offset-correction mechanism needs a few clock cycles until
the output of the amplifier is within the specified offset-voltage limits.

Typically, this amplifier startup time is not a critical item from an overall system perspective as it is
usually well within the power-up time of the whole system. This may be the reason why many op amp
manufacturers do not show this parameter within their Zero-Drift amplifier datasheets. One
exception is Microchip Technology, which provides a typical specification along with a performance
graph for the startup timing (e.g., the MCP6V31 datasheet). It should be noted that the startup time
also depends on the configured gain of the amplifierlarger gains can increase the overall start-up
time.

Summary

Zero-Drift amplifiers have opened up performance levels previously thought not feasible or cost
prohibitive, and they are well on their way to becoming a natural choice for all areas of signal-path
applications, including the consumer space. The application of op amps always requires due
diligence in order to avoid instability, excess noise and signal errors. Zero-Drift amplifiers are
essentially no different.

The starting point is finding the right op amp for the application and then developing the circuit for
optimum performance. The strengths of Zero-Drift amplifiers, such as ultra-low offset and drift and
the absence of 1/f noise, fit particularly well with low-bandwidth sensor applications. Once designers
begin to understand Zero-Drift amplifiers, including how the elimination of 1/f noise is accomplished
and how to maintain low noise and drift performance, they will quickly start to realize the full
potential of this latest stage in the evolution of amplifier performance.

References:
1. Portable Design Magazine, Kevin Tretter, Auto-Zero Operational Amplifiers: Inherent Benefits in
Portable Signal-Conditioning Applications, September 2008.
2. EDN, Steve Taranovich, Conditioning Techniques for Real-World Sensors, November 15, 2012
3. EDN, Bruce Trump, 1/f Noise the flickering candle, March 4, 2013
4. Microchip Technology Inc., MCP6V01, MCP6V11, MCP6V31 Datasheets
5. Microchip Technology Inc., Kumen Blake, AN1258 Op Amp Precision Design: PCB Layout
Techniques