Digital Electronic Systems Unit 5

Integrated Circuit Technology

This unit describes the performance characteristics and parameters of various gates that are
available commercially as integrated circuits (ICs). There are three digital integrated circuit
(IC) technologies used to make the basic logic gates CMOS, TTL and ECL. CMOS and
TTL are the most common technologies.
CMOS (Complementary metal oxide semiconductor)
Most large scale ICs and microprocessors are implemented using CMOS technology
to construct the gates at chip level. This technology uses Field Effect Transistors.
Advantages low power dissipation, improving switching speed (due to ever
reducing transistor size), fully restored logic levels, very high levels of integration and
performance.
TTL (Transistor transistor logic)
This technology uses Bipolar Junction Transistors to construct the gates at chip level.
Advantage not as sensitive to electrostatic discharge as CMOS therefore no
handling precautions. Fast switching speed, but uses more power than CMOS.
ECL (Emitter-coupled logic)
This is also a bipolar technology. Advantage much faster than TTL, but uses much
more power than TTL also. This technology is not very commonly used.
Basic Operational Characteristics and parameters
When working with digital electronics, one should be familiar, not only with the logical
operation of Integrated Circuits (I.C.), but also with such operational properties as voltage
levels, noise immunity, propagation delays, fanout and loading. In this section the practical
aspects of these properties are discussed briefly.
DC supply voltage
The nominal supply voltage of the dc supply for CMOS and TTL devices is +5 Volts (though
3.3V CMOS is also available). This supply must be connected if the logic functions are to
work. It should be noted that this is usually omitted from the logic diagram for simplicity.
Shown below is what the gate would look like with the power supply attached.
+5
volts

Input A

Output F

Input B

Digital Electronic Systems Unit 5

Logic Level
So far we have talked about binary 1s and 0s or logic HIGHs and logic LOWs but we have
never put a figure on it. Ideally the logic level HIGH would be represented by +5 volts and
the logic level LOW represented by 0 Volts. These two levels hold true for both TTL and
CMOS devices. However because of small fluctuations in the dc power supply and from
surrounding noise, it is necessary to have a tolerance on these voltage levels so that they do
not have to be so precise. The tolerance level also depends on whether the logic level is
being used as an input or an output. Examples of logic tolerances are shown below.
INPUTS
TTL Logic

5v

5v
HIGH

2v

VIH(min)
VIL(max)

?
0.8 v LOW
0v
0v

CMOS Logic

5v

5v

OUTPUTS
5v
2.4 v

5v
HIGH
?

0.4 v
0 v LOW

5v

HIGH

VIH(min)
VIL(max)

LOW
0v

0v

VOL(max)

0v

5v

VOH(min)

4.9 v

3.5 v HIGH
1.5 v
?

VOH(min)

?
0.1 v
0v

VOL(max)
LOW

0v

Voltage tolerances for TTL and CMOS logic

It can be seen that the CMOS gate fully restores the logic levels to typically within 0.1V of
the supply levels.
Noise Immunity
Noise is unwanted voltage that is induced in the electrical circuits and can present a threat to
the proper operation of the circuit. Wires and other conductors within a system pick us stray
high-frequency electromagnetic radiation from adjacent conductors or from any other
external source. Note that power-line voltage fluctuation is a source of low frequency noise.
In order to avoid getting incorrect logic levels at the output of any circuit, the circuitry must
have a certain noise immunity. This is the ability to tolerate a certain amount of noise. It
relies on the fact that there is some small tolerance on the input of the waveform. Shown
below is a sample of what can happen if the noise becomes too great, causing the input signal
to go below or above the circuits noise immunity level.

Digital Electronic Systems Unit 5

Outside the noise tolerance of the gate

Input A

VIL(max)

Input A
Output

VIL (OV)

Output

V IH (5V)

Input A
Output

Input A

VIH(min)
Outside the noise tolerance of the gate

Output

Illustration of the effects of input noise on gate operation

Propagation Delay
When a signal propagates through a circuit there is a delay caused by how long it takes to go
from the input to the output. There are two propagation delays specific to logic gates:

tPHL :
the time between a designated point on the input pulse and the corresponding point on the
output pulse when the output is changing from HIGH to LOW.

tPLH :
the time between a designated point on the input pulse and the corresponding point on the
output pulse when the output is changing from LOW to HIGH.

The propagation delay limits the frequency that the circuit can work at. The greater the
propagation delay then the lower the maximum frequency. Thus, a higher-speed circuit has a
smaller propagation delay.

Digital Electronic Systems Unit 5

50%
Input
Output
50%

t PHL

t PLH

Propagation delay times of an inverter

Fan-out and Loading
The fan-out of a logic gate is the maximum number of inputs that can be connected to a gates
output, while still maintaining the output voltage levels within the specified limits. Fan-out is
specified in terms of unit loads. A unit load for a logic gate equals one input to a like circuit.
Driving Gate

Load Gate

10

The driving XOR gate output fans out to 10 like gate inputs

Digital Electronic Systems Unit 5

Types of fixed-function logic gates

All of the basic logic operations (NOT, AND, OR, NAND, NOR, XOR) are available in some
or all of the integrated circuit technologies. Logic gates are recognised by the use of the
prefix 74 or 54 in front of the device number. The prefix 54 is generally for military use and
74 prefix for commercial use. The integrated circuit technologies are designated prefixes as
follows:
5V CMOS Category
74HC
74HCT
74AC
74ACT
74AHC
74AHCT
3.3V CMOS Category
74LV
74LVC
74ALVC
BiCMOS Category
74BCT
74ABT
74LVT
74ALB
TTL Category
74
74S
74AS
74LS
74ALS
74F

Prefix Designation
High speed CMOS (74 indicates commercial grade)
High speed CMOS (T indicates TTL compatibility)
Advanced CMOS
Advanced CMOS (TTL compatible)
Advanced High-speed CMOS
Advanced High-speed CMOS (TTL compatible)
Prefix Designation
Low voltage CMOS
Low voltage CMOS
Advance Low-voltage CMOS
Prefix Designation
BiCMOS (Combines both CMOS and TTL)
Advance BiCMOS
Low voltage BiCMOS
Advanced low voltage BiCMOS
Prefix Designation
Standard TTL (no letter)
Schottky TTL
Advanced Schottky TTL
Low Power Schottky TTL
Advanced Low Power Schottky TTL
Fast TTL

Prefix designation for the various integrated circuit technologies

Digital Electronic Systems Unit 5

Common logic gate configurations and their standard identifier digits are as follows:
Gate Configuration
Quad 2-input NAND
Quad 2-input NOR
Hex inverter
Quad 2-input AND
Triple 3-input NAND
Triple 3-input AND
Dual 4-input NAND
Dual 2-input AND
Triple 3-input NOR
Single 8-input NAND
Quad 2-input OR
Quad 2-input XOR

Identifier Digits
00
02
04
08
10
11
20
21
27
30
32
86

Identifier Digits for standard gate configurations

Note that in the gate configuration descriptions, a single means 1 gate per IC, a dual means 2
gates per IC, a treble means 3 gates per IC, a quad means 4 gates per IC and a hex means 6
gates per IC.
Therefore, for example, a 74LV02 is a 3.3V CMOS quad 2-input NOR gate integrated circuit.
Example:
74LS00 Integrated Circuit (IC) is a TTL QUAD 2-input NAND IC. It has 14 pins:

Power Supply
+5V
14

indicates
pin 1

13

12

11

10

7
Ground
0V

74LS00 Quad 2-Input NAND IC

6

Digital Electronic Systems Unit 5

Example:

Data Sheet for 74LS00 Chip [page 1]

Digital Electronic Systems Unit 5

Data Sheet for 74LS00 Chip [page 2]

Digital Electronic Systems Unit 5

Explanation of Data Sheet Parameters

VC C

The dc voltage that supplies power to the device. Below the specified minimum,
reliable operation can not be guaranteed and above the specified maximum, damage
may occur to the device.

IO H

The output current that the gate provides (sources) to a load when the output is at
the HIGH level. By convention, the current out of a terminal is assigned a negative
value.

IO L

The output current that the gate sinks when the output is at the LOW level. By
convention, the current into a terminal is assigned a positive value.

VI H

The value of the input voltage that can be accepted as a HIGH level by the gate.
This parameter and the next three are relevant to Noise immunity.

VI L

The value of the input voltage that can be accepted as a LOW level by the gate.

VO H

The value of HIGH level output voltage that the gate produces.

VO L

The value of LOW level output voltage that the gate produces.

II H

The value of input current for a HIGH level input voltage.

II L

The value of input current for a LOW level input voltage.

IO S

The output current when the gate is shorted to ground and with input conditions that
would establish a HIGH level on the output.

IC C H

The total current from the VC C supply when all gate outputs are at the HIGH level.

IC C L

The total current from the VC C supply when all gate outputs are at the LOW level.