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Microwave Amplifiers - Single Stage Design [1]
INTRODUCTION
We limit this tutorial to single stage transistor amplifiers. Background material covering characteristics of
microwave transistors and gain and stability of general two port amplifier circuits can be found in Chapter 11 of [1].
The relevant equations from those sections are reproduced here for completeness.
Two-Port Power Gains
The three types of power gains for an arbitrary two-port network connected to source and load impedances, ZS and
ZL are:
Power Gain = G = PL/Pin is the ratio of power dissipated in the load ZL to the power delivered to the
input of the two-port network. This gain is independent of ZS, although some active circuits are
strongly dependent on ZS.
Available Gain = GA = Pavn/Pavs is the ratio of the power available from the two-port network to the
power available from the source. This assumes conjugate matching of both the source and the load,
and depends on ZS but not ZL.
Transducer Power Gain = GT = PL/Pavs is the ratio of the power available from the two-port network to
the power available from the source. This depends on both ZS and ZL.
These definitions differ primarily in the way the source and load are matched to the two-port device; if the input and
output are both conjugately matched to the two-port, then the gain is maximized and G = GA = GT. Equations for
these gains in terms of the S parameters of the active device and the four different reflection coefficients, shown in
Figure 1 and defined below, follow:
Figure 1. A Two-port network with general source and load impedances.

2
(
)
(1)
S 21 1 L
P
G= L =
Pin 1 in 2 1 S 22 L
( 2)
S 21 1 S
P
G A = avn =
Pavs 1 S 11 S 2 1 out
(3)
2
2
)(
)
2
S 21 1 S 1 L
P
GT = L =
2
2
Pin
1 S in 1 S 22 L
where
( 4)
L =
Z L Z0
Z Z0
, S = S
ZL + Z0
Z S + Z0
and
(5a )
in =
Z in Z 0
S S
= S 11 + 12 21 L
Z in + Z 0
1 S 22 L
(5b)
out =
Z out Z 0
S S
= S 22 + 12 21 S
Z out + Z 0
1 S11 S
Special cases of the transducer power gain occur when both the input and output are matched for zero reflection (L
= S = 0) and when the device is unilateral (S12 = 0 or is negligibly small) so that in = S11. For these cases we have:
( 6)
(7)
GT = S 21
GTU =
S 21
(1 )(1 )
2
S
2
1 S11 S
1 S 22 L
Matching networks can be designed for various criteria such as maximum gain, specified gain or specified noise
figure so that the circuit of Figure 2 can model the single-stage amplifier.
Figure 2. The general transistor amplifier circuit.

If we look at the transducer power gain of (3), we see that it accounts for both source and load mismatch. From (3),
we can define separate effective gain factors for the input matching network, the transistor itself, and the outputmatching network as follows:
(1 )
2
(8a )
GS =
(8b)
G0 = S 21
1 S in
2
(1 )
2
(8c )
GL =
1 S 22 L
Then the overall transducer gain is GT = GSG0GL. If the transistor is unilateral, so that S12 = 0 or is small enough to
be ignored, then in = S11, out = S22 and the unilateral transducer gain reduces to GTU = GSG0GL, where
(1 )
2
(9a )
GS =
( 9b)
G0 = S 21
1 S11 S
(1 )
2
(9c )
GL =
1 S 22 L
Stability
In the circuit of Figure 2 oscillation is possible if either the input or output port impedance has a negative real part
which would imply that |in| > 1 or |out| > 1. Because in and out depend on the source and load matching
networks, the stability of the amplifier depends on S and L as presented by the matching networks. Thus, we
define two types of stability:
1.
2.
Unconditional stability: The network is unconditionally stable if |in| < 1 and |out| < 1 for all passive source and
load impedances.
Conditional stability: The network is conditionally stable if |in| < 1 and |out| < 1 only for a certain range of
passive source and load impedances. This case is also referred to as potentially unstable.
Note that the stability condition of a network is frequency dependent, so that it is possible for an amplifier to be
stable at its design frequency but unstable at other frequencies.
Applying the above requirements for unconditional stability to (5) gives the following conditions that must be
satisfied by S and L, if the amplifier is to be unconditionally stable:
S12 S 21 L
< 1,
1 S 22 L
(10a )
in = S11 +
(10b)
out = S 22 +
S12 S 21 S
< 1.
1 S 11 S
If the device is unilateral (S12 = 0), these conditions reduce to the simple results that |S11| <1 and |S22| < 1 are
sufficient for unconditional stability. Otherwise, the inequalities of (10) define a range of values for S and L
where the amplifier will be stable. Finding this range for S and L can be facilitated by using the Smith chart, and
plotting the input and output stability circles. The stability circles are defined as the loci in the S (or L) plane for
which |in| = 1 (or |out| = 1). The stability circles then define the boundaries between stable and potentially unstable
regions of S and L. S and L must lie on the Smith chart (|S| < 1, and |L| < 1 for passive matching networks).
In the complex plane, an equation of the form | - C| = R represents a circle with center at C (a complex number)
and a radius R (a real number). Equations (10) can be put in this form (details are in [1]). The results are:
(S
=
S11* )
22
(11a )
CL
(11b)
RL =
(11c )
= S11 S 22 S12 S 21
S 22
S12 S 21
S 22
Similar results can be obtained for the input stability circle by interchanging S11, and S22:
(S
=
(12a )
CS
(12b)
RS =
*
)
S 22
11
S 22
S12 S 21
2
S11
Given the S parameters of the device, we can plot the input and output stability circles to define where |in| = 1 and
|out| = 1. On one side of the input stability circle we will have |out| (or |in|) < 1, while on the other side we will
have |out| (or |in|) > 1. These regions are defined in Figure 3 for the indicated values of |in|.
If the device is unconditionally stable, the stability circles must be completely outside (or totally enclose) the Smith
chard. Alternatively, it can be shown that the amplifier will be unconditionally stable if the following necessary and
sufficient conditions are met:
Figure 3. Output stability circles for a conditionally stable device. (a) |S11| < 1. (b) |S11| > 1.
2
1 S11 S 22
(13a )
K=
(13b)
<1
2 S12 S 21
>1
Recently, a new criterion has been derived that combines the K- parameters into a test involving only a singe
parameter, . The details of the derivation can be found in [2].
(14)
1 S11
S 22 S11* + S 21 S12
>1
To illustrate the method for determining stability, we will do Example 11.2 from [1]. All references to equations are
to that text. Mathcad will be used for this example.
Example 11.2
as follows:
The S parameters for the HP HFET-102 GaAs FET at 2 GHz with a bias voltage Vgs = 0 are given
0.894 e
0.020 e
S :=
3.122 ej 123.6 deg 0.781 e j 27.6 deg
j 60.6 deg
j 62.4 deg
Determine the stability of this transistor by calculating K and ||, and plot the stability circles.
Solution
From equations 11.31 and 11.24 we compute K and || as
:= S
K :=
1+
= 0.696
)2 (
S1 , 1
)2 (
S2 , 2
)2
2 S1 , 2 S2 , 1
arg( ) = 83.07 deg

K = 0.607
Since | | < 1, but K <1, the device is potentially unstable. The centers and radii of the stability circles are given by equations
11.28 and 11.29
C L :=
S 2 , 2 S 1 , 1
RS :=
)2 (
)2
S1 , 2 S2 , 1
RL :=
C S :=
S2, 2
S2, 2
)2 (
S1, 1
)2 (
)2
S1 , 2 S2 , 1
S1, 1
)2 (
arg ( C L) = 46.687 deg
RL = 0.5
)2
S 1 , 1 S 2 , 2
C L = 1.363
C S = 1.132
arg ( C S) = 68.461 deg
RS = 0.199
)2
This data can be used to plot the input and output stability circles. First, the smith chart must be constructed. The
contours for a Smith chart are stored in the file smithc.prn. First read in this file and set up the plot using the
following commands:
X := READPRN( "smithc.prn")
k := 1 .. rows( X)
SR := X ORIGIN
SI := X ORIGIN+ 1
These instructions plot the first column of numbers in the .prn file on the horizontal axis against the second column
on the vertical axis, creating a simplified Smith chart, with the following gridlines:
Circles of constant resistance r for r = 0, .2, .5, 1, 2, and 5.
Contours of constant reactance x are at x = 0, .2, .5, 1, 2, 5, -.2, -.5,- 1, -2, and -5.
To plot the stability circles on the chart, plot the vector, CL + RL and CS = RS. The sequence of instructions below
shows this procedure.
f ( , ) := exp( j )
step := 0 , .01 .. 1
((
((
((
((
realCL( step) := Re f RL , 2 step + CL
imagCL( step) := Im f RL , 2 step + CL

realCS ( step) := Re f RS , 2 step + CS
imagCS ( step) := Im f RS , 2 step + CS
The unstable regions of operation are the intersections of the stability circles and the outer edge of the Smith chart
shown below.
Circles of
constant
resistancefor r =
0, .2, .5, 1, 2,
and 5.
Contours of
constant
reactance forx
= 0, .2, .5, 1,
2, 5, -.2, -.5,1, -2, and -5.
gridlines from SMITHC.PRN

Load stabiltiy circle
Center, load stability circle
Source stability circle
Center, source stability circle
SINGLE-STAGE TRANSISTOR AMPLIFIER DESIGN

Design for Maximum Gain (Conjugate Matching)
After the stability of the transistor has been determined, and the stable regions for S and L have been located on
the Smith chart, the input and output matching sections can be designed. Since G0 of (8b) is fixed for a given
transistor, the overall gain of the amplifier will be controlled by the gains, GS and GL, of the matching sections.
Maximum gain will be realized when these sections provide a conjugate match between the amplifier source or load
impedance and the transistor. Because most transistors appear as a significant impedance mismatch (large |S11| and
|S22|), the resulting frequency response will be narrowband. In the next section we will discuss how to design for
less than maximum gain, with a corresponding improvement in bandwidth. Broadband amplifier design will be
discussed in the next tutorial.
With reference to Figure 2 and our knowledge of conjugate impedance matching, we know that maximum power
transfer from the input matching network to the transistor will occur when in = S* and the maximum power
transfer from the transistor to the output matching network will occur when out = L*. Then, assuming lossless
matching sections, these conditions will maximize the overall transducer gain. By satisfying these criteria and
manipulating the equations given above (see [1] for details), the values for S and L are:
(15a )
S =
B1 B12 4 C 2
2C1
L =
(15b)
B2 B22 4 C 2
2C 2
where
2
S11
(16a )
B1 = 1 + S 11 S 22
(16b)
B2 = 1 + S 22
(16c )
*
C1 = S11 S 22
(16c )
C 2 = S 22 S11*
2
2
We now do Example 11.3 from [1] using Mathcad.

Example 11.3 [1] Design an amplifier for maximum gain at 4.0 GHz using single-stub matching sections.
Calculate the plot the input return loss and the gain from 3 to 5 GHz.
The S parameters at 4.0 GHz for the GaAs FET are given as follows:
0.72 e 1j 116 deg 0.03 e1j 57 deg
S :=
2.6 e1j 76 deg 0.73 e 1j 54 deg
Solution
We first check the stability of the transistor. From equations 11.31 and 11.32 we compute K and || as
:= S
K :=
1+
arg( ) = 162.289 deg
= 0.488
)2 (
S1 , 1
)2 (
S2 , 2
)2
K = 1.195
2 S1 , 2 S2 , 1
Since || < 1, and K > 1, the device is unconditionally stable at 4.0 GHz. There is no need to plot the stability
circles. For maximum gain, we should design the matching sections for a conjugate match to the transistor. Thus,
S = *in and L = *out, and S, L can be determined from (11.43) and (11.44):
B1 := 1 +
S1 , 1
)2 (
S2 , 2
)2 (
)2
B2 := 1 +
S2 , 2
)2 (
S1 , 1
)2 (
)2
C1 := S1 , 1 S2 , 2
C2 := S2 , 2 S1 , 1
We use the proper sign for equations (11.43) so that S < 1 and L < 1 since |S11| < 1.
S :=
L :=
B1
B1 4 ( C1
2
)2
2 C1
B2
B2 4 ( C2
2
2 C2
)2
( )
S = 0.872
arg S = 123.407 deg
L = 0.876
arg L = 61.026 deg
( )
dB := 1
The effective gain factors of (11.19) can be calculated as
GSdB := 10 log
G0dB := 10 log( S2 , 1
GSdB = 6.197 dB
) 2
G0dB = 8.299 dB
1 ( L )2
GLdB := 10 log
( 1 S ) 2
2, 2 L
GLdB = 2.213 dB
So the overall transducer gain will be

GTmaxdB := GSdB + G0dB + GLdB
GTmaxdB = 16.71 dB
To match the source, we first calculate the normalized admittance looking toward the input generator (the load in
this case) from the output of the source matching network. It is given by
Z0 := 50
yS :=
1 S
yS = 0.3 1.819j
1 + S
We must now move toward the load (the 50 internal impedance of the generator) to a point where the real part of
the normalized admittance on a 50 line is equal to 1.
2j
1 S e
yS ( ) :=
Guess:
:= 1
2j
1 + S e
:= 0 ,
.. 2
20
2
:= .9
( (
:= root Re yS ( ) 1 ,
= 0.75
Re y S ( )
So the length of the transmission line is

lSt :=
lSt = 0.119
At this point the normalized admittance is
yS 2 lSt = 1 + 3.559j
so we need an open circuited stub with a normalized suseptance of 3.559. This line has length
lSopen :=
1
2
( ( (
atan Im yS 2 lSt
)))
lSopen = 0.206
We go through the same procedure for the output of the amplifier.

yL :=
1 L
1 + L
yL = 0.089 0.586j
We must now move toward the load to a point where the real part of the normalized admittance on a 50 line is
equal to 1.
yL( ) :=
2j
1 Le
2j
1 + Le
:= 1
:= 0 ,
.. 2
20
The final amplifier circuit created in Serenade Design Suite is shown in Figure 4.
Figure 4. Serenade Design Suite schematic of the design of Example 11-3 [1].
This circuit only shows the RF components; the amplifier will also require some bias circuitry. The return loss and
gain were calculated using Serenade Design Suite, using a .flp file for the transistor created from the S parameters
given above. The contents of the .flp file are:
FET11_3 3GHZ 5GHZ 3 50 1
*FET for Example
FET for Example 11.3 of Pozar.
3GHZ 0.80 -89.0 2.86 99.0 0.03 56.0 0.76 -41.0
4GHZ 0.72 -116.0 2.60 76.0 0.03 57.0 0.73 -54.0
5GHZ 0.66 -142.0 2.39 54.0 0.03 62.0 0.72 -68.0
The results of the simulation are plotted in Figure 5, and show the expected gain of 16.7 dB at 4.0 GHz, with a very
good return loss. The bandwidth where the gain drops by I dB is about 2.5%.
Design for a Specific Gain
In many cases it is preferable to design for less than the maximum obtainable gain, to improve bandwidth or to
obtain a specific value of amplifier gain. This can be done by designing the input and output matching sections to
have less than maximum gains; in other words, mismatches are purposely introduced to reduce the overall gain. The
design procedure is facilitated by plotting constant gain circles on the Smith chart, to represent loci of S and L that
give fixed values of gain (GS and GL). To simplify our discussion, we will only treat the case of a unilateral device.
The more general case of a bilateral device are discussed in detail in references cited in [1].
Figure 5. Results of the design of Example 11.3 [1].

In many practical cases |S12| is small enough to be ignored, and the device can then be assumed to be unilateral.
This greatly simplifies the design procedure. The error in the transducer gain caused by approximating |S21| as zero
is given by the ratio GT/GTU. It can be shown that this ratio is bounded by
(17)
(1 + U )
<
GT
1
<
GTU (1 U )2
where U is defined as the unilateral figure of merit,
(18)
U=
S12 S 21 S11 S 22
(1 S )(1 S )
2
11
22
Usually an error of a few tenths of a dB or less justifies the unilateral assumption.

For a design for specific gain we first define normalized gain factors as
(19a )
(19b)
gS =
gL =
1 S
(1 )
(1 )
1 S11 S
1 L
1 S 22 L
11
22
For fixed values of gS and gL, (19) represent circles on the S or L plane with center and radius given by
10
( 20a )
( 20b)
CS =
RS =
g S S11*
1 (1 g S ) S 11
1 g S 1 S11
1 (1 g S ) S11
Similarly, for the output section we have
( 21a )
( 21b)
CL =
RL =
*
g L S 22
1 (1 g L ) S 22
1 g L 1 S 22
1 (1 g L ) S 22
These results can be used to plot a family of circles of constant gain for the input and output sections. Then S and
L can be chosen along these circles to provide the desired gains. The choices for S and L are not unique, but it
makes sense to choose points close to the center of the Smith chart to minimize the mismatch and thus maximize the
bandwidth. We now illustrate an amplifier design for specified gain by doing Example 11.4 of [1] using Mathcad.
(Again, references to equation numbers are for those in [1].)
Example 11.4 Design an amplifier to have a gain of 11 dB at 4.0 GHz. Plot constant gain circles for GS = 2 dB
and 3 dB, and GL = 0 dB and 1 dB. Calculate and plot the input return loss and overall amplifier gain from 3 to 5
GHz. The S parameters at 4.0 GHz for the FET are given as follows:
1j 120 deg
0.75 e
S :=
2.5 e1j 80 deg
1j 70 deg
0.6 e
Solution
Since S12 = 0 and |S11| <1 and |S22| <1, the transistor is unilateral and unconditionally stable. From (11.48) we
calculate the maximum matching section gains as
dB := 1
GSmaxdB := 10 log
1 ( S1 , 1
G0dB := 10 log( S2 , 1
GLmaxdB := 10 log
) 2
G0dB = 7.959 dB
1 ( S2 , 2
GSmaxdB = 3.59 dB
GLmaxdB = 1.938 dB
So the overall transducer gain will be

GTmaxdB := GSmaxdB + G0dB + GLmaxdB
GTmaxdB = 13.487 dB
Thus we have 2.5 dB more gain than is required by the specifications. We use (11.49), (11.52), and (11.53) to
calculate the following data for the constant gain circles.
11
gS ( GS) := GS 1 ( S1 , 1
) 2
gL( GL) := GL 1 ( S2 , 2
) 2
CS ( GS) :=
RS ( GS) :=
CL( GL) :=
RL( GL) :=
gS ( GS) S1 , 1
1 ( 1 gS ( GS) ) ( S1 , 1
)2
1 gS ( GS) 1 ( S1 , 1
) 2
2
1 ( 1 gS ( GS) ) ( S1 , 1 )
gL( GL) S2 , 2
1 ( 1 gL( GL) ) ( S2 , 2
)2
1 gL( GL) 1 ( S2 , 2
) 2
2
1 ( 1 gL( GL) ) ( S2 , 2 )
For
GSdB3
GSdB3 := 3 dB
gS ( GS3) = 0.873
GS3 := 10
10
GS3 = 1.995
CS ( GS3) = 0.705
arg( CS ( GS3) ) = 120 deg
RS ( GS3) = 0.168
GSdB2
GSdB2 := 2 dB
gS ( GS2) = 0.693
GS2 := 10
10
GS2 = 1.585
CS ( GS2) = 0.628
arg( CS ( GS2) ) = 120 deg
RS ( GS2) = 0.293
GLdB1
GLdB1 := 1 dB
gL( GL1) = 0.806
GL1 := 10
10
GL1 = 1.259
CL( GL1) = 0.52
arg( CL( GL1) ) = 70 deg
RL( GL1) = 0.303
GLdB0
GLdB0 := 0 dB
gL( GL0) = 0.64
GL0 := 10
10
GL0 = 1
CL( GL0) = 0.441
arg( CL( GL0) ) = 70 deg
RL( GL0) = 0.441
This data can be used to plot the noise figure circle on the Smith chart. As in previous examples, we need to
generate the Smith chart. The contours for a Smith chart are stored in the file smithc.prn. First read in this file
and set up the plot using the following commands:
k := 1 .. rows( X)
SR := X ORIGIN
SI := X ORIGIN+ 1
12
To plot the gain circles on the chart, plot the vector, CS + RS. The sequence of instructions below shows this
procedure.
f ( , ) := exp( j )
step := 0 , .01 .. 1
((
)
)
CSI( step , GS) := Im( f ( RS ( GS) , 2 step) + CS ( GS) )
CSR ( step , GS) := Re f RS ( GS) , 2 step + CS ( GS)
The source gain circle is plotted below in Figure 6. We do the same for the load gain circles.
f ( , ) := exp( j )
step := 0 , .01 .. 1
((
CLR ( step , GL) := Re f RL( GL) , 2 step + CL( GL)
((
CLI( step , GL) := Im f RL( GL) , 2 step + CL( GL)
The choices for the design values of reflection coefficients are those closest to the center of the Smith Chart
satisfying the design requirement of 11 dB. We choose GS = 2 dB and GL = 1 dB so that the reflection coefficients
have values
j arg( CS ( GS2 ) )
S :=
CS ( GS2) RS ( GS2) ) e
L :=
CL( GL1) RL( GL1) ) e
j arg( CL( GL1) )
( )
S = 0.336
arg S = 120 deg
L = 0.216
arg L = 70 deg
( )
Z0 := 50
yS :=
1 S
yS = 1.142 0.748j
1 + S
yS ( ) :=
Guess:
2j
1 S e
:= 1
2j
1 + S e
:= 0 ,
.. 2
20
:= .9
( (
:= root Re yS ( ) 1 ,
Re y S ( )
= 1.138

lSt :=
lSt = 0.181
13
Smith chart with constant gain circles.

3 dB source gain
Center, 3 dB source gain
2 dB source gain
Center, 2 dB source gain
1 dB load gain
Center, 1 dB load gain
0dB load gain
Center, 0 dB load gain
Figure 6. Smith chart with constant gain circles.

y S 2 l St = 1 + 0.713j
14
lSopen :=
1
2
( ( (
atan Im yS 2 lSt
)))
lSopen = 0.099

yL :=
1 L
yL = 0.798 0.34j
1 + L
equal to 1.
yL( ) :=
2j
1 Le
:= 1
2j
1 + Le
Guess:
:= 0 ,
.. 2
20
2
:= .3
:= root ( Re( yL( ) ) 1 , )
Re y L( )
= 0.284
)
1

lLt :=
lLt = 0.045
y L 2 l Lt = 1 0.443j
lLopen :=
1
2
( ( (
)))
atan Im yL 2 lLt
lLopen = 0.066
Since this is negative, we add .5 to the length to get

lLopen := lLopen + .5
lLopen = 0.434
The final amplifier circuit created in Serenade Design Suite is shown in Figure 7. This circuit only shows the RF
components; the amplifier will also require some bias circuitry. The return loss and gain were calculated using
Serenade Design Suite, using a .flp file for the transistor created from the S parameters given above. The contents of
the .flp file are:
FET11_4 3GHZ 5GHZ 3 50 1
*FET for Example
FET for Example 11.4 in Pozar
3GHZ 0.80 -90.0 2.8 100.0 0.0 0.0 0.66 -50.0
4GHZ 0.75 -120.0 2.5 80.0 0.0 0.0 0.60 -60.0
5GHZ 0.71 -140.0 2.3 60.0 0.0 0.0 0.58 -85.0
The results of the simulation are shown in Figure 8. The bandwidth over which the gain varies by + 1 dB or less is
about 25%, which is considerably better than the bandwidth of the maximum gain design of Example 11.3. The
return loss, however, is not very good, being only about 5 dB at the design frequency.
15
Figure 7. Serenade Design Suite schematic of the design of Example 11-4 [1].
Figure 8. Serenade Design Suite results of the design of Example 11-4 [1].
Low-Noise Amplifier Design
Besides stability and gain, another important design consideration for a microwave amplifier is its noise figure. In
receiver applications especially, it is often required to have a preamplifier with as low a noise figure as possible
since the first stage of a receiver front end has the dominant effect on the noise performance of the overall system.
16
Generally it is not possible to obtain both minimum noise figure and maximum gain for an amplifier, so some sort of
compromise must be made. This can be done by using constant gain circles and circles of constant noise figure to
select a usable trade-off between noise figure and gain.
The noise figure of a two-port amplifier can be expressed as
( 22)
F = Fmin +
RN
Y S Yopt
GS
where the following definitions apply:

YS = GS + jBS = source admittance presented to transistor.
Yopt = optimum source admittance that results in minimum noise figure.
Fmin = minimum noise figure of transistor, attained when YS = Yopt.
RN = equivalent noise resistance of transistor.
GS = real part of source admittance.
Instead of the admittance YS and Yopt, we can use the reflection coefficients S and opt, where
1 1 S
,
Z 0 1 + S
( 23a )
YS =
( 23b)
Yopt =
1 1 opt
.
Z 0 1 + opt
The quantities Fmin, opt and RN are characteristics of the particular transistor being used, and are called the noise
parameters of the device; they may be given by the manufacturer, or measured. We can manipulate these equations
to arrive at circles of constant noise figure with radii and centers given by
( 24a )
RF =
( 24b)
CF =
N N + 1 opt
opt
N +1
N +1
),
with
( 24c )
N =
F Fmin
2
1 + opt .
4RN / Z 0
We illustrate the design method by doing Example 11.5 in [1] with Mathcad.
Example 11.5 A GaAs FET is biased for minimum noise figure and has the following S parameters and noise
parameters at 4 GHz:
1.6
0.05 e
0.6 e
1.9 ej 81 deg 0.5 e j 60 deg
j 60 deg
S :=
j 26 deg
Fmin := 10
10
RN := 20 ohm
j 100 deg
opt := .62 e
Z0 := 50 ohm
Design an amplifier having a 2.0 dB noise figure with the maximum gain that is compatible with this noise figure.
(We have to convert 2.0 dB to an absolute value for Fmin.)
Solution
First we compute the unilateral figure of merit from equation 11.47.
17
U :=
S1 , 2 S2 , 1 S1 , 1 S2 , 2
1 ( S1, 1
) 2 1 (
dB := 1
) 2
S2 , 2
Errorupper := 20 log( 1 U)
Errorupper = 0.532 dB
Errorlower := 20 log( 1 + U)
Errorlower = 0.501 dB
Next, we use equations 11.59 and 11.61 to compute the center and radius of the 2 dB noise figure circle:
2
F := 10
CF :=
RF :=
10
( F Fmin) Z0
N :=
opt
4 RN
1 + opt
N N + 1
opt
) 2
N = 0.102
arg( CF) = 100 deg
CF = 0.563
N+1
)2
RF = 0.245
N+1
This data can be used to plot the noise figure circle on the Smith chart. As in previous examples, we need to
generate the Smith chart. The contours for a Smith chart are stored in the file smithc.prn. First read in this file
and set up the plot using the following commands:
k := 1 .. rows( X)
SR := X ORIGIN
SI := X ORIGIN+ 1
To plot the noise figure circle on the chart, plot the vector, CF + RF. The sequence of instructions below shows this
procedure.
f ( , ) := exp( j )
step := 0 , .01 .. 1
((
((
realCF ( step) := Re f RF , 2 step + CF
imagCF ( step) := Im f RF , 2 step + CF
The noise figure circle is plotted in Figure 1. Minimum noise figure occurs for S = opt. We need to calculate data
for several input section constant gain circles. From equation 11.92,
2
gS S1 , 1
1 gS 1 ( S1 , 1 )
RS :=
CS :=
2
2
1 ( 1 gS) ( S1 , 1 )
1 ( 1 gS) ( S1 , 1 )
These values must also be plotted on Figure 1.
((
) )
imagCS ( step) := Im( f ( RS , 2 step) + CS)
realCS ( step) := Re f RS , 2 step + CS
18
gS .947
Fig. 1. Smith chart with the noise figure circle.
Circles of
constant
resistancefor r =
0, .2 .5, 1, 2,
and 5.
Contours of
constant
reactance forx
= 0, .2, .5, 1,
2, 5, -.2, -.5,1, -2, and -5.

Noise figure circle
Center, noise figure circle
Source stability circle
Center, source stability circle
Using trial and error for the value of gS and the zoom and crosshair features of Mathcad, we find that the
intersection of the gS circle and the noise figure circle is the desired value of S.
S := 0.141035 + j 0.522189
S = 0.541
( )
arg S = 74.886 deg
yielding
)2
( 1 S ) 2
1, 1 S
GS := 10 log
GS = 1.702 dB
For the output section we choose L = S22* for a maximum GL of
GL := 10 log
1 ( S2 , 2
GL = 1.249 dB
The transistor gain is

G0 := 10 log( S2 , 1
) 2
G0 = 5.575 dB
so the overall transducer gain will be

GTU := GS + G0 + GL
GTU = 8.527 dB
19
1 S
Z0 := 50
yS :=
yS = 0.449 0.663j
1 + S
yS ( ) :=
2j
1 S e
:= 1
2j
1 + S e
:= 0 ,
:= 1.5
Guess:
.. 2
20
( (
:= root Re yS ( ) 1 ,
= 1.417
Re y S ( )
lSt :=
lSt = 0.226
yS 2 lSt = 1 + 1.286j
lSopen :=
( ( (
atan Im yS 2 lSt
)))
lSopen = 0.145

:= S
B2 := 1 +
L :=
S2 , 2
)2 (
S1 , 1
B2 4 ( C2
2
B2
)2 (
C2 := S2 , 2 S1 , 1
)2
)2
yL :=
1 L
1 + L
( )
L = 0.457
2 C2
arg L = 68.435 deg
yL = 0.512 0.55j
equal to 1.
yL( ) :=
2j
1 Le
2j
1 + Le
:= 1
:= 0 ,
20
20
.. 2
Guess:
:= 1.5
( (
:= root Re yL( ) 1 ,
Re y L( )
= 1.522

lLt :=
lLt = 0.242
y L 2 lLt
= 1 + 1.027j
:=
( ( (
)))
atan Im y L 2 lLt
lLopen = 0.127
2
A complete AC circuit schematic from Serenade Design Suite, using open-circuited shunt stubs in the matching
sections, is shown in Figure 9. The results of the analysis of the circuit are shown in Figure 10. The .flp file
follows:
lLopen
FET11_5 3GHZ 5GHZ 3 50 1

*FET for Example 11.5
FET for Example 11.4 in Pozar
3GHZ 0.6 -60.0 1.9 81.0 0.05 26.0 0.5 -60.0
4GHZ 0.6 -60.0 1.9 81.0 0.05 26.0 0.5 -60.0
5GHZ 0.6 -60.0 1.9 81.0 0.05 26.0 0.5 -60.0
NOI RN
4GHZ 1.6 0.62 100 0.4
Notice that we include noise data in this file and display noise figure in the results.
Figure 9. Schematic for the specified noise figure amplifier of Example 11.5 [1].
21
Figure 10. Results for the specified noise figure amplifier of Example 11.5 [1].
[1] David M. Pozar, Microwave Engineering, John Wiley & Sons, Inc., New York, 1998.
[2] M. L. Edwards and J. H. Sinksy, "A New Criteria for Linear 2-Port Stability Using a Single Geometrically
Derived Parameter,: IEEE Trans. Microwave Theory and Techniques, vol. MTT-40, pp. 2803-2811, December
1992.
22

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Microwave Amplifiers - Single Stage Design [1]

Figure 1. A Two-port network with general source and load impedances.

Figure 2. The general transistor amplifier circuit.

arg( ) = 83.07 deg

arg ( C L) = 46.687 deg

arg ( C S) = 68.461 deg

realCL( step) := Re f RL , 2 step + CL

imagCL( step) := Im f RL , 2 step + CL

imagCS ( step) := Im f RS , 2 step + CS

gridlines from SMITHC.PRN

SINGLE-STAGE TRANSISTOR AMPLIFIER DESIGN

We now do Example 11.3 from [1] using Mathcad.

0.72 e 1j 116 deg 0.03 e1j 57 deg

arg( ) = 162.289 deg

arg S = 123.407 deg

arg L = 61.026 deg

The effective gain factors of (11.19) can be calculated as

So the overall transducer gain will be

So the length of the transmission line is

At this point the normalized admittance is

We go through the same procedure for the output of the amplifier.

Figure 5. Results of the design of Example 11.3 [1].

where U is defined as the unilateral figure of merit,

Usually an error of a few tenths of a dB or less justifies the unilateral assumption.

Similarly, for the output section we have

So the overall transducer gain will be

arg( CS ( GS3) ) = 120 deg

arg( CS ( GS2) ) = 120 deg

CL( GL1) = 0.52

arg( CL( GL1) ) = 70 deg

RL( GL1) = 0.303

CL( GL0) = 0.441

arg( CL( GL0) ) = 70 deg

RL( GL0) = 0.441

CSR ( step , GS) := Re f RS ( GS) , 2 step + CS ( GS)

CLR ( step , GL) := Re f RL( GL) , 2 step + CL( GL)

CLI( step , GL) := Im f RL( GL) , 2 step + CL( GL)

CL( GL1) RL( GL1) ) e

j arg( CL( GL1) )

arg S = 120 deg

So the length of the transmission line is

Smith chart with constant gain circles.

gridlines from SMITHC.PRN

Figure 6. Smith chart with constant gain circles.

We go through the same procedure for the output of the amplifier.

:= root ( Re( yL( ) ) 1 , )

So the length of the transmission line is

At this point the normalized admittance is

Since this is negative, we add .5 to the length to get

where the following definitions apply:

1.9 ej 81 deg 0.5 e j 60 deg

realCF ( step) := Re f RF , 2 step + CF

imagCF ( step) := Im f RF , 2 step + CF

realCS ( step) := Re f RS , 2 step + CS

Fig. 1. Smith chart with the noise figure circle.

gridlines from SMITHC.PRN

arg S = 74.886 deg

For the output section we choose L = S22* for a maximum GL of

The transistor gain is

so the overall transducer gain will be

So the length of the transmission line is

At this point the normalized admittance is

We go through the same procedure for the output of the amplifier.