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IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 44, NO.

4, APRIL 2009

1041

A Low Power 6-bit Flash ADC With Reference


Voltage and Common-Mode Calibration
Chun-Ying Chen, Michael Q. Le, Member, IEEE, and Kwang Young Kim

AbstractIn this paper, a low power 6-bit ADC that uses reference voltage and common-mode calibration is presented. A method
for adjusting the differential and common-mode reference voltages
used by the ADC to improve its linearity is described. Power dissipation is reduced by using small device sizes in the ADC and relying
on calibration to cancel the large non-ideal offsets due to device
mismatches. The ADC occupies 0.13 mm2 in 65 nm CMOS and
dissipates 12 mW at a sample rate of 800 MS/s from a 1.2 V supply.
Index TermsAnalog-to-digital (A/D) conversion, calibration,
mixed analogdigital integrated circuits, offset cancellation.

I. INTRODUCTION

N MANY mobile applications, a low power and low resolution (6 bits) ADC is required to cover a wide range of
sampling rates up to 800 MS/s [1][5]. A flash ADC is suitable
for such applications because of its simplicity and inherently
fast operation [6], [7]. However, a flash ADC exhibits a tradeoff
between power and linearity as will be explained below. The
performance of a flash ADC is determined mostly by its sampling rate and the random offset in each of the comparison circuits. Techniques such as averaging and offset sampling have
been used to reduce the effects of these random offsets [8][16].
As the minimum channel length is reduced in advanced process
technologies, the power can also be reduced by using a constant
W/Lmin ratio (where Lmin is the minimum channel length) for
the devices in the comparison circuits. However, the device mis[17][19] has not reduced at the same
match parameter
rate as Lmin in the latest process technologies. Thus, circuits
that have been scaled with a constant W/Lmin ratio will exhibit
larger random offsets than in the previous process technology
using the same W/L ratio. In order to maintain the same linearity performance when compared to older process technologies, the devices here must be sized relatively large to keep the
random mismatches below an acceptable level. In contrast, the
area and power of digital circuitry scales well with the channel
length reduction. The presented flash ADC in this paper utilizes
digital calibration techniques to both save power and improve
linearity [20]. It thus overcomes the inherent power versus linearity tradeoff associated with this type of data converter.
This paper is organized as follows. Section II provides background. Section III introduces our digital calibration techniques.
Measured results are presented in Section IV, which is followed
by the conclusion in Section V.
Manuscript received August 21, 2008; revised November 07, 2008. Current
version published March 25, 2009.
The authors are with Broadcom Corporation, Irvine, CA 92618 USA (e-mail:
cychen@broadcom.com).
Digital Object Identifier 10.1109/JSSC.2009.2014701

Fig. 1. Fully differential preamplifier.

II. BACKGROUND
In a 6-bit flash ADC, the input signal is first sampled using a
track-and-hold amplifier (THA). Then, 63 comparison circuits
make binary decisions based on the difference between the sampled signal and 63 reference voltages. Each comparison circuit
consists of a preamp and a comparator. The preamp amplifies
the difference between the sampled signal and its corresponding
reference voltage. The difference is then quantized by a comparator (CMP).
Fig. 1 shows the circuit for the preamp. The output of the
preamp is

(1)
is the gain of preamp, and
and
are the differential input signal and reference voltage,
respectively. Random static and dynamic offsets in the comparison circuits usually limit the linearity of a flash ADC. Due to
random device mismatches, transistor M1 is not exactly equal
to transistor M2. Likewise, transistor M3 is not equal to transistor M4. This mismatch can be modeled as an offset voltage
that appears at the input of the preamp. Each comparison circuit
has a different input referred offset. The random nature of the
input referred offset will cause non-linearity in the output of the
ADC and results in poor DNL and INL.
The standard deviation of the random offset in each preamp
with two differential pairs (as shown in Fig. 1) can be approximated as
where

(2)
is a process specific parameter and
is the
where
transistor gate area. For a 6 bit ADC to achieve better than

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IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 44, NO. 4, APRIL 2009

5.7 ENOB, the preamps are usually sized large enough to keep
below 0.1 LSB,
the standard deviation of random offset
where 1 LSB is equal to the full scale voltage divided by [15].
Therefore, the transistor gate area
can be expressed as
(3)
is the full-scale input voltage of the ADC. Therewhere
fore, the gate area for each input transistor of the preamp is deand the
, both of which are limited by
termined by
the process technology and supply voltage. Increasing the size
of the input transistors in the preamps increases the load capacitance of the track and hold amplifier (THA) which then increases the required THA power dissipation to operate at a given
speed. The power dissipation is proportional to the preamp input
.
transistor gate area, which is inversely proportional to
Hence, the THA power dissipation is also limited by the device
mismatch parameter which is fixed for a given process technology. To save power dissipation, the devices in the preamp
) in our
of the ADC are intentionally sized small (about 0.5
design. With only Vt mismatch, the resulting 1 sigma input-referred offset for the differential pairs shown in Fig. 3 is about
1.7 LSB for the technology used in this design. Calibration can
be used to improve the performance of the ADC that has been
optimized for low power.
III. CALIBRATION TECHNIQUE
For an ideal comparison circuit, the offset due to device mismatch is zero and the input signal is always compared against
its ideal reference voltage is Ref[k]. However, in the practical
case each comparison will have an error because the effective
reference voltage for each comparison circuit is shifted from its
ideal value due to random mismatches. The basic idea of our
calibration technique is to determine the offset voltage that exists in each comparison circuit and then use a different reference
voltage, Ref_cal[k], that cancels the offset voltage in each comparison circuit.
Fig. 2 shows a block diagram of the ADC with calibration. A
resistor ladder generates the reference voltages for the comparison circuits. In addition to having 1 LSB steps for the ideal reference voltages, the resistor ladder also generates 1/3 LSB steps
to allow for finer adjustments of the reference voltages used for
calibration. Two switches are connected to the signal input of
every preamp. During calibration, the signal input is bypassed
and the corresponding ideal reference voltage (Ref[63:1]) is
applied to the signal input of the preamp. Switches are also
placed in front of the reference voltage input of each preamp.
These switches allow different voltages to be selected as the reference voltage to the preamp (Ref_cal[63:1]). Since the extra
voltages used for calibration are generated from the same resistor ladder and the switches negligibly load the normal signal
path of the comparison circuits, no extra power is required.
The reference voltage step size is 1/3 LSB with a 5 bit control
signal. Thus, the reference voltage calibration range is about
5 LSBs which is enough to cover a 3 sigma variation in the Vt
mismatch. The devices in each differential pair are sized such
that the one sigma offset of each differential pair is less than
1.7 LSB. Compared to a design that achieves 0.1 LSB offset

Fig. 2. Block diagram of ADC with reference voltage calibration.

without any calibration, the size of preamp has been reduced by


278 times in our design. This will reduce the power dissipation
of the preamp and THA circuits dramatically.
At the start of calibration, the selected reference voltage is the
same as the ideal reference voltage Ref[k] that is applied to the
signal input of the kth preamp. If there is zero offset
, the comparison circuit output dithers between 1 with a
mean value of zero. However, if there is a nonzero offset between the signal input and the reference input, the output has a
nonzero mean value. The comparison circuit output is integrated
to determine which direction to adjust the reference voltage. The
reference voltage is adjusted until the comparison circuit output
has a mean value of zero. Once this condition is reached, the
input referred offset Vos[k] (which includes both static and dynamic offsets) is cancelled and the calibrated reference voltage
used by the kth preamp is
(4)
Since the matching of resistors is much better than required for
6-bit ADC resolution, the reference voltages from the resistor
ladder are treated as ideal, having negligible random errors.
Thus, the maximum residual offset voltage should be bounded to
1/3 LSB after calibration is complete. The calibration process
is only required to be done once at power up. After the ADC
has been calibrated, the digital calibration circuit is disabled
and therefore consumes no power during normal operation.
The number of control bits that are required for the calibration of each comparison circuit is set by the ratio of the desired
correction range divided by the calibration step size. This ratio
determines how many reference voltages are required for each
comparison circuit. If the correction range is wide, the comparison circuits can tolerate large device mismatches. This allows the device sizes inside the comparison circuits to be sized
smaller allowing for lower power operation. When a small calibration step size is used, the reference voltage adjustment is
more accurate and the performance of ADC will be improved.
However, more digital control bits are required when a large correction range and small calibration step size are desired. Thus,
there is an area tradeoff in choosing the correction range and step
size. Fig. 3 plots the simulated ENOB when using different calibration step sizes as a function of the comparison circuit offset
(1 sigma). Here, the calibration range is from negative 15 steps

CHEN et al.: A LOW POWER 6-bit FLASH ADC WITH REFERENCE VOLTAGE AND COMMON-MODE CALIBRATION

Fig. 3. ENOB as a function of the comparison circuit offset for different calibration step sizes.

to positive 15 steps (using a 5 bit control signal). If the calibration step size is small, the ENOB is high (due to the finer
calibration steps), but the ENOB will fall off quickly when the
random mismatch (3 sigma) is outside the reduced calibration
range. However, if the calibration step is large the maximum attainable ENOB is lower in the practical range of comparison circuit offsets. In our design we choose to implement 31 selectable
reference voltages that are 1/3 of an LSB apart as a tradeoff between the power/performance and cost. This allows us to correct for up to approximately 3 sigma random offsets which is
required for good production yield.
During calibration, the comparison circuit that is being
calibrated has its output applied to the input of the digital
accumulator. A single digital calibration circuit is shared
among all of the comparison circuits to save area at the expense
of a longer calibration time. The digital accumulator acts as
an integrator. If the mean output in the comparison circuit
is nonzero, the accumulator will ramp until it overflows or
underflows. When an overflow/underflow condition occurs, the
reference ladder voltage is incremented or decremented by 1/3
LSB, respectively, and the digital accumulator is reset to zero.
A digital gain control in the accumulator allows the loop gain to
be adjusted. A larger loop gain will allow the calibration loop
to converge more quickly for each comparison circuit at the
expense of having more variance in the steady-state calibrated
values. At the start of calibration, each comparison circuit has
a random offset voltage. The offset gradually gets reduced until
the error is within about 1/6 of an LSB in optimum case.
For the preamp circuit shown in Fig. 1, the gain is very
sensitive to the common mode mismatch between the reference ladder common mode voltage and the THA common
in the hold mode. A
mode output voltage
conventional common-mode feedback loop will force the
common-mode output voltage of the THA to be equal to the
reference ladder common-mode voltage in track mode. However, the common mode voltages can be significantly different
in the track and hold modes due to charge injection or the clock
feed through from the THA switches. Thus, the hold mode
common-mode output voltage will be shifted from the reference
ladder common-mode voltage. This difference has to be much
less than Vdsat of the input transistors in the preamp otherwise

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the effective gain of the preamp will be reduced dramatically.


For a low power preamp design, the differential pair is usually
operating near (or in) the subthreshold region where its Vdsat is
small. Thus, the common-mode mismatch needs to be small to
have sufficient gain from the preamp. To reduce this common
mode mismatch, a common mode calibration loop is used.
Fig. 4(a) shows the block diagram of common mode calibration circuit. One additional comparison circuit is required by
the common-mode calibration loop. This comparison circuit is
wired differently to the preamp than in the previous comparison
circuits used by the ADC. In Fig. 1 the preamp compares the difference between the input signal and reference voltage. But for
the configuration in Fig. 4 it compares the difference between
and the reference ladder midthe THA common mode
. The output of the differential preamp is
point

(5)
Hence, the preamp amplifies of the common mode difference
and
when wired in this configuration. The
between
preamp output is then quantized by a comparator. The comparator output is then integrated to determine the direction to
. Once the common-mode voltage is adjusted to its
adjust
proper value, the output of the comparator will have a mean
value of zero. At this point, the common mode voltage difference between the THA output and the reference ladder will be
minimized and limited by the residual offset of the comparison
circuit. However, the comparison circuit offset is small relative
to the common mode mismatch between the THA output and
the reference ladder.
Since the clock used in this comparison circuit is the same as
the one used in the other 63 comparison circuits, the comparator
makes its binary decision only when the THA is in the hold
mode. Since this comparator output is used to adjust the THA
common-mode level, the loop ignores the THA while it is in the
track mode which is desired. The same digital calibration circuit
that was used by the other 63 comparison circuits is used here to
save area. The disadvantage of sharing this circuitry is that the
calibration time will be longer since it is done serially.
IV. MEASURED RESULTS
Fig. 5(a) shows a histogram of the 5-bit calibration code
values after the reference voltages for 40 test chips have been
calibrated. The 5 bit reference voltage adjustment gives a code
that ranges from 15 to 15. Each step in the code corresponds
to a 1/3 LSB step. The measured 1 sigma offset is about 4.36
steps which is equal to 1.5 LSBs. Thus, the 3 sigma value is
about 13 steps which is equal to 4.5 LSBs. Since our design
has a 5 LSB correction range, the measured results show that
we have sufficient coverage in our calibration loop to handle
3 sigma offset variations which will provide good production
yield. Fig. 5(b) shows a histogram of 5 bit codes after the
THA output common-mode voltage has been calibrated. In
the common mode calibration loop, each code corresponds
to a 1 LSB change in the common-mode voltage. Again, the

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IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 44, NO. 4, APRIL 2009

Fig. 4. (a) Block diagram of common-mode calibration. (b) Preamp compares the common mode difference between signal and reference.

Fig. 5. Histogram of codes for (a) reference voltage calibration and (b) common mode calibration from 40 chips.

Fig. 6. (a) ENOB versus temperature for three chips. (b) ENOB versus input frequency at 800 MS/s.

3 sigma variation plus the mean value of the offset is less than
our correction range. Here, the average offset is nonzero. The
mean value gives a measure of the offset introduced by charge
injection and clock feed through in the THA.
ENOB as a function of temperature for three test chips is
shown in Fig. 6(a). The ADC was initially calibrated at room
temperature. Next, the temperature was varied from 25 C to
125 C. The measured variation in ENOB over this temperature
span is within 0.15 bits. Since the variation over temperature
is small, it is sufficient to calibrate the ADC only once during
the initial startup. Fig. 6(b) plots the measured ENOB as a function of input frequency at a sampling frequency of 800 MS/s.
The ENOB is better than 5.2 up to the Nyquist frequency. The
ENOB falls off as a function of frequency because of bandwidth
limitations in the THA circuit since we optimized the design for
low power operation in a frequency band around 200 MHz.

The measured output spectrum before and after calibration is


shown in Fig. 7. The spurious free dynamic range of the ADC is
about 35 dB before calibration and about 54 dB after calibration.
This represents roughly a 19 dB improvement in SFDR when
using calibration.
The plots in Fig. 8 show the measured INL and DNL before
and after calibration. Before calibration, both the INL and DNL
are greater than 2 LSBs which results in a measured ENOB of
less than 3. After calibration, the measured INL and DNL are
both less than half a LSB and the ENOB is about 5.6. So, there
is greater than 2.5 bit improvement in the ADC linearity.
This 6 bit ADC was fabricated in a 65 nm digital CMOS technology and occupies 0.13 mm . A die photo is shown in Fig. 9.
Table I provides a performance summary for this ADC. This
ADC shows a better figure of merit compared to two recent published papers [20].

CHEN et al.: A LOW POWER 6-bit FLASH ADC WITH REFERENCE VOLTAGE AND COMMON-MODE CALIBRATION

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TABLE I
PERFORMANCE SUMMARY

Fig. 7. Output spectrum before and after calibration.

submicron process technologies where the mismatch properties


of the process have not scaled proportionally with the channel
length reduction.
REFERENCES

Fig. 8. INL and DNL before and after calibration.

Fig. 9. Die photograph.

V. CONCLUSION
A 6-b ADC that uses reference voltage and common-mode
calibration has been presented. This ADC uses digital calibration to both reduce power and improve linearity allowing us
to overcome the inherent power versus linearity tradeoff in the
ADC design. This ADC may be of interest in high speed, low
power applications and is suitable for implementation in deep

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Chun-Ying Chen received the B.S. degree in


electrical engineering from National Taiwan University, Taipei, Taiwan, in 1989, and the M.S. and
Ph.D. degrees in electrical engineering from University of Michigan, Ann Arbor, in 1993 and 1997,
respectively.
From 1991 to 1993, he served as a second rank
Lieutenant in the Taiwanese army. In 1997, he joined
Motorola Inc., Tempe, AZ. Two years later, he joined
National Semiconductor Corporation, Santa Clara,
CA, working on CMOS analog circuit design. Since
2000 he has been with Broadcom Corporation, Irvine, CA, doing analog and
mixed-signal circuit design. He has 40 U.S. patents granted or pending in the
areas of PLLs/frequency synthesizers, power management, filters, and high
speed data converter.

IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 44, NO. 4, APRIL 2009

Michael Q. Le (S97M08) received the B.S., M.S.,


and Ph.D. degrees in electrical engineering from the
University of California, Davis, in 1994, 1998, and
2000, respectively.
From 1994 to 1995, he was with Level One Communications, Sacramento, CA. Since April 2000, he
has been a member of the technical staff at Broadcom
Corporation, Irvine, CA, where he has been involved
in the development of high-speed serial gigabit transceivers, analog front ends for HDD read channels,
and analog front ends for Blu-ray readers/writers.
His research interests include mixed-signal integrated circuits, adaptive
equalization, timing recovery, and calibrated ADCs.

Kwang Young Kim was born in Seoul, Korea, in


1960. He received the B.S. degree in electronics engineering from Seoul National University, Korea, in
1984, the M.S. degree in electrical engineering from
Marquette University, Milwaukee, WI, in 1986 and
the Ph.D. degree in electrical engineering from the
University of California, Los Angeles, in 1996.
From 1996 to 1998, he worked on CMOS ADC at
Rockwell Semiconductor Systems, Newport Beach,
CA. In 1998, he joined Broadcom Corporation,
Irvine, CA. His current interests are in low power
analog and mixed-signal circuit.

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