Vector Spaces and Graphs

Given any collection K of vectors on S over R , one can define two natural
vector spaces associated with K
S(K) (Span of K) { f : f is a linear combination of vectors in K }
(to produce a typical f we take some finite set of vectors g1 , ...., gn and
linearly combine them using some elements of R )
If K is the set of rows of

f1

fr
S(K) is the set of all vectors which have the form

f1


1 r

fr

for an arbitrary choice of 1 , ., ., r .

If f , f S(K), it is easy to verify that f + f S(K). So S(K) is a
vector space.
We Define the space K { g : < f , g > = 0, wherever f K }
Once again it is easily verified that K is a vector space.
These two ways of generating vector spaces from a given set K of vectors are
very common in network theory.
A graph should be visualized as a set of points with pairs of them joined by
means of lines. Formally, to define a particular graph we need to know
1. the set of vertices V
2. the set of edges E
3. for each edge, the end points.
This could be defined through an incidence function f with, for each e E,
f (e) {v1 , v2 }
where v1 , v2 are the end points of e. We permit an edge to have a single end
point so that we may have
f (e) {v}
Graphs of the above kind are called undirected since we are not specifying
which end point is to be treated as the first end point.
The graph in Figure 1 is the triple (V, E, f ) where
V = {a, b, c, d}
1

e4

a
e1

.d

e2

e3

Figure 1: undirected Graph Gu

E = {e1 , e2 , e3 , e4 }
f (e1 ) = {a, b}
f (e2 ) = {a, c}
f (e3 ) = {b, c}
f (e4 ) = {a}
Observe that a vertex can be isolated without being the end point of any edge
but every edge has at least one end point.
Graphs can be directed with edge having a first and a second end point. In

e4

a
e1

.d

e2

e3

Figure 2: Directed Graph Gd

this case the graph can be thought of as a triple (V, E, fd ) with
fd (e1 ) = (a, b), fd (e2 ) = (a, c), fd (e3 ) = (b, c), fd (e4 ) = (a, a).
Graphs can be associated with vector spaces in some nice ways.

Incidence matrix of a directed graph

A natural way of associating a graph with vector spaces is to use vectors to
represent incidence relationship at nodes or to indicate which are the positive
and negative end points of an edge. The incidence matrix arises out of this
viewpoint. For a directed (or oriented) graph G, the incidence matrix A is
defined as follows. For each node i there is a row i of A and for each edge j
there is a corresponding column j.

0 if edge j is not incident at node i or edge j is a

self loop (an edge with a single end point)

A(i, j) =
+1
if edge j is leaving node i

1
if edge j is entering node i

Observe that

1. every column has one +1, one -1 and remaining entries zero or is entirely
zero,
2. if a node is isolated, the corresponding row in the incidence matrix is zero,
3. from the incidence matrix, the graph can be reconstructed except for the
node positions of self loops.
The characteristic feature of an incidence matrix is that every column is
either fully zero or has one +1, one -1 and other entries zero. Given any such
matrix, one can immediately build a graph corresponding to it. More than one
graph can correspond to a given incidence matrix only if there are zero columns,
because the corresponding self loop may be incident at any vertex.
Note: In the above statement, we have used same graph in a loose way,
regarding two graphs as same if renaming of nodes and edges makes them appear
the same. More formally, if (V1 , E1 , f1 ), (V2 , E2 , f2 ) are two directed graphs, we
call them isomorphic if there exist one-to-one onto functions
: V1 V2
: E1 E2
s.t.
f1 (e) = (v1 , v2 ) f2 ((e)) = ((v1 ), (v2 )).
The word isomorphic is loosely to be interpreted as essentially the same.

Example
The graphs G1 and G2 of Figure 3 are isomorphic.
(a) = a etc
(e1 ) = e1 etc
3

e4

d
a

e1
b

e 5

e2
c

e3

e 3

e 2

e5

e 1
a
e 4

d
Figure 3
f1 (e1 ) = (a, b)

f2 ((e1 )) = f2 (e1 ) = (a , b ) = ((a), (b)).

The question might arise in the mind of the reader as to the manner in which
self loops are represented, because we seem to be losing information about where
they are incident. Electrically speaking, the important quantities are currents
and voltages. The position of the self loop is irrelevant as far as currents and
voltages are concerned. So the information lost is not very important. On the
other hand, by keeping the column corresponding to the self loop as a zero
column, there are advantages which will emerge presently.

e7
a

e1

e2
e3

g
e5

e4
d

e6

Figure 4: Graph G

For the graph G of Figure 4, the incidence matrix is

a
b
c
d
f
g

e1
+1
1

0
0

e2 e3
+1 0
0 +1
1 1
0
0
0
0
0
0

e4 e5 e6 e7
0
0
0 0
+1 0
0 0

0 +1 0 0

1 0 +1 0

0 1 1 0
0
0
0 0

Let us examine the product Ax for graph G of Figure 4.

x1

+1 +1 0
0
0
0 0
x2
1 0 +1 +1 0
0 0
x3

0 1 1 0 +1 0 0
x4

0

0
0 1 0 +1 0
x5

0
0
0
0 1 1 0
x6
0
0
0
0
0
0 0
x7
The resulting column vector has one entry per row of A, i.e. per node of G and
the vector is

x1 + x2
x1 + x3 + x4

x2 x3 + x5

.
z=

x4 + x6
x5 x6
0

Clearly, since each row of A has a +1 corresponding to branch leaving the node,
-1 corresponding to branch entering the node, 0 when branch does not touch the
node, if we regard the xi as currents in the corresponding branch, the entry of
z corresponding to a node a will be the net current leaving a. Thus, x satisfies
KCL iff Ax = 0. Observe that in the KCE for node a, the coefficient for
current in self loop e7 is zero since the current i7 that enters a also leaves it.
Let us next examine the product
[T A] = y T
We have

e1 e2
+1 +1
1 0

0 1
g

0
0

0
0
0
0

e3 e4
0
0
+1 +1
1 0
0 1
0
0
0
0

e5 e6 e7
0
0 0
0
0 0
+1 0 0
0 +1 0
1 1 0
0
0 0

= [(a b ) (a c ) (b c ) (b d ) (c f ) (d f ) 0]
5

Each column of A is either fully zero or has one +1 and one -1. It follows
therefore that a typical term in the product vector y T will be either zero or
have the form (x y ), where the edge in question (corresponding to the
column) leaves node x and enters y. We may interpret this as follows. If we
assign potentials a , b , c , d , f , g to the nodes of the graph in Figure 4, the
voltage that will appear in the branches will be, for a typical branch e that
leaves x and enters y, (x y ). Hence, T A gives the voltage vector derived
from the potential vector T by taking differences of potential at the endpoints
of each edge. We claim,
Theorem 1 A vector y on the branches of a graph G satisfies KVL iff
(a) algebraic sum of the values y(e) around each loop in the graph is zero.
equivalently,
(b) the vector y can be derived from a potential vector on the nodes of the
graph. (Here derived means y(e) = x y , when e leaves x and enters
y.)
Let us examine the above statement keeping the graph G of Figure 4 in mind.
Consider the vector
(y(e1 ), y(e2 ), . . . , y(e7 )).
If it satisfies condition (a) above, we must have (taking clockwise orientation
for loops)
y(e1 ) + y(e2 ) y(e3 )
y(e7 )

=
=

0
0

y(e6 ) y(e4 ) + y(e3 ) + y(e5 )

To show condition (a) implies condition (b), we must find a suitable potential
vector (a b c d f g ) from which y can be derived. We could proceed
common sensically. Assign potential f to node f , travel to d by e6 and set
d = f + v6 , set b = d + v4 , set c = v3 + b , set a = v2 + c and set
potential g to g.
But will the resulting potential vector come out to be the same if we traverse
the nodes using a different route? The answer is yes if condition (a) is satisfied.
Because if we reach say node a from node f through two different paths and
get two different values, say f + v6 + v4 + v1 and f + v5 + v2 , then v6 + v4 +
v1 v5 v2 6= 0, i.e. some loop will have algebraic sum not equal to zero. (In
general, two such routes will not give a simple loop but it can always be broken
up into simple loops and edges traversed forward and backward.)
To prove condition (a) from condition (b), consider the LHS of the equation
y(e1 ) + y(e2 ) y(e3 ) = 0.
If y is derived from , the LHS is (b c ) (a b ) + (a c ). Since
every term x occurs once with a + sign and once with a - sign, this reduces to
6

zero.
Thus we see that a vector y satisfies condition (a) iff it satisfies condition (b).
The above argument can be made rigorous and general and not based on an
example. However the essential ideas of the proof are as given above. We will
take Theorem 1 as true.
It follows by the discussion preceding the theorem that for a vector y on
branches of a graph to satisfy KVL is equivalent to say
y T = T A for some .
We are now in a position to prove the fundamental theorem of electrical network.
Theorem 2 (Tellegens Theorem (weak form)) Let G be a graph. Let x, y
be vectors on E(G). Then, if y satisfies KVL and x satisfies KCL,
y T x = 0.
Proof We have
yT x =

(T A)x

(since y satisfies KVL)

(Ax)

T (0)

(since x satisfies KCL)

Theorem 3 (Tellegens Theorem (Strong form)) Let Vv (G),Vi (G) denote

the collection of all branch vectors which satisfy KVL, KCL respectively of the
graph G. Then
(Vv (G)) = Vi (G)
Proof By Tellegens theorem(weak form), we have
Vi (G) (Vv (G))
T

Let x (Vv (G)) . We then have y T x = 0 whenever y Vv (G), i.e., ( A)x =

0 for every .
Choose = [1, 0, . . . , 0], [0, 1, . . . , 0], . . . It follows that x each row of A
i.e. Ax = 0. Thus
(Vv (G)) Vi (G)
The reverse containment is shown before already. So we have
(Vv (G)) = Vi (G).

v,i

Figure 5
One consequence of Tellegens theorem is a result which we often take for
granted: The net power absorbed by all the devices in the network is zero.
Recall that if we use the same arrow to represent both voltage and current of
a device, then the power absorbed by the device is v.i. Hence, the net power
absorbed by all the devices is v T i = vj ij = 0 since v satisfies KVL and i
satisfies KCL.
However, Tellegens theorem is not a consequence of conservation of power.
Consider the circuits in Figure 6.

v 2,i2

v 1 , i1

v 1,i1

v 2,i 2

v5

v 3,i3

v 4,i4

v 3,i3

v 4,i4

Figure 6
Tellegens Theorem implies not only
v T i = 0 , (v )T i = 0
but also
v T i = 0 , (v )T i = 0
Surely, the latter two equations have nothing to do with power!
Next, let us examine the difference between the weak and strong forms of
Tellegens theorem. Consider the vectors along x-axis and z-axis in Figure 7.
Clearly, all these pairs of vectors are perpendicular to each other. On the other
hand, the set of all vectors perpendicular to every vector along z-axis is more
than the set of all vectors along the x-axis, it is actually all vectors in the x-y
plane.
The strong form is like the second statement. If Vv (G) is the collection of all
vectors along the z-axis, Vi (G) is the x-y plane.

Figure 7

Exercise
Build a 3-element network whose spaces Vi (G), Vv G are line through the origin
and plane through the origin.

Tutorial on Tellegens Theorem

1. In a phasor(sinusoidal steady state) circuit, show that
(a) v T i = 0,
(b) (v )T i = 0,
(c) (v )T i = 0,
(d) v T i = 0.
Recall that only (b) and (c) yield real and reactive power as real and
imaginary parts and have physical significance. Nevertheless, the others
are true too.
2. Enclose a subset of nodes of a network in a surface. Show that the net
current leaving the surface is zero.
3. Consider a 2-port network made up of resistors.
(a) Let v1 , v2 , i1 , i2 denote the port voltages and currents and v1 , v2 , i1 , i2 ;
v1 , v2 , i1 , i2 denote distinct port conditions. Show that
v1 i1 + v2 i2 = v1 i1 + v2 i2 .
(b) Generalize to n-ports.

(c) Show that if R or G matrix exists for this network, it must be symmetric.
(d) What properties must the hybrid ((v1 , i2 ) on one side and (i1 , v2 ) on
the other) and ABCD matrices ((v1 , i1 ) on one side and (v2 , i2 ) on
the other) have?
4. Consider a 2-terminal network made up of positive resistors. Show that if
any of the resistors is increased in value, the overall resistance increases.
5. Let N be a network composed of resistors, voltage sources and current
sources. Let PJ , P , PJ denote the total power absorbed by the resistors respectively, when both voltage and current sources are active, only
voltage sources are active and only current sources are active. Show that
PJ = P + PJ .
(assume that the network has unique solution for arbitrary values of
sources).
6. (a) In a network with positive resistors and a single current source, show
that no branch current can exceed the current source value.
(b) State and prove the voltage version of the above statement.
(c) What if there were both voltage and current sources?
(d) Will the above results be true for any devices more general than
resistors?
7. Let N be a network with current sources and resistors and which has a
unique solution. Consider the solutions [iJ , iR ] of KCL agreeing with the
given currents iJ of the current sources. Among all such solutions, show
that the one that minimizes power loss in the resistors will correspond to
the actual current in the network.

Mintys Theorem
A result which is as basic to electrical network theory as Tellegens theorem
is Mintys theorem. Indeed, it is possible to show that the two theorems are
formally equivalent. In this section, we will state and prove this theorem in its
weak form, state the strong form and indicate its proof. We will also consider
a few applications to electrical networks and graphs. But we need a few preliminary definitions of basic notions about graphs. The underlying concepts,
however, are important in their own right.

Subgraphs
Unless otherwise stated, let us henceforth use graph to mean directed graph,
i.e., every edge in the graph has an arrow, or equivalently, has a designated positive and negative node.A graph is said to be connected if we can start from any
10

node x and reach any other node y in the graph by traversing a sequence (called
alternating sequence) of nodes and edges of the form x, e1 , v2 , e2 , . . . , ek , y,
where each node is an endpoint of the succeeding and preceding edges whenever
such edges exist. Figure 8 shows a disconnected graph.

d
e2

e1
b

e6

e4
c

e3

e5
e7

Figure 8: Disconnected graph G

Observe that from the node b, we cannot reach the node d through an
alternating sequence.
Let G be a graph on vertices V and edges E. We say a graph G1 on vertices
V1 and edges E1 is a subgraph of G iff
(a) V1 V
(b) E1 E
(c) the endpoints of each edge e E1 are the same in G and G1 .

a
e1

e3

e4
d

e2

e1

e1

e2

c
b

e3

e5
e6

a
e2

.d

e3

g3

Figure 9: Subgraphs
We often use terms such as subgraph on an edge set E1 or subgraph on a
vertex set V1 . By a subgraph on E1 , we mean a subgraph of the original graph
with edges in E1 and vertices, those that are endpoints of edges in E1 . Similarly,
by a subgraph on V1 , we mean a subgraph with vertices V1 and edges those that
have both end points in V1 . When we deal with directed graphs, we will also
maintain the same arrow direction for an edge e E1 in both G and G1 . We
say a subgraph is proper if it is not the same as the original graph.
11

Maximal and Minimal

We often need to use the words maximal and minimal as adjectives qualifying
subsets with respect to a specified property. Consider the family of subsets
shown within curly brackets below :{{1}, {2, 3, 4}, {2, 3, 4, 5}, {6, 7, 8, 9, 10, 11, 12}}
In this family, the subset {1} is maximal in the sense that no other subset in
the family properly contains this subset. The subset {2, 3, 4} is not maximal
since {2, 3, 4, 5} {2, 3, 4} and {2, 3, 4, 5} also belongs to the family. The subset
{6, 7, 8, 9, 10, 11, 12} is, ofcourse, maximal in this family. On the other hand, {1}
is minimal in the sense that no other subset in the family is a proper subset of
this subset. (The only such subset is the null subset which is not in this family).
The subset {2, 3, 4, 5} is not minimal since {2, 3, 4} {2, 3, 4, 5}. Both subsets
{2, 3, 4} and {6, 7, 8, 9, 10, 11, 12} are minimal. Observe that the words minimal
and maximal do not imply minimum size and maximum size respectively, since
{1} is maximal with respect to the property of being in the above mentioned
family and {6, 7, 8, 9, 10, 11, 12} is minimal.
We can extend the use of these adjectives to objects other than subsets by
extending the idea of contained in. If G1 is a subgraph of G, it is, in an
intuitive sense, contained in G.
For instance, consider the graph G in Figure 8. Let us call the subgraph on
the left as Gleft . Clearly, Gleft is a connected subgraph of G with the property that
it is not a proper subgraph of any other connected subgraph of G. Therefore,
one can say Gleft is a maximal connected subgraph of G. A maximal connected
subgraph of a given graph is called a connected component of the graph.
In general, maximal and minimal are with respect to a partial ordering
of objects. A partial order on a set S has the following properties. For every
a, b S, we have a b or b a. If both a b and b a, then a = b. Further,
if a, b, c S such that a b, b c, then a c. With respect to the partial
order , an element x is maximal iff no y S is such that x y and x 6= y.
Minimal is defined similarly.

Circuits, Crossing edge sets and Cutsets

A circuit graph is a connected graph with every vertex having exactly two edges
incident on it. In a given graph, a set of edges forms a circuit iff the subgraph
on it is a circuit graph. For the graph G in Figure 9, the subgraph G2 in the
same figure is a circuit subgraph. The set of edges {e1 , e2 , e3 } is a circuit.
We use the term directed circuit as follows. First in the given circuit graph
define an orientation as shown in Figure 10. If all arrows support or all arrows
oppose this orientation, then we say that the circuit graph is oriented and the
corresponding circuit is directed.
The circuit graph of Figure 10 is not oriented, while the one in Figure 11
is. [If one wishes to be formal, orientation can be defined to be an alternating

12

c
e2

e3

e1

e4

e5

Figure 10: Orientation for a circuit graph

sequence of edges and vertices starting and ending at the same vertex with each
succeeding edge being incident at the preceding vertex.]
c
e2

e3

e1

e4

e5

Figure 11: Oriented circuit graph

A crossing edge set of a graph on vertex set V is defined as the set of all
edges with one end point in V1 and another in V2 , where {V1 , V2 } is a partition
of V (i.e. V1 V2 = V and V1 V2 = ). (In Figure 12, {e7 , e8 , e9 } is a crossing
edge set.)

v1
e1

e2
e3

e9

e8
e7
e4
e5

e6

v2
Figure 12: Crossing edge set
We say the crossing edge set is directed if all the arrows are directed from
13

V1 to V2 or from V2 to V1 . Figure 13 shows a directed crossing edge set.

v1

e9

e8
e7

v2
Figure 13: Directed crossing edge set
A cutset is a minimal crossing edge set of the graph, i.e., it is a crossing edge
set which does not properly contain another. Figure 14(a) shows a crossing edge
set that is not minimal since it contains the ones in Figure 14(b).

.b

e1

e2

.c

.a
.c

e1

.c

e2

e2

.b

(b)

(a)

Figure 14: Non minimal crossing edge set

Given a crossing edge set that is not minimal, how does one extract a cutset
out of it?
We first obtain a neat way of visualizing cutsets. Let us begin with a connected graph G. Let C be a crossing edge set corresponding to a partition
(N1 , N2 ) (i.e. C is the set of all edges with one end point in N1 and another
in N2 ). Then C is a crossing edge set iff the subgraphs of G on N1 , N2 are
connected.
Suppose the subgraphs on N1 , N2 are connected. We claim that C is a
minimal crossing edge set. To see this, note that removal of a crossing edge
set (say corresponding to N1 , N2 ) disconnects the graph since there no longer
would be any edges between N1 and N2 . Now let C be a proper subset of C.
Observe that removal of C cannot disconnect the graph since the subgraphs on
14

N1

Connected
e1

e2

e3

Connected
N2
Figure 15: Cutset
N1 and N2 are connected and C C has atleast one edge which now connects
these two connected graphs. For instance, in Figure 16, to go from a in N1 to
d in N2 , go from a to b, which is possible since subgraph on N1 is connected,
travel from b to c through edge e and travel from c to d in N2 , which is possible
since subgraph on N2 is connected. This proves that C is a minimal crossing
edge set, i.e. it is a cutset.

N1

.b
e

d
N2

.c

Figure 16
Suppose the subgraph on N1 is not connected and N1 can be partitioned into
node sets N11 ,N12 , where the subgraph on N11 is connected. Now, consider the
15

node partition (N11 ,N2 N12 ). The corresponding crossing edge set is clearly
contained in the original crossing edge set. (Note that there are edges between
N11 and the rest of the nodes since the graph is connected. All these edges are
between N11 and N2 , since there are no edges between N11 and N12 ). Now we
have a crossing edge set C2 between N11 and N2 N12 where the subgraph on
N11 is connected but that on N2 N12 may not be. If the latter case happens
to be true, N2 N12 can be partitioned as N21 , N22 , . . . , N2k such that the
subgraphs on each subset of these nodes are connected.
N11

N12

N11

C1

C2

N4

N3

N12

N4
N2 U N12

(a)

(b)

Figure 17
Since the original graph G is connected, there must be edges between N11
and each of the sets N21 , N22 , . . . Consider the partition of vertices N N21 , N21
The set of edges C3 between these node sets is clearly contained in the previous
set C2 . But we know that the subgraph on N N21 is connected (since the
subset of vertices N11 is linked to all the vertices in N N21 and further the
subgraph on N11 is connected). This sequence of steps is illustrated in Figures
17 and 18.
We are now in a position to state and prove Mintys theorem weak form.
Theorem 4 Mintys Theorem (weak form) Let G be a directed graph. Let
e be an edge in G. Then one and only one of the following is true.
(a) e belongs to a directed cutset.
(b) e belongs to a directed circuit.
Proof We first note the (a) and (b) cannot both be true. Figure 19 should make
it clear. If e belongs to both a directed cutset and a directed circuit, moving
from a to l along e and back again to a is not possible without encountering an
arrow in the opposite direction.
Next, let us show that one of the two eventualities must necessarily occur.
Start from b and move away from it always choosing outward arrows. Let N2
be the set of all vertices reached by this process. (Whenever you reach a vertex,
16

N11

N4

C3

N12

N3

(c)

Figure 18: Extracting a cutset

e2

e1

e3

Figure 19: Directed circuit and cutset

record, next to it, the last vertex from which it was reached. This way the
directed path by which a vertex was reached is also remembered.) One of two
things must happen. Either a N2 or a
/ N2 . If a N2 , we can start from
a, move to b through the directed edge and then get back to a by a directed
path, which will give us a directed circuit. If a
/ N2 , consider the partition
of the vertex V (G) into (V (G)N2 ,N2 ). Clearly, a V (G)N2 . All arrows
must be directed (including ofcourse e) from V (G)N2 to N2 . If e is directed

17

from N2 to V (G)N2 , the head of the arrow of e , which is outside N2 , is

clearly reachable by a directed path. But this contradicts the definition of N2 .
We conclude, therefore, that the partition ((V (G)N2 ),N2 ) corresponds to a
directed crossing edge set.

Mintys Theorem (Strong form)

The strong form of Mintys theorem is colourful. It is usually called coloured
graph theorem.
Theorem 5 Mintys Coloured Graph Theorem Let G be a directed graph.
Let edges of G be coloured red, blue or green. Let e be a green edge. Then one
and only one of the following must occur.
1. e belongs to a directed cutset with only green and red edges, in which all
the green edges are directed the same way, with respect to an orientation
of the cutset.
2. e belongs to a circuit with only green and blue edges, in which all the
green edges are directed the same way with respect to an orientation of the
circuit.
Proof It is easily seen that both of these situations cannot occur simultaneously. This part of the proof is essentially the same as for the weak form
case.
To see that one of the two must occur we proceed as follows:
Open circuit all the red edges (i.e., remove the edges, leaving the end points
in place) and short circuit all the blue edges (remove the edge, but fuse the end
points).
The resulting graph, Greduced , satisfies Mintys Theorem (weak form). So e
belongs to a directed circuit or a directed cutset in Greduced .
Suppose e belongs to a directed circuit, Lreduced in Greduced . Observe that
each node of Greduced is a group of nodes connected through blue edges in G.
So Lreduced can be expanded into a circuit in G which has only green and blue
edges and where all the edges of Lreduced (green) are directed the same way
with respect to an orientation of the circuit.
Suppose e belongs to a directed cutset in Greduced . There will be a partition
of its vertex set corresponding to this cutset. Each vertex of Greduced is a group
of vertices of G fused together. Also each vertex in G belongs to one such
cluster which is a vertex of Greduced . Therefore, when vertices of Greduced are
partitioned, this partition can be made into a partition of the vertices of G
by making the vertices of Greduced into the corresponding cluster of G. Now
reintroduce the blue edges. Clearly these must have both endpoints within one
of the two blocks of the partition. (Otherwise when the blue edge is shorted its
end points will lie in both blocks in Greduced which contradicts the fact that the
blocks form a partition of vertices of Greduced ).However some red edges may now
18

lie with one end point in one block and another in the other block. Therefore
the original green cutset now becomes a green red cutset. (Observe that inside
the two blocks of vertices we will continue to have connected subgraphs even
after the fused vertices of Greduced are enlarged). Since originally the green
edges were directed the same way they will continue to be directed the same
way even in G with all the green edges directed the same way with respect to
the corresponding partition of vertices.

Planar Networks and Duality

A graph is said to be planar if it can be drawn on a plane without edges crossing
each other. The graph in Figure 20a is planar because although it is drawn so
that edges are crossing each other, it can be redrawn as in Figure 20 so that
they do not.

(a)

(b)
e2
e1

m1

e7
e3

.
e4
m3

.m

e6
2

e5

e8

.
m0

Figure 20: Planar Graph

When a planar graph is drawn on a plane without edges crossing, it divides the
plane into regions (or windows or meshes) including the outermost regions.
Consider the graph in Figure 21.
Choose a clockwise orientation for all the interior meshes and an anticlockwise
orientation for the outermost mesh. Construct the mesh matrix where each row
corresponds to a mesh with the entry corresponding to edge e equal to +1 if the
orientation of e agrees with the orientation of the mesh, equal to -1 if it opposes
19

e2
e1

e7
e3
m2

m1

e6

e4
m3

e5
e8

m0

Figure 21: Planar Graph with Oriented Meshes

and zero if the edge e is not in the mesh. For the graph of
matrix is as follows

1 1
1 1 0
0
0
0
0
1
0
1
1
1
M =
0
0
0
1
1
0
0
1 1 0
0
0 1 1

Figure 21, the mesh

0
0

1
1

Observe that each edge is in exactly two meshes (including the outermost mesh)
and its orientation agrees with that of one of the meshes and opposes that of
the other. It follows that each column has exactly one +1 and one -1 in it.
This makes the mesh matrix of the original graph into the incidence matrix of
another graph.
Theorem: Let a planar graph G be connected. Then the number of meshes
of G (including the outermost) is e v + 2, where e is the number of edges and
v the number of vertices.
Proof: Observe that a tree graph is a planar graph and has v 1 edges and a single (outermost) region. Thus for a tree, the number of regions is e v + 2(= 1).
For any graph G, let m(G) e v + 2. Now, let the theorem be true for graph
for which m(G) k, where k 1.
Let the given graph G satisfy m(G) = k + 1. Since G is not a tree, it must
contain atleast one circuit and therefore, the graph when drawn on the plane
will divide it into atleast two regions. Let e lie in one of these meshes (i.e. re the two regions in which e lies
gions). Open circuit e. In the resulting graph G,
will merge into a single region. Hence, the number of rows in the mesh matrix
=k (since the number of edges has
will reduce by 1. However, G satisfies m(G)
reduced by 1 and the number of vertices remains the same). Hence, the mesh
matrix of G has k rows. It follows that the mesh matrix of G has k + 1 rows.
Q.E.D.
The mesh matrix of G is the incidence matrix of another graph G d , which we
20

will call the dual of G. This graph has m(G) nodes and the same number of
edges as G. G d can be built by inspection as follows:1. Spread G on the plane
2. Place one node nj in each mesh mj of G
3. Give each mesh of G a clockwise orientation and the outermost mesh an
anticlockwise orientation.
4. Whenever edge e in G lies at the boundary of meshes mi and mj , the edge
e in G d joins nodes ni and nj . If direction of e agrees with orientation
mi , it will oppose the orientation of mj and e will then be directed from
ni to nj .

Observe that when G is spread on the plane, we can move from any region to
any other region by repeatedly moving from a region to another which shares a
boundary edge with it. It follows that G d is connected (this is true even when
G is not). Hence dropping one row of the incidence matrix of G d will result in
a set of independant rows. Hence the space spanned by the rows of the mesh
matrix of G has dimension e v + 1. But each row of this matrix is a current
vector of G. Hence the rows of the mesh matrix of G span Vi (G) (since Vi (G)
has dimension e v + 1). We know that this matrix is the incidence matrix of
G. It follows that
Vi (G) = Vv (G d )
and therefore by Tellegens Theorem (strong form),
Vv (G) = (Vi (G)) = (Vv (G d )) = Vi (G d )
The above fact can be used to build dual networks, where currents of one
network behave like voltages of the other.
Let N = (G, D) be a network defined on a planar graph. (Here the device
characteristic is a collection of pairs of vectors (v, i), which could be taken as
functions of time). Define Dd {(x, y) : (y, x) D}.
The dual network N d is defined to be (G, Dd ). Thus the constraints of the
network N and N d are
N :

v Vv (G)
i Vi (G)
(v, i) D

Nd :

v
Vv (G d ) = Vi (G)
i Vi (G d ) = Vv (G)
(
v , i) Dd i.e., (i, v
) D
21

To build the dual of a planar network, we first build the dual graph. Then
we dualize each device or group of coupled devices. Table gives dual pairs of
devices.
N

Nd

1.

(resistor)
v = Ri

(conductance)
i = R
v

2.

(capacitor)
i = C dv
dt

(inductor)
di
v = C dt

3.

(inductor)
di
v = L dt

(capacitor)
i = L dv
dt

4.

(forward biased diode)

v0
i0
v.i = 0

(reverse biased diode)

i 0
v 0
v.i = 0

5.

(vcvs)
i1 = 0
v2 v1 = 0

(cccs)
v1 = 0
i2 i1

6.

(ideal transformer)
v1 nv2 = 0
ni1 + i2 = 0

(ideal transformer, turns ratio inverted,

one of the windings polarity reversed)
i1 ni2 = 0
nv1 + v2 = 0

v = volts
i = J Amps

i = Amps
v = J volts

7.
8.

While it is true that dual networks can be constructed only for planar networks, it is worth noticing that duality ideas are more generally applicable than
just for planar networks.
Let us define a generalized network M (V, D), where V is a vector space
on a set S over R and D (the device characteristics) is a collection of ordered
pairs of vectors (x, y), x, y being on S. To solve this network means to find
(x, y) s.t.
xV
y V
(x, y) D
We could define the dual network Md (V , Dd ), where Dd {(x, y) :
(y, x) D}. It is clear that (x, y) is a solution of M iff (y, x) is a solution of
22

Md . Suppose the device characteristic D is defined by

x =
xR Ry R = 0
We could define generalized loop analysis for M as follows:
Let B be a matrix whose rows form a basis for V . We then have




x
B BR
=0
xR
i.e.,
B R xR = B x
using xR = Ry R ,
B R Ry R = B x
using

B T
B TR

y
yR

,
B R RB TR = B x

(1)

The equations (1) may be called generalized loop analysis for M. We could
define generalized cutset analysis for a network with device characteristic
yJ = J
y G GxG = 0
as follows:
Let Q be a matrix whose rows form a basis for V. We then have



yJ
QJ Q G
=0
yG
i.e.,
QG y G = QJ y J
using y G = GxG , we have,
QG GxG = QJ y J
using

QTG
QTJ

xG
xJ

,
QG GQTG = QJ y J

(2)

Equations (2) may be called generalized cutset analysis equations. It is clear

that whenever we can perform generalized loop analysis for M, we are essentially performing generalized cutset analysis for Md . Thus the two are dual
procedures.
23

Problems
Set 1
1. Build the incidence matrix for the graphs in Figure 22.
a
a

e3

e1

b
b

e1

e2

e5

e2
e3

e4
f

e4

e6

e6

e5

e11

e12

e7
e8

(a)

e9

g
e10

e13

(b)

Figure 22
2. Let be a column vector with entries a ,b ,.... Premultiply the incidence
matrix A by T for the graphs in Figure 22. Assign a , b , ... as potentials
to the nodes and recompute T A directly as a voltage vector corresponding
to these potentials.
3. Let x be a column vector with entries x1 ,x2 ,.... Post multiply the incidence
matrix A by x for the graphs in Figure 22. Assign x1 , x2 , ... as currents
in the edges and recompute Ax directly as current injected at the nodes.
4. Show that the collection of vectors of the form v T =T A ( arbitrary) and
x such that Ax=0 form vector spaces. Show that these two vector spaces
are complementary orthogonal.
5. Show that summing the rows of an incidence matrix results in a new
incidence matrix - similarly for deletion of columns. How are the corresponding graphs related to the original graph?
6. How does the incidence matrix of a disconnected graph look? Characterize
the solution space of T A=0.
(Hint: What interpretation can you give to T A?)
7. Suppose Ax=0 = x=0 where A is the incidence matrix of graph G.
Describe G.

Set 2
1. Prove the rules for working with partitioned matrices. Assume that the
partitions are compatible.

24

(a) A (B1 |B2 ) = (AB1 |AB2 )





A1
A1 B
(b)
B=
A2
A2 B


B1
(c) (A1 A2 )
= A1 B1 + A2 B2
B2
2. Let matrices A, B be row equivalent. Show that a set of columns of A
are linearly independent iff the corresponding columns of B are linearly
independent.
3. Let E be an elementary matrix. Show that EA has independent rows iff
A has independent rows.
4. Show that an elementary matrix E always has an inverse i.e there exists
a matrix E such that EE =E E=I.
Hence show that the product of elementary matrices is invertible.
Show that a square matrix with linearly independent rows is the product
of a sequence of elementary matrices and is therefore invertible.
5. Show that the row rank and column rank of a matrix are the same.
6. Show that all bases (maximally independent subsets of vectors) of a vector
space always have the same size.
7. Let V be a vector space on a set S over . Show that
dim(V) + dim(V ) = |S|

Set 3
1. For the graphs in Figure 23:
(a) Build all trees using Feussners Method.
(b) Construct the incidence matrices.
(c) Find the RRE of the incidence matrices.
2. Solve the circuits in Figure 24.
3. For the graphs in Figure 23:
(a) What are the dimensions of current space and voltage space?
(b) Consider only the collection of all vectors of the form (i1 , i2 , i3 , i4 )
and of the form (v1 , v2 , v3 , v4 ).
What are the dimensions of the corresponding vector spaces?
Can you associate a graph with each of these spaces?
(c) Can you build a basis for the current space which has the form of an
incidence matrix?
25

a
a

e2

e1
e1

e2

e2

c
e1

e3
a

c
e3

e3

e5

e4

e4

g
e4

e5

e6

e8
e7
d

e6

e7

(c)

(b)

(a)

Figure 23
1

1A
+

2
3

2A
4

3A

6V

2V

4V
+

4V

2V

4A

(a)

(b)

Figure 24
4. For the vector spaces which are the rowspaces of the matrices given, find
the bases for the complementary orthogonal spaces.

1 1 2 0 0 0
2 0 4 1 0 0

(a)
3 0 1 0 1 0
4 0 1 0 0 1

1 0 0 4 5
6
1 1 0 1 1 0

(b)
0 0 1 0 0 1
0 0 0 0 0
0
5. Consider the following collections of matrices.
(a) [0]nxn
(b) All matrices of the form
r nr

26



r
0
0
nr
0
K
Do these collections have identity matrices?
With respect to the collection which matrices have inverses?




x1
A
A
6. Given
= b, show how you would build an equivalent
1
2
x2
system A1 x1 = b.
7. Find the inverse of:

1 2 0 0
1 0 0 0

(a)
0 0 1 1
0 0 1 1

1 0
(b) 0 1 0
0 0 1

1 0 0 0
0 0 1 0

(c)
0 1 0 0
0 0 0 1

0 0 1 2
0 0 1 0

(d)
1 1 0 0
1 1 0 0
8. Let A =

A11
A21

A12
A22

with A11 ,A invertible. Show that:

A1 can be expressed in terms of A1

11 explicitly and some other submatrices.

Set 4
1. For the graphs in Figure 25, build the fundamental cutset and fundamental
circuit matrices with respect to the tree {e5, e6, e7, e8, e9}.
In each case build the RRE of the matrices.
2. Given two trees t0 and tf of a connected graph, show how to build a
sequence of trees
t0 , t1 , t2 , ... tf
where each tree differs from the preceding element in a single edge. Illustrate your scheme by taking t0 = {e1 , e2 , e3 , e4 , e5 } and tf = {e5 , e6 , e7 , e8 , e9 }
for the graphs in Figure 25.
27

e5
e3
e6

e1
e5

e4

e6

e2
e2
e7

e8

e1

e7

e9
e8
e9
e4

e3

(a)

(b)

Figure 25
3. For the graphs in Figure 25, build atleast 10 elementary current and voltage vectors indicating the edges in the support of these vectors.
4. Show that elementary current vector support is a circuit of the graph and
that for elementary voltage vector is a cutset.
5. Show that circuits of a graph satisfy the following properties:
(a) If C1 , C2 are distinct circuits of G, neither is properly contained in
another.
(b) If e1 (C1 C2 ) and ec (C1 C2 )
Show that there exists a circuit C3 (C1 C2 ) s.t e1 C3 and
ec
/ C3 .
Prove that cutsets of G also satisfy the above properties.
6. Show that a circuit of graph G can intersect a cutset of G only in an
even number of edges. Define directed circuits and directed cutsets in a
natural manner. Show that no edge in G can belong to a directed circuit
as well as a directed cutset.
7. Show the following for a graph G:
tree
minimal set of edges of G for which corresponding induced subgraph is
connected and has all vertices of G.
minimal set of edges intersecting every cutset
maximal set of edges containing no circuit
cutset minimal set of edges intersecting every tree
circuit minimal set of edges intersecting every cotree

28