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Data Sheet
Lead (Pb) Free
RoHS 6 fully
compliant
RoHS 6 fully compliant options available;
-xxxE denotes a lead-free product
Description
Features
Applications
Isolated Voltage Sensing in AC and Servo Motor Drives
Isolated DC-Bus Voltage Sensing in Solar Inverters,
Wind Turbine Inverters
Isolated Sensor Interfaces
Signal Isolation in Data Acquisition Systems
General Purpose Voltage Isolation
CAUTION: It is advised that normal static precautions be taken in handling and assembly
of this component to prevent damage and/or degradation which may be induced by ESD.
Functional Diagram
VDD1 1
8 VDD2
VIN 2
7 VOUT+
SHDN 3
6 VOUT
GND1 4
5 GND2
SHIELD
Figure 1.
NOTE: A 0.1 mF bypass capacitor must be connected between pins 1 and
4 and between pins 5 and 8.
Pin No.
Symbol
Description
VDD1
VIN
Voltage input
SHDN
GND1
GND2
VOUT-
Negative output
VOUT+
Positive output
VDD2
Ordering Information
ACPL-C87B/C87A/C870 is UL recognized with 5000 Vrms/1 minute rating per UL 1577.
Table 2.
Option
Part number
(RoHS Compliant)
Package
Surface Mount
ACPL-C87B
ACPL-C87A
ACPL-C870
-000E
Stetched
SO-8
-500E
Tape &
Reel
X
IEC/EN/DIN EN
60747-5-5
Quantity
80 per tube
To order, choose a part number from the part number column and combine with the desired option from the option
column to form an order entry.
Example:
ACPL-C87A-500E to order product of Surface Mount package in Tape and Reel packaging with IEC/EN/DIN EN 60747-5-5
Safety Approval and RoHS compliance.
Contact your Avago sales representative or authorized distributor for information.
C87B
YWW
RoHS-COMPLIANCE
INDICATOR
1
DATE CODE
12.650
(0.498)
6.807 0.127
(0.268 0.005)
1.905
(0.075)
0.64
(0.025)
7
3.180 0.127
(0.125 0.005)
0.381 0.127
(0.015 0.005)
1.590 0.127
(0.063 0.005)
45
0.450
(0.018)
0.750 0.250
(0.0295 0.010)
11.50 0.250
(0.453 0.010)
0.200 0.100
(0.008 0.004)
1.270
(0.050) BSG
0.254 0.100
(0.010 0.004)
Note:
Lead coplanarity = 0.1 mm (0.004 inches).
Floating lead protrusion = 0.25mm (10mils) max.
Regulatory Information
The ACPL-C87B/C87A/C870 is approved by the following organizations:
IEC/EN/DIN EN 60747-5-5
Approval with Maximum Working Insulation Voltage VIORM = 1414 Vpeak.
UL
Approval under UL 1577, component recognition program up to VISO = 5000 Vrms/1 min. File 55361.
CSA
Approval under CSA Component Acceptance Notice #5, File CA 88324
Symbol
Value
Unit
Conditions
L(101)
8.0
mm
Minimum External
Tracking (External Creepage)
L(102)
8.0
mm
0.5
mm
> 175
CTI
Isolation Group
IIIa
Symbol
Value
I-IV
I-IV
I-IV
I-IV
I-III
Climatic Classification
55/105/21
Units
VIORM
1414
Vpeak
VPR
2652
Vpeak
VPR
2262
Vpeak
VIOTM
8000
Vpeak
TS
IS,INPUT
PS,OUTPUT
175
230
600
C
mA
mW
RS
109
Notes:
1. Insulation characteristics are guaranteed only within the safety maximum ratings, which must be ensured by protective circuits within the
application.
Symbol
Min.
Max.
Units
Storage Temperature
TS
-55
+125
TA
-40
+105
Supply Voltage
VDD1, VDD2
-0.5
6.0
VIN
-2
VDD1 + 0.5
VIN
-6
VDD1 + 0.5
Logic Input
VSD
-0.5
VDD1 + 0.5
Output Voltages
VOUT+, VOUT
-0.5
VDD2 + 0.5
Notes:
1. DC voltage of up to -2 V on the inputs does not cause latch-up or damage to the device.
2. Transient voltage of 2 seconds up to -6 V on the inputs does not cause latch-up or damage to the device.
3. Absolute maximum DC current on the inputs = 100 mA, no latch-up or device damage occurs.
Symbol
Min.
Max.
Units
TA
-40
+105
VDD1
4.5
5.5
VDD2
3.0
5.5
VIN
2.0
VSD
VDD1 0.5
VDD1
Notes:
1. 2 V is the nominal input range. Full scale input range (FSR) is 2.46 V.
Unless otherwise noted, TA = -40 C to +105 C, VDD1 = 4.5 V to 5.5 V, VDD2 = 3.3 V to 5.5 V, VIN = 0 2 V, and VSD = 0 V.
Symbol
Min.
Typ.[1]
Max.
Unit
Test Conditions/Notes
Fig.
VOS
-9.9
-0.3
9.9
mV
TA = 25 C
3, 4
|dVOS/dTA|
V/C
TA = 40 C to +105 C
; Direct short across inputs.
G0
Parameter
DC CHARACTERISTICS
21
0.995
1.005
V/V
TA = 25 C; VDD2 = 5 V;
Note 2.
6, 7
0.994
0.999
1.004
V/V
TA = 25 C; VDD2 = 3.3 V;
Note 2.
6, 7
G1
0.99
1.01
V/V
TA = 25 C; Note 2.
6, 7
G3
0.97
1.03
V/V
TA = 25 C; Note 2.
6, 7
dG/dTA
-35
ppm/C
TA = -40 C to +105 C
Nonlinearity
NL
0.05
VIN = 0 to 2 V, TA = 25 C
9, 10
Magnitude of NL Change
vs. Temperature
|dNL/dTA|
0.0002
%/C
TA = -40 C to +105 C
11
VINR
Referenced to GND1
FSR
2.46
Referenced to GND1
VIL
0.8
VIH
VDD 0.5 5
IIN
-0.1
0.1
TA = 25 C
TA = 25 C
-0.0015
mA
dIIN/dTA
nA/C
RIN
1000
Output Common-Mode
Voltage
VOCM
1.23
VOUT+ or VOUT
VOUTR
Vocm
1.23
VSD = 0 V. Note 4.
|IOSC|
30
mA
VOUT+ or VOUT,
shorted to GND2 or VDD2
Output Resistance
ROUT
36
VOUT+ or VOUT
VIN = 0 V
13
Unless otherwise noted, TA = -40 C to +105 C, VDD1 = 4.5 V to 5.5 V, VDD2 = 3.3 V to 5.5 V, VIN = 0 2 V, and VSD = 0 V.
Parameter
Symbol
Typ.[1]
Min.
Max.
Unit
Test Conditions/Notes
Fig.
mVrms
Vin = 0 V;
Output low-pass filtered
to 180 KHz. Note 3.
12
AC CHARACTERISTICS
Vout Noise
Nout
0.013
f3 dB
kHz
Guaranteed by design
Input to Output
Propagation Delay
50%-10%
tPD10
70
100
2.2
3.0
Step input.
18
50%-50%
tPD50
3.7
5.5
Step input.
18
50%-90%
18
tPD90
5.3
6.5
Step input.
tR/F
2.7
4.0
Shutdown Delay
tSD
25
40
Vin = 2 V
Enable Delay
tON
150
200
CMTI
15
kV/s
VCM = 1 kV, TA = 25 C
PSR
-78
dB
IDD1
10.5
mA
VSD = 0 V
VSD = 5 V
10
17
POWER SUPPLIES
Input Side Supply Current
15
15
IDD2
6.5
12
mA
5 V supply
6.1
11
mA
3.3 V supply
Notes:
1. All Typical values are under Typical Operating Conditions at TA = 25 C, VDD1 = 5 V, VDD2 = 5 V.
2. Gain is defined as the slope of the best-fit line of differential output voltage (VOUT+ VOUT-) versus input voltage over the nominal range, with offset
error adjusted.
3. Noise is measured at the output of the differential to single ended post amplifier.
4. When is VSD = 5 V or when shutdown is enabled, Vout+ is close to 0V and Vout- is at close to 2.46 V. This is similar to when VDD1 is not supplied.
Symbol
Min
Input-Output Momentary
Withstand Voltage
VISO
5000
Resistance (Input-Output)
RI-O
Capacitance (Input-Output)
CI-O
Typ
Max
Units
Test Conditions
Note
Vrms
1, 2
> 1012
0.5
pF
f = 1 MHz
Notes:
1. In accordance with UL 1577, each optocoupler is proof tested by applying an insulation test voltage 6000 Vrms for 1 second (leakage detection
current limit, II-O 5 mA). This test is performed before the 100% production test for partial discharge (method b) shown in IEC/EN/DIN EN 607475-5 Insulation Characteristic Table.
2. The Input-Output Momentary Withstand Voltage is a dielectric voltage rating that should not be interpreted as an input-output continuous
voltage rating. For the continuous voltage rating, refer to the IEC/EN/DIN EN 60747-5-5 insulation characteristics table and your equipment level
safety specification.
3. This is a two-terminal measurement: pins 14 are shorted together and pins 58 are shorted together.
5
4
3
2
1
0
-1
-2
-3
-4
-5
2
1.5
1
Offset (mV)
Offset (mV)
All 3(sigma symbol) plots are based on characterization test result at the point of product release. For guaranteed
specification, refer to the respective Electrical Specifications section.
-0.5
-1.5
4.5
5
Vdd1(V)
10
8
6
4
2
0
-2
-4
-6
-8
- 10
-2
5.5
3.5
5.5
1.003
M+3
Mean
1.002
M- 3
1.001
1.000
0.999
0.998
-55
-35
-15
25
45
Temp (C)
65
85
105
0.997
125
4.5
1.00300
1.002
1.00200
1.001
1.00100
Gain (V/V)
1.003
1.000
0.999
0.997
5
Vdd1 (V)
5.5
1.00000
0.99900
0.99800
0.998
3
3.5
4.5
5.5
0.99700
-55
-35
-15
Vdd2 (V)
Figure 7. Gain vs Supply VDD2
4.5
Vdd2 (V)
Gain (V/V)
Offset (mV)
0
-1
Gain (V/V)
0.5
25 45
Temp (C)
65
85
105 125
0.1
0.08
0.08
0.06
0.06
NL (%)
NL (%)
0.1
0.04
0.02
0
0.02
4.5
5
Vdd1 (V)
4.5
5.5
Vin = 0 V
Vin = 1 V
Vin = 2 V
13
AC Noise (mVrms)
NL (%)
15
11
9
7
5
3
1
-55
-35
-15
25
45
Temp (C)
65
85
105
-1
125
20
40
60
80
100
Freq Filter (khz)
120
140
VOUT+
VOUT
2.5
0
-1
2
Gain (dB)
VOUT+, VOUT
3.5
17
1.5
1
-2
-3
-4
0.5
0
Vdd2 (V)
-5
0
0.5
5.5
0.1
0.09
0.08
0.07
0.06
0.05
0.04
0.03
0.02
0.01
0
0.04
1.5
VIN
2.5
-6
1000
Figure 14. Frequency Response
10000
Bandwidth (Hz)
100000
160
5
Prog Delay (S)
Phase (deg)
200
180
160
140
120
100
80
60
40
20
0
1000
4
3
2
TPLH 50-10
TPLH 50-50
TPLH 50-90
1
10000
Bandwidth (Hz)
100000
-55
0V
2V
Vin
0V
+2 V
VOut Diff
tSD
tON
0V
-2.46 V
Figure 17. Shutdown And Wakeup Input To Output Timing Diagram. VOut Diff = VOut+ - VOut-
2V
VIN
0V
2V
VOut Diff
0V
TPLH50-10
TPLH50-50
TPLH50-90
Figure 18. Input to Output Propagation Delay Timing Diagram. VOut Diff = VOut+ - VOut-
10
-15
25
45
Temp (C)
5V
VSD
-35
65
85
105
125
Definitions
Application Information
Gain
Application Circuit
Gain is defined as the slope of the best-fit line of differential output voltage (VOUT+ VOUT-) over the nominal input
range, with offset error adjusted out.
Nonlinearity
Nonlinearity is defined as half of the peak-to-peak output
deviation from the best-fit gain line, expressed as a percentage of the full-scale differential output voltage.
R2
10K
C1
100 pF
C2
100 nF
GND1
L2
U1
VDD1
VDD2
VIN
VOUT+
SHDN
VOUT-
GND1
GND2
ACPL-C87X
VDD2
R6
10K, 1%
R3
10K,1%
C3
100 nF
GND2
Vout
R4
10K,1%
C4
100 pF
V+
U2
OPA237
R5
10K, 1%
GND2
V-
R1
RIN
+
GND
R2
ACPL-C87x
Figure 20. Simplified Input Stage.
HV+
U
V
W
Vdd
+
GND
HVNTC Thermistor
IGBT Module
Figure 21. Thermistor sensing in IGBT Module
12
ACPL-C87x
Post
Amp
ADC
MCU
HV+
R1
Floating
Positive Supply
IN
78L05
C2
0.1F
C1
0.1F
Gate Drive
Circuit
5V
VDD2
VDD1
VOUT+
VIN
R2
13
OUT
Cin
0.1nF
ACPL-C87A
SHDN
VOUT-
GND1
GND2
C3
0.1F
PC Board Layout
The design of the printed circuit board (PCB) should
follow good layout practices, such as keeping bypass
capacitors close to the supply pins, keeping output signals
away from input signals, the use of ground and power
planes, etc. In addition, the layout of the PCB can also
affect the isolation transient immunity (CMTI) of the ACPLC87x, primarily due to stray capacitive coupling between
the input and the output circuits. To obtain optimal CMTI
performance, the layout of the PC board should minimize
For product information and a complete list of distributors, please go to our web site:
www.avagotech.com
Avago, Avago Technologies, and the A logo are trademarks of Avago Technologies in the United States and other countries.
Data subject to change. Copyright 2005-2013 Avago Technologies. All rights reserved.
AV02-3563EN - Mar 4, 2013