Practical Considerations for Application Specific

Time Interleaved ADCs

Aaron Buchwald

I. I NTRODUCTION
Parallel processing of ADCs leads to performance gains by
exploiting efficient arrays of reduced speed quantizers that
operate on sub-sections of the signal, partitioned usually in
time [1], [2] or perhaps in frequency [3][5]. Interleaving in
the time-domain, Fig. 1, is more widely used as frequency subbanding approaches require precise knowledge of channelizing
filter transfer functions and therefore more computationally
intensive reconstruction and calibration.
Whether paralyzation is implemented in the time- or frequency domain, the very nature of interleaving forces the
input signal to branch and traverse multiple paths on its
way to the output. Physically distinct circuits process various
sub sections of the signal: any mismatch results in patterndependent artifacts. Sources of errors and their impact on the
combined output of parallel ADCs have been analyzed and
described as early as the 1980s [6], [7], further into the 1990s
[8], [9], and more recently by several authors [10][15].
Often the goal of proposed calibration techniques are ambitious with aims to provide workable solutions for virtually
all classes of input signals. With mixed-signal SoCs being
more common due to ever increasing integration, rarely are we
concerned with general applications, but need only concentrate
on the specific. The two most common embedded applications
for time-interleaved ADCs are: 1) channelization of multichannel frequency division multiplexed signals such as in
cable and satellite TV and 2) baseband applications for optical
and backplane transceivers. The first is best understood by
viewing signals and errors in the frequency domain, while
the second is easiest to understand in the time domain. This
paper will focus on the requirements and impact of error
sources on ADCs for the first class of applications, broadband
frequency channelization. Error sources will be revisited in the
context of their sensitivity to overall system performance for

ADC

DADC1
Clk1

VIN

ADC

DADC 2
Clk2

ADC

Calibration

AbstractTime interleaving provides an additional degreeof-freedom in achieving ultra-fast quantization at reasonably

high resolution, However, mismatches in multiple paths of the
signal chain create systematic errors. Mitigating all possible
time-interleaved errors comes at a heavy cost in complexity,
risk, power and performance. Knowing which errors are most
important and which can be neglected in any given application is
essential for picking an appropriate architecture and calibration
scheme. This paper will review specification requirements, specifically for frequency division multiplexed channels where time
interleaved ADCs are finding increased use. Instead of lumping
all error sources into a single metric such as ENOB, different
types of error sources are treated separately to determine their
impact on overall system performance.

DADC3
Clk3

ADC

DADC 4
Clk4

Fig. 1. Block diagram of a four-slice time-interleaved ADC.

these specific applications. ADCs for baseband applications

can be viewed similarly, but differing requirements will lead
to different choices for optimal design.
A. Multi-Purpose vs. Application Specific ADCs
By definition there are two classes of data converters:
multi-purpose and application-specific. The most stringent
requirements are placed on multi-purpose ADCs for test-andmeasure applications and stand-alone off-the-shelf converters.
Without a knowledge of the input signal, all possibilities must
be considered and accounted for. No simplifying assumptions
are allowed, thus making background calibration blind and
more challenging. Furthermore, there is little tolerance for
non-idealities. In demanding applications for spectral analysis
equipment, no trace of time-interleaving spurs can be tolerated.
Although achieving calibrated results of 80dB SFDR at 2.5GS/s is difficult, it is nevertheless possible [2], albeit at the
cost of increased complexity and power.
This level of sophistication in calibration is difficult to
match for high-volume SoCs (System on Chips). Fortunately
most embedded applications do not require it. Additionally,
overall performance is much less sensitive to some types of
errors than others. Armed with this knowledge, targeted simplifications can be made which leads to optimal architectural
choices and drastic improvements in power, area, risk and cost.
II. ADC S FOR B ROADBAND M ULTI -C HANNEL S YSTEMS
Historically, multi-channel communication systems, such as
broadcast video, distributed independent channel information
across a wide frequency band. In the case of both cable
and satellite, a significant investment in hardware and system
protocols makes it advantageous to continue using existing

Digitized Cable TV Spectrum

ADC

THA

desired in-band channel

tilt

1
ADC

THA

ACI

ADC

THA

+
-

Frequency

Fm

Fs /2

12
ADC

THA

Calibration

Amplitude

Digital

Fig. 2. Snapshot of cable TV spectrum.

ADC

THA

ADC

THA

ADC

ADC

90o Delay

Fig. 4. One single time-interleaved ADC followed by digital channelizers

takes the place of several analog tuners.
+

IQ PLL

ADC

IQ PLL

Digital

90o Delay

ADC

ADC

IQ PLL

N
1

ADC

90o Delay

Fig. 3. Implementation of multiple analog direct conversion tuners followed

by lower speed baseband or IF ADCs.

channels. Any incremental upgrade in services or increase in

data rates must operate within the confines of pre-defined
frequency boundaries. An example of a cable spectrum is
shown in Fig. 2. The bandwidth extends from approximately
DC to 1-GHz. It contains legacy analog channels together with
standard-definition and high-definition digital television plus
internet protocol data. Traditionally a user would be interested
in only one channel of video or data at a time. Only one tuner
was needed for channelization and down-conversion, while
one receiver was needed for demodulation. With the continued
appetite for bandwidth, two separate service enhancements
dictate the use of multiple channelizers: gateways and gigabitper-second modems.
To increase cable modem throughput using the existing
infrastructure of the cable network multiple channels are
needed. It is possible to transmit approximately 38-Mb/s in
a single 6-MHz channel. For higher data rates, approaching
a throughput of 1-Gb/s, approximately 24 physical channels
are logically bonded, appearing to the user as a single 1Gb/s link. Providing frequency translation, down-conversion
and channelization of 24 channels by traditional means in
the analog domain, requires several direct-conversion tuners
as represented in Fig. 3. Synthesis of center frequencies,
multiple harmonic rejection mixers, filters and image rejection
functions all must be accomplished by analog circuits. Channelized baseband signals are eventually sampled with a parallel
bank of low speed ADCs. Crosstalk and sensitivity become
significant problems as many critical functions residing in the
analog domain require high accuracy and isolation.

Alternatively, all-digital channelization can be used,

whereby a single ADC is moved to the front-end, provided
it has enough bandwidth and resolution to capture the entire
spectrum at once. Such an architecture using a time-interleaved
ADC is illustrated in Fig. 4 and can be implemented for cable
[16], [17] or satellite [18]. This approach, though radically
different from that of Fig. 3, uses many of the same sub-blocks.
Track-and-hold circuits replace mixers. An array of subsampled time-interleaved ADCs replace the baseband ADCs.
All the analog accuracy requirements are now localized to the
front-end of the ADC and no frequency synthesis is needed as
sampling occurs at a fixed rate. Signal processing happens after
quantization in the digital domain where frequency synthesis, down-conversation and image-rejection are accomplished
without error or crosstalk. Best of all, the digital channelizers
are portable and scalable to as many channels as desired.
III. C ATEGORIES OF P RIMARY E RROR S OURCES
Primary error sources in time interleaved ADCs are shown
in Fig. 5. The first column is fundamental, including additive
random noise and quantization. Additive noise is dictated by
KT /C and 1/gm . No amount of calibration can reduce these
error sources: they can only be mitigated by brute force design
reducing thermal noise requires an increase in either area or
power. Likewise, sufficient levels must to be included to ensure
quantization noise is not detrimental to overall performance.
This simply entails increasing the number of physical bits in
the converter.
Errors in the second column of Fig. 5, describe distortion
mechanisms present in any single-slice ADC. These include
quasi-linear distortion from the front-end buffers and track and
hold, linear and nonlinear radix errors and element mismatch.
Calibration is often used to eliminate these errors within a
single ADC slice without increasing area and power. Fig. 6
illustrates linear radix correction of a pipelined ADC. Provided
that the interstage gains are known, the linear radix for each
stage can be adjusted for correct signal reconstruction. This
can also be implemented as a nonlinear combination of the
sub-codes D1 D4 . Possible background calibration methods

Fundamental

Single-Slice
Distortion

Time Interleaving

Noise

Smooth INL

Offsets

INL

probability

Quantization

Fs/4

Radix errors

VPP
Fs/2

probability

Fs/2

Fs/4

Cap Mismatch

Time-Skew

Fs/2

Fs/4

Fig. 5. Summary of errors in time-interleaved ADCs. Those in bold are

additive, whereas the others are multiplicative and therefore either proportional
to signal amplitude or to the signal amplitude raised to a power such a Va3 .

Stage
#1

D1

Stage
#2

Fig. 7. Probability density function of a single sine wave of amplitude a.

Gain

Stage
#3

D2

D3

Stage
#4

D4

D
D
D4
x = D1 + 2 + 3 +
A1 A2 A1 A3 A2 A1

Fig. 6. Linear radix calibration. The optimized digital output is a linear

combination of the digital outputs of each of the pipelined stages.

add a dither signal into the residue prior to amplification

[2]. The dither can be explicitly added [19] or by adding
an extra level to the DAC and modulating it with a pseudo
random sequence [20], [21]. The nonlinearity is then estimated
in the background through statistical analysis or through decorrelation of the output of the dithered nonlinear amplifier
with the dither sequence. While [22], [23] provided a solid
framework for calibrating linear errors in a pipelined ADC, the
extension to nonlinear calibration is more complex as noted
in [22], the desired approach is a computationally efficient
technique that operates in a nonlinear fashion directly on the
raw digital bits of the pipeline, referred to as the code domain,
[24]. This, together with a look-up table, compensates for the
static nonlinear transfer function of the interstage amplifier
and MDAC.
The third column of errors are those associated with multipath mismatches which only become problematic in the presence of time-interleaving. These include offset errors which
are often viewed as static. Offsets can drift due to 1/f noise
producing artifacts that show up in the output spectrum if
the correction bandwidth is not fast enough. Mismatch in
gains generate amplitude modulated errors while time skew in
samplers result in phase modulation of errors with the input
signal. Additional variations in bandwidth of the slices makes
the gain and time-skew errors both frequency dependent and
non-orthogonal.
A. Additive vs. Multiplicative Errors
All error sources affect the signal in either an additive or
multiplicative way. Additive errors are thermal noise, quanti-

zation, radix errors, element mismatch and offsets. These are

the most problematic in frequency channelization applications
because they do not scale with the signal. As the amplitude
is reduced, signal information eventually drops below the
fixed noise. Conversely, multiplicative errors are much less
important. These errors reduce accordingly when the signal
energy drops, meaning if the SNR is adequate for large
signal, it is still adequate when the signal is small. When
designing a time-interleaved ADC for broadband capture, it
is precisely these multiplicative errors, namely smooth, quasilinear distortion and mismatch of gain and time skew that can
be significantly relaxed. This leads to design tradeoffs which
drastically simplify the front-end circuitry and the calibration
scheme.
B. Subtle Effects and Problems with Simple Metrics
One of the difficulties in producing an optimal multichannel time-interleaved design from a standard list of metrics
is that traditional ADC specifications assume a sine wave
input. Any metric can have contributions from many different
types of error sources. For example, THD (Total Harmonic
Distortion) may result from compressive distortion of the
smooth quasi-linear front-end transfer function, but it also
arises due to jagged radix errors and element mismatch.
These errors scale differently with amplitude, rendering a
lumped specification for THD virtually meaningless. We do
not care much about lumped THD. What we care about is
how the THD scales with amplitude. What is needed then is
a separate specification for smooth multiplicative distortion
and abrupt, jagged, distortion, otherwise the ADC is likely
to be over-designed in one area and under-designed in another.
C. Clipping and Distortion
Back-off desensitizes ADC-based broadband channelizers to
multiplicative error sources. In order to prevent hard-clipping,
the rms level of the signal is set significantly lower than for a
full scale sine wave. Previously when dealing with a single
baseband channel the optimal signal level was determined
by the peak-to-average ratio of a given modulation technique
(256 QAM). For broadband applications, where hundreds of
channels are captured simultaneously, the modulation scheme
in any one channel is irrelevant. Independent signals combine
to produce a Gaussian distribution regardless.
Despite the actual distribution of the input signal, ADCs are
generally specified assuming a full-scale sine wave input of the
form a cos (2fn t) which has a probability density function
shown in Fig. 7. If 128 independent sine waves spanning the
spectrum are added, but are not allowed to clip, each tone

Rare occurrence.

very little signal

activity at the ends.

Clipping
error

Assume an Ideal INL Profile

INL

VPP

Clipping
error

Squared error

INL2

VPP

Weighted
squared
error

Fig. 8. Probability density function of 128 equal amplitude sine waves.

Hard
clipping
at ADC

significant
clipping
occurs

Weighted
squared
error

Signal
Probability

Fig. 10. For an ideal ADC there is no error in the operating range. As the
signal clips, the error is equal to the difference of the signal value and the
clipped value.

VPP

Fig. 9. Probability density function

of 128 equal amplitude sine waves. Each
tone is scaled down by a factor of 128.
Clipping
Distortion

needs to be scaled linearly.

128
a X
cos (2fn t) .
128 n

Clipping
Distortion

Vpp RMS

Total Noise

1
p
2

errsq ( ) =

(1)

The resulting probability density function is nearly Gaussian

as Fig. 8 shows. Clearly, most of the signal energy is centered
in the middle with a large percentage of extreme levels rarely
exercised. To improve SNR the amplitude must increase.
However, putting the rms level back to that of a full-scale
sine wave via square root scaling, results in the probability
density function of Fig. 9, which will exhibit significant hard
clipping.

Initially considering an ideal ADC, when this backed-off

Gaussian distribution is applied to the input, the error is zero
for all levels. Errors only exist due to an over-range condition
and increases linearly with the difference between the signal
and the clipping level. This is illustrated in Fig. 10. The
squared clipping error, or cost c(x)2 , is multiplied by the
probability, producing a weighted error energy. For a Gaussian
probability density, the average squared error is calculated as
Z
1 x 2
1
errsq () =
(3)
c(x)2 e 2 ( ) dx
2

Optimal back-off depends on the level of additive noise

present. If the noise is large as illustrated conceptually in
the top half of Fig. 11, The signal level can be increased
further before clipping-induced distortion becomes dominant.
However when the additive noise is small, as in the lower part
of Fig. 11, the distortion will exceed the additive noise at a
smaller signal amplitude. A family of curves can be plotted
for various additive noise levels to determine the back-off that

c(x)2 e

1
2

(x

) dx

Gaussian
Squared
INL

Fig. 11. Changing the back-off impacts the total error due to clipping. The
higher the noise floor the larger the signal needs to be before the distortion
equals the integrated noise.
44
42

24
8.3-bit
Front-End Noise

38

04
83

36

63
7.3-bit
Front-End Noise

34
32

43

)Bd( RNS

Knowing that the signal is Gaussian distributed can be

exploited to determine the optimal back-off. For discrete tones
the scaling is backed-off relative to a full-scale sine wave by
kbo .
128
1
a X

cos (2fn t)
(2)
kbo 128 n

Vpp
RMS

40

D. Optimal Back-off

23

30

6.3-bit
Front-End Noise

28

515
1

414
1

313
1
212
1
111
1
010
1
99
)Bd( elacSlluF ot tcepser htiw ffokcaB

03
82
62
88

Backoff with respect to Full-Scale (dBFS)

Fig. 12. For low amplitude signals increasing amplitude increases the SNR
one dB per dB until clipping dominates and SNR falls abruptly. The optimal
back-off depends on the level of additive noise.

produces the best SNR. Fig. 12 illustrates the optimal back-off

with respect to full-scale for cases where the front-end noise
is at three different levels. For 6.3-bits of additive noise the
ideal back-off is 11-dBFS, while for additive noise of 8.3-bits
the signal must be attenuated further to 12-dBFS to obtain the
peak SNR.
E. Optimal Back-off with Distortion
The impact of distortion on the overall error is evaluated
in the same way as clipping. Rather than assuming the INL
profile is ideal, the actual smooth memoryless transfer
characteristic such as that coming from compressive distortion
in the front-end is used, Fig. 13. This squared error now begins

Continuous Time or Quasi-Linear Distortion Amplifiers, Buffers, THA

INL

Squared Error due to quasi-linear distortion

INL2
Total integrated
distortion ratio
improves 1dB per dB
for broadband

Extreme INL errors are still

stimulated by the tail of a
Gaussian signal although
much less frequently

THD improves 2dB

per dB for sinewaves

Fig. 13. INL errors for compressive distortion with overlay of Gaussian and
single-tone probabilities.
0.03
Errors Due to
LNA Distortion
= 7.67-bits

Probability Error2

0.025

0.02

0.015

0.01

0.005

0
1.5

Errors Due to
Clipping with
Broadband signal
At 11-dB Backoff
=7.8 bits

Errors Due to
Clipping with
Broadband signal
At 11-dB Backoff
= 7.8 bits

0.5
0
0.5
Normalized Input Signal

1.5

Fig. 14. The optimal back-off level must include the static distortion. This
method allows calculation of overal system sensitivity to distortion.

to increase and show soft-clipping before full-scale is reached.

Weighting the squared error by the probability density function
generates a family of weighted error curves: one example is
shown in Fig. 14. The total error is found by integrating. The
back-off needed to achieve optimal SNR is obtained and will
be somewhat higher (lower signal) and the peak SNR will
be lower than for an ideal ADC. The actual back-off setting
depends on the distortion profile of the front-end circuits.
1) Quasi-Linear vs. Abrupt Discontinuities: There are
many types of distortion. The INL profile used in the adjustment for back-off should consider only the quasi-linear
distortion which arrises from buffers and track and hold circuits. It should not account for abrupt nonlinearities from radix
errors or capacitor mismatch. To determine how distortion
impacts overall performance, consider the probability density
function for a sine wave. This has the same rms value as the
Gaussian as shown at the bottom of Fig. 13. Large distortion
at the extremes of the input range are never seen by the low
amplitude sine wave and are not exercised at all. Distortion
for a sine wave is reduced by the cube of the back-off for a
system dominated by the 3rd harmonic while the signal itself
is reduced linearly: the resulting THD improves by the square
of the back-off or 2-dB per dB.
The key observation that allows for relaxed distortion in
ADC designs is seen from Fig. 13. The signal energy for
a broadband signal is primarily concentrated in the center
where the transfer function is linear. The tails of the Gaussian
rarely hit the larger compressive distortion errors. It is found in
practice that this distortion can be relaxed by approximately

the rms back-off relative to a full-scale sine wave or 1-dB

per dB. For example, an ADC requiring a 62-dB (10-bits)
noise floor with an optimal back-off of 15dBFS (12-dB with
respect to a sine wave) will have a distortion requirement
of only 62- minus 12- or 50-dB (8-bits). This reduction in
required accuracy of the front-end buffers and track and hold
by two bits, significantly simplifies the design and impacts
architecture and circuit choices.
F. Time Skew Errors
Signals are generally sampled on a uniformly spaced grid.
Any timing variations causes the value to differ from what is
expected. For small timing deviations, errors are proportional
to the timing skew and the slope of the signal at the sampling
instant.

s(t) 
(4)
err(nT ) = t
t nT

Integrating the squared error over a full sine wave period, the
SNR is found to be
1
= 2fin trms
(5)
SNR
Because the error of a single tone is proportional to the signal
slope and therefore proportional to the input frequency, lower
frequencies have lower time skew errors. Finding the overall
noise in general requires taking the derivative of the complete
spectrum. This can be approximated quite accurately assuming
a flat spectrum. Because the noise adds in an rms fashion
however, the integration of squares involves a factor of 1/3
in squared noise. Therefore, its not surprising that the total
broadband
noise relative to the maximum frequency is reduced

by 3 (4.77-dB). Time skew is also a multiplicative error.

The accuracy is significantly relaxed in the presence of backoff. Continuing with an example of an ADC with a 62-dB
noise floor, time skew requirements are reduced by 12-dB due
to back off and another 4.77-dB from the above broadband
considerations. To achieve a noise floor of 62-dBFS, the time
skew needed is only 62- minus 12- minus 4.77 or only 45.23dB. The rms timing accuracy needed to achieve this moderate
SNR is given by
1
trms =
(6)
SNR 2fmax
For a maximum frequency of 1-GHz the timing skew accuracy
is relaxed to 869-fs as opposed to 126-fs which would have
been needed to achieve 62-dB. For this rms skew of 869-fs
the 2 peak-to-peak spread is 3.75-ps or 1.75-ps. This
design target is within the limits to achieve without requiring
background calibration.
G. Gain Errors
Gain errors are simple to calculate and are clearly proportional to the signal. Therefore, a one percent mismatch in gain
results in an error signal with an amplitude of one percent of
the intended signal. For a converter with 62-dB additive SNR,
and back-off of 15-dBFS the gain accuracy needs to be 62minus 12- or 50-dB. This can easily be achieved digitally so
that all slices are matched to better than 50-dB.

VIN

H. Offsets

noffset

= nnoise + nmargin +
1
6.02 10 log

fs /2
fBW

1
6.02 10 log

N

slice

(8)

This calculation is best represented by example. If a 12-bit

ADC is implemented with a 10-bit (nnoise ) noise level and a
sample rate of fs equal to 3.6-GHz where the bandwidth of
each channel is 6-MHz (fs ), then the resolution of the offset
correction needed for Nslice = 4 is
noffset = 10 + 1 + 4.11 0.5 = 14.6

bits

(9)

Although the converter outputs 12 bits and has a 10-bit

noise floor, the offset needs to be corrected
to the equivalent
quantization noise of 14.6 bits (1/(214.6 12)). This is 1-LSB
error at the 16.4 bit level so offset correction needs to extend
to 16 bits to avoid corrupting performance in the channels in
which the offset spurs fall.
IV. A RCHITECTURE C ONSIDERATIONS
System SNR is 2-bits less sensitive to distortion, gain and
time-skew errors. Relaxing front-end distortion leads one to
use as few slices as possible. Even if there is distortion in
the input network due to insufficient tracking or settling time,
the modest requirements of 50-dB are not difficult to meet and
likely would not necessitate additional parallization to increase
tracking or settling time. Four slices allows symmetric layout,
balanced loading and simple clock generation. 1 An example
of a four slice architecture is shown in Fig. 15, [17], [25]. The
design for both the clock and input network can be laid out
in a star configuration, thus matching these paths to all four
slices as closely as possible. Offsets and gain errors are easy to
remove statistically by setting the mean and variance of each
slice to that of a master slice. Since the requirement for times
skew (section III-F) is only to maintain a peak-to-peak range
1 Using two slices is not a good choice. Time-interleaving entails many
complications, so that if the design can be achieved with two slices, one
ought to eliminate all the calibration and try harder to achieve performance
goals with only one slice.

ADC

ADC

Clk2

DADC 4

DADC1
Clk1

ADC

ADC

Clk4

DADC3

Calibration

If the total energy from all offset errors is split equally between
Nslice /2 bins then the rms offset tone, which falls in one
of the desired channels needs to be smaller than the in-band
noise. If a margin of 2nmargin is assumed to avoid the offset
error dominating the SNR, then the accuracy of the offset
correction needs to be significantly better than the resolution of
broadband noise. The offset accuracy required is given below
in bits.

DADC 2
Calibration

It is straightforward to approximate the level of offset

correction needed. Broadband noise spreads evenly across the
entire Nyquist band. The amount falling in any one channel of
bandwidth fBW is equal to the equivalent quantization noise
of n effective bits improved by the processing gain such that
s
fBW
ninband = nnyq
.
(7)
fs /2

Clk3
ClkFs

Fig. 15. Four slice time-interleaved ADC for cable applications.

of 3.5-ps, several simplifications in the calibration algorithm

can be adopted. A course correction of any systematic skew
could be made during factory test or at start-up. Calibration
can remain frozen thereafter. Background adjustments are not
necessary as the differential skew will track temperature and
voltage changes to well within range.
V. S ECOND -O RDER E FFECTS
Nonidealities in physical implementations result in error
sources being both nonlinear and correlated. Although all the
primary errors were described as independent in section III,
problems arise when these errors interact with each other,
which impacts global convergence and causes limit cycling or
settling to non-optimal points. An assortment of these effects
are described in the context of the ADC of the following
section.
A. 8x Time-Interleaved ADC with Slow Reference
An example of an eight-way time interleaved pipelined architecture is shown in Fig. 16. A slow ( 1-MS/s) recirculating
ADC with dynamic capacitor shuffling is used to provide a
reference sample: the error between the actual sample and the
reference is used to drive all background calibration. A single
LMS loop converges all error sources simultaneously [24].
Within each ADC slice the radix is corrected: a lookup table
is populated to mitigate errors due to capacitive mismatch in
the MDAC. The gain, offset and time-skew errors of each slice
are corrected by forcing them to match the reference ADC.
System-identification (SI) methods are used for calibration in
this design. Since LMS updates are driven by observations
from a known reference, this approach, which is common in
control systems and adaptive equalizers, is known to be robust
and have good convergence properties.
The layout of the ADC is shown in Fig. 17. All calibration
circuitry resides on chip as does an 8k-sample memory for
use in test. All error correction is performed exclusively in
the digital domain, directed only by the magnitude of the subsampled error between the main ADC slices and the reference
ADC, with the exception of the sample phase. Time-skew
correction is similar to clock recovery in that information
about both magnitude and direction are necessary. Here, a
hybrid approach is used to determine direction, which is a
combination of small additional analog and digital circuitry
[26]. The LMS engine then drives a digital code, which in

VI
Stage
#1

TH

Stage
#2

D1

Stage
#3

Stage
#4

D3

D2

D4

x! = G y(D1 , D2 , D3 , D4 ) +Voff
8
Radix and Cap
mismatch correction

LMS Calibration

SLOW
ADC

TH

Measure & Compare

Fig. 16. Block diagram of an eight-slice time-interleaved, background

calibrated ADC.

24 Digital Tuners
Memory#

LNA##

AGC&#

2.7 GS/s
12-b ADC

LNA

Channelizers#1:12#

LOWPASS
FILTER

PGA#

HIGH
SPEED
INTERFACE

DDFS

Tx
Tx

LOWPASS

Calibration#FILTER

BUF
XTAL
OSC

FFT#Processor#

PLL
SERIAL
INTERFACE

PLL#
&#
CLK#
Gen#

Channelizers#13:24#

Serial#Output#

the calibration is incomplete is due to the limited resolution

of the correction circuit (50-fs step size for skew adjust) and
the fact that error sources interact. Albeit small, the calibrated
spectrum still shows some artifacts of time-interleaving, which
are visible. These artifacts are common and also seen in other
implementations at various levels. [27], [28].
Slice-dependent kickback provides an explanation for incomplete convergence as was identified in the lab [29]. Kickback on any one slice will be sampled on the successive slices
until it completely settles. Any kickback independent of the
signal appears as an offset when it is subsampled by the next
slice and mixed to DC. Signal dependent kickback results in
a linear filter. This alters gain and skew errors in a frequency
dependent way. In the design of Fig. 16 the timing adjustments
are made in the analog domain. Whenever the time instant
moved, the kickback changed. This changed offsets and caused
frequency dependent gains and time skews. The LMS loop
wandered around in a limit cycle trying to converge all errors
simultaneously. Interactions of error sources will always prevent the total system error from converging to its ideal value.
Improving this situation must be addressed at the architectural
level as described in the following section.
VI. A RCHITECTURE C ONSIDERATIONS

Fig. 17. Layout of a 2.5GS/s 12-bit ADC with 71dB SFDR through the first
Nyquist zone and 60dB through the 3rd Nyquist zone.

Amp

-10

Nyquist
Zone 1

1GHz

2GHz

3GHz

4GHz

5GHz

6GHz

Amplitude dBFS

-20

-30

SFDR 75dBc

-40

-50

-60

-70

3rd

-80

-90

-100
0

200

400

600

800

1000

1200

Frequency (MHz)

Fig. 18. Measured frequency response with an 8k-sample FFT for an input
in the first Nyquist zone, fin = 252-MHz and fs =2.525GS/s.

turn adjusts the edge position of eight capacitive clock-delayDACs, thus closing time-skew correction in the analog domain.

B. Kickback and Vdd Modulation

A measured 8k-sample spectrum of the ADC with a 2.525GHz external sample clock and an input near fs /10 is shown
in Fig. 18. SFDR of 75-dBc is achieved and is limited by the
third harmonic of the input buffer and track and hold Despite
effective background calibration, artifacts of time interleaving
remain in the output spectrum. Global convergence using one
LMS engine has the potential to achieve an optimal solution
assuming all error sources are orthogonal. The extent to which

Because there is no perfect isolation between slices, error

sources interact when adjustments are made in the analog
domain. Kickback and instantaneous Vdd droop modulates the
signal. In order to minimize this interaction a hybrid approach
can be adopted. Course analog adjustments are used to get the
circuit close to ideal performance followed by fine adjustments
in the digital domain.
Digital time skew adjustments require filtering at fullspeed. Although a general purpose interpolation filter can be
costly, a simpler method using a digital slope estimator is
more efficient. The correction at each sample is estimated
by multiplying t by the slope [27]. Implementing timing
correction with a slope estimater is economical when calibrating nonlinearities of buffer and track and hold [2] as
the slope of the signal is also needed to correct dynamic
distortion in the front-end. An efficient and robust calibration
scheme is illustrated in Fig. 19. It uses a slope estimation
filter for both time skew correction and as input to a Volterra
filter which corrects for front-end nonlinearity. Digital fine
correction breaks the interaction between control loops making
error sources orthogonal which leads to more predictable
convergence. This architecture has the ability to achieve high
linearity of the front-end via calibration and very low residual
time-interleaving artifacts.
VII. C ONCLUSION
ADCs are specified assuming a full-scale sine wave is
applied as an input. However, performance of the converter
with a single tone is not representative of ADC performance
with actual signal statistics. ADCs for broadband channelizers
must back-off the rms level of the signal to avoid hard
clipping. As the input is broadband, Gaussian-distributed and

Simple Volterra Filter

b( ) 3
a( ) 3

RMS
LNA

PGA

ADC

Radix

NonLinear
MDAC

CapMismatch
LUT

Mean &
Zero
Crossing

d/dt
T

Time Skew
Adjustment

Course Skew
500-1000fs
XTAL
OSC

PLL

Fig. 19. Block diagram of a time-interleaved ADC system using a slope

filter for timing correction and as a Volterra filter for buffer and track and
hold calibration.

concentrated at low to moderate amplitudes, performance is

much less sensitive to multiplicative errors such as quasi-linear
distortion, time skews and gain errors. Additionally the signal
statistics for embedded applications are known in advance
so that significant simplifications in calibration schemes can
be reliably used. Auto-correlation and zero-crossing timing
measurements work well in these environments because the
richness of the signal spectrum provides more than sufficient
randomness. As a rule-of-thumb multiplicative errors can each
be relaxed by the back-off, or reduction in amplitude as
compared to a full-scale sine wave, by as much as two full
bits for cable applications. This has profound implications on
architecture choices and circuit design.
ACKNOWLEDGMENT
The author would like to thank the team formerly at Mobius
Semiconductor for all their original ideas, enthusiasm and
hard work on multiple time-interleaved ADCs with various
architectures spanning a wide range of sample rates in many
processing nodes: primarily, Dr. Avi Madisetti, Dr. Ralph
Duncan, Dr. Jurgen van Engelen, Espen Olsen, Dr. Sasidhar Lingham, Jatan Shah, Howard Baumer, John Sin, Dr.
Francesco Gatta Dr. Hairong Yu, Dr. Tommy Yu, Rajesh
Radhamohan and Ted Buchwald.
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