386

CHAPTER 12 LNA DESIGN

FIGURE 12.9. Complete 1.5-GHz, 8-mW

single-ended LNA.

The finished LNA then appears as shown in Figure 12.9. The bias transistor's
width and current are arbitrarily chosen as a tenth of [hat of the main transistor. Even
though a simple reference current source is shown, it may be advantageous to use a
constanl-g,,, bias source to stabilize gain and input impedance over temperature and
supply (see Chapter 10).
The cascoding transistor is chosen here to have the same width as the main device. This choice is common, but it is somewhat arbitrary and thus not necessarily
ideal. Two competing considerations constrain the size of the cascoding transistor.
The gate-drain overlap capacilance can reduce the impedance looking into the gate
and drain of
considerably, degrading both thc noise performancc and input match.
It is a straightforward matter to show that, for equal-sized common-source and cascoding devices, the resistive component at the input is given by

The degenerating induc~ancemust therefore be increased to compensate.

To suppress these consequences of the Miller effect, one would normally desire a
relatively large cascoding device in order to reduce the gain of the comnion-source
transistor. However, the parasitic source capacitance associated with a large device
effectively increases the amplification of the cascoding device's own internal noise
at high frequencies. Merging the source region of the cascoding transistor with the
drain region of tlie comnion-source device is effective in reducing many of these
problems, and is most readily implemented by making the two devices equal. One
should also consider the possibility of pulling extra current out of the source of M 2
to increase selectively the bias current of just the cascoding device to increase its g,,,.
Measurements made on actual amplifiers essentially identical to this example typically reveal noise figures somewhat in excess of the calculated minimum of 2.2 dB.

12.5

DESIGN EXAMPLES

387

owing to various parasitic cffecls. To ~niniliiizrthe noise tigure dcgradation. i t is

particularly important to ensure that the resistive part of the input ilitpedance is big
enough by guaranteeing n sufficicn~lylarge degeneration inductance and by mitigating the Miller effect. Failure to do so elevares the noise figure - not only because
of the deviation from Cop,,but also because i l exacerbates the effect of any noise
due lo loss in the gate inducrance. As a consequence, it is critical to keep [he gate
inductor's Q as high as possible, and i t is also advisable to use a somewhat larger
source inductance than the theorelic:~lvalue, since the noise consequences of excessive inductance are niuch less serious than for insufficient inductance. Following this
advice can easily keep NF degradation below 0.5 dB, whereas ignoring it can just as
easily increase noise figure by over 1.5 dB.
Another potential source of NF dcgradation is the thermal noise of the subsware.
as discussed in the previous chapter. Recall that rhis epi noise produces a drain noise
component whose value is givcn by

As noted earlier, this noise source is often completely negligible above about I GHz
for typical process technologies. but one must always verify whether this generality
holds in any specific instance. .
At frequencies well below the pole frequency of I/RsubCch,this extrinsic noise
contribution can nonetheless remain negligible if model parameters satisfy the following inequality:
Rsub 5 2 R s .
(63)
In many technologies, i t may be possible to satisfy this inequality comfortably by
surrounding the transistor wilh many substrate contacts. In extreme cases it may
be necessary to break up the main device into several subscctions, each of which is
surrounded with a large quantity of substrate taps in order to reduce to a practical
minimum the contribution of epi noise.
By using a combination of tliese strategies, it is entirely possible to achieve noise
figures below 1 dB in the gigahefiz rangc at quite reasonable power consumptions
fe.g., 0.9 dB NF at 7.5 mW), making CMOS LNAs competitive with those built using
other t e c h n ~ l o g i e s . ~ ~

12.5.2

DIFFERENTIAL LNA

The single-ended LNA architecture has at least one important shortcoming, and that
is its sensitivity to parasitic ground inductance. It is clear from [he schematic of
Figure 12.9 that the ground return of the signal source is supposed to be at the same

20

J.-S.Goo cr al.. "A Noise Optiniizalion Tcchniquc for lnrcgratcd Low-Noisc Amplifiers:' IEEE I.
Solid-Slav Circuirs. v. 37, no. 8.August 2002. pp. 994-1002.