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FPGAinterviewquestions,FPGAinterview
questions&answers.
FPGAinterviewquestions&answers.

ClickhereforanexcellentdocumentonSynthesis

WhatisFPGA?
Afieldprogrammablegatearrayisasemiconductordevicecontainingprogrammable
logiccomponentscalled"logicblocks",andprogrammableinterconnects.Logic
blockscanbeprogrammedtoperformthefunctionofbasiclogicgatessuchasAND,
andXOR,ormorecomplexcombinationalfunctionssuchasdecodersor
mathematicalfunctions.InmostFPGAs,thelogicblocksalsoincludememory
elements,whichmaybesimpleflipflopsormorecompleteblocksofmemory.A
hierarchyofprogrammableinterconnectsallowslogicblockstobeinterconnectedas
neededbythesystemdesigner,somewhatlikeaonechipprogrammablebreadboard.
Logicblocksandinterconnectscanbeprogrammedbythecustomerordesigner,after
theFPGAismanufactured,toimplementanylogicalfunctionhencethename
"fieldprogrammable".FPGAsareusuallyslowerthantheirapplicationspecific
integratedcircuit(ASIC)counterparts,cannothandleascomplexadesign,anddraw
morepower(foranygivensemiconductorprocess).Buttheiradvantagesincludea
shortertimetomarket,abilitytoreprograminthefieldtofixbugs,andlowernon
recurringengineeringcosts.Vendorscansellcheaper,lessflexibleversionsoftheir
FPGAswhichcannotbemodifiedafterthedesigniscommitted.Thedesignsare
developedonregularFPGAsandthenmigratedintoafixedversionthatmore
resemblesanASIC.
Whatlogicisinferredwhentherearemultipleassignstatementstargetingthe
samewire?

Itisillegaltospecifymultipleassignstatementstothesamewireinasynthesizable
codethatwillbecomeanoutputportofthemodule.Thesynthesistoolsgiveasyntax
errorthatanetisbeingdrivenbymorethanonesource.
However,itislegaltodriveathreestatewirebymultipleassignstatements.

Whatdoconditionalassignmentsgetinferredinto?

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Conditionalsinacontinuousassignmentarespecifiedthroughthe?:operator.
Conditionalsgetinferredintoamultiplexor.Forexample,thefollowingisthecode
forasimplemultiplexor
assignwire1=(sel==1'b1)?a:b

Whatvalueisinferredwhenmultipleproceduralassignmentsmadetothesame
regvariableinanalwaysblock?

Whentherearemultiplenonblockingassignmentsmadetothesameregvariableina
sequentialalwaysblock,thenthelastassignmentispickedupforlogicsynthesis.For
example
always@(posedgeclk)begin
out<=in1^in2
out<=in1&in2
out<=in1|in2

Intheexamplejustshown,itistheORlogicthatisthelastassignment.Hence,the
logicsynthesizedwasindeedtheORgate.Hadthelastassignmentbeenthe&
operator,itwouldhavesynthesizedanANDgate.
1)Whatisminimumandmaximumfrequencyofdcminspartan3seriesfpga?
Spartanseriesdcmshaveaminimumfrequencyof24MHZandamaximumof248
2)Tellmesomeofconstraintsyouusedandtheirpurposeduringyourdesign?
Therearelotofconstraintsandwillvaryfortooltotool,IamlistingsomeofXilinx
constraints
a)TranslateonandTranslateoff:theVerilogcodebetweenTranslateonand
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Translateoffisignoredforsynthesis.
b)CLOCK_SIGNAL:isasynthesisconstraint.Inthecasewhereaclocksignalgoes
throughcombinatoriallogicbeforebeingconnectedtotheclockinputofaflipflop,
XSTcannotidentifywhatinputpinorinternalnetistherealclocksignal.This
constraintallowsyoutodefinetheclocknet.
c)XOR_COLLAPSE:issynthesisconstraint.ItcontrolswhethercascadedXORs
shouldbecollapsedintoasingleXOR.
Formoreconstraintsdetaileddescriptionrefertoconstraintguide.
3)Supposeforapieceofcodeequivalentgatecountis600andforanothercode
equivalentgatecountis50,000willthesizeofbitmapchange?inotherwordswill
sizeofbitmapchangeitgatecountchange?
Thesizeofbitmapisirrespectiveofresourceutilization,itisalwaysthesame,for
Spartanxc3s5000itis1.56MBandwillneverchange.
4)WhataredifferenttypesofFPGAprogrammingmodes?whatareyou
currentlyusing?howtochangefromonetoanother?
BeforepoweringontheFPGA,configurationdataisstoredexternallyinaPROMor
someothernonvolatilemediumeitheronorofftheboard.Afterapplyingpower,the
configurationdataiswrittentotheFPGAusinganyoffivedifferentmodes:Master
Parallel,SlaveParallel,MasterSerial,SlaveSerial,andBoundaryScan(JTAG).The
MasterandSlaveParallelmodes
Modeselectingpinscanbesettoselectthemode,referdatasheetforfurtherdetails.
5)TellmesomeoffeaturesofFPGAyouarecurrentlyusing?
Iamtakingexampleofxc3s5000toansweringthequestion.
Verylowcost,highperformancelogicsolutionfor
highvolume,consumerorientedapplications
Densitiesashighas74,880logiccells
Upto784I/Opins
622Mb/sdatatransferrateperI/O
18singleendedsignalstandards
6differentialI/OstandardsincludingLVDS,RSDS
TerminationbyDigitallyControlledImpedance
Signalswingrangingfrom1.14Vto3.45V
DoubleDataRate(DDR)support
Logicresources
Abundantlogiccellswithshiftregistercapability
Widemultiplexers
Fastlookaheadcarrylogic
Dedicated18x18multipliers
Upto1,872KbitsoftotalblockRAM
Upto520KbitsoftotaldistributedRAM
DigitalClockManager(uptofourDCMs)
Clockskewelimination
Eightglobalclocklinesandabundantrouting
6)Whatisgatecountofyourproject?
Wellminewas3.2million,Idontknowyours.!
7)Canyoulistoutsomeofsynthesizableandnonsynthesizableconstructs?
notsynthesizable>>>>
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initial
ignoredforsynthesis.
delays
ignoredforsynthesis.
events
notsupported.
real
Realdatatypenotsupported.
time
Timedatatypenotsupported.
forceandrelease
Forceandreleaseofdatatypesnotsupported.
forkjoin
Usenonblockingassignmentstogetsameeffect.
userdefinedprimitives
Onlygatelevelprimitivesaresupported.
synthesizableconstructs>>
assign,forloop,GateLevelPrimitives,repeatwithconstantvalue...
8)Canyouexplainwhatstruckatzeromeans?
ThesestuckatproblemswillappearinASIC.Sometimes,thenodeswillpermanently
tieto1or0becauseofsomefault.Toavoidthat,weneedtoprovidetestabilityin
RTL.Ifitispermanently1itiscalledstuckat1Ifitispermanently0itiscalled
stuckat0.
VerilogFAQ

9)Canyoudrawgeneralstructureoffpga?

SynthesisFAQ
DigitalFAQ
TimingFAQ
ASICFAQ
CmosFAQ

MiscFAQ
Home

10)DifferencebetweenFPGAandCPLD?
FPGA:
a)SRAMbasedtechnology.
b)Segmentedconnectionbetweenelements.
c)Usuallyusedforcomplexlogiccircuits.
d)Mustbereprogrammedoncethepowerisoff.
e)Costly
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CPLD:
a)FlashorEPROMbasedtechnology.
b)Continuousconnectionbetweenelements.
c)Usuallyusedforsimplerormoderatelycomplexlogiccircuits.
d)Neednotbereprogrammedoncethepowerisoff.
e)Cheaper
11)Whataredcm's?whytheyareused?
Digitalclockmanager(DCM)isafullydigitalcontrolsystemthat
usesfeedbacktomaintainclocksignalcharacteristicswitha
highdegreeofprecisiondespitenormalvariationsinoperating
temperatureandvoltage.
ThatisclockoutputofDCMisstableoverwiderangeoftemperatureandvoltage,
andalsoskewassociatedwithDCMisminimalandallphasesofinputclockcanbe
obtained.TheoutputofDCMcomingformglobalbuffercanhandlemoreload.
12)FPGAdesignflow?

Also,Pleaserefertopresentationsectionsynthesispptonthissite.
13)whatisslice,clb,lut?
Iamtakingexampleofxc3s500toanswerthisquestion
TheConfigurableLogicBlocks(CLBs)constitutethemainlogicresourcefor
implementingsynchronousaswellascombinatorialcircuits.
CLBareconfigurablelogicblocksandcanbeconfiguredtocombo,ramorrom
dependingoncodingstyle
CLBconsistof4slicesandeachsliceconsistoftwo4inputLUT(lookuptable)F
LUTandGLUT.
14)Canaclbconfiguredasram?
YES.
Thememoryassignmentisaclockedbehavioralassignment,Readsfromthememory
areasynchronous,Andalltheaddresslinesaresharedbythereadandwrite
statements.
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15)Whatispurposeofaconstraintfilewhatisitsextension?
TheUCFfileisanASCIIfilespecifyingconstraintsonthelogicaldesign.Youcreate
thisfileandenteryourconstraintsinthefilewithatexteditor.Youcanalsousethe
XilinxConstraintsEditortocreateconstraintswithinaUCF(extention)file.These
constraintsaffecthowthelogicaldesignisimplementedinthetargetdevice.Youcan
usethefiletooverrideconstraintsspecifiedduringdesignentry.
16)WhatisFPGAyouarecurrentlyusingandsomeofmainreasonsfor
choosingit?
17)DrawaroughdiagramofhowclockisroutedthroughoutFPGA?

18)Howmanyglobalbuffersarethereinyourcurrentfpga,whatistheir
significance?
Thereare8oftheminxc3s5000
AnexternalclocksourceenterstheFPGAusingaGlobalClockInputBuffer
(IBUFG),whichdirectlyaccessestheglobalclocknetworkoranInputBuffer(IBUF).
ClocksignalswithintheFPGAdriveaglobalclocknetusingaGlobalClock
MultiplexerBuffer(BUFGMUX).Theglobalclocknetconnectsdirectlytothe
CLKINinput.
19)Whatisfrequencyofoperationandequivalentgatecountofurproject?
20)Tellmesomeoftimingconstraintsyouhaveused?
21)Whyismaptimingoptionused?

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Timingdrivenpackingandplacementisrecommendedtoimprovedesign
performance,timing,andpackingforhighlyutilizeddesigns.
22)Whataredifferenttypesoftimingverifications?
Dynamictiming:
a.Thedesignissimulatedinfulltimingmode.
b.Notallpossibilitiestestedasitisdependentontheinputtestvectors.
c.Simulationsinfulltimingmodeareslowandrequirealotofmemory.
d.Bestmethodtocheckasynchronousinterfacesorinterfacesbetweendifferent
timingdomains.
Statictiming:
a.Thedelaysoverallpathsareaddedup.
b.Allpossibilities,includingfalsepaths,verifiedwithouttheneedfortestvectors.
c.Muchfasterthansimulations,hoursasopposedtodays.
d.Notgoodwithasynchronousinterfacesorinterfacesbetweendifferenttiming
domains.
23)ComparePLL&DLL?
PLL:
PLLshavedisadvantagesthatmaketheiruseinhighspeeddesignsproblematic,
particularlywhenbothhighperformanceandhighreliabilityarerequired.
ThePLLvoltagecontrolledoscillator(VCO)isthegreatestsourceofproblems.
Variationsintemperature,supplyvoltage,andmanufacturingprocessaffectthe
stabilityandoperatingperformanceofPLLs.
DLLs,however,areimmunetotheseproblems.ADLLinitssimplestforminsertsa
variabledelaylinebetweentheexternalclockandtheinternalclock.Theclocktree
distributestheclocktoallregistersandthenbacktothefeedbackpinoftheDLL.
ThecontrolcircuitoftheDLLadjuststhedelayssothattherisingedgesofthe
feedbackclockalignwiththeinputclock.Oncetheedgesoftheclocksarealigned,
theDLLislocked,andboththeinputbufferdelayandtheclockskewarereducedto
zero.
Advantages:
precision
stability
powermanagement
noisesensitivity
jitterperformance.
24)GiventwoASICs.onehassetupviolationandtheotherhasholdviolation.
howcantheybemadetoworktogetherwithoutmodifyingthedesign?
Slowtheclockdownontheonewithsetupviolations..
Andaddredundantlogicinthepathwhereyouhaveholdviolations.
25)Suggestsomewaystoincreaseclockfrequency?
Checkcriticalpathandoptimizeit.
Addmoretimingconstraints(overconstrain).
pipelinethearchitecturetothemaxpossibleextentkeepinginmindlatencyreq's.
26)WhatisthepurposeofDRC?
DRCisusedtocheckwhethertheparticularschematicandcorresponding
layout(especiallythemasksetsinvolved)catertoapredefinedrulesetdependingon
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thetechnologyusedtodesign.Theyareparameterssetasidebytheconcerned
semiconductormanufacturerwithrespecttohowthemasksshouldbeplaced,
connected,routedkeepinginmindthatvariationsinthefabprocessdoesnoteffect
normalfunctionality.Itusuallydenotestheminimumallowableconfiguration.
27)WhatisLVsandwhydowedothat.WhatisthedifferencebetweenLVSand
DRC?
Thelayoutmustbedrawnaccordingtocertainstrictdesignrules.DRChelpsinlayout
ofthedesignsbycheckingifthelayoutisabidebythoserules.
Afterthelayoutiscompleteweextractthenetlist.LVScomparesthenetlistextracted
fromthelayoutwiththeschematictoensurethatthelayoutisanidenticalmatchto
thecellschematic.
28)WhatisDFT?
DFTmeansdesignfortestability.'DesignforTestorTestability'amethodologythat
ensuresadesignworksproperlyaftermanufacturing,whichlaterfacilitatesthefailure
analysisandfalseproduct/piecedetection
Otherthanthefunctionallogic,youneedtoaddsomeDFTlogicinyourdesign.This
willhelpyouintestingthechipformanufacturingdefectsafteritcomefromfab.
Scan,MBIST,LBIST,IDDQtestingetcareallpartofthis.(thisisahotfieldandwith
lotsofopportunities)
29)TherearetwomajorFPGAcompanies:XilinxandAltera.Xilinxtendsto
promoteitshardprocessorcoresandAlteratendstopromoteitssoftprocessor
cores.Whatisthedifferencebetweenahardprocessorcoreandasoftprocessor
core?
Ahardprocessorcoreisapredesignedblockthatisembeddedontothedevice.Inthe
XilinxVirtexIIPro,someofthelogicblockshavebeenremoved,andthespacethat
wasusedfortheselogicblocksisusedtoimplementaprocessor.TheAlteraNios,on
theotherhand,isadesignthatcanbecompiledtothenormalFPGAlogic.
30)Whatisthesignificanceofcontaminationdelayinsequentialcircuittiming?
Lookatthefigurebelow.tcdisthecontaminationdelay.

Contaminationdelaytellsyouifyoumeettheholdtimeofaflipflop.Tounderstand
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thisbetterpleaselookatthesequentialcircuitbelow.

Thecontaminationdelayofthedatapathinasequentialcircuitiscriticalforthehold
timeattheflipflopwhereitisexiting,inthiscaseR2.
mathematically,th(R2)<=tcd(R1)+tcd(CL2)
ContaminationdelayisalsocalledtminandPropagationdelayisalsocalledtmaxin
manydatasheets.
31)WhenareDFTandFormalverificationused?
DFT:
manufacturingdefectslikestuckat"0"or"1".
testforsetofrulesfollowedduringtheinitialdesignstage.
Formalverification:
Verificationoftheoperationofthedesign,i.e,toseeifthedesignfollowsspec.
gatenetlist==RTL?
usingmathematicsandstatisticalanalysistocheckforequivalence.
32)WhatisSynthesis?
Synthesisisthestageinthedesignflowwhichisconcernedwithtranslatingyour
Verilogcodeintogatesandthat'sputtingitverysimply!Firstofall,theVerilog
mustbewritteninaparticularwayforthesynthesistoolthatyouareusing.Ofcourse,
asynthesistooldoesn'tactuallyproducegatesitwilloutputanetlistofthedesign
thatyouhavesynthesisedthatrepresentsthechipwhichcanbefabricatedthroughan
ASICorFPGAvendor.
33)Weneedtosampleaninputoroutputsomethingatdifferentrates,butIneed
tovarytherate?What'sacleanwaytodothis?
Many,manyproblemshavethissortofvariableraterequirement,yetweareusually
constrainedwithaconstantclockfrequency.OnetrickistoimplementadigitalNCO
(NumericallyControlledOscillator).AnNCOisactuallyverysimpleand,whileitis
mostnaturallyunderstoodashardware,italsocanbeconstructedinsoftware.The
NCO,quitesimply,isanaccumulatorwhereyoukeepaddingafixedvalueonevery
clock(e.g.ataconstantclockfrequency).WhentheNCO"wraps",yousampleyour
inputordoyouraction.Byadjustingthevalueaddedtotheaccumulatoreachclock,
youfinelytunetheAVERAGEfrequencyofthatwrapevent.Nowyoumayhave
realizedthatthewrappingeventmayhavelotsofjitteronit.True,butyoumayuse
thewraptoincrementyetanothercounterwhereeachadditionalDivideby2bit
reducesthisjitter.TheDDSisarelatedtechnique.Ihavetwoexamplesshowingboth
anNCOsandaDDSinmyFileArchive.Thisistrickytograspatfirst,but
tremendouslypowerfulonceyouhaveitinyourbagoftricks.NCOsalsorelateto
digitalPLLs,TimingRecovery,TDMAandother"variablerate"phenomena

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