AN1906

APPLICATION NOTE

Using the STV9380A Vertical, Class-D Amplifier in TV Sets

Philippe Maige, Display and Scalers Application Lab

INTRODUCTION
The STV9380A is an integrated amplifier operating in class-D for the vertical deflection of a cathode
ray tube (CRT). Class-D is a modulation method where the output transistors work in a high
frequency switching mode. The output signal is restored by filtering the output square wave with an
external LC filter. The major interest of class-D operation is its low power dissipation compared to
traditional amplifiers operating in class AB, thereby eliminating the need for a heatsink.
The STV9380A can handle deflection yoke currents of up to 2.5App (Amps peak-to-peak). Thus, it
is suitable for medium-sized CRT TV applications. If more current is needed, it is possible to use the
STV9381 (up to 3App).
If the current in the deflection yoke never exceeds 2 App, it is possible to use the STV9383. The
STV9380A, STV9383 and STV9381 are similar to each other except for the drive capability of the
output stage. Consequently, these circuits are fully compatible from an application point of view
(except for eventually the current capability of the power supply and the size of the filter coil), and,
therefore, the present application note applies to each of these ICs.
These ICs can be used in monitors but, due to the particularities of the monitor environment,
adherence to special application recommendations is necessary. Please refer to application note
AN1880, Using the Optimwatt STV9383 in a Monitor.
If the current in the TV deflection yoke never exceeds 1.5App, it is possible to use the STV9382
with some minor modifications to the application. In this case, please refer to application note
AN1890,Using the STV9382 Vertical, Class-D Amplifier in TV Sets.
Note: use of the STV9382 in a monitor is not recommended.

20 April 2004

Version 1.0

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Table of Contents
Chapter 1

Circuit Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4

1.1

General Description ............................................................................................................. 4

1.2

Circuit Architecture ............................................................................................................... 4

1.3

Modulator ............................................................................................................................. 5

1.4

Output Stage ........................................................................................................................ 7

1.5

Flyback Detector .................................................................................................................. 8

Chapter 2

Using the STV9380A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10

2.1

Choice of Yoke-type and Power Supply Calculation .......................................................... 10

2.2

Loop Stability ...................................................................................................................... 12

2.3

Filter Calculation ................................................................................................................ 13

2.4

Other Components Around the STV9380A ........................................................................ 15

2.4.1

Filter Capacitors ..................................................................................................................................................15

2.4.2

Flyback Capacitor ...............................................................................................................................................16

2.4.3

Cboot Capacitor ..................................................................................................................................................16

2.4.4

Vreg (pin 8) .........................................................................................................................................................16

2.4.5

Feedcap Capacitor (pin 9) ..................................................................................................................................16

2.4.6

Rfreq (pin 10) ......................................................................................................................................................16

2.5

Driving the STV9380A ........................................................................................................ 16

2.5.1

Single-Ended Vertical Ramp Input ......................................................................................................................17

2.5.2

Differential (or Symmetrical) Vertical Ramp Inputs .............................................................................................22

2.6

Removing Deflection Yoke Noise ....................................................................................... 23

2.7

Supplying the STV9380A ................................................................................................... 24

2.8

Lack of Flyback Detection ................................................................................................ 25

Chapter 3

Example Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26

3.1

50 Hz TV ............................................................................................................................. 26

3.2

100Hz TV ........................................................................................................................... 31

Chapter 4
4.1

Application Troubleshooting and PC Board Layout Hints . . . . . . . . . . . . . . . .37

Frequently Encountered Problems ..................................................................................... 37

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4.1.1

Noisy Raster at the Top and Bottom of the Screen Image ..................................................................................37

4.1.2

Excessive Heating of the Filter Coil ....................................................................................................................37

4.1.3

Noisy Raster on the Whole Screen, not only at the Top and Bottom ..................................................................37

4.1.4

Thermal Drift of the Vertical Amplitude and/or Centering ...................................................................................37

4.1.5

Excessive Ringing of Yoke Current or Voltage After Flyback ..............................................................................38

4.1.6

Current in the Deflection Yoke is Flat Just After the Flyback ............................................................................38

4.1.7

Occasional Lack of Flyback ..............................................................................................................................39

4.1.8

Jittering of the First Few Lines at the Top of the Screen .....................................................................................39

4.1.9

Systematically Missing Flyback ..........................................................................................................................39

4.1.10

Behavior of the Vertical Stage during TV Switch-on/Switch-off Transients .........................................................40

4.2

PCB Layout Hints. .............................................................................................................. 41

4.2.1

General Recommendations ................................................................................................................................41

4.2.2

Reducing EMI .....................................................................................................................................................41

4.2.3

Heat Evacuation ..................................................................................................................................................42

Chapter 5

Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43

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Circuit Description

1.1

General Description
Except for the output stage, which is class-D, the operation of the STV9380A is comparable to that
of a traditional linear vertical amplifier.
A reference sawtooth is applied to the circuit as input. This sawtooth is amplified and applied as a
current to the deflection yoke. This current is measured by means of a low value sense resistor. The
voltage across the sense resistor is used as a feedback signal in order to guarantee conformity of
the yoke current with respect to the reference input.
The overvoltage necessary for fast retrace is obtained by means of an electrolytic capacitor
charged to the power supply voltage of the circuit. During flyback, this capacitor is connected in
series with the supply for the power output stage. This method has been used for several years with
linear vertical boosters and is called internal flyback or flyback generation. It avoids the need of
an additional power supply while reducing the flyback duration.

1.2

Circuit Architecture
Referring to Figure 1, the STV9380A is composed of:
- an input preamplifier. It is a true operational amplifier whose differential inputs and single-ended
output are accessible. This makes the circuit highly adaptable; it is possible to apply a sawtooth
input with either a positive or negative slope, or a differential signal. It is also possible to accurately
adjust the static and dynamic characteristics of the feedback loop.
- a modulator which, starting from the signal delivered by the preamplifier, generates a high
frequency square wave with variable duty cycle. This modulator has an overall gain of +10 (non
adjustable).
- an output stage including power transistors required for scanning and flyback.
- a flyback detector which is basically a comparator detecting that the feedback amplifier is no
longer in a linear mode. When flyback is detected, switching is done in the output stage in order to
apply the appropriate yoke overvoltage required for fast retrace.

4/44

input
signal

STV9380A

output signal

flyback
detection

L
modulator

output

Gain = 10

stage

input
preamplifier

filter

feedback signal

deflection
yoke

Rs

current
sense
resistor

Figure 1: STV9380A Architecture and Simplified Application Schematic

Naturally, the STV9380A also integrates functional support blocks such as biasing, a voltage
reference and power supply monitoring.

1.3

Modulator
The function of the modulator is to convert a low-frequency analog input waveform into a highfrequency square wave (a two-level, high/low signal) that can be applied to the output stage. The
information of the low-frequency input signal is contained in the varying duty cycle of the highfrequency output signal. This type of modulator is frequently called a PWM or Pulsed Width
Modulator.
As described in Section 1.2, the modulator has an overall gain of +10 (non adjustable). It is in fact
composed of a preamplifier with a fixed gain of -5 followed by the modulator itself having a fixed gain
of -2.
The preamplifier (gain of -5) is composed of an operational amplifier and two integrated resistors.
The output of this preamplifier is not accessible. Do not confuse it with the input operational
amplifier described in Section 1.2.
This modulator having a gain of -2 is obtained with a feedback structure using two integrated
resistors and a high gain pulse width modulator (PWM). In order to correct the non linearities
introduced by the output stage, the feedback signal is taken from the output of the circuit.
Thanks to this architecture, there is a monitoring of the output voltage (feed-back) which reduces
the risk of distortion and non linearities introduced by the output stage and variations in Vcc. That is
to say, the feed-back reduces the internal resistance of the output stage and improves power supply

5/44

rejection. This closed-loop configuration also allows an accurate setting of the gain of the
modulator.
This local feed-back, internal to the circuit, should not be confused with the overall feed-back
monitoring the current in the deflection yoke with the sense resistor Rs.
An external capacitor Cf filters the output square wave in order to supply the PWM input with a
signal having a low ripple.
Low frequency gain. Calling B the PWM open-loop gain and A the feedback modulator gain, it can
be shown that:

R2
B
A = ------- -----------------------------R1
R1 + R2
B + -------------------R1
With B = 90 and R2/R1 = 2, A = -1.94.

R2
60K
preamplifier
from input
amplifier

(pin 14)

+Vcc

pin 9
R1

- PWM
+ gain=B=90

30K

Cf

output
stage

pin 4
OUT

-Vcc
Gain=-5

Gain=A=-2

The capacitor Cf is external to the IC

Figure 2: PWM Architecture, Over-all Gain Am = 10

In the following, we consider A = -2 for simplicity. Similarly, we will consider that the overall gain of
the modulator, as described in the previous paragraph, is given by

Am = 5 2 = 10
Modulator bandwidth. The external filtering capacitor Cf, connected between pin 9 (feedcap) and
ground, introduces a cut-off frequency Fc:

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B
Fc = ---------------------------2 R2 Cf
B and R2 are fixed internally: B = 90 and R2 = 60K (typically).

The recommended value of Cf is 4.7nF which leads to a 50 kHz bandwidth.

Switching frequency setting. The PWM contains an oscillator which determines the switching
frequency. The resistor Rfreq, connected between pin 10 and Vcc-, fixes the switching frequency.
The recommended value of this resistor is 10K which leads to 145kHz (typically) for the switching
frequency. This frequency is suitable for vertical deflection applications. It is not recommended to
change, or particularly, reduce this frequency because then filtering will become more difficult.

1.4

Output Stage
Without the need of the flyback, the output stage would essentially only require two power
transistors that connect, alternately, the output to the supplies Vcc+ and Vcc-. However, due to
flyback, the output stage has to be more sophisticated.
Figure 3 below is a simplified view of the output stage. Power Transistors T1 and T2 are used for
class-D operation working in a switching mode during the scanning phase. T3, T4 and T5 are
required for the flyback operation. Of course, electrolytic Cfly is external to the IC.

T3

D4
+VccPOW
(pin16)

D3

(pin5)

T4

+
Cfly

T1
D1

(pin6)
T5

OUT
(pin4)
T2

-Vcc
D2

-VccPOW
Figure 3: Power Output Stage

T5, which is much smaller than the other transistors, is represented as a simple switch in Figure 3.

7/44

Detailed operation of the output stage.

Scanning phase. During this phase, T3 is OFF, T4 and T5 are ON, and T1 /T2 conduct current
alternatively. Capacitor Cfly is charged to a voltage close to (Vcc+)-(Vcc-).
First half of the scanning: during this phase, current is sourced by the circuit. When T1 is ON, T1/D4
and T4 conduct. When T1 is OFF, T2/D2 conduct.
Second half of the scanning: during this phase, the circuit sinks current. When T1 is ON, T1/D1 and
T4 conduct. When T1 is OFF, T2 conducts.

Flyback. When the flyback is detected, T4 and T5 are switched OFF, T3 is switched ON, T2 is
switched OFF and T1 is switched ON.
First half of the flyback: T1/D1 sink current. Current passes through capacitor Cfly and through T3/
D3.
Second half of the flyback: current is sourced by the circuit. It goes through T3, through the
capacitor Cfly, and through T1
At the end of flyback T3 is switched OFF, T4 and T5 are switched ON, and the cycle repeats.
Note that during the first half of the flyback, the capacitor Cfly is charged and during the second half
it is discharged. Due to losses, Cfly is discharged more than it is charged. Charge compensation is
done during the scanning phase thanks to T5.

1.5

Flyback Detector
Principle of flyback detection. During the scanning phase, current in the deflection yoke follows the
reference input signal, i.e. the amplifier operates in a linear mode. In this case, suppose that the
output voltage of the circuit is in the range -10V/+10V. Since the gain of the modulator is set at 10,
the voltage at the preamplifier output (pin 14) is in the range -1V/+1V. At the return of the input
sawtooth, the current in the yoke no longer follows the reference input signal, the feedback is no
longer linear, and the output voltage of the preamplifier increases. When a 1.5 V threshold is
reached, a comparator detects the flyback.
Transistor switching is then done inside the output stage in order to apply an overvoltage to the yoke
which allows a fast retrace.
When the yoke current approaches the reference value, the system returns to being linear. When
the preamplifier output drops below 0.45V, the end of flyback is detected, i.e., the high frequency
switched signal is applied to the yoke again and the scanning phase restarts as well.
The flyback detector is basically a comparator with hysteresis. Hysteresis avoids false triggering at
the end of flyback due to damped oscillations which are sometimes present at the output of the
preamplifier.

8/44

Figure 4 below illustrates the waveforms present during flyback.

Figure 4: Preamplifier Output (pin 14, 1 V/div) and Yoke Current (0.2A/div), Time Base: 0.1 ms/div

9/44

Using the STV9380A

2.1

Choice of Yoke-type and Power Supply Calculation

The power supply of the STV9380A must be in the range +/-10V to +/-18V. This is comparable to
the range used with STs family of linear vertical boosters. Consequently, a majority of the yokes
used with linear boosters can also be used with the class-D STV9380A.
Thanks to yoke current monitoring and good power supply rejection by the STV9380A, the value of
Vcc is not critical; nevertheless a minimum value, which depends on the characteristics of the yoke,
is required.

To simplify the analysis, suppose that Vcc+ = Vcc- = Vcc (there is generally no interest in choosing
the magnitude of Vcc- different from Vcc+).

Considering the scanning phase, if the high side transistor T1 is ON during interval t1 and the low
side transistor T2 is ON during t2, a duty cycle, , can be defined as:

t1
t1
= ---------------- = ----t1 + t2
T
where T = t1 + t2 is the switching period.

Neglecting the drain-source voltage of the output transistors, the average output voltage is:

t1
t2
VOUTav = Vcc ----- Vcc ----- = ( 2 1 ) Vcc
T
T

The duty cycle is such that 0 < < 1, but it is recommended to maintain in the range 20 to 80 %
for the nominal operating point (i.e. nominal yoke current).

The corresponding average output voltage is:

0.6 Vcc < VOUTav < 0.6 Vcc

Required Supply Voltage for a Given Yoke

All resistors in the circuit must be considered: Ry the yoke resistor; R S the output current sense
resistor (Rsense); Rself the parasitic resistance of the filtering inductance, and Ron the equivalent
drain-source resistance of the output transistors.
10/44

STV9380A
feedback
filter inductor

deflection yoke

Ly

Out
pin 4

Rself

Ry

filter
cap

sense
resistor

Rs

Note: filter damping network is not included for simplicity.

Figure 5: External Output Circuit

Calling Ip the peak current in the yoke, the voltage resulting from the resistive part of the load is:

Vr = Ip ( Ry + Rs + Rself + Ron )

It is also necessary to take into account the inductive component: Ly is the yoke inductance and L
the filtering inductance. The voltage induced by the inductive part is:

2Ip
Vl = ( L + Ly ) --------------Tscan

where Tscan is the scanning duration. The minimum power supply is thus:

1
Vccmin = ( Vr + Vl ) ------0.6

Example: For Ron = 0.9, Ry = 5.5, Rself = 0.15, RS = 0.5 , Ip =1.1Amps, L = 1 mH, Ly = 7mH
and Tscan =19ms:
Vr = 7.75 V and Vl = 0.93V.
Therefore, Vccmin = 14.5 V. A Vcc between 15V and 16 V is perfect.
11/44

2.2

Loop Stability
As with any feedback system, stability must be analyzed carefully. The input preamplifier, whose
gain can be adjusted with external components, allows setting the loop gain in order to have good
regulation and stability, simultaneously. In order to predict loop behavior, particularly stability of the
closed-loop, it is convenient to analyze the open-loop gain. For that, the loop is opened at RS
because this is the location of a low impedance node.

input
signal
(grounded)

STV9380A
flyback
detection

L
modulator

output

Gain = 10

stage

input
amplifier

filter

DY

(Ly, Ry)

Rs
Vin

Vout

Figure 6: Virtual Opening for Loop Gain Calculations

Static open-loop gain. Static open-loop gain is the product of preamplifier gain (Gpreamp) and
modulator gain (Gmod) multiplied by the attenuation caused by the sense resistor, Rs. Calling this
attenuation Att:

Rs
Att = --------------------------------------Rs + Ry + Rself
Calling Gol the open-loop gain:

Gol = Gpreamp Gmod Att

12/44

Rs must be a low value resistor in order to save power. RS = Ry /10 is generally a good value.
Consequently Att is close to 0.1. Gmod is already 10, thus the product Gmod Att is close to unity
and consequently:

Gol Gpreamp
The loop gain can be easily set to the desired value thanks to resistors, external to the circuit, which
are connected to the input of the operational amplifier. Loop gain Gol has to be chosen for each
application in accordance with the dynamic characteristics of the loop and, therefore, depends on
the characteristics of the yoke. A value too low will give a poor accuracy and cause distortion of the
sawtooth while a value too high may cause instability.
In practice, good results are generally obtained with Gol around 10 (20dB).

Dynamic behavior of the loop. The dominant pole of the open-loop frequency response is mainly
due to the yoke itself. More precisely, the cut-off frequency is:

Rself + Ry + Rs
Fdp = --------------------------------------2 ( L + Ly )
where Ly and L are the yoke and filtering inductances, respectively.

The second pole is due to the low-pass LC filter, therefore:

1
Fsp = ----------------------2 LC
For stability, the filter cut-off frequency must be higher than the gain-bandwidth product of the
feedback system (i.e. a single pole response up to the unity-gain frequency).

Fsp > Fdp Gol

For a typical deflection yoke, Fdp is in the range 100Hz~200Hz. Choosing the low frequency gain of
the open-loop equal to 10 results in a unity-gain frequency in the range 1kHz ~ 2kHz.

2.3

Filter Calculation
The low-pass filter is necessary to attenuate switching frequency components present at the
amplifier output. If a filter is not used, a noisy picture is obtained due to a current ripple in the yoke
at the switching frequency. An LC filter is suggested.

13/44

STV9380A

filtering inductor

deflection yoke

Out
pin 4

filtering
capacitor

R
damping
resistor

sense
resistor

feedback
signal

Rs

Figure 7: Low-Pass Filter

It was found experimentally that the cut-off frequency of the low-pass filter must be different from
the horizontal scanning frequency. So, it is suggested to choose the low-pass cut-off between the
unity-gain frequency of the loop and the horizontal scanning frequency Fh.

1
Gol Fdp < ----------------------- < Fh
2 LC

Choosing L, C and R. Once the cut-off frequency is chosen, the L C product is fixed, but the final
values of L and C depend on the damping factor, k, given by

1
Lk = ------- --2R C

where R is an additional damping resistor. From a cost point of view, there is interest in choosing a
low value of inductance, but this leads to insufficient damping or a value of R that risks increasing
power dissipation. The final choice for RLC is, therefore, a compromise between performance and
cost.
A value too low for k will result in unwanted ringing of the yoke current and, in severe cases, even
lead to instability of the feedback system.

14/44

Remark: As the yoke is mainly inductive, the inductance to be considered for the filter calculation is
theoretically not L, but L in parallel with Ly. Generally L << Ly since the difference is small.
Generally, there is a resistor in parallel with the yoke (often mounted on the yoke itself). This resistor
also participates in damping the filter. As this resistor is dissipative, its value must not be too low. It
can also be omitted generally.

A capacitor can be added in series with damping resistor R. This allows reducing the value of R for
good damping, while reducing the power dissipated by R itself.

Figure 8 shows an example of an LC filter proposed for 50Hz TVs.

1mH
STV9380A

Deflection Yoke
470nF

68
1F

Figure 8: Example LC Filter for 50Hz TV Applications

Selecting the filter coil, practical consideration: The filter coil conducts the same current that flows in
the deflection yoke. Consequently, this coil must handle this current without excessive heating and
without saturation of its magnetic core. Saturation causes coil inductance to decrease, and this
generally lead to a noisy image at the top and the bottom of the raster. Saturation also generates
overheating of the core and sometimes to audio noise as well.
In order to reduce losses, the resistance of the copper coil should be kept low: for example, less
than 0.5 .
Respecting these recommendations, the filtering coil is not really a critical component; a large
variety of low-cost, standard components exist from many manufacturers.

2.4

Other Components Around the STV9380A

2.4.1

Filter Capacitors
Good filtering of the power supplies is essential in order to obtain good circuit operation. Two kinds
of capacitors are required: energy storage electrolytics and ceramic capacitors for filtering.
Although the supply rejection of the STV9380A itself is very good, in order to reduce ripple on the
power supplies two 1000F capacitors are recommended as energy storage elements.
Three 100 nF filtering capacitors are recommended between Vcc- and SGND (pin 11), Vcc+ and
SGND, and between Vcc+ and Vcc-. These capacitors must be mounted as close to the IC as
possible.

15/44

2.4.2

Flyback Capacitor
The flyback capacitor is connected between pin 5, Cfly+, and pin 6, Cfly-. 100F with low ESR is
recommended. This capacitor must handle the full power supply voltage of the STV9380A: for
example, with Vcc = +/-15V, the flyback capacitor rating must be at least 30V.

2.4.3

Cboot Capacitor
The booostrap capacitor, Cboot, is connected between pin 7 (BOOT) and pin 4 (OUT). Cboot is an
energy storage element driving the high side output transistor, T1; a value of 220nF is
recommended.

2.4.4

Vreg (pin 8)
Vreg is an internal voltage reference and a 100nF filtering capacitor must be connected between
pin 8 and Vcc-. This voltage reference is for internal use only, no other components than the filtering
capacitor must be connected on pin 8.

2.4.5

Feedcap Capacitor (pin 9)

The capacitor connected between pin 9 (Feedcap) and pin 11 (SGND) is called Cf in Section 1.3
and introduces a cut-off at

B
Fc = ---------------------------2 R2 Cf
where B = 90 and R2 = 60K (typically).
Since there is local feedback at the modulator level, the condition for stability is

Fc < 0.7 Fsw

where FSW is the switching frequency. Since 100kHz < FSW < 200 kHz, an Fc around 50kHz
satisfies the stability condition. This cut-off is obtained with Cf = 4.7nF.

2.4.6

Rfreq (pin 10)

The resistor Rfreq, connected between pin 10 and Vcc-, fixes the switching frequency. The
recommended value of this resistor is 10 K which leads to a 145kHz switching frequency
(typically). This frequency is suitable for the vertical deflection application, and it is not
recommended to change it, particularly to reduce it because the filtering would become more
difficult.
However, if one wants to do so, it is possible, on condition that Rfreq remains in the range
7 K 14K. The switching frequency is roughly inversely proportional to the value of resistor Rfreq.
A 470pF capacitor is connected in parallel with Rfreq in order to remove some parasitic pulses and
improve the stability of the oscillator.

2.5

Driving the STV9380A

The input amplifier of the STV9380A is a true operational amplifier allowing great flexibility when
interfacing with a scanning processor. Most often, the vertical ramp to be amplified is delivered by
the scanning processor as either a single-ended voltage or a differential current. Thus, two
examples of STV9380A interfacing will be described.

16/44

2.5.1

Single-Ended Vertical Ramp Input

Data for the design of the input circuitry are:
- vertical ramp peak-to-peak amplitude and average (or middle) value.
- peak-to-peak current in the deflection coil and value of sense resistor Rs.

Vertical ramp
Vpp

Vav

(input signal)

Voltage on Rs
Ipp x Rs

0V

(output signal)
Figure 9: Input and Output Ramp Signals

The input vertical ramp, which has a positive slope, is applied to the inverting input of the input
amplifier through a resistor. A DC voltage is applied to the non-inverting input in order to center the
raster. A centering adjustment can be done by varying this DC voltage or by varying the average
value of the vertical ramp (Vav).

STV9380A
input amplifier

R4

R3

deflection yoke

input vertical
ramp

12
_

R1

DC voltage
(voltage reference)

13

14
R5

R2

VOUT
Rs

Figure 10: Schematic to Use for Calculating Component Values Associated With Input Amplifier (LowFrequency)

As recommended in Section 2.2, RS = Ry /10. Since the gain of the modulator Gmod is 10, the gain
from Vpin14 to VOUT is close to unity. If we suppose it is exactly one for simplicity, the schematic
becomes:
17/44

STV9380A
input amplifier

R4

R3

input vertical
ramp

12
_

R1

DC voltage
(voltage reference)

13

1
14
R5

R2

VOUT
Rs

Figure 11: Simplified Schematic for Calculating Component Values Associated With Input Amplifier (LowFrequency)

The circuit is now very easy to analyze: R3/R5 in parallel with R4 determine the gain from output to
input, R5/R4 determine the loop gain, and R1/R2 generate the DC voltage on the non-inverting
input for centering the raster.
Example: Vpp=2V, Vav=2V, Rs=0.5 and Ipp=2.2Amps
R4 equal to 33K is chosen. R5 = 3.3K in order to set loop gain equal to 10. (R1, R2 and R3 do
not interact with setting the loop gain). R4//R5=3 K. (R4//R5 means R4 in parallel with R5).

The output voltage across RS is: VOUT = 2.2 x 0.5 = 1.1V (peak-to-peak).

R4 R5
R4 + R5

Vpp
VOUT

2
1.1

This allows setting the value of R3 to: R3 = -------------------- ---------------- = 3 ------- = 5.45 K

A normalized value of 5.6K is chosen.

R1 and R2 calculation. R1 and R2 form a resistor divider on the DC voltage that is applied on the
non-inverting input of the operational amplifier. Their values are chosen such that when the
sawtooth input is at a mid-value of 2V, the current in the deflection yoke becomes zero.

18/44

Suppose the DC voltage before the divider is 5V.

33 K

5.6K
2V

Vin

R1

5V
13

Iy = 0

DY

12

0V
14
3.3K

0V

R2
0.5

Rs

Figure 12: R1 and R2 Calculation

From Figure 12, the voltage on the inverting input of the amplifier is:

3
Vin = 2 ---------------- = 0.7 V
3 + 5.6
Thus, R1 and R2 must be such that:

R2
5 -------------------- = 0.7 V
R1 + R2
In addition, the impedances seen by the both inputs of the amplifier should be the same in order to
minimize offset voltage introduced by the input current of the amplifier. That is:

R3//R4//R5 = R1//R2 = 1.95K

Solving gives: R1 = 13.93 K and: R2 = 2.26 K

Normalized values of 15K and 2.4K should be used.

In order to have good raster centering stability with the temperature, the voltage reference and
input sawtooth should not have any thermal drift or, if a thermal drift exits, it must be the same for
both voltages. This is generally the case as both signals are provided by the scanning processor.
Also, to obtain a good raster stability (amplitude and centering), all resistors must be good quality
with low thermal coefficient.

19/44

Sawtooth Input with Negative Slope. For the rare case where the scanning processor provides a
vertical sawtooth with negative slope, the sawtooth must be applied to the non-inverting input of the
amplifier, and the voltage reference applied to the inverting one in order to have the right polarity for
current in the deflection yoke.
STV9380A
input amplifier

R4

R3

DC voltage

deflection yoke
12
+

R1

14

13

input vertical
ramp

R5
R2

Rs

Figure 13: Use of a Vertical Sawtooth with Negative Slope

Filtering the Input Signal. The input signal can contain noise coming from, for example, the
switched-mode power supply or the line deflection stage. If too high, this noise can cause a noisy
raster. In this case, it is necessary to filter the input signals and limit the bandwidth of the input
amplifier with some additional capacitors.

C3

STV9380A
input amplifier

R4

R3

deflection yoke

input vertical
ramp

C2
12
_

R1

DC voltage
(voltage reference)

13

14
R5

C1

R2

Rs

Figure 14: Removing Noise with Filter Capacitors C1, C2 and C3

C1. The value of this capacitor is not critical because the voltage on the non-inverting input of the
amplifier is DC. A value of several nanoFarads or tens of nanoFarads is generally OK.
20/44

C2. This capacitor must remove high-frequency noise without distorting the input sawtooth. Thus,
C2 must generally be less than 1nF. In fact, the filtering efficiency of C2 depends on the output
impedance of the ramp generator. In order not to capacitively load the ramp generator and to
increase the filtering efficiency of C2, a resistor may be added between the ramp generator output
and R3-C2. Note that excessive ramp filtering can create flyback detection problems.
C3. It is recommended to limit the bandwidth of the input amplifier to approximately 25kHz. For
example, with R4 = 33K, C3 = 180 pF is a good value.
To be effective, C1 and C2 must be located close to the STV9380A and not in the area of the
scanning processor.

21/44

Differential (or Symmetrical) Vertical Ramp Inputs

In this case, the outputs of the scanning processor are generally current generators delivering
complementary signals.

I+

I-

Iinpp

Iav

Iinpp

Iav

Figure 15: Differential Input Currents

Figure 16 below shows a proposed schematic for differential inputs.

If we consider R4 much larger than R2, the amplifier becomes a classic differential amplifier with:

R3
Voutpp = 2 Iinpp R2 -------------------R1 + R3

I+
STV9380A
input amplifier

R1
R4

input vertical
ramp

R3
12
_

R1

2.5.2

13

1
14
R2

I-

R3

R2

Vout

Rs

Figure 16: Simplified Schematic for Differential Inputs

22/44

Example: Iinpp = 0.5 mA (input current), R S = 0.5 and Ioutpp = 2.2 Amps.
R1 = 3K, R2 = 3.3K and R3 = 1.5 give Voutpp = 1.1V.

Note that the values of R1 and R3 can be be arbitrarily chosen as only their ratio appears in the
equation above for Voutpp. In practice, however, their values determine the operating points of the
differential outputs of the scanning processor. These outputs are current sources, thus R1 and R3
must be chosen in accordance with the compliance of these current sources (refer to the data sheet
of the scanning processor used).

In order to set loop gain to 10, R4 must equal 33K. In Figure 17, it should be noted that R4 on the
inverting input of the operational amplifier is virtually in parallel with R2, and thus the amplifier is
not fully balanced. This can create some offset. It is possible to add an R4 in parallel with the R2
connected to the non-inverting input to balanced the amplifier. That is to say, on pin 13, R2 can be
replaced by R2= R2//R4 (3K in our example).

Filtering Capacitors. If some noise is present on the input signals, it is possible to filter it with two
small capacitors in parallel with the two R3 resistors. This filtering must be slight in order not to
introduce excessive distortion of the input signals.
However, this application, which is differential, is theoretically less sensitive to noise than
applications using a single-ended input drive. A 180 pF capacitor in parallel with R4 (33K) is also
recommended to reduced the bandwidth of the feedback loop.

2.6

Removing Deflection Yoke Noise

Due to magnetic and capacitive coupling between the horizontal and vertical deflection yokes, some
noise at the horizontal frequency and its harmonics can be induced in the vertical deflection yoke.
This noise can enter the STV9380A through the feedback path and create some troubles like jitter
on the flyback triggering or mixing with the class-D switching frequency, creating some low
frequency interference superimposed to the vertical signal.
The visible result of this is a noisy raster, although the input signal of the booster is clean and the
vertical application is well designed generally speaking.
In this case, it is recommended to filter the feedback signal with a capacitor.
Figure 17 illustrates this filtering for an application with a single-ended input, but it naturally applies
for differential inputs, as well.

23/44

C3

180 pF
R4

R3

STV9380A
input amplifier

33K

input vertical
ramp

Vertical DY

C2

in

12
_

R1

DC voltage
(voltage reference)

13

14
R5b

C1

R2

high freq.
noise

R5a

1.8 K
C4

1.5K
6.8nF
Rs

Figure 17: Filtering of High Frequency Noise in the Feedback Path

Resistor R5 is split into two equal or nearly equal resistors and capacitor C4 shunts the noise to
ground. In order not to compromise the stability of the closed-loop, the suggested cut-off frequency
of the filtering is close to 30kHz.
Note: this additional filtering, which is recommended for monitor applications, is generally not
necessary in televisions. This filtering should not be introduced unless a noisy raster image remains
after having already applied the recommendations regarding C1, C2 and C3 of Section 2.5.1 and
Section 2.5.2.

2.7

Supplying the STV9380A

Since power dissipation of this class-D vertical application is low, power can be taken from the EHT,
(high-voltage transformer). The advantage of this is that operation of the vertical and horizontal
deflection stages is simultaneous. That is to say, if the horizontal deflection stage is halted or
disabled, the vertical stage is halted automatically as well. This is particularly convenient for a
stand-by mode or, for example, in case of horizontal deflection stage failure.
As shown in Figure 18 below, only two, fast recovery diodes and two capacitors are needed to
generate power for the STV9380A.

+Vcc
EHT

TRANSFORMER

1000F
25V

+
Gnd

1000F
25V

+
-Vcc

Figure 18: Suggestion for Generating Power Supply Voltages

24/44

Remark: If the vertical application is far from the EHT transformer, it may be wise to split each
1000F capacitor in Figure 18 into two 470F capacitors. In this case, the rectifying diodes and two
470F capacitors are located close to the EHT transformer and the other two capacitors are located
close to the STV9380A. This allows reducing the length of connections carrying high-frequency
switched currents and consequently reduces the risk of generating EMI.

2.8

Lack of Flyback Detection

Operation of a TV set without vertical scanning can damage the CRT. For this reason, a safety
function generally exists which detects a lack of flyback condition and blanks the video in order to
avoid a horizontal white line in the middle of the screen.
Probably many solutions exist to detect lack of flyback, but a very simple and reliable one consists
of sensing the voltage on the negative side of the flyback capacitor, Cfly (pin 6 of the STV9380A).
This has been similarly done with linear boosters for many years.
During normal operation of the vertical stage, a square wave exists on pin Cfly- (pin 6). During
flyback, the voltage on pin 6 is close to +Vcc and close to -Vcc during the remaining time. In case of
a vertical deflection failure or deflection yoke de-connection, the voltage on pin Cfly- is constant and
equal to -Vcc. Thus, it is very easy to detect the lack of flyback. Figure 19 below shows an example
of a schematic performing this function.

+
Cfly+

5
Cfly

STV9380A

Vguard

100F/50 V

1K

100K

Cfly-

low power
NPN

1N4148
1F

100
K

+Vcc
-Vcc
Figure 19: Example of Schematic for Lack of Flyback Detection

The output signal, often called Vguard, is low during normal operation (NPN transistor conducting).
It is high in the case of vertical scanning stop (NPN transistor turned off).

25/44

Example Applications
Two application examples are now described in detail: a class-D vertical deflection stage for a 50Hz
TV with a single ended input signal and a class-D vertical deflection stage for a 100Hz TV with
differential inputs.

3.1

50Hz TV
The deflection yoke characteristics are: Ly = 8mH, Ry = 5.4 and Ipp = 2.2Amps.

A LC filter composed of a 1mH inductor and 470 nF capacitor is used. The resistance of the filtering
coil is: Rself = 0.3.

The sense resistor RS must be close in value to Ry/10. Thus RS = 0.5 is chosen.

The resistive voltage drop of the application is

Vr = Ip ( Ry + Rs + Rself + Ron )
or

Vr = 1.1 ( 5.4 + 0.5 + 0.3 + 0.9 ) = 7.81 V

For the inductive voltage:

2Ip
3
2.2 Vl = ( L + Ly ) --------------- = ( 8 + 1 ) 10 -------------------= 1.04 V
3
Tscan
19 10
Minimum power supply voltage (Vccmin) is:

1
Vccmin = ( Vr + Vl ) ------- = 14.75 V
0.6
So a value of Vcc = +/-15V is chosen.

Low frequency dynamic characteristics of the loop.

Open-loop gain. The gain of the input operational amplifier is set at 10, thus:

Rs
Gol = Gpreamp Gmod --------------------------------------- = 10 10 0.0806 = 8.1
Rs + Ry + Rself

26/44

Dominant pole:

Rself + Ry + Rs
0.3 + 5.4 + 0.5
Fdp = --------------------------------------- = ------------------------------------------= 110Hz
3
2 ( L + Ly )
2 ( 1 + 8 ) 10
Unity gain frequency:

Fug = Fdp Gol = 110 8.1 = 888Hz

The cut-off frequency of the filter is 7.3kHz, and the horizontal line frequency is 15625 Hz. Thus, the
cut-off frequency is a compromise between the unity-gain frequency and the horizontal line
frequency, as recommended in Section 2.3.

Input circuit design.

The next figure shows the characteristics of the sawtooth to amplify. The voltage reference for the
centering adjustment is equal to 3.5V.

Vertical ramp
Vpp=3V

Vav=3.5V

(input signal)

Voltage across Rs
Ipp x Rs =2.2 x 0.5 =1.1V

0V

(output signal)
Figure 20: 50 Hz TV Example - Input Vertical Ramp and Output Voltage across Sense Resistor

Applying the same methodology as in Section 2.5.1 leads to the following schematic (the filtering
capacitors are not shown):

27/44

STV9380A
input amplifier

33K

8.2K

deflection yoke
8.2 K

DC voltage
3.5V

8mH, 5.4

12
_

input vertical
ramp

13

14
3.3K

3K
0.5

Rs

Figure 21: Input and Feedback Signal Processing for 50 Hz TV Example

A complete application schematic is shown below in Figure 22.

28/44

0.5

DY
1 F
+ 100 V

68

-Vcc

470

Resistors values in

Vcc = +/- 15 V

Ipp = 2.2 A

DY: 5.4, 8mH

-Vcc

4.7 nF

100n F

3.3K

sgnd

IN-

Feedcap
Freq

IN+

EAout

+Vcc

Vreg

Boot

CFfly-

+VccP

-VccP

out
Cfly+

-Vcc

-Vcc

-Vcc
-Vcc

-Vcc

-Vcc

STV9380A

470 pF

100F
+
220 nF

10K

-Vcc

470 nF
100 V

1 mH

-Vcc

-Vcc

33 K

3 K

180 pF

8.2 K
3.5 Vdc

input vertical
ramp

+Vcc

8.2 K

1000F

47 nF

100 nF

100nF 100nF

1000 F

29/44
+

Figure 22: 50Hz TV Example - Complete Vertical Application Schematic

Experimental results. The following figures show some waveforms obtained with an oscilloscope,
with the application corresponding to Figure 22.

Figure 23: General View of the Current and Voltage on the Deflection Yoke

Figure 23: Upper trace: current in the deflection yoke, 0.5 A/div. Lower trace: voltage on high side of
the deflection yoke versus ground, 20V/div. Time base: 5 ms/div.

Figure 24: Current and Voltage on the Deflection Yoke (Flyback)

Figure 24 shows the flyback in more detail (calibration: 10V/div, 0.5A/div and 200 s/div.) The
damped oscillation at the end of the flyback is normal and is due to the filter. The current in the
deflection yoke reaches a stable value in much less than one millisecond; this is correct for 50Hz
applications.

30/44

Figure 25: Current in the Deflection Yoke and Voltage at the Output of the Error Amplifier

Figure 25 shows the current in the deflection yoke as in the previous figure, but the voltage is taken
at the output of the error amplifier (pin 14 of the IC, 1V/div). This illustrates the flyback detection
principle: when the voltage on pin 14 rises rapidly, a comparator detects the need for flyback. When
the current in the yoke approaches the reference value, the system returns to a linear mode. When
the preamplifier output drops below 0.45V, the end of the flyback is detected. After a short transient
phase with a damped oscillation caused by the LC filter, the scanning phase starts again.

Power saving. Total power consumption of the vertical class-D application under the above
mentioned conditions was measured to be about 4.5W. The corresponding power consumption of a
linear solution is about 10.6W. Thus, at the vertical application level, the power savings between the
two solutions is 6.1W. However, taking in account the efficiency of the switch-mode power supply,
the total power saved on the primary side of the switch-mode power supply is close to 7W.
The power dissipation of the STV9380A is around 1 W, and it does not need heatsink.

3.2

100Hz TV
The deflection yoke characteristics are: Ly = 6 mH, Ry = 4.5 and Ipp = 2.3 Amps.

Filter design. Since the horizontal frequency is 31kHz, the filter cut-off frequency can be slightly
increased compared to the previous, 50Hz TV example. Thus, the filter capacitor is reduced from
470nF to 330 nF. The consequence of this is increased filter damping, and this is favorable for the
settling time of the current in the deflection yoke after flyback.

Power supply voltage. Although a lower value should be acceptable for the scanning phase, the
supply voltage actually chosen is + /-16 V in order to reduce retrace time, the duration of which is
more critical in 100Hz than in 50Hz applications.

31/44

Sense resistor. The value is 0.5 in order to satisfy the criterion RS close to Ry /10.

Low-frequency dynamic characteristics of the loop.

Applying the same calculations as in Section 3.1, it can be shown that the loop gain, Gol, is close to
9.4. The dominant pole frequency, Fdp, is 120Hz, and the unity-gain frequency, Fug, is1.13 kHz.

Input circuit design.

The next figure shows characteristics of the sawtooth delivered by the scanning processor. It is a
symmetrical (or differential) current signal.

I+ Iinpp=0.5mA

I-

Iinpp=0.5mA

Iav=0.5 mA

Iav=0.5mA

Figure 26: Input Signals for the 100 Hz TV Application

Figure 27 below is a simplified schematic for the input and feedback signal processing (valid for lowfrequency). Resistors R1 and R3 remain to be calculated. They need to be such that the current in
the deflection yoke produces 1.15VPP across the sense resistor Rs.

32/44

I+

0.5mAPP
STV9380A
input amplifier

R1
33 K

input vertical
ramp
(differential)

R3
12
+

R1

13

1
14
3.3K

I-

R3

3K

Vout = 1.15Vpp

0.5mAPP

Rs

0.5

Figure 27: Input and Feedback Signal Processing the for 100Hz TV Set Example

As was explained in Section 2.5.2:

R3
Voutpp = 2 Iinpp R2 -------------------R1 + R3
Consequently:

R3 Voutpp
1.15
------------------= --------------------------------- = -----------------------------------------------= 0.383
3
3
R1 + R3
2 Iinpp R2
2 0.5 10 3 10
For example, R1 = 6.2K and R3 = 3.9K (normalized values) lead to:

R3 ------------------= 0.386
R1 + R3
This is very close to the theoretical value. Note that the absolute values of R1 and R3 can be
arbitrarily chosen as only their ratio appears in the formula but, in practice, their absolute values
determine the operating point of the differential outputs of the scanning processor (which are
current sources). For example, choosing R1 = 620K and R3 = 390K is correct from a ratio point
of view but would lead to an unrealistic voltage at the junction of R1 and R3. Therefore, R1 and R3
must be chosen in accordance with the compliance of the output current sources of the scanning
processor.
Filtering capacitors may be added in parallel with the two R3 resistors if the input signal is noisy.
These capacitors must be kept as small as possible in order not to distort the vertical ramp.
Excessive filtering of the input signals may cause bad flyback detection.

33/44

0.5

DY
1 F
+
100 V

68

-Vcc

470

Resistors values in

Vcc = +/- 16 V

Ipp = 2.3A

DY: 4.5 , 6 mH

-Vcc

4.7 nF

100n F

-Vcc

3.3K

sgnd

Freq

EAout

Boot

IN-

+Vcc

CFfly-

Feedcap

+VccP

Cfly+

IN+

-VccP

out

Vreg

-Vcc

-Vcc

-Vcc
-Vcc

-Vcc

STV9380A
-Vcc

470pF

100F
+
220 nF

10K

-Vcc

330 nF
100 V

1 mH

-Vcc

100 nF

33 K

3.9 K

6.2 K

6.2 K

+Vcc

1000F

3.9 K

I+

C: optional filtering capacitors

3 K

180 pF

100nF 100nF

1000 F

Figure 28: 100 Hz TV Example - Complete Vertical Application Schematic

34/44

I-

Experimental results. The following figures show some oscilloscope waveforms obtained from the
application corresponding to Figure 28 above.

Figure 29: General View of the Current and Voltage on the Deflection Yoke

Figure 29: Upper trace: current in the deflection yoke, 0.5 A/div. Lower trace: voltage on high side of
the deflection yoke versus ground, 20V/div. Time base: 2ms/div.

Figure 30: Current and Voltage on the Deflection Yoke (Flyback)

Figure 30 shows the flyback in more detail (calibration: 10V/div, 0.5A/div and 200 s /div.) The
damped oscillation at the end of the flyback is normal and is due to the filter. The current in the
deflection yoke is stabilized in much less than 0.8 milliseconds which is correct for a 100 Hz
application.

35/44

Figure 31: Current in the Deflection Yoke and Voltage at the Output of the Error Amplifier

Figure 31 shows the current in the deflection yoke, but the voltage is taken at the output of the error
amplifier (pin 14 of the IC, 1 V/div). This illustrates the flyback detection principle: when the voltage
on pin 14 rises rapidly, a comparator detects the need for flyback. When the current in the yoke
approaches the reference value, the system re-enters the linear mode. When the preamplifier
output drops below 0.45V, the end of the flyback is detected. After a short transient phase with a
damped oscillation caused by the LC filter, the scanning phase starts again.

Power saving. Total power consumption of the vertical class-D application under the above
mentioned conditions was measured to be about 4.4W. The corresponding power consumption of a
linear solution is about 10.5W. Thus, at the vertical application level, the power savings between the
two solutions is 6.1W. However, taking in account the efficiency of the switch-mode power supply,
the total power saved on the primary side of the switch-mode power supply is more than 7 W.
The power dissipation of the STV9380A is around 1.1 W, so it does not need a heatsink.

36/44

Application Troubleshooting and PC Board Layout Hints

4.1

Frequently Encountered Problems

Below is a list of problems and proposed solutions that are sometimes encountered when
developing a TV application using the STV9380A vertical amplifier.

4.1.1

Noisy Raster at the Top and Bottom of the Screen Image

Applying an uniform picture, for example a white image, the raster seems noisy, particularly at the
top and bottom of the screen.
Possible cause: the filter coil (1mH) is too small and saturates when conducting peak deflection
yoke current. When saturation occurs, the value of self inductance decreases causing filtering of the
switching frequency to be insufficient which results in excessive noise at the top and bottom of the
screen image.
The solution, of course, consists in using a coil with higher current carrying capability. It is generally
agreed that self inductance must not decrease by more than 10 % of its nominal value when
conducting peak current.

4.1.2

Excessive Heating of the Filter Coil

Excessive heating of the filter coil and/or acoustic noise emission results from using a coil with
insufficient current carrying capability.
Note that excessive heating of the coil generally causes degradation of the characteristics of the
magnetic core material which can result in saturation and thus risks creating a noisy raster. So, as
mentioned in the previous paragraph, the solution consists of using a larger coil.

4.1.3

Noisy Raster on the Whole Screen, not only at the Top and Bottom
Input signals applied to the STV9380A must be free from high-frequency components, especially
those at the horizontal frequency. If a large component at the horizontal frequency enters the
STV9380A, mixing with the switching frequency results which can create low-frequency noise that
is impossible to eliminate with the output filter. This too can lead to a noisy raster and is avoided by
filtering the input signals with small capacitors located close to the STV9380A as explained in
Section 2.6, Figure 17. The feedback path can induce signal components at the horizontal
frequency in the STV9380A. This is more sensitive in 100 Hz than in 50Hz applications. This
problem can be avoided by filtering the feedback path as explained in Section 2.6.

4.1.4

Thermal Drift of the Vertical Amplitude and/or Centering

As the STV9380A is an amplifier using a large amount of feedback, thermal drift of the gain and
offset introduced by the IC itself are normally negligible. Thermal drift of the scanning amplitude or
centering value can occur if the discrete resistors, external to the STV9380A, have insufficient
temperature stability. In order to obtain stable scanning, use high-quality, low thermal coefficient
precision resistors - metal-film resistors, for example. This also applies to RS because the amplitude
of the raster is inversely proportional to the value of this resistor.
If thermal drift still occurs, it can be the result of drift of the input signals. For example, with a signalended, vertical input ramp, drift can occur if the sawtooth and DC raster centering voltages are not
correlated (e.g. generated by two different ICs).

37/44

4.1.5

Excessive Ringing of Yoke Current or Voltage After Flyback

Excessive ringing of yoke current or voltage after flyback can result from insufficient damping by the
LC filter. If ringing occurs, a damping resistor in the range 150~390 can be introduced between
the high-side of the deflection yoke and ground.
1mH
Deflection Yoke

STV9380A

470nF

68

RDAMP
220

1F

Figure 32: Filter Example with Additional Damping Resistor

Excessive ringing can also result from insufficient phase and gain margin because the open-loop
gain of the feedback system is too large. The recommended, low-frequency value of open-loop gain
is 10 as explained in Section 2.2.
Note: The damping resistor values specified in this Application Note are suggested values, but
some adjustment of their value may be required in the actual application. This results from the fact
that a deflection yoke is a complex, non-linear, component with losses. Consequently, modeling it as
a simple, series LR network does not necessarily lead to reliable calculation or simulation results.

4.1.6

Current in the Deflection Yoke is Flat Just After the Flyback

Referring to figure Figure 33 below, a flat zone response just after flyback generally occurs in

Flat Zone

Figure 33: Flat Zone Current Just After Flyback (Poor Linearity at the Top of the Screen)

low-current applications when the damping resistor, RDAMP, is connected directly in parallel with the
deflection yoke.
The reason for this phenomenon is that when the damping resistor is connected in parallel with the
deflection yoke, resistor RS of Figure 34 senses not only current in the deflection yoke but also
current in the damping resistor. However, during flyback, the current in RDAMP is not necessarily
negligible compared to that in the deflection yoke.

38/44

The solution is to increase or even suppress the damping resistor connected in parallel with the
deflection yoke.
1mH

470nF

68
1F

RDAMP

STV9380A

Deflection
Yoke

RS

Figure 34: Increase or Displace RDAMP to Reduce Flat Zone or Ringing Just After Flyback

If this introduces excessive ringing, then connect the damping resistor between the high-side of the
deflection yoke and ground (as described in the previous Section 4.1.5).
Remark: Some scanning processors deliver a vertical sawtooth with a narrow flat interval after the
sawtooth return. In this case, a flat in the deflection yoke current just after flyback is normal as this
current is just a scaled image of what is received as input.

4.1.7

Occasional Lack of Flyback

One possible cause of this is excessive bandwidth limitation of the input amplifier. Generally, this
results from the filtering capacitor connected between pins 12 and 14 having a value that is too
large. The recommended RC time constant for the feedback network between pins 12 and 14 is
around 6s (i.e. a cut-off frequency in the range of 25 to 30kHz).
False flyback triggering can also result from residual horizontal noise coming from the feedback
path. In this case, additional filtering of the feedback path can be done as explained in Section 2.6.
As flyback is triggered by the return of the input sawtooth, excessive sawtooth filtering can also
induce occasional false flyback detection.
On can check the rise time of the voltage on pin 14 at the flyback instant. The rise time must be in
the range of 5 to 20 s. A rise time larger than 30 to 40s may induce incorrect flyback detection,
particularly in a noisy application.

4.1.8

Jittering of the First Few Lines at the Top of the Screen

Reason: residual horizontal noise in the vertical section coming from the feedback path.
Solution: same as described in the previous paragraph, i.e. limiting the bandwidth of the input
amplifier and, if necessary, introducing additional filtering in the feedback path as explained in
Section 2.6

4.1.9

Systematically Missing Flyback

Possible reason: reversed polarity of the input ramp.
Figure 35 below shows the corresponding deflection yoke waveforms, voltage and current.

39/44

Figure 35: Deflection Yoke Current (0.2 A/div) and Voltage Across (10 V/div) with Reversed Input Signal (No
Flyback Operation)

4.1.10 Behavior of the Vertical Stage during TV Switch-on/Switch-off Transients

It is important to check the behavior of the vertical amplifier during switch-on or switch-off of the TV
set. Some scanning processors deliver erratic signals during these transient phases, and since it is
an amplifier, the STV9380A will try to reproduce at its output, the signals it receives as inputs.
Consequently, it is the responsibility of the developer or manufacturer to check that the maximum
ratings of the IC are not exceeded during these switch-on/switch-off transient phases.
Figure 36 shows an example starting phase under good conditions where no abnormal waveforms
are observed.

Figure 36: Example Start-up Under Good Conditions, Vcc+ and Vcc-: 5 V/div, Deflection Yoke Current: 0.5 A/div

40/44

Note that the IC integrates a safety function which disables the output stage if one of the power
supplies is lower than 6.5V (typical) in order to avoid any risk of erratic behavior due to the booster
itself.

4.2

PCB Layout Hints.

4.2.1

General Recommendations
As with any power switching device, good PCB layout is very important for obtaining good results
with the STV9380A.
We recommend a compact board layout with discrete components mounted close to the IC with
short board traces, particularly for the supply decoupling capacitors. Also, components associated
with the amplifier input (resistors and filtering capacitors) must be located close to the STV9380A.
The vertical amplifier must not be located close to a magnetic component operating at the horizontal
frequency in order to minimize any disturbance caused by magnetic fields, especially those
generated by the high voltage (EHT) supply transformer.
It is recommended to keep the scanning and vertical processors separate from each other to avoid
supply or ground coupling between them and to prevent the class-D switching operation of the
vertical amplifier from interfering with the scanning processor.
A large or wide ground path is recommended. In fact, any empty layout area should be filled with
ground metal in order to have a good, low-noise ground potential across the entire board.

4.2.2

Reducing EMI
The signal at the output of the STV9380A (pin 4) is a large amplitude square wave with fast
transitions (e.g from -Vcc to +Vcc or from +Vcc to -Vcc in a few tens of ns). For this reason the
output of the circuit is potentially a source of EMI.
To reduce the risk of EMI, shorten the length of the output connections as much as possible; that is
to say, the filtering coil and capacitor Cboot must be located close to pin 4. Also, the nature and
location of the filtering or decoupling capacitor between +VccP and -VccP is critical. This capacitor
(around 100nF) must be of good quality with low series resistance (ESR). It needs to be connected
directly between supply pins 16 and 17.
In case of severe EMI, it is possible to reduce dv/dt of the output signal by connecting a small
capacitor between the output of the circuit (pin 4) and -Vcc (pin3). However, doing this increases the
power dissipated in the circuit, therefore this capacitor must be kept as small as possible (the
maximum recommended is 390pF).

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4.2.3

Heat Evacuation
Under normal conditions, the STV9380A does not need a heatsink, however, it is possible to
enhance heat conduction away from the IC by laying-out a copper PCB area under the IC which is
connected to pins 1, 2, 3, 18, 19 and 20. This is particularly recommended in applications where the
deflection yoke current is greater than 2.2Amps (approx.) because power dissipation in the circuit
then will become greater than 1Watt.
Figure 37 below shows the thermal resistance junction-to-ambient, RthJA, as a function of copper
PCB area.
Note: Pins 1, 2, 3, 18, 19 and 20 are connected to Vcc-.
R thJA
(C/W)

Copper Area 35 m
Thickness

70

PC Board

60

50

40
0

12

Area (cm)

Figure 37: Thermal Resistance with On-board Square Heatsink vs. Copper Area

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Revision History
The following table summarizes the modifications applied to this document.
Revision
1.0

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Description
Initial version

Date
20 April 2004

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