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Laboratory
George Ciobanu
431Gb
Reference
George Ciobanu.................................................................................................................1
431Gb................................................................................................................................ 1
Reference........................................................................................................................... 1
Data Acquisition Systems..................................................................................................1
Laboratory.......................................................................................................................... 1
Lab 1 Logarithmic Amplifier..........................................................................................3
1. Introduction................................................................................................................3
2. Proceedings................................................................................................................5
3. Questions.................................................................................................................... 7
Lab 2 Inductive Displacements I.....................................................................................9
1. Purpose....................................................................................................................... 9
2. Introduction................................................................................................................9
3. Schematic description...............................................................................................10
3. Proceedings..............................................................................................................13
Lab 3 Inductive Displacements II.................................................................................16
1. Purpose..................................................................................................................... 16
2. Device description....................................................................................................16
3. Proceedings..............................................................................................................16
Lab 4 Voltage Frequency Converter...........................................................................18
1. Theory...................................................................................................................... 18
2. Proceedings..............................................................................................................22
Lab 5 Sample and Hold Circuits...................................................................................25
1. Theory...................................................................................................................... 25
The logarithmic converter has a large domain of applications. It is used in analog calculus
elements (multiplication, division, powers) and in dynamic compression circuits.
We will study a logarithmic converter in which the conversion element is a bipolar
transistor connected in the negative feedback loop of an operational amplifier (transdiode).
The Ebers-Moll relation gives us the dependency of the collector current on the baseemitter and the collector-base voltages.
Where IS is the saturation current that characterizes the transistor in the active normal
region and R=0.30.8 is the quota between the emitter and the collector currents in the inverse
active region.
For the previous schematic, the transistor Q is operating in the active normal region at a
null collector-base voltage (the OA is said to be ideal).
Neglecting the unit compared to exp(qvBE/kT) and replacing vCB=0, we get:
The compensation of the effect of the temperature is made either by thermostating the
pair of transistors that make the conversion or by choosing the resistor R 1 dependent on the
temperature.
The sizes that define the transfer characteristics of a logarithmic converter are the
conversion slope
[V/decade]
and the input voltage Vi0, for which the output voltage is null.
[V]
2. Proceedings
R2 R1 kT
0.51k 8k
ln 10 slope
30,47 ln 10 slope 508.4 2.30(mV )
R1
q
0.51k
I SI
I
7.720 10 3 SI 1.0020
I SR
I SR
Then, with the same Ii=0.01 fixed, Vr is adjusted from the P3 potentiometer until Vo=0.
Obtained for Vr=12.92V
Next, the Vo(Vi) characteristic is determined for Ri=1K in these cases:
1)The offset voltage of OA2 is compensated. This table is obtained:
Vi(V)
Vo(V)
5
-2.78
2
-2.4
1
-2.07
0.5
-1.66
0.2
-1.24
0.1
-0.96
0.05
-0.71
0.02
-0.48
0.01
-0.38
0.2
-1.24
0.1
-0.96
0.05
-0.74
0.02
-0.53
0.01
-0.39
0.2
-1.25
0.1
-0.96
0.05
-0.69
0.02
-0.38
0.01
-0.20
5
-2.7
2
-2.37
1
-2.03
0.5
-1.65
5
-2.71
2
-2.35
1
-2
0.5
-1.64
Next we graphically determined the characteristics Vo(Ii) and Ic(Vbe) of transistor Qi for
the collector current values indicated in table T1
1 Vo
room
-->2
Vbe
temp
Vo
warm
Vbe
warm
-3,25
-0,67
-2,75
-0,7206
-2,58
-0,62
-2,36
-0,68
-2,22
-0,6
-1,99
-0,66
0,5
-1,81
-0,57
-1,66
-0,64
0,2
-1,4
-0,54
-1,21
-0,61
0,1
-1,07
-0,51
-0,97
-0,58
-0,71
-0,47
-0,62
-0,55
-0,31
-0,44
-0,24
-0,52
-0,04
-0,42
-0,03
-0,49
0,5
0,3
-0,4
0,62
-0,47
0,2
0,7
-0,37
0,63
-0,45
0,1
0,94
-0,35
0,88
-0,43
1,6
-0,34
1,18
-0,41
1,72
-0,31
1,57
-0,38
2,07
-0,29
1,84
-0,38
0,5
2,33
-0,27
2,17
-0,35
0,2
2,78
-0,22
2,5
-0,32
0,1
3,06
-0,19
3,05
-0,29
0,05
3,38
-0,17
3,51
-0,27
0,02
3,66
-0,15
3,61
-0,25
1-->3
1-->4
3. Questions
1) For the logarithmic converter studied in this paper, the characteristic Vo(Ii) covers
more decades than the Vo(Vi) characteristic. Explain why. Is this situation general, or is it
specific to this converter?
7
2. Introduction
The displacement x of the magnetic core between the two coils which are included in the
differential inductive transducer determine opposite variations of their inductances. The coils are
powered by an AC current with opposite phase voltages, +Va and Va with the pulsation . The
output voltage Vm, measured at the middle of the transducer has the value:
Because usually
the first relation becomes:
Supposing that the inductance has a linear variation with the displacement x of the
magnetic core:
Conclusion: the output voltage is roughly proportional with the magnetic core
displacement.
In reality, this dependency is not linear:
3. Schematic description
The displacement measuring converter is made of a voltage stabilizer STAB, that
supplies a stable 7.5V to the oscillator OSC. The oscillator provides an alternating voltage with
a frequency f of about 5kHz for supplying the transducer through S1 and S2 wrappings of the
transformer TR1 and a reference voltage (S3 wrapping) to command the phase sensitive detector
PD.
The output voltage Vm of the transducer is amplified by the transconductance amplifier
ATA, tuned on the frequency of the oscillator. Through the transformer TR2, the current output
excites the signal input of the phase detector PD. The current at the output of the PD is filtered
by a low pass filter that assures a continuous voltage proportional to Vm (or with the magnetic
core displacement) and is displayed by a voltmeter V.
The voltage stabilizer STAB is of a derivative kind. The derivation stabilizing element is
made of T5,Z1,R4,R5 and the filtering capacitor C6.
The oscillator OSC is a 3-point LC one. The oscillation frequency is determined by the
circuit P, C3, the oscillation amplitude limitation is done through the divider R2, R3 and C4.
In the secondary wrappings S1 and S2 of the TR1 transformer the +Va, -Va supply voltages
are created and in the secondary wrapping S3, the reference voltage Vr for the PD.
The transducer can be connected through pin 1 straight to the potentiometer P 1 for
maximum sensitivity or through pin 2 and R1 for a lower sensitivity. The sensitivity is adjusted
using the potentiometer P1.
The transconductance ATA amplifier is made of the filtering circuit R11, C2, transistor T2,
R6, T1, R7, R8 and the TR2 transformer with the secondary S2 tuned through C5 on the frequency
of the oscillator.
The input unit of this amplifier is the alternating voltage from the cursor of the P
potentiometer, transmitted through C1 in the base of the T2 transistor, and the output unit is the
current introduced in the secondary circuit S2 at the input of the PD. Through the secondary
wrapping S1, a series-series feedback is created, which determines the increase of the
impedances of the amplifier both in the input circuit and in the input circuit.
The phase sensitive detector PD, monoalternating, is built from the transistors T3, T4,
which open for a single semialternance of the voltage Vr. These transistors are inversely
connected (emitter as collector and collector as emitter), the resulting residual voltage being
lower than in the case of the normal connection.
The low pass filter is made of R11 and C7.
Because the PD and LPF are galvanically isolated from the rest of the circuit, we can
arbitrarily connect to the ground the output pins of the PD (pin 1 and pin 2) from the connector
number 2.
10
11
12
3. Proceedings
We will determine the characteristics xME(x), L1(x), L2(x) where xME is the
displacement measured with the voltmeter at the output of PR 9309, L1 and L2 the coils
inductances of the transducer (PR 9314/05), and x the displacement mechanically measured
with the help of the micrometric screw. For this purpose, the micrometric screw is set to 0,00
and the displacements are from 2 to 2 mm until 20mm. The inductances L1 and L2 are measured
with a RLC bridge.
x
xME[
V]
L1
[H]
L2
[H]
13
10
12
14
18
20
0,467
16
0,611
5
0,534
0,389
0,244
0,099
0,035
7
0,157
0,321
0,757
0,912
2,36
3,11
4,11
5,19
6,13
6,8
7,23
7,49
7,59
7,53
7,3
7,72
7,7
7,39
6,81
5,89
4,82
3,56
2,63
2,04
1,76
1,68
14
15
4. Questions
1.Why must the oscillation amplitude be stabilized for the oscillator OSC?
Oscillation amplitude of the oscillator OSC must be stabilized because the oscillator
supplies an alternating voltage to power the transducer and the alternating voltage Va must have
an oscillation amplitude stabilized so that the output voltage amplitude oscillation Vm be
stabilized.
2.Does the purity of the sinusoidal signal applied to the transducer matter?
The sinusoidal signal applied to the transducer must be pure for the output signal of from
the transducer to be pure, because the output signal is proportional to the x displacement ot the
magnetic core.
3. The comparator was adjusted for measuring a aluminum rod having length 100mm at
a temperature of 20 oC. Meanwhile the lab temperature has risen to 25oC. What difference will
be indicated if the rod length is measured in the new conditions?
lAL=l0[1+t]= l0+l0t
l0=100mm
1=AL=24*10-6/C
t=25C- 20C=5C=>l=lAL-l0=1l0t=12m
4. Which graph shows the eventual mistuning between the frequency of the oscillator and
the frequency on which the transconductance ATA amplifier is tuned?
5. Which are the criterions to make the dimensions of the low pass filter?
The criterions to make a LPF are:
1 )The cut off frequency of the filter > oscillator frequency in order to remove the higher
harmonics from the oscillator specter in the case the signal is not pure.
2) The voltage drop on capacitor C7 must be equal with the voltage drop at the output of
DSF such that the adaptation condition be accomplished.
16
2. Device description
The device is made of the following devices:
STAND which measures the object using the TL402 displacement transducer
COMP CP402 comparator
MEASURING BOARD, MB on which we can measure the supply voltages and
the transducer voltages
The schematic includes the following:
Oscillator O with a frequency around 5kHz, with the stabilized amplitude, having two
voltages +Va and -Va with opposite phases, to excite the A and B transducers, as well as the
origin fixation potentiometer P. The same oscillator transmits through a secondary wrapping the
reference voltage Vr to the phase sensitive detector DP.
AC summing amplifier ASA, that sums the outputs of the A and B transducers, as well as
the output from the potentiometer P.
Phase sensitive detector PD and the low pass filter LPF, having a schematic similar to the
one in the previous lab.
I indicator, with a 0 on the center, that allows the measurement of the relative
displacements in two ways compared to the origin, fixed mechanically from S 2 and S4 and
electrically from P.
Measuring board, which allows the following voltages to be measured: supply voltage
(pins 6 and 14), transducer output (pin 5), LPF output (pin 11), ground (pin 2).
3. Proceedings
The voltages mentioned at point 2 are measured for the extreme positions. Afterwards,
the thickness differences are measured for a sheet of paper, a piece of hair, copper plated PCB
and gold plated PCB.
17
18
The voltage in the emitter of Q1 at the initial moment is higher than in the base because it
just jumped from the previous metastable state (VEH) to VEH + (VEH-VEL) and as a result, Q1
doesnt decrease to VEL when Q1 is open under the action of the positive feedback loop and
symmetrically, it determines the blocking of Q2.
Because the conductor at the right of C has the voltage VEH, the left side conductor
linearly evolves towards with a rate
until VE1 will reach VEL and the previously mentioned feedback loop is triggered.
If, for simplicity we say the temperature of the Q1-Q4 transistors is the same and
VBE1=VBE2=VBE3=VBE4=VD:
In this figure, for the first semi-period (T/2), the voltage variation in the emitter of Q 1, VE1
must have a dimension variation of 2(VEH-VEL) from t0 to t0+T/2, we can write:
20
Which means that the frequency is directly proportional with the current I if the
denominator is a constant. We consider C as constant, so we only need to analyze the other term.
If we design the circuit in such a way that R7IB4<<VZ+VD and R10IB2<<VZ+VD or at least
(R10IB2-R7IB4)<<VZ+VD we can write:
Where VD0, VZ0 are the voltages at a reference temperature (25C) and dt=(t-t0) is the
variation of the temperature with the reference temperature; ktD and ktZ are the temperature
variation coefficients of the voltages VD and VZ.
ktD is negative, typically placed between (22.2) mV/C and ktZ has positive values for
diodes with VZ0>5.6V.
We can see that the sum VZ+VD is independent on the temperature variations dt if
ktZ+ktD=0, which means finding a Zener diode having ktZ=+22.2mV/C. An acceptable solution
is BZX79-C6V2 from PHILIPS, having a typical ktZ=2.3mV/C.
Finally,
In the schematics, we find the symmetrical output circuits for TTL or CMOS compatible
volvages with an active voltage decrease through Q11 (or Q12) and passive rising of the voltage
through R7 (R12). These logical inverters are commanded by the level translators Q9, D2, R3, R4
or (Q10, D6, R13, R14).
]Between the emitters (pins 5 and 7) we can connect C capacitors of different values,
connecting pin 9 with pins 6, 8 and 13.
The current commanded sources I from figure 1 are made of the OA1 transconductance
converter (connected as an inverter) and Q9, Q10, Q7, Q8, Q5, Q6. The cascode connection of the
pairs of transistors Q7, Q5 respectively Q8, Q6 has the purpose of assuring a high output
impedance to the current generators I seen from the emitters of the transistors Q 1 and Q2.
OA1 can have its offset voltage adjusted through R13, R17, R19, R20, R21 and the filtering
capacitor C5.
21
Considering the current amplification of the Q5, Q6 transistors as being very high,
IC7=IC8=IC5=IC6=I.
22
23
2. Proceedings
All connections must be done with the POWER OFF.
The OA1 offset can be adjusted by connecting pins 24 with 16 and 10 with 18 and by
measuring pin 24. Firstly, the minimum value is chosen by varying the potentiometer. After that,
we switch from pin 16 to pin 17 and we adjust the voltage to a minimum value by rotating the
R19 potentiometer. The 10 to 18 connection is removed.
VR[V]
iC5+iC6
0,1
0,020
84
0,020
51
0,041
35
iC5-iC6
0,000
33
(iC5+iC6)/(iC5iC6)
125,3
03
0,2
0,039
01
0,039
65
0,078
66
0,000
64
122,9
06
VR[V]
0,03
0,09
0,3
0,9
f[Hz]
T/2 (+) [ms]
T/2 (-) [ms]
T/2(+)-T/2(-)
T/2(+)+T/2(-)
f [kHz]
4,03
92
92
0
184
3,9
108
108
0
216
0,41
5,95
97
79
18
176
0,628
17,17
28,8
28,8
0
57,6
1,76
56,75
9,4
8,4
1
17,8
0,85
1,04
1,4
0,8
0,84
0,28
0,28
0,088
0,24
T/2(+)-T/2(-)
-0,36
-0,04
0,152
T/2(+)+T/2(-)
2,44
1,64
f [kHz]
43,86
0,014
8
T/2(+)-T/2(-)
40
0,011
6
0,014
4
0,002
8
0,56
134,1
5
0,006
3
T/2(+)+T/2(-)
0,026
iC5[mA]
iC6[mA]
24
0,5
0,098
59
0,098
81
0,197
4
0,000
22
897,2
73
1
0,200
84
0,195
23
0,396
07
2
0,390
1
0,381
3
0,771
4
0,005
61
0,008
0,006
8
0,022
8
10
0,96
1,9
0,95
1,84
1,91
3,74
0,008
8
0,01
0,06
70,60
07
87,65
91
191
62,333
3
0,009
0,002
7
0,015
3
0,328
9
187,8
7
2,7
2,7
0
5,4
19,29
0,028
0,23
0,20
2
0,25
8
Obs.
6>9
C=1uF
8>9
C=10n
F
9>13
C=100
pF
25
26
The sample and hold circuit is like an analog switch that at the sampling command, takes
the instantaneous value of the signal from the input and holds it as a continuous current voltage
in a capacitor. For a quality S/H circuit, the following requirements must be fulfilled:
C must load as fast as possible
during the HOLD stage, the variation in time of the voltages must be as low as
possible
The following schematic corresponds to these requirements (two repeaters):
27
The circuit is relatively fast, but because the two amplifiers are independent, the errors
introduced by each one get summed.
If we need a higher low frequency tracking precision, we add the both operational
amplifiers in the negative feedback loop:
From the schematics we see that if the switch is in the S position, vO=vI, no matter how
imperfect the K switch is. If the switch is in the H position, the AO 1s loop is open, its output
gets saturated, which leads to a slow change to the sampling operation. During the hold
operation, the capacitor C discharges with a current
Where IA is the polarization current of the input of the OA1, the residual current of the K
switch in the blocking state (KH). Supposing I=constant, we get a speed of variation of the
memorized voltage:
The S/H circuit studied in this lab work has the following schematic:
In the sampling interval, switches K2 and K3 are closed and the switch K1 is open. The
operational amplifier OA2 works as a repeater, same as OA1, which has its feedback loop closed
through K2 and OA2. Both OA1 and OA2 must have the maximum slew rate sufficiently high in
order tot track the signal shape. The speed of charge of C2 can be limited by the maximum value
of the OA1 output current. The C2 capacitor is discharged through K3.
Supposing OA1 and OA2 are ideal and their characteristic is linear
28
Voltages V11 , V12 are obtained zero and are thus not represented
Voltages Vc4 and Vc5 with aproximately the same representation differing only the rising times
which for Vc4 is 0.18 ms, and for Vc5 is 0ms and respectively the falling time which are 0 ms ,
respectivelly 4us. The period as is observed is T=0.58ms.
29
For Vc5 the falling time is 40us and the period T=104us.
2. Determine the maximum charging current of the memory capacitor. The circuit is put int sampling
mode. At the input, a rectangular signal is applied: Vi vv = 5V fi= 1kHz with duty factor 1:1. V12 is
represented and the front duration is measured tr and the amplitude of the capacitors terminals V12 vv:
30
As observed from the figure above, tr=4ms, and V12vv=5V. For input current calculation the
following formula is used:
I max C1
V12VV
tr
31
32