Professional Documents
Culture Documents
Leon Chen
ARM Taiwan, Senior FAE
Oct. 14, 2010
Agenda
1.
Overview
Market challenges
Introducing the family
Common technology benefits
Spanning the applications
3.
Fundamental technologies
Processor core
Thumb-2 instruction set
NVIC
CoreSight
Ecosystem and CMSIS
4.
5.
Summary
2. The processors
Cortex-M0
Cortex-M1
Cortex-M3
Cortex-M4
Market challenges
Energy efficiency
Wireless sensors, motor control, metering
Energy efficiency
Lower energy costs
Ease of use
Lower software costs
High performance
Competitive products
32-bit/DSC applications
8/16-bit applications
16/32-bit applications
Lowest cost
Performance efficiency
Optimised connectivity
April 2005
8051
TI MSP430
Freescale HCS08
Microchip PIC18
AVR8
Atmel AVR32
Microchip dsPIC
TI C2000
Microchip PIC32
Infineon C166
Renesas SuperH
Microchip PIC24
Infineon C166
TI MSP430
Freescale 58xxx
Atmel AVR32
10
The Products
11
3 Channels to market
13
Launched 2004
14
DSP
MCU
Ease of use
C Programming
Interrupt handling
Ultra low power
15
Cortex-M4
Harvard architecture
Single cycle MAC
Floating Point
Barrel shifter
Thumb-2 technology
ARMv6 SIMD and DSP
Single cycle MAC (Up to 32 x 32 + 64->64)
Optional decoupled single precision FPU
Integrated configurable NVIC
Compatible with Cortex-M3 processor
Microarchitecture
16
32-bit MCU
32-bit Cortex-M4
Fundamental
Technologies
18
Thumb-2
Enables a performance optimised blend of 16/32-bit instructions
All processor operations can all be handled in Thumb state
Supported across the Cortex-M processor range
Thumb
ARM7
19
Cortex-M0
Cortex-M3
Cortex-M4
Cortex-R4
Cortex-A9
20
8051
1.
Cortex-M
1.
Tail-chain
Code density
A, XL ; 2 bytes
B, YL ; 3 bytes
AB; 1 byte
R0, A; 1 byte
R1, B; 3 bytes
A, XL ; 2 bytes
B, YH ; 3 bytes
AB; 1 byte
A, R1; 1 byte
R1, A; 1 byte
A, B ; 2 bytes
A, #0 ; 2 bytes
R2, A; 1 byte
A, XH ; 2 bytes
MOV
B, YL ; 3 bytes
MUL
AB; 1 byte
ADD
A, R1; 1 byte
MOV
R1, A; 1 byte
MOV
A, B ; 2 bytes
ADDC
A, R2 ; 1 bytes
MOV
R2, A; 1 byte
MOV
A, XH ; 2 bytes
MOV
B, YH ; 3 bytes
MUL
AB; 1 byte
ADD
A, R2; 1 byte
MOV
R2, A; 1 byte
MOV
A, B ; 2 bytes
ADDC
A, #0 ; 2 bytes
MOV
R3, A; 1 byte
16-bit example
ARM Cortex-M
MOV R1,&MulOp1
MOV R2,&MulOp2
MULS r0,r1,r0
MOV SumLo,R3
MOV SumHi,R4
(Memory mapped multiply
unit)
* 8051 needs at least one cycle per instruction byte fetch as they only have an 8-bit interface
22
Leakage + dynamic
Sleep mode
Leakage only
Power off
Zero power
Power off
Power consumption
Active
Power Off
23
Deep Sleep
(WIC)
Deep Sleep
Sleep
Not To scale
interrupt-controlled processing
24
300
100
50
M0
your device
PIC18L
150
MSP430
200
Available for
250
Active Mode
Sleep Mode
Sleep On Exit
Active
Mode
ISR
Sleep Mode
Sleep Mode
Deep Sleep
Active Mode
Communicate to system
26
Power (mW)
9 mW
Average power = 13 W
99.9% Sleep
1 W
0.1
9 mW
0.2
0.3
99.8
99.9
100
Time (%)
Power (mW)
1 W
0.1
27
0.2
0.3
99.8
99.9
100
Time (%)
Cortex-M0 integration
Cortex-M0
JTAG or
Serial Wire
DAP
DWT
Bus
ROM /
Flash
Debugger (e.g.
Vision)
SRAM
Data Watchpoint
BPU
Core debug support
(halt, single step, etc)
Processor
core
Debugger access to
memory, peripherals
and optional test
logic
Peripherals
Additional
test logic
USB
JTAG or Serial
Wire
In-Circuit Debugger
(e.g. ULINK2)
28
Microcontroller
Targeted embedded
system
29
AHB-lite
APB
AHB-Lite
On-chip RAM,
ROM or FLASH
Single Master
Simple Slaves
APB
Bridge
Keypad
Pipelined operation
Timers
GPIO
UART
PMU
ARM
0xF0000000
Reserved
0xE0100000
Cortex-M0
interrupts
0xE0000000
Reset
Controller
GPIO 1
GPIO 0
GPIO 2
GPIO 1
SRAM
ROM
ctrl
ctrl
GPIO 0
On-chip
ROM
0x40000800
0x40000000
On-chip
RAM
0x40001000
0x20000000
31
32
Plug it in
No Installation!
RVDS 4.0
DS-5
MDK-ARM
RL-ARM
System
Simulation
Fast
Models
Vision
simulator
RVI, RVT2,
DSTREAM
ULINK2,
ULINKPro
Hardware
platforms
Eval boards
& MPS
Target
Connection
Boards
34
35
36
37
RO Totals
25000
30000
61%
51%
25000
20000
20000
15000
15000
10000
10000
5000
5000
0
0
ARM
Thumb
Thumb (M1)
Processor
ARM7TDMI
ARM7TDMI
Cortex-M1
Cortex-M3
ARM
Thumb2
Object
ARM
Thumb
Thumb
Thumb-2
Thumb
Thumb (M1)
Thumb2
Standard
MicroLib
% saving
Library Total
21,352
8,980
61%
RO Total
25,608
12,816
51%
Library Total
17,156
6,244
57%
RO Total
20,129
9,348
50%
Library Total
16,452
5,996
64%
RO Total
19,472
9,016
54%
Library Total
15,018
5,796
63%
RO Total
18,616
8,976
54%
DEBUGGERS
OPERATING SYSTEMS
39
Conclusions
Cortex-M spans the spectrum of embedded applications
Hardware and software compatibility and reuse
High performance
Enables competitive products
40
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