ANAND INSTITUTE OF HIGHER TECHNOLOGY Chennai-603 103

DEPARTMENT OF ELECTRONICS AND INSTRUMENTATION ENGINEERING

CS2071 COMPUTER ARCHITECTURE
Subject code/ Name: CS2071/ COMPUTER ARCHITECTURE
Faculty: C.MAGESHKUMAR
Class: IV EIE A&B

Date: 15.07.2013
Semester: VII

UNIT I INSTRUCTION SET ARCHITECTURE

I.

CONTENT
Introduction to computer architecture
1. Why we study computer architecture?
2. History of computer
3. Basic units of a digital computer
4. Computer level hierarchy & Computer system engineering
5. Computer architecture & Computer organization
6. Von Neumann architecture
7. MIPS architecture, Memory and processing subsystems, Registers (miniMIPS)
8. Data size and Data types
9. Models and abstraction in programming (High-level vs. low-level programming)

Page no.
2
2
2
3
3
4
4
5
7
8

Instructions
1. Instruction for miniMIPS and its execution (example)
2. ISA & Instruction set design and evolution
3. Instruction formats
4. Instruction types
5. Overview of all 40 miniMIPS instruction
6. Pseudo-instruction
7. Macro-instruction

9
9
9
11
13
17
18
19

III.

Addressing
1. Addressing
2. Addressing modes of miniMIPS

20
20
20

IV.

Procedures and data

1. Simple procedure calls
2. Stack organization for data storage
3. Data types (refer I.8)

22
22
23
25

Assembly language programs

1. Assembly language
2. Steps in transforming assembly language program to machine language program
3. Assembler directives
4. Running assembler programs
5. Pseudo-instruction and Macro-instruction (refer II.6 and II.7)

26
26
26
28
28

II.

V.

VI.

VII.

Instruction set variations

1. Complex instructions
2. Alternative addressing modes
3. Variations in instruction format
Review of Digital Design

30
30
31
32

(will be discussed with memory systems(unit-IV))

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CS2071_Computer Architecture

I. INTRODUCTION TO COMPUTER ARCHITECTURE

1. Why we study computer architecture?
The purposes of studying architecture are
To gain knowledge about designing / building a new computer
To gain knowledge about designing / building a new version of computer
To improve software performance
To find solution with embedded computer system

To purchase a new computer

2. History of computer
Processor
technology

Memory
innovations

I/O devices introduced

Dominant look & fell

0 (1600s)

(Electro)- mechanical

Wheel, card

Lever, dial, punched card

Factory equipment

1 (1950s)

Vacuum tube

Magnetic drum

Paper tape, magnetic tape

Hall-size cabinet

2 (1960s)

Transistor

Magnetic core

Drum, printer

Room-size mainframe

3 (1970s)

SSI/MSI

RAM/ROM chip

Disk, keyboard, video

monitor

Desk-size mini

4 (1980s)

LSI/VLSI

SRAM/DRAM

Network, CD, mouse

Desktop/ laptop

5 (1990s)

ULSI,SOC(system
on chip)

SDRAM, flash

Sensor/actuator,
point/click

Invisible, embedded

Present

Artificial intelligence

Parallel computing, biometrics

Moores Law:

Moores law gives the exponential increase

in number of devices on a chip over years.
There is an annual increase of 60%.
i.e., 1.6 devices per year.
Therefore 8 devices for every 5 years.

TIPS

Tb

Processor
1.6 / yr
2 / 18 mos
10 / 5 yrs

Processor performance

Memory

GIPS

80486

R10000
Pentium II
Pentium
256Mb
68040
64Mb

Gb
1Gb

16Mb
80386
68000
MIPS
80286

4Mb

Mb

1Mb

4 / 3 yrs

256kb
64kb

kIPS
1980

1990

2000

Calendar year

CMageshKumar_AP_AIHT

CS2071_Computer Architecture

kb
2010

Memory chip capacity

Generation

3. Basic units of a digital computer:

Memory

The six main units of a digital computer

1. Input unit
2. Arithmetic & logic unit
CPU (central processing unit)
3. Data path & Control
4. Memory system
5. Link (bus structure)
6. Output unit

Control

Processor

Input

Link

Datapath

CPU

Input/Output
Output

To/from network

I/O

Fig.1. Basic units of a digital computer

4. COMPUTER LEVEL HIERARCHY & COMPUTER SYSTEM ENGINEERING

4. a. Computer level hierarchy:
|
Software
|
|
Hardware
|

Level 6
Level 5
Level 4
Level 3
Level 2
Level 1
Level 0

user
High level language
Assembly language
System software
Machine
Control
Digital logic

Executable programs, software (.exe)

C, C++, java, .
Assembly code
OS, library codes
ISA, instructions
Hardwired control, microwired
Circuits, gates. etc,..

4. b. Computer system engineering:

H ig h le v e l
v ie w

C o m p u t e r o r g a n iz a tio n

Circuit designer

Logic designer

C o m p u t e r a rc h i t e c t u r e

Electronic components

H a rd w a re

Computer designer

System designer

Application designer

Application domains

S o f tw a r e

Low le v e l
v ie w

Fig.2. Computer system engineering

4. c. Methods used to improve system performance.

The methods used to improve system performance are
1. Processor clock
2. Basic Performance Equation
3. Pipelining
4. Clock rate
5. Instruction set
6. Compiler

CMageshKumar_AP_AIHT

CS2071_Computer Architecture

5. COMPUTER ARCHITECTURE & COMPUTER ORGANIZATION

Computer organization:
Computer organization deals with operational units and interconnections that realize computer architectural
specifications.
Architectural specifications refers to control signal, interface between computers, interface between CPU,
memory, input/output peripherals.
Microarchitecture, also known as Computer organization is a lower level, a detailed description of the system
that is sufficient for completely describing the operation of all parts of the computing system, and how they are
inter-connected and inter-operate in order to implement the ISA.

Computer architecture:
Computer Architecture is an area of study that deals with the computer at the interface between hardware and
software.
Computer Architecture deals with the structure and behavior of a computer including the information formats.
Computer Architecture encompasses a set of ideas that are applicable to design or understand any computer
virtually from tiniest embedded microprocessors to most powerful supercomputers
Computer architecture is more hardware oriented than computer systems.

6. VON NEUMANN ARCHITECTURE

AC - Accumulator
MQ multiplier quotient
MBR (DR) memory buffer register /
data register
IBR instruction buffer register
PC program counter
IR instruction register
MAR (AR) memory address register

Fig.3. Expanded model of von Neumann architecture or IAS (Institute For Advance Studies) computer

AC & MQ registers for temporary storage for operand and results

DR holds the data o be written / read from addressed word of main memory
PC To monitor the sequence of instruction execution
To store the address of next instruction to be executed
IBR holds the instruction that is to be executed next
IR holds the instruction that is currently executed
MAR (AR) holds the address of the main memory to / from which data is to be transferred.
Control signals to fetch the instruction, decode the opcode, routing information correctly

7. MIPS ARCHITECTURE & MEMORY AND PROCESSING SUBSYSTEMS FOR MINIMIPS

7. a. MIPS (Microprocessor without Interlocked Pipeline Stages )Architecture :

MIPS (originally an acronym for Microprocessor without Interlocked Pipeline Stages) is a reduced instruction
set computer (RISC) instruction set architecture (ISA) developed by MIPS Technologies (formerly MIPS
Computer Systems, Inc.).
The early MIPS architectures were 32-bit, with 64-bit versions added later. Multiple revisions of the MIPS
instruction set exist, including MIPS I, MIPS II, MIPS III, MIPS IV, MIPS V, MIPS32, and MIPS64.
The current revisions are MIPS32 (for 32-bit implementations) and MIPS64 (for 64-bit implementations). MIPS32
and MIPS64 define a control register set as well as the instruction set.

Fig.4.

The first commercial MIPS model, the R2000, was announced in 1985. It added multiple-cycle multiply and
divide instructions in independent on-chip unit.
New instructions were added to retrieve the results from this unit back to the register file and these resultretrieving instructions were interlocked.
It had thirty-one 32-bit general purpose registers, but no condition code register. Unlike other registers, the
program counter is not directly accessible. The R2000 could be booted either big-endian or little-endian.
The R2000 also had support for up to four co-processors, one of which was built into the main CPU and handled
exceptions, traps and memory management, while the other three were left for other uses. One of these could be
filled by the optional R2010 FPU, which had thirty-two 32-bit registers that could be used as sixteen 64-bit
registers for double-precision.
MIPSel refers to a MIPS architecture using a little endian byte order. Since almost all MIPS microprocessors have
the capability of operating with either little endian or big endian byte order, the term is used only for processors
where little endian byte order has been pre-determined.

7. b. MEMORY AND PROCESSING SUBSYSTEMS FOR miniMIPS.

...
m 2 32

Loc 0 Loc 4 Loc 8

4 B / location

Memory

up to 2 30words

Loc
Loc
m 8 m 4

...
EIU
(Main proc.)

$0
$1
$2

$31

ALU

Execution
& integer
unit

Integer
mul/div
Hi

FPU

$0
$1
$2

(Coproc. 1)

Floating point unit

$31

FP
arith

Lo

TMU
(Coproc. 0)

Design of mul & divide

BadVaddr Trap &

Status memory
Cause unit
EPC

Design of floating point ALU

Fig. 5. Memory and Processing Subsystems for miniMIPS

Execution and integer unit (EIU):

It is the EIU that understand and executes the basic miniMIPS instructions mostly ALU / logic operations.
EIU has 32 general purpose registers, each of which is 32 bits wide and can hold the content of one memory
location is shown in fig.6.

Name Register number

Usage
$zero
0
the constant value 0
$v0-$v1
2-3
values for results and expression evaluation
$a0-$a3
4-7
arguments
$t0-$t7
8-15
temporaries
$s0-$s7
16-23
saved (by callee)
$t8-$t9
24-25
more temporaries
$gp
28
global pointer
$sp
29
stack pointer
$fp
30
frame pointer
$ra
31
return address

Fig.6. Registers of miniMIPS

7. C. MIPS REGISTERS.
(NOTE: REFER FIG.6.)
In MIPS, the operands must be registers.
32 registers are provided
each register stores a 32-bit value
compilers associate variables with registers
registers are referred to by names such as $s0 and $t1
we use the s registers for values that correspond to variables in our programs
we use the t registers for temporary values
For example, consider this example from the text:
f = (g + h) - (i + j);
We choose registers to store the values of our variables: f in $s0, g in $s1, h in $s2, i in $s3, and j in $s4.
Well also need to store temporary values, which we will store in $t0 and $t1.
The MIPS code: add $t0, $s1, $s2
7.d. Floating point unit (FLU):
In computing, floating point describes a method of representing an approximation of a real number in a way that
can support a wide range of values. The numbers are, in general, represented approximately to a fixed number of
significant digits (the mantissa) and scaled using an exponent. The base for the scaling is normally 2, 10 or 16.
The typical number that can be represented exactly is of the form:
Significant digits baseexponent
Example: 152853.5047 = 1.528535047105
summary:
MIPS operands
Name

Example
Comments
$s0-$s7, $t0-$t9, $zero, Fast locations for data. In MIPS, data must be in registers to perform
32 registers $a0-$a3, $v0-$v1, $gp,
arithmetic. MIPS register $zero alw ays equals 0. Register $at is
$fp, $sp, $ra, $at
reserved for the assembler to handle large constants.
Memory[0],
30

memory Memory[4], ...,

words

Memory[4294967292]

Accessed only by data transfer instructions. MIPS uses byte addresses, so

sequential w ords differ by 4. Memory holds data structures, such as arrays,
and spilled registers, such as those saved on procedure calls.

8. DATA SIZE AND DATA TYPES:

8.a. Data size
In miniMIPS, there are 3 datasize as follows,
1. Byte 8 bits
2. Word 4 bytes (32 bits)
3. Double word 8 bytes (64 bits)
8.a.1 word
In computer architecture, word can be defined as a 32-bit data element stored in a register or memory
location with an address.
A word is a unit of data of a defined bit length (32 bit in miniMIPS) that can be addressed and moved
between storage and the computer processor.
A word can hold
Instruction
Signed integer
Unsigned integer
Floating point number
Strings of ASCII characters
8.b.word length
Word length is defined as the total number of bits used to represent. In general 1 word equals 32 bits.
Usually, the defined bit length of a word is equivalent to the width of the computer's data bus so that a word
can be moved in a single operation from storage to a processor register.
For any computer architecture with an eight-bit byte, the word will be some multiple of eight bits.
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8.c. Byte Addressability:

Byte Addressability is used for assigning successive memory address to successive memory location. This
type of assigning is used in modern computers.
One byte=8 bits. Example:32bits Address:0,4,8....
8.d. Bid-Endian format
The name big-Endian is used when lower byte addresses are used for the most significant bytes (the left most
bytes) of the word. (most significant byte has lowest address)
8.e. Little Endian format
The name little-Endian is used when lower byte addresses are used for the less significant bytes (the right
most bytes) of the word. (Least significant byte has lowest address)
8.f. Data types

Example:
Type

S.no.
1
2
3
4

Data types
Signed integer
Unsigned integer
Floating point number
Bit string

Datasize
word
word
word
doubleword
word
doubleword

8-bit number Value32-bit version of the number

Unsigned 0010 1011 43

Unsigned 1010 1011 171
Signed
Signed

byte
byte
byte

0010 1011
1010 1011

+43
85

0000 0000 0000 0000 0000 0000 0010 1011

0000 0000 0000 0000 0000 0000 1010 1011
0000 0000 0000 0000 0000 0000 0010 1011
1111 1111 1111 1111 1111 1111 1010 1011

In miniMIPS, signed integers are represented in 2s complement format.

Signed Integer in 8-bit format (values) = [-27, 27-1] = [-128, 127]
Signed Integer in 32-bit format (values) = [-231, 231-1]
In machine representation, sign of signed integer from its most significant bit
o 0 for +
o 1 for
UnSigned Integer in 8-bit format (values) = [0, 28-1] = [0, 255]
UnSigned Integer in 32-bit format (values) = [0, 232 -1]

Decimal and hexadecimal constants

Decimal
25, 123456, 2873
Hexadecimal 0x59, 0x12b4c6, 0xffff0000
9. MODELS AND ABSTRACTION IN PROGRAMMING (High-level vs. low-level programming)
Abstraction: Abstraction is a process by which data and program are defined with a representation similar in form to
its meaning.

t e mp= v[ i]
v [ i]= v[ i+ 1]
v [ i+1 ]= te mp

O n e tas k =
m any s tatem ents

A s se m b ly
la ng ua g e
instr uc tio ns ,
m ne m o nic
Compiler

Sw ap v[ i ]
an d v[i + 1]

Hig h-le ve l
la ng ua g e
s ta te me n ts
Interpreter

V e ry
hig h -le ve l
la ng ua g e
o b je c tive s
o r ta s k s

M ore c onc rete, m ac hin e-s p ec ific , err o r -p ron e;

har der to w rite, rea d, debu g, or m ai ntain

ad d
ad d
ad d
lw
lw
sw
sw
jr

O n e s ta tem e nt =
s e ver al ins truc tions

$2 ,$5, $ 5
$2 ,$2, $ 2
$2 ,$4, $ 2
$1 5,0( $ 2)
$1 6,4( $ 2)
$1 6,0( $ 2)
$1 5,4( $ 2)
$3 1

Assembler

M o re a bs trac t, m ac hine -inde pe nde n t;

eas ier to write, r ead, de bu g, o r m a intai n

Ma c hi ne
la ng ua g e
ins tr uc tio ns ,
b ina r y (he x)

00 a5 102 0
00 42 102 0
00 82 102 0
8c 62 000 0
8c f2 000 4
ac f2 000 0
ac 62 000 4
03 e0 000 8

M o s tly one-to-on e

Fig.7. Abstraction in programming (High-level vs. low-level programming)

II.INSTRUCTIONS
1. INSTRUCTION FOR miniMIPS AND ITS EXECUTION (example)
High -le vel lang uag e s tatem ent:

a = b + c

As sem bly languag e instruc tion:

ad d $t8 , $s2 , $s1

Machine lan gua ge ins truction:

000000 10010 10001 11000 00000 100000

A LU-type
ins truction

Instruction
c ache
P
C

Register
file

$17
$18

Instruction
fetch

Register Register Regis ter

18
17
24

Register
rea dout

Data c ache
(not us ed )

A ddition
opcode

Unused

Regis ter
file

ALU
$24

Ope ration

Data
rea d/s tore

Regis ter
writeb ack

Fig.8. A typical instruction for MiniMIPS and steps in its execution

2. INSTRUCTION SET ARCHITECTURE (ISA) & INSTRUCTION SET DESIGN AND EVOLUTION:
2.a. Instruction set design:
The instruction set attributes are
1. Consistent, with uniform and generally applicable rules
2. Orthogonal, with independent features non-interfering
3. Transparent, with no visible side effect due to implementation details
4. Easy to learn/use (often a byproduct of the three attributes above)
5. Extensible, so as to allow the addition of future capabilities
6. Efficient, in terms of both memory needs and hardware realization

Processor
design
team

New
machine
project

Instruction-set
definition

Implementation

Performance
objectives

Fabrication &
testing

?
Tuning &
bug fixes
Feedback

Fig.9. Processor design and implementation process

Sales
&
use

2.b INSTRUCTION SET ARCHITECTURE (ISA):

Instruction is a word/ language easily interpreted by machine/hardware

Instructions are the language of the machine
An instruction set, or instruction set architecture (ISA), is the part of the computer architecture related to
programming, including the native data types, instructions, registers, addressing modes, memory architecture,
interrupt and exception handling, and external I/O.
ISA includes a specification of the set of opcodes (machine language), and the native commands implemented
by a particular processor

Combination of instruction set, parts of machine, its functionality will produce correct, compact, fast programs.
The instruction set / instruction set architecture we are going to discuss is instruction set of miniMIPS
Mini- minimal, MIPS microprocessor without interlocked pipeline stages.
Registers, memory location (data storage), machine instruction are concerned by the complier and assembly
programmer.

Instruction set design goals:

To maximize performance
To minimize cost
To reduce design time
Machine instruction:
Machine instruction typically contains
an opcode
one or more source operands
possibly a destination operand
Opcode:

Operand

An opcode (operational code) is a binary code or bit pattern that defines an operation.
An opcode (operation code) is the portion of a machine language instruction that specifies the
operation to be performed.
Example: opcode for Addition operation is 32 100010 in binary
In computer programming languages, the definitions of operator and operand are almost the same.
In computing, an operand is the part of a computer instruction which specifies what data is to be
manipulated or operated on, whilst at the same time representing the data itself.
In assembly language, an operand is a value (an argument) on which the instruction, named by
mnemonic, operates. The operand may be a processor register, a memory address, a literal constant,
or a label.

MiniMIPS add & subtract instructions;

e.g., compute:
g = (b + c) (e + f)
add $t8,$s2,$s3
# put the sum b + c in $t8
add $t9,$s5,$s6
# put the sum e + f in $t9
sub $s7,$t8,$t9
# set g to ($t8) ($t9)
Classification of instruction types.
Computer must have instructions capable of performing four types of operations
1. Data transfer between memory and processor (Load & Store)
2. Arithmetic and logic operations (Integer, Floating Point, logical operations)
3. Program sequencing and control (Jump, Conditional Branch, Call & Return)
4. Input / output transfer (move, copy, read, write)

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Classification of instruction sets.

A complex instruction set computer (CISC) has many specialized instructions, which may only be rarely
used in practical programs.
A reduced instruction set computer (RISC) simplifies the processor by only implementing instructions
that are frequently used in programs; unusual operations are implemented as subroutines, where the extra
processor execution time is offset by their rare use.
Theoretically important types are the minimal instruction set computer (MISC) and the one instruction
set computer (IISC) but these are not implemented in commercial processors.
Another variation is the very long instruction word (VLIW) where the processor receives many
instructions encoded and retrieved in one instruction word.
Features of RISC architecture
Small set of instructions, each of which can be executed in approximately same amount of time.
Load/Store architecture
Limited addressing modes that eliminate or speed up address calculations.
Simple, uniform instruction formats that facilitate extraction/decoding of various fields and allow overlap
between opcode interpretation and register readout.
Advantages of CISC architecture
Economy in the number of instructions used translates to smaller storage space requirements,
Fewer memory accesses and more effective use of cache space.
Closer correspondence between machine instructions and operations commonly found in high level languages
Facilitate program compilation, understanding, troubleshooting and modification.
Disadvantages of CISC architecture
Complex instruction sets are undesirable because inclusion of mechanisms to interpret all the possible
combinations of opcodes and operands might slow down even very simple operations.
Will be rarely used
Makes instruction set more complex.

3. miniMIPS INSTRUCTION FORMATS.

Simplicity and uniformity of instruction formats is common in modern RISC designs that aim to execute the most
commonly used operations as fast as possible at less expense.
There are 3 instruction formats in miniMIPS. They are
Register
Immediate
Jump

Fig.10. Instruction formats

 3.1 REGISTER INSTRUCTION FORMAT in miniMIPS:

31

op

25

rs

rt

20

rd

15

10

sh

fn

6 bits

5 bits

5 bits

5 bits

5 bits

6 bits

Opcode

Source
register 1

Source
register 2

Destination
register

Shift
amount

Opcode
extension

Register instruction format is of 32 bits long that is divided into 6 fields

Field
No. of bits
naming
usage
1
6
fn
Opcode extension
2
5
sh
Shift amount
3
5
rd
Destination register
Result is stored
4
5
rt
Source register 2
Input data
5
5
rs
Source register 1
Input data
6
6
op
opcode
Operational code will be specified.
Opcode for ADD 32 - (100000)
Fn- (Opcode extension) function field serves as an extension of opcode, to allow more than one operations to be
defined.
Sh (Shift amount) field is used in instructions that specify a constant shift amount
Example: sll $t0, $s1, 2 ---- this value 2 will be specified in sh field
$to = ($s1) left shifted by 2
3.2 IMMEDIATE INSTRUCTION FORMAT in miniMIPS:
31

op

25

rs

20

rt

15

operand / offset

6 bits

5 bits

5 bits

16 bits

Opcode

Source
or base

Destination
or data

Immediate operand
or address offset

Immediate instruction format is of 32 bits long that is divided into 4 fields

Field No. of bits
naming
usage
1
16
Operand /offset Immediate operand or address offset
2
5
rt
Source register 2
Result is stored (data)
3
5
rs
Source / base register
Input data
4
6
op
opcode
Operational code will be specified.
Opcode for addi = 8 (001000)
Opcode for Load (lw) = 35
Used in both Arithmetic and logic instructions and also for load/store operations
Operand /offset field
o When used as immediate operand:
Holds an integer that is constant throughout the operation
Works same as rt in register format
Example: addi t0, s0, 61 (to = rt, s0 = rs and Operand = 61)
Therefore, t0 = (s0) + 61
Operand field is only 16 bits long. So the valid range is (-32768 to 32767) for signed integer
and [0 x 0000, 0x ffff] for hexadecimal contants
o When used as offset:
In load, store, branch instructions 16 bit field (offset) is added to base value in rs to get
memory address for read/write (transfer of control)
For branch instructions, offset work as word, instructions always occupy 32-bits memory
For data access, offset is used as
Number of bytes forward (positive) relative to base address
Number of bytes backward (negative) relative to base address
Data (rt) field :
o Acts as data destination for load operation
Acts as data source for store operation

 3.3 JUMP INSTRUCTION FORMAT in miniMIPS:

31

Field
1

op

25

jump target address

6 bits

1 0 0 0 0 0 0 0 0 0 0 0 260 bits
0 0 0 0 0 0 0 1 1 1 1 0 1

Opcode

Memory word address (byte address divided by 4)

jump instruction format is of 32 bits long that is divided into 2 fields

No. of bits
naming
usage
26
Jump
For memory word
target
address
address
6
op
opcode
Operational code will be specified.
Opcode for ADD 32 - (100000)
Jump target address
o For unconditional transfer of control to instructions in specified address
o Only 26 bits are available in address field
o Used to carry a word address as opposed to a byte address

4. INSTRUCTION TYPES
Classification of instruction types:
Computer must have instructions capable of performing four types of operations
1. Data transfer between memory and processor (load and store instructions)
2. Arithmetic and logic operations
3. Program sequencing and control (jump and branching instructions)
4. Input / output transfer
4.1 SIMPLE ARITHMETIC AND LOGIC INSTRUCTIONS:
4.1.1 ARITHMETIC INSTRUCTIONS:
Arithmetic instructions follow R-format and I-format instruction.
The arithmetic instructions ADD and SUB have a format that is common to all two-operand ALU instructions.
For these, the fn field specifies the arithmetic/logic operation to be performed.
add $t0,$s0,$s1
sub $t0,$s0,$s1

# set $t0 = ($s0)+($s1)

# set $t0 = ($s0)-($s1) R

31

op

25

31

addi $t0,$s0,61

op

rt

15

rd

10

sh

fn

S ourc e
regis ter 1
25

rs

S ourc e
regis ter 2
20

rt

D es tinat ion
regis ter
15

Unus e d

add = 32
s ub = 34

o p e ra n d / o ffs et

0 0 1 0 0 0 0 1 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 0 1
addi = 8

20

0 0 0 0 0 0 1 0 0 0 0 1 0 0 0 1 0 1 0 0 0 0 0 0 0 0 1 0 0 0 x 0
A LU
ins truc tion

# set $t0 to ($s0)+61 I

rs

S ourc e

Des tination

Im m ediate o pe ran d

Instructions such as addi allow us to perform an arithmetic or logic operation for which one operand is a small
constant
o When used as immediate operand:
Holds an integer that is constant throughout the operation
Works same as rt in register format
Example: addi t0, s0, 61 (to = rt, s0 = rs and Operand = 61), Therefore, t0 = (s0) + 61
Operand field is only 16 bits long.
So the valid range is (-32768 to 32767) for signed integer and
[0 x 0000, 0x ffff] for hexadecimal contants
There is no SUBI instructions, but it can be accomplished by adding a negative value.
miniMIPS has a 32-bit adder and all inputs should be 32 bit long. So, the 16-bit immediate operand must be
converted to 32-bit value before it is given as input to adder. This is done by SE (sign extenion) by taking 2s
complement for signed number.

Multiply & Divide instruction:

Multiply
Divide
op

31

25

mult rs,rt - (rs)*(rt) = Hi, Lo

div rs,rt - (rs)/(rt) = Hi, Lo
rs

rt

20

rd

15

10

sh

fn

0 0 0 0 0 0 1 0 0 0 0 1 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 1 1 0 x 0
ALU
instruction

Source
register 1

Source
register 2

Unused

Unused

mult = 24
div = 26

mfhi and mflo instructions: MiniMIPS instructions for copying the contents of Hi and Lo registers into general
registers
op
rs
rt
rd
sh
fn
31
25
20
15
10
5
0
R 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 1 00 x 0
ALU
instruction

Unused

Unused

Destination
register

Unused

mfhi = 16
mflo = 18

4.1.2 LOGIC INSTRUCTIONS:

Logic instructions operate on a pair of operands on a bit-by-bit basis
The key difference between andi, ori, xori and addi is that 16-bit operand of a logical instruction is 0extended from left to turn it into 32-bit format for processing.
and $t0,$s0,$s1
# set $t0 = ($s0)^($s1)
or
$t0,$s0,$s1
# set $t0 = ($s0)($s1)
xor $t0,$s0,$s1
# set $t0= ($s0) ($s1)
nor $t0,$s0,$s1
# set $t0 = (($s0) ($s1))
__________________________________________________
andi $t0,$s0,61
# set $t0 to ($s0)61
ori $t0,$s0,61
# set $t0 to ($s0)61
xori $t0,$s0,0x00ff # set $t0 to ($s0) 0x00ff

LOGICAL SHIFTS:
MiniMIPS instructions for left and right shifting:
sll $t0,$s1,2
srl $t0,$s1,2
sllv $t0,$s1,$s0
srlv $t0,$s1,$s0
31

op

25

rs

20

rt

15

rd

10

sh

fn

0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 1 0 1 0 0 0 0 0 0 1 0 0 0 0 0 x 0
ALU
instruction

31

# $t0=($s1) left-shifted by 2
# $t0=($s1) right-shifted by 2
# $t0=($s1) left-shifted by ($s0)
# $t0=($s1) right-shifted by ($s0)

op

Unused

25

rs

Source
register

20

rt

Destination
register

15

rd

Shift
amount

10

sh

sll = 0
srl = 2

fn

0 0 0 0 0 0 1 0 0 0 0 1 0 0 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 1 x 0
ALU
instruction

Amount
register

Source
register

Destination
register

Unused

sllv = 4
srlv = 6

4.2 LOAD AND STORE INSTRUCTIONS:

Load and store instructions follow I format

Instructions that carry out data transfer between memory and processor (load and store instructions)
o load instructions - data transfer from memory to processor
o store instructions - data transfer from processor to memory
Load and store instructions transfer whole word (32 bit) between memory and processor
Each instruction specifies a register and a memory address.
op
rs
rt
operand / offset
Example: lw $t0,40($s3)
31
25
20
15

1 0 x 0 1 1 1 0 0 1 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 0 0
lw = 35
sw = 43

Base
register

Data
register

Offset rel ati ve to base

Note on base and offset:

Memory
Address in
base register

A[0]
A[1]
A[2]
.
.
.

Offset = 4i
Element i
of array A

A[i]

The memory address is the sum

of (rs ) and an imm ediate value.
Calling one of these the base
and the other the offset is quite
arbitrary. It would m ake perfect
sense to interpret the address
A($s3) as having the base A
and the offset ($s3). However,
a 16-bit base confines us to a
small portion of m emory space.

Data (rt) field $t0 register:

o Acts as data destination for load operation
o Acts as data source for store operation
lw $t0,40($s3)
sw $t0,A($s3)

# load mem[40+($s3)] in $t0

# store ($t0) in mem[A+($s3)] -- ($s3) means content of $s3

For memory address:

o Memory address is obtained by adding 16-bit signed integer (constant offset) and the base value in
register rs . i.e., by adding 40 and content of $S3 we get the memory address.

To load the constant value:

o If constant is small (< = 16 bit)
That can represented by 16-bit or less
Can be loaded into register by using addi instruction
The first operand is the constant value
The second operand is $zero register (1st register in 32 genral purpose registers of
miniMIPS)
o If constant is large (> 16 bit)
That can be represented by 32 bits
32 = 16 + 16
Upper half bit is added by lui instruction
Lower half bit is added by ori instruction
MiniMIPS lw and sw instructions and their memory addressing convention that allows for simple access to
array elements via a base address and an offset

lui $s0,61

# The immediate value 61 is loaded in upper half of $s0 with lower 16 bit set to 0s
31

op

25

rs

20

rt

15

operand / offset

0 0 1 1 1 1 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 0 1
lui = 15

Unused

Destination

Imm ediate operand

0 0 0 0 0 0 0 0 0 0 1 1 1 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Content of $s0 after the instruction is executed

 Load and store instructions for byte-size data elements.

o Bytes can be used to store ASCII characters or small integers.
o MiniMIPS addresses refer to bytes, but registers hold words.
lb $t0,8($s3)
# load rt with mem[8+($s3)] and sign-extend to fill reg
lbu $t0,8($s3)
# load rt with mem[8+($s3)] and zero-extend to fill reg
sb $t0,A($s3)
# LSB of rt to mem[A+($s3)]

op

31

rs

25

rt

20

immediate / offset

15

1 0 x x 0 0 1 0 0 1 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0
lb = 32
lbu = 36
sb = 40

Base
register

Data
register

Address offset

4.3 JUMP AND BRANCH INSTRUCTIONS:

Jump and Branch Instructions follow J, I, R format

j verify
# go to memory location named verify

The jump instruction causes program execution to proceed from the location whose numeric or symbolic
address is provided, instead of continuing with the next instruction in sequence
For the jump instruction, 26-bit address field in instruction is augmented with 00 to the right and 4 highorder bits of program counter (PC) to left to form a complete 32-bit address.

op

31

jump target address

25

0 0 0 0 1 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 0 1

j=2

x x x x 0 0 0 0 0 0 1 1 1 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
From PC

Effective target address (32 bits)

# go to address that is in $ra;

# $ra may hold a return address
Jump register (jr) instruction specifies a register ($ra) as holding the jump target address.
jr $ra is used to effect a return from a procedure to point from which the procedure is called.
Follows R-instruction format
jr $ra

31

op

rs

25

rt

20

rd

15

10

sh

fn

0 0 0 0 0 0 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0
ALU
instruction

Source
register

Unused

Unused

Unused

jr = 8

BRANCH INSTRUCTIONS:
Conditional branch instructions allow us to transfer control to given address when a condition of interest is met.
bltz $s1,L
# branch on ($s1)< 0 (branch when less than zero)
31

op

25

rs

20

rt

15

operand / offset

0 0 0 0 0 1 1 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 0 1
bltz = 1

beq $s1,$s2,L
bne $s1,$s2,L

Source

Zero

Relative branch distance in words

# branch on ($s1)=($s2) (branch when equal)

# branch on ($s1)($s2) (branch when not equal)
31

op

25

rs

20

rt

15

operand / offset

0 0 0 1 0 x 1 0 0 0 1 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 0 1
beq = 4

Source 1

Source 2

Relative branch distance in words

 slt $s1,$s2,$s3

# if ($s2)<($s3), set $s1 to 1 else set $s1 to 0; (set when less than zero)
# often followed by beq/bne
31

op

25

rs

20

rt

15

rd

10

sh

fn

0 0 0 0 0 0 1 0 0 1 0 1 0 0 1 1 1 0 0 0 1 0 0 0 0 0 1 0 1 0 1 0
ALU
instruction

slti $s1,$s2,61

Source 1
register

Source 2
register

Destination

Unused

slt = 42

# if ($s2)<61, set $s1 to 1

# else set $s1 to 0
31

op

25

rs

20

rt

15

operand / offset

0 0 1 0 1 0 1 0 0 1 0 1 0 0 0 1 0 0 0 0 0 0 0 0 0 0 1 1 1 1 0 1
slti = 10

Source

Destination

Immediate operand

5. OVERVIEW OF ALL 40 MINIMIPS INSTRUCTION

Type
COPY
(3)
ARITHMETIC
(12)

LOGIC
(7)

MEMORY
ACCESS
(5)
CONTROL
TRANSFER
(7)

SHIFT
(6)

Instruction
Load upper immediate
Move from Hi
Move from Lo
Add
Subtract
Set less than
Add immediate
Set less than immediate
Add unsigned
Subtract unsigned
Multiply
Multiply unsigned
Divide
Divide unsigned
Add immediate unsigned
AND
OR
XOR
NOR
AND immediate
OR immediate
XOR immediate
Load word
Store word
Load byte
Load byte unsigned
Store byte
Jump
Jump register
Branch less than 0
Branch equal
Branch not equal
Jump and link
System call
Shift left logical
Shift right logical
Shift right arithmetic
Shift left logical variable
Shift right logical variable
Shift right arith variable

Usage
lui rt,imm
mfhi rd
mflo rd
add rd,rs,rt
sub rd,rs,rt
slt rd,rs,rt
addi rt,rs,imm
slti rd,rs,imm
addu rd,rs,rt
subu rd,rs,rt
mult rs,rt
multu rs,rt
div rs,rt
divu rs,rt
addiu rs,rt,imm
and rd,rs,rt
or rd,rs,rt
xor rd,rs,rt
nor rd,rs,rt
andi rt,rs,imm
ori rt,rs,imm
xori rt,rs,imm
lw rt,imm(rs)
sw rt,imm(rs)
lb rt,imm(rs)
lbu rt,imm(rs)
sb rt,imm(rs)
j L
jr rs
bltz rs,L
beq rs,rt,L
bne rs,rt,L
jal L
syscall
sll rd,rt,sh
srl rd,rt,sh
sra rd,rt,sh
sllv rd,rt,rs
srlv rd,rt,rs
srav rd,rt,rs

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6. PSEUDO-INSTRUCTION
Pseudoinstructions allow us to formulate computations and decisions in alternative forms that are
not directly supported by hardware .
MiniMIPS assembler takes care of translating these alternative forms to basic form that is supported
by existing hardware instruction (hardware supported instruction).
Some pseudo instruction should be replaced by one or more than one instruction .
Pseudoinstruction are predefined, fixed, and look like machine instructions
o Example of One-To-One Pseudoinstruction:
not s0 #complement($s0) (not supported by MiniMIPS H/W) is converted to
the real instruction
nor $s0,$s0,$zero
# complement ($s0) (supported
by MiniMIPS H/W)
Example of one-to-several pseudoinstruction:
abs

$t0,$s0

# put |($s0)| into $t0 ( absolute value)

is converted to the sequence of real instructions:

add
slt
beq
sub

$t0,$s0,$zero
# copy x into $t0
$at,$t0,$zero
# is x negative?
$at,$zero,+4 # if not, skip next
$t0,$zero,$s0 # the result is 0x

instr

How is a macro different from a procedure?

Control is transferred to and returns from a procedure
After a macro has been replaced, no trace of it remains
Type
COPY

ARITHMETIC

SHIFT
LOGIC
MEMORY
ACCESS
CONTROL
TRANSFER

PseudoInstruction
Move
Load address
Load immediate
Absolute value
Negate
Multiply (into register)
Divide (into register)
Remainder
Set greater than
Set less or equal
Set greater or equal
Rotate left
Rotate right
NOT
Load doubleword
Store doubleword
Branch less than
Branch greater than
Branch less or equal
Branch greater or
equal

Usage
move regd,regs
la regd,address
li regd,anyimm
abs regd,regs
neg regd,regs
mul regd,reg1,reg2
div regd,reg1,reg2
rem regd,reg1,reg2
sgt regd,reg1,reg2
sle regd,reg1,reg2
sge regd,reg1,reg2
rol regd,reg1,reg2
ror regd,reg1,reg2
not reg
ld regd,address
sd regd,address
blt reg1,reg2,L
bgt reg1,reg2,L
ble reg1,reg2,L
bge reg1,reg2,L

What is the difference between Pseudoinstructions & Macroinstructions?

Pseudoinstructions are incorporated in the design of assembler and are thus fixed for the user but macros are user
defined.
Pseudo instructions looks exactly like an instruction, but macro looks more like a procedure in a high level
language.
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7.MACRO-INSTRUCTION

A macroinstructions (macro) is a mechanism to give a name to an often-used sequence of instructions

(shorthand notation) to avoid having a specify sequence in full each time.
Macros are user-defined and resemble procedures (have arguments)

How is a macro different from a pseudoinstruction?

Pseudoinstruction are predefined, fixed, and look like machine instructions
Macros are user-defined and resemble procedures (have arguments)
Example: speaking EIE instead of Electronics and Instrumentation Engineering

Macro fromat:
.macro

name(args)

...
.end_macro

# macro and arguments named

# instrs defining the macro
# macro terminator

Write a macro to determine the largest of three values in registers and to put the result in a fourth register.
Solution:
.macro mx3r(m,a1,a2,a3) # macro and arguments named
move m,a1
# assume (a1) is largest; m = (a1)
bge m,a2,+4
# if (a2) is not larger, ignore it
move m,a2
# else set m = (a2)
bge m,a3,+4
# if (a3) is not larger, ignore it
move m,a3
# else set m = (a3)
.endmacro
# macro terminator
If the macro is used as mx3r($t0,$s0,$s4,$s3), the assembler replaces the arguments m, a1, a2, a3 with $t0, $s0, $s4,
$s3, respectively.

III. ADDRESSING and ADDRESSING MODES.

1. ADDRESSING:

Addressing is the method by which location of an operand is specified within an instruction.

2. ADDRESSING MODES OF MINIMIPS

The way in which the location of an operand is specified in an instruction.

A method used to specify where operands are to be found and where result must go.
To get the location of operand.

MiniMIPS uses six addressing modes as follows:

Addressing

Instruction

Other elements invol ved

Some place
in the machine

Implied

Extend,
if required

Immediate
Reg spec

Register

Reg f ile

Constant offset

Base
Reg base

PC-relative

Operand

Reg f ile

Reg
data

Reg data

Add

Mem
addr

Add

Mem
addr

Constant offset

PC

Pseudodirect

PC

Mem
Memory data

Mem
Memory data

Mem
addr Memory Mem
data

Fig.10. Addressing modes

1. Implied addressing mode:
operand or data comes from a predefined place which is not specified in the instruction.
operand or result goes to a predefined place which is not specified in the instruction.
Example:
o jal proc #jump to location proc and link to the address specified in $RA
2. Immediate addressing mode
Operand is given in instruction itself
Example:
o addi to, s1, 61
3. Register addressing mode
Operand is taken from a specified register.
Result is placed in a specified register
(register location alone specified)
Example:
o add t0, s1, s2 (R type. 2 operand register & 1 result register)
4. Base addressing

Operand is stored in memory and the corresponding memory location is computed by adding an offset
(16-bit signed integer) with content of specified base register.
Example:
o lw to, 40($s1) - [40 + content of S1] gives the memory location

5. PC-Relative addressing.

Operand is stored in memory and the corresponding memory location is computed by adding an offset
(16-bit signed integer) with content of program counter.
Here the offset is appended with 2 0s at the right end.
Example:
o bltz $s1, imm [imm + content of program counetr] gives the memory location.

6. Pseudo direct addressing.

Jump Instruction is an example for Pseudo direct addressing.

j verify
# go to memory location named verify
The jump instruction causes program execution to proceed from the location whose numeric or symbolic
address is provided, instead of continuing with the next instruction in sequence
For the jump instruction, 26-bit address field in instruction is augmented with 00 to the right and 4
high-order bits of program counter (PC) to left to form a complete 32-bit address.
op

31

0 0 0 0 1 0

25

ju m p ta rg e t a d d re s s

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 0 1

j = 2

x 0 0 0 0 0 0 1 1 1 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

F ro m P C

E ff ec t i ve tar get ad d res s (3 2 bit s )

IV.

PROCEDURES AND DATA

1.

SIMPLE PROCEDURE CALLS:

Defn.:A procedure is a subprogram that when called or initiated performs a specific task, leading to one or
more results, based on the input parameters (arguments) with which it is provided and returns to the point of
call.
Instruction used for invoking a procedure call : jal proc
jal jump and link. i.e., jump to (transfer the control) the specified location proc and link back (return the
control) to the next instruction from where the procedure is invoked (called).
When
Opcode for jal instruction = 3 (000011)
Using a procedure involves the following sequence of actions:
1. Initialize input parameters (arguments) in places known to procedure (regs $a0-$a3)
2. Transfer control to procedure, saving the return address (jal)
3. Acquire storage space, if required, for use by the procedure
4. Perform the desired task
5. Put results in places known to calling program (regs $v0-$v1)
6. Return control to calling point (jr)
MiniMIPS instructions for procedure call and return from procedure:
jal proc # jump to loc proc and link; link means save the return address (PC)+4 in $ra ($31)
jr rs # go to loc addressed by rs
main
P repa re
to c all
PC

jal

pr oc

P repa re
to c ontinue

proc
S a ve, etc .

Res tore
jr

$ra

Fig.11. Illustrating a Procedure Call --- Relationship between the main program and a procedure
main

PC

jal

abc

Prepare
to call
Prepare
to continue

abc

Procedure
abc
Save
xyz
jal

Procedure
xyz

xyz

Restore
jr

$ra

jr

$ra

Fig.12. Illustrating a nested Procedure Call --- Relationship between the main program, procedures

As a procedure is executed, it makes use of registers to hold operands and partial results. Upon returning
from the procedure, the calling program might reasonably expect to find its own operands and partial results
where they were prior to procedure call.
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2.

To avoid the overhead associated with large number of register save and restore operations during procedure
calls the following set of registers are used by procedure.
o $v0-$v1
o $t0 - $t9
The division of responsibility between calling program and called program is quite sensible
calling program main program
called program callee program procedure
caller-saved registers: $v0-$v1, $t0 - $t9
o these registers are not disturbed by main program
o results of procedure execution are to be saved in these registers
o no need to restore the original content of the registers that was before the execution of procedure.
callee-saved registers: $a0-$a3, $s0-$s7, $gp, $sp, $fp, $ra
o These registers are not disturbed by procedure
o results of main memory are to be saved in these registers
o The original content of the registers that was before the execution of procedure are to be restored
after execution of procedure.
Saving of register content is required only if it will be used in future by caller / callee.
A single procedure can accept upto 4 arguments (input parameters), return upto 2 results and many
intermediate values
In Fig.12, the procedure abc calls procedure xyz. Before calling xyz, the calling procedure abc
performs some preparatory actions such as
o putting arguments in registers $a0-$a3
o saving any of the registers $v0-$v1, $t0 - $t9

STACK ORGANIZATION FOR DATA STORAGE

A common mechanism for saving things or making room for temporary data that a procedure needs is the use
of a dynamic data structure known as stack.
Data are stored in CPU registers and computer memory
Proper organization of Data items of same types can be done for ease access.
Data items of same types are organized in form of arrays and accessed using array pointer
Defn.:
o Stack is a list of data element usually words or bytes with accessing restriction that the data elements
can be added or removed at only one end of the list only.
Type of data structure used : last-in-last-out (LIFO)
The below diagram (fig.13) shows miniMIPS memory mapping and use of 3 pointer registers.
Stack pointer is a register used to hold the address of the stack.
Stack pointer is denoted by $SP in MIPS register and it always points at top data elementcurrently holding
in stack
Stack allows us to pass/return an arbitrary number of values
Using the Stack for Data Storage in below figures 14 and 15.
Data elements are added to stack by pushing them onto the stack and retrieved by popping them (fig. 15).
PUSH:
o Push operation is to insert a new data element on stack
o During Push operation $SP is incremented to add new data
push: addi $sp,$sp,-4 content of $SP is added with (-4) and the result is in $SP
sw $t4,0($sp) $SP + 0 = $SP. The content of $t4 in stored in address specified in $SP
POP:
o Pop operation is to remove a stored data element from stack
o During Push operation $SP is decremented to remove old data
pop: lw $t5,0($sp) $SP + 0 = $SP. The content of (address specified in $SP) are loaded to $t5.
addi $sp,$sp,4 content of $SP is added with 4 and the result is in $SP
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Note: please refer chapter 6, section 6.2 and 6.3, 6.5 (arrays) for detailed description.
Hex address

00000000

4 MB

Reserved

1 M words

Program

Text segment
63 M words (252 MB)

00400000

10000000

Addressable
with 16-bit
signed offset

Static data

10008000

Data segment

1000ffff

Dynamic data
448 M words

$gp
$28
$29
$30

$sp
$fp

Stack

Stack segment

7ffffffc

Second half of address

space reserved for
memory-mapped I/O

Fig.13. Memory Map in MiniMIPS - Overview of the memory address space in MiniMIPS
$sp

z
y
..
.

Local
variables
Saved
registers

Frame for
current
procedure

Old ($fp)

$sp

$fp

c
b
a
..
.

c
b
a
..
.

Frame for
current
procedure

Frame for
previous
procedure

$fp
Before calling

After calling

Fig.14. Use of the stack by a procedure

sp

b
a

Push c

sp

c
b
a

Pop x

sp
sp = sp 4
mem[sp] = c

b
a

x = mem[sp]
sp = sp + 4

Fig.15 Effects of PUSH and POP operations on a stack

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3.

Example of Using the Stack:

Saving $fp, $ra, and $s0 onto the stack and restoring them at the end of the procedure

Please refer section I.8

DATA TYPES
ASCII (American standard code for information interchange)

A 32-bit word has no inherent meaning and can be interpreted in a number of equally valid ways in
the absence of other cues (e.g., context) for the intended meaning.
Bit pattern
(02114020) hex

0000 0010 0001 0001 0100 0000 0010 0000

00000010000100010100000000100000
Add instruction
00000010000100010100000000100000
Positive integer
00000010000100010100000000100000
Four-character string

V.
1.

ASSEMBLY LANGUAGE PROGRAMS

ASSEMBLY LANGUAGE

Defn.: Assembly language is a low level language in which there is a very strong one-to-one
correspondence between language and computer architectures machine code instruction.
Example: add $to, $s8, $s5
addi $t1, $s7, 43
The advantage of assembly language.
o Extreme efficiency
o An assembly language program uses up much less memory
o Runs much faster.
Assembly language programs are divided roughly into 5 parts
o Header
o Equates
o Data
o Body
o Closing
Assembly language allows use of symbolic names for instructions and operands.
Assembly languages (assembler) accepts numbers in a variety of number representation

2.
STEPS IN TRANSFORMING ASSEMBLY LANGUAGE PROGRAM TO MACHINE
LANGUAGE PROGRAM

$2,$5,$5
$2,$2,$2
$2,$4,$2
$15,0($2)
$16,4($2)
$16,0($2)
$15,4($2)
$31

00a51020
00421020
00821020
8c620000
8cf20004
acf20000
ac620004
03e00008

Executable
machine
language
program

Loader

add
add
add
lw
lw
sw
sw
jr

Machine
language
program

Linker

Assembly
language
program

Assembler

MIPS, 80x86,
PowerPC, etc.

Library routines
(machine language)

Memory
content

Overall process:
Multiple program modules that are independently assembled are linked together and combined with predeveloped library routines to form a complete executable machine language program which is then
loaded into computers memory
Steps:
1. Assembler converts assembly language program into machine language program.
2. Linker links multiple machine language program modules together to form an executable machine
language program.
3. Loader loads executable machine language program into memory.

2.a. ASSEMBLER
Defn.: Assembler is program that translates instruction sequences written in symbolic assembly
language into machine language
Assembler accepts numbers in a variety of number representation and automatically convert thgem to
required machine formats
Assembler allows the use of pseudo instructions and macroinstructions.
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Steps carried by assembler to translate assembly language into machine language are as follows
o Step1: Reads source file containi9ng assembly language program
Reads instruction and identifies operation symbols, registers, instruction label.
Assigns approx. opcode for instruction symbol from corresponding opcode table
Finds meaning of registers by referring corresponding reference table
o Step2: Creates a symbol table containing name and corresponding address
o Step3: Builds program text and data segment
o Step4: Forms a object file containing header, text, data and relocation information.
Relocation information: produced by assembler that contains the information for relocation of various
modules of same program and used by loader to relocate, link all modules with correct memory address
into one executable machine language program
Instruction location counter: determines relative position of instruction in machine language program
that gives numeric equivalent of instructions lable
Assembly language program
addi
sub
add
test: bne
addi
add
j
done: sw

Symbol
table

Fig.16.

$s0,$zero,9
$t0,$s0,$s0
$t1,$zero,$zero
$t0,$s0,done
$t0,$t0,1
$t1,$s0,$zero
test
$t1,result($gp)

done
result
test

28
248
12

Location

Machine language program

0
4
8
12
16
20
24
28

00100000000100000000000000001001
00000010000100000100000000100010
00000001001000000000000000100000
00010101000100000000000000001100
00100001000010000000000000000001
00000010000000000100100000100000
00001000000000000000000000000011
10101111100010010000000011111000
op
rs
rt
rd
sh
fn
Field boundaries shown to facilitate understanding

Determined from assembler

directives not shown here

An assembly-language program, its machine-language version, and the symbol table

created during the assembly process.

2.a.1 TYPES OF ASSEMBLER (1PASS AND 2 PASS)

Pass 1: Construction of symbol table in one go by (phase)

Symbol: is a string of characters that is used as an instruction label or a variable name.
Pass 2: Construction of symbol table in 2 phase
o Here in symbol table backward branching and forward branching is done.
Backward branching: if symbol location is already known, then its value is entered
Forward branching: if symbol location is unknown, then symbol alone will be entered
and location value is left blank
2.b. LINKER
Multiple program modules are linked by linker program
Linker determines memory location for each module that will occupy and relocates all address within
program to corresponding module.
Function of linker
Ensuring correct interpretation (resolution) of labels in all modules
Determining the placement of text and data segments in memory
Evaluating all data addresses and instruction labels.
Forming an executable program with no unresolved references.
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2.c.

LOADER
Transfers the program from secondary memory to main memory for execution
Function of loader
Determining the memory needs of the program from its header.
Copying text and data from the executable program file into memory.
Modifying / shifting addresses, where needed during copying.
Placing program parameters onto stack.
Initializing all machine registers, including stack pointer
Jumping to a startup routine that calls the main routine.
3.

ASSEMBLER DIRECTIVES:

(Refer section 7.2/page no. 126 in text book 1 by B.Parhami for more detailed description )

4.

Assembler directives provide assembler with information on how to translate the program but do not
lead to generation of corresponding machine instruction.
Assembler directives specify the layout of data in the programs data segment or define the variables
with symbolic names and desired initial values.
In MIPS, assembler directives begins with a period . To distinguish them from instruction.
.macro name(args)
# macro and arguments named
...
# instrs defining the macro
.end_macro
# macro terminator
.text beginning of programs text
.end end of segment
.data beginning of data segment

RUNNING ASSEMBLER PROGRAMS

(Refer section 7.6/page no. 133 in text book 1 by B.Parhami for more detailed description)

SPIM is a simulator that can run MiniMIPS programs

The name Spim comes from reversing MIPS
Three versions of Spim are available for free downloading:
PCSpim
for Windows machines
xspim
for X-windows
spim
for Unix systems

In below figure,
Register contents are shown in top panel
The programs text segment is shown in second panel with each line containing [hex memory
address], hex instruction content, opcode and parameters
The programs data segment is shown in third panel with each line containing a hex memory
address and conyents of 4 words (16 bytes) in hex format.
Message produced by SPIM are displayed in fourth panel

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PCSpim User Interface

Menu bar
Tools bar

PCSpim
File Simulator Window Help

File

Registers

Open
Sav e Log File
Ex it

Simulator
Clear Regis ters
Reinitializ e
Reload
Go
Break
Continue
Single Step
Multiple Step ...
Breakpoints ...
Set Value ...
Disp Symbol Table
Settings ...

Window
Tile
1 Messages
2 Tex t Segment
3 Data Segment
4 Regis ters
5 Console
Clear Console
Toolbar
Status bar

Status bar

PC
= 00400000
Status = 00000000
R0
R1

(r0) = 0
(at) = 0

EPC
= 00000000
Cause = 00000000
HI
= 00000000
LO
= 00000000
General Registers
R8 (t0) = 0
R16 (s0) = 0
R24
R9 (t1) = 0
R17 (s1) = 0
R25

Text Segment
[0x00400000]
[0x00400004]
[0x00400008]
[0x0040000c]
[0x00400010]

0x0c100008
0x00000021
0x2402000a
0x0000000c
0x00000021

jal 0x00400020 [main]

addu $0, $0, $0
addiu $2, $0, 10
syscall
addu $0, $0, $0

;
;
;
;
;

43
44
45
46
47

Data Segment
DATA
[0x10000000]
[0x10000010]
[0x10000020]

0x00000000 0x6c696146 0x20206465

0x676e6974 0x44444120 0x6554000a
0x44412067 0x000a4944 0x74736554

Messages
See the file README for a full copyright notice.
Memory and registers have been cleared, and the simulator rei
D:\temp\dos\TESTS\Alubare.s has been successfully loaded

For Help, press F1

Base=1; Pseudo=1, Mapped=1; LoadTrap=0

Input/Output Conventions for MiniMIPS:

Input/output and control functions of syscall in PCSpim

5. PSEUDO-INSTRUCTION AND MACRO-INSTRUCTION

(REFER II.6 AND II.7)

VI.

INSTRUCTION SET VARIATIONS

1. COMPLEX INSTRUCTIONS

MiniMIPS instruction performs relatively simple task such as single arithmetic / logic operations, copying of
basic data elements or transfer of control.
Defn.: a complex instruction is one that can potentially perform multiple memory accesses in course of its
execution
There is no standard definition for complex instruction.
Some instructions may be quite complex to describe and understand but easy to decode and excute
Dont confuse pseudoinstruction and macro instruction with complex instruction
Example:
o Chksum regd, reg1, reg2
Set regd to checksum (XOR) of all bytes in array whose start address is in reg1 and end
address is in reg2
Steps involved in chksum instruction
XORing the next byte to a running checksum
Incrementing a pointer
Comparing the pointer with end address
Repeating if the comparison is unequal.
o sortup reg1, reg2
Arrange the integer words in array whose start address is in reg1 and end address is in reg2.
Merits:
o Use of more complex instruction leads to shorter text (i.e., reduces number of lines in a program)
o Less memory requirements
o Programs may become easier to write/read/understand
o Fewer memory accesses for instructions
o Potentially faster execution (complex steps are still done sequentially in multiple cycles, but
hardware control can be faster than software loops)
Demerits:
o Mastering more number of complex instruction and its usuage in appox. places in quite challenging
o Complex instruction will be rarely used.
o Makes instruction set more complex
o More complex format (slower decoding)
o Less flexible (one algorithm for polynomial evaluation or sorting may not be the best in all cases)
o If interrupts are processed at the end of instruction cycle, machine may become less responsive to
time-critical events (interrupt handling)
Examples of complex instructions in two popular modern microprocessors and two computer families of
historical significance

Machine

Instruction

Effect

Pentium

MOVS

Move one element in a string of bytes, words, or doublewords using addresses

specified in two pointer registers; after the operation, increment or decrement the
registers to point to the next element of the string

PowerPC

cntlzd

Count the number of consecutive 0s in a specified source register beginning with

bit position 0 and place the count in a destination register

IBM 360-370

CS

Compare and swap: Compare the content of a register to that of a memory

location; if unequal, load the memory word into the register, else store the
content of a different register into the same memory location
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Digital VAX

POLYD

Polynomial evaluation with double flp arithmetic: Evaluate a polynomial in x,

with very high precision in intermediate results, using a coefficient table whose
location in memory is given within the instruction

2. ALTERNATIVE ADDRESSING MODES:

((Refer section 8.2/page no. 142, 143, 144 in text book 1 by B.Parhami for more detailed description))

The way in which the location of an operand is specified in an instruction.

A method used to specify where operands are to be found and where result must go.
To get the location of operand.

Alternative addressing modes as follows:

Addressing

Instruction

Other elements invol ved

Some place
in the machine

Implied

Extend,
if required

Immediate
Reg spec

Register

Constant offset

Base
Reg base

PC-relative

Reg f ile

Reg
data

PC

Reg data

Add

Mem
addr

Add

Mem
addr

Constant offset

PC

Pseudodirect

Reg f ile

Mem
Memory data

Mem
Memory data

Mem
addr Memory Mem
data

With 6 addressing modes already seen include 4 more addressing modes as follows
Indexed addresing
Update (with base) addresing
Update (with indexed) addresing
Indirect addresing

Operand

Addressing

Instruction

Other elements involved

Indexed

Reg file
Add

Index reg
Base reg
Increment amount

Update
(with base)

Base reg

Update
(with index ed)

Add

Base reg
Index reg

Mem
addr Memory Mem
data

Mem
Incre- addr
Mem
Memory data
ment

Reg file

Increment
amount

Indirect

Reg file

Operand

Mem
addr Memory Mem
data

Increment

PC

Mem data

Memory
Mem addr
This part maybe replaced w ith any
Mem addr,
other form of address specif ication
2nd access

Memory
Mem data,
2nd access

Fig.17. Addressing modes

3. VARIATIONS IN INSTRUCTION FORMAT

zero-address instruction syscall (control transfer)

o Zero-Address Architecture: Stack Machine
Stack holds all the operands (replaces our register file)
Load/Store operations become push/pop
Arithmetic/logic operations need only an opcode: they pop operand(s) from the top of the
stack and push the result onto the stack
Example: Evaluating the expression (a + b) (c d)

If a variable is used again, you may have to push it multiple times

Special instructions such as Duplicate and Swap are helpful

One address instruction-jump instructions

Syntax: j verify
where verify-holds the address of a procedure
o One-Address Architecture: Accumulator Machine
The accumulator, a special register attached to the ALU, always holds operand 1 and the
operation result. Only one operand needs to be specified by the instruction
Example: Evaluating the expression (a + b) (c d)
Load a
add
b
Store t
load c
subtract d
multiply t

Two address instructions -mult, div, addi

Syntax: mult $s0,$s1
o Two-Address Architectures
Two addresses may be used in different ways:
Operand1/result and operand 2
Condition to be checked and branch target address
Example: Evaluating the expression (a + b) (c d)
load $1,a
add
$1,b
load $2,c
subtract $2,d
multiply $1,$2

A variation is to use one of the addresses as in a one-address machine and the second one to
specify a branch in every instruction

Three address instructions add,sub,and,or

Syntax: add $t0, $s0,$s1

Category

Format

Opcode

Description of operand(s)
One implied operand in register $v0

0-address

1-address

2-address

0 rs rt

24 mult

Two source registers addressed, destination implied

3-address

0 rs rt rd

32 add

Destination and two source registers addressed

12 syscall
Address

Jump target addressed (in pseudodirect form)

Example 80x86 instructions ranging in width from 1 to 6 bytes; much wider instructions (up to 15 bytes) also
exist

Type

Format (field widths shown)

1-byte

5 3

2-byte

4 4

3-byte

4-byte

5-byte

4 3

6-byte

8
8

8
32

32

Opcode

Description of operand(s)

PUSH

3-bit register specification

JE

4-bit condition, 8-bit jump offset

MOV

8-bit register/mode, 8-bit offset

XOR

8-bit register/mode, 8-bit base/index,

8-bit offset

ADD

3-bit register spec, 32-bit immediate

TEST

8-bit register/mode, 32-bit immediate

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Instruction format and hardware structure for URISC.

Ultimate reduced instruction set computer (URISC):
Assembly language form:
label: urisc dest,src1,target # subtract source1 from source2, replace source2 with the result, and
jump to target address if result is negative

URISC instruction:

Word 1

Word 2

Word 3

Source 1

Source 2 / Dest

Jump target

Com p
C in

PC in

MDR in

MAR in

Read

P
C

Adder
N in

R in

Write

M
D
R

M
A
R

Z in
N

1 Mux 0

Memory
unit

PCout

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