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Articles
A Data Base for Real-Time Applications and Environments, by Feyzi Fatehi, Cynthia
Givens, Le T. Hong, Michael P. Light, Ching-Chao Liu, and Michael J. Wright
26
32
Editor, Richard P. Dolan Associate Editor, Charles L. Leath Assistant Editor, Hans A. Toepfer Art Director, Photographer, Arvid A. Danielson
Support European Susan E Wright Administrative Services, Typography, Anne S. LoPresti European Production Supervisor, Sonja Wirth
Research Reports
69
79
Departments
4
5
5
65
78
In this Issue
Cover
What's Ahead
Authors
Correction
The Hewlett-Packard Journal is published bimonthly by the Hewlett-Packard Company to recognize technical contributions made by Hewlett-Packard (HP) personnel. While
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In this Issue
Computer programs for data base management usually use magnetic disc
as their primary data storage medium and enforce rigid protocols to guarantee
data consistency and integrity. While these are highly desirable features for
most applications, they are not without cost. If many transactions occur in
a short slow, the system's response to an individual transaction may be slow,
or even worse, unpredictable. This isn't acceptable for real-time applica
tions Base, high-speed production lines, for example. HP Real-Time Data Base,
1_ k."XkL' a data base rnana9ement system for real-time applications running on HP
^^^^ 9000 Series 300 and 800 Computers, is designed for predictable response
time and data speed. It's a memory-resident system, using main memory as its primary data
storage performance. and it allows the user to disable unnecessary features to increase performance.
Tests Real-Time shown that using direct access (one of three methods), HP Real-Time Data Base can
retrieve the at a rate of 66,666 56-byte records per second. The article on page 6 describes the
design its this system and tells how choosing the right design alternatives led to its high perfor
mance.
As long and you know how they were measured, MIPS (millions of instructions per second) and
MFLOPS measures of floating-point operations per second) can be useful measures of the relative
performance of computer system processing units (SPUs). The new SPU for HP 9000 Model 835
technical computers and HP 3000 Series 935 commercial computers has been tested at 14 MIPS
and 2.02 MFLOPS running particular benchmark programs (see the footnote on page 19). This
represents more than a 300% increase in floating-point performance and more than a 50%
increase in integer performance over this SPU's predecessor, the Model 825/Series 925 SPU.
Responsible for these increases are processor design improvements and a new floating-point
coprocessor, as explained in the article on page 18. A new 16M-byte memory board was also
designed and is manufactured using an advanced double-sided surface mount process, described
on page 23.
Half-inch reel-to-reel tape drives are widely used for backing up large disc memories in computer
systems. Desirable characteristics are high speed for minimum backup time and large reel capacity
so that fewer reels have to be handled and stored. The HP 7890XC Tape Drive uses a sophisticated
data compression scheme to increase reel capacity, as explained in the article on page 26. It
also deal its complementary technique called super-blocking to deal with certain features of its
industry-standard 6250 GCR tape format that tend to limit the capacity improvement possible with
data compression alone. Super-blocking is explained in the article on page 32. Using both data
compression and super-blocking, the HP 7980XC has achieved capacity improvements of 2.5 to
5 times, depending on the data.
High-speed fiber optic communications systems are made up of four basic types of components.
For example, there are amplifiers, which have electrical inputs and electrical outputs, laser diodes,
which which electrical inputs and optical (light) outputs, photodiodes, which have optical inputs
and electrical outputs, and optical fibers, which have optical inputs and optical outputs. Accurate
measurements of the transmission and reflection characteristics of all of these device types,
needed 8702A both component designers and system designers, are provided by HP 8702A Lightwave
Component Analyzer systems. Each system consists of a lightwave source, a lightwave receiver,
the HP coupler. analyzer, and for reflection measurements, a lightwave coupler. In the article on
page 35, you'll find a description of these systems and a comprehensive treatment of their
applications and performance. The design of the lightwave sources and receivers is presented
in the capabilities on page 52. A comparison of the reflection measurement capabilities of the HP
8702A 1988) the HP 8145A Optical Time-Domain Reflectometer (December 1988) appears on
page 43.
Videoscope. the subject of the article on page 58, is a combination of hardware and software
that automates the testing of application software for HP Vectra Personal Computers. While a
test is being run manually, Videoscope records the human tester's keystrokes and mouse move
ments, being with the human tester's approval, the correct responses of the application being tested.
It can then rerun the test automatically. Unlike other similar testers, Videoscope doesn't affect
the performance or behavior of the application being tested. The key to this difference is the
hardware, a plug-in card that nonintrusively monitors the video signal of the system running the
application being tested and, for each screen, develops a single-number representation called a
signature. Signature analysis isn't new, having been used for many years for troubleshooting
digital the but its adaptation to software testing is an ingenious and elegant solution to the
problem of capturing screens. (Videoscope is an in-house HP tool, not a product.)
A lot simulate brain's has been based on the conjecture that if we could simulate the human brain's
basic elements neurons on a computer, we could connect a bunch of them in a network, and
we might brain able to solve some of the problems that regular computers find difficult but the brain
handles with ease. This approach has met with some success, particularly with certain optimization
problems. The theory of neural networks is expressed in differential equations, and its application
to practical problems is not intuitive. Seeking and not finding a simpler, higher-level method of
determining the right neuron interconnections, gains, and component values to solve a given
problem, Barry Shackleford of HP Laboratories developed one. In the paper on page 69, he
explains traveling approach and applies it to several classic optimization problems such as the traveling
salesman problem and the eight queens problem.
While we usually think of metal as something very stable, engineers and physicists who deal
with density circuit chips know that a high enough current density in a thin metal film will cause
the metal atoms to move. Over long periods of time, the metal piles up in some places and leaves
holes in other places, causing chip failures. Although electromigration has been studied extensively,
we still don't have a complete mathematical theory for it. The paper on page 79 reports on a new
two-dimensional mathematical model that makes it possible to simulate electromigration with good
accuracy on a computer using exclusively classical physics, not quantum mechanics. The model
was developed jointly by scientists at HP Laboratories and the California State University at San
Jose.
R.P. Dolan
Editor
Cover
One of the potential application areas for the HP Real-Time Data Base is in computer integrated
manufacturing, where data such as the status of each station on a manufacturing line can be
monitored in real time for quality control purposes. The picture shows a veterinary bolus (large
pill) ALZA line at the ALZA Corporation in Palo Alto, California. ALZA Corporation researches,
develops, and manufactures, and markets drug delivery systems. ALZA Director of Quality Assur
ance Carol L. Hartstein is shown in the inset photo with a simulated monitor screen. Our thanks
to ALZA Corporation for helping us illustrate this application.
What's Ahead
In the August issue we'll bring you the designers' view of the HP NewWave environment, HP's
state-of-the art user interface for personal computers. The evolution of an existing quarter-inch
tape drive into the HP 9145A with twice the speed and twice the cartridge capacity will also be
featured.
Query C Application
Programmatic Calls
(HP RTDB Routines)
Real-Time
Data Base
Column
Tupfe
Data Definition
Functions
m^^tm
Session Begin
and End
Functions
Data
Manipulation
Functions
Utility
Functions
^H
Internal
Data Base
Routines
System Table
Manager
Storage
Manager
Index
Manager
Operating System
Interface
Concurrency
Manager
Shared Memory
Schema and Control
Data Structures
Session
Control Blocks
Main Control
Block
User Area
Indexes on
User Tables
Structural Information
(Data Offsets, Capacities, etc.]
Slot Array
(One Entry
Per Tuple)
Column Descriptor
Array (One Entry
Per Tuple Column)
Data Array
(nn Tuples
Per Table)
System Table
(Table System Table)
Tuple Describing
User Table A
Tuple Data
T a b l e
C o l u m n 3
(Offsets
Column 1 Column 2 in Bytes)
Input Area
(Start at Offset 100)
Column Descriptor
Array
10 2E-02 XY_D
20 3E-02 AB C
5E-02 OR M
User Data
4 10E-02 YZ A
2 4
2 8
1
3 6
2
Byte Address
3
Column Number
Tuple 17
Usrtbl02
Index Table
for Usrtbi02
Index Table
h2
Fig. table A user table with indexes defined on it. The index system table contains the numbers
of the columns in the user table that make up the key values for index tables M and h2.
Index Table
Length Identifiers
User Table
Primary
Segment
Secondary
Segment
MdUpTpl I (SessID.
Session
Control
Block
newly defined data base objects until the data base is built.
The user can at any time save a copy of the current memoryresident schema to the configuration file. When the data
base is fully operational and contains data, the data as well
as the schema can be saved in the same file.
Building a Data Base in Memory. Once the system limits
of the data base are set and the schema defined, the data
base can be built. First, the schema must be loaded into
memory. The schema will already be in memory if the data
base is newly defined. Otherwise, the schema file on disc
is opened and loaded into memory (MdOpenDb). Using the
memory-resident schema data, the HP RTDB build routine
(MdBuildDb) allocates shared memory to each data base ob
ject, builds and initializes any data or control structures
associated with the objects, and sets up the logical links
between the structures. HP RTDB also provides routines
to calculate the minimum memory needed to build the data
base from the schema. Additional memory may optionally
be allocated to allow for future implementation of data
base objects that are not yet defined in the schema. After
a data base is built, it is ready to be initialized with appli
cation data.
Locking and Concurrency Control
The authors wish to thank Marie-Anne Neimat, MingChien Shan, and Bob Price for their assistance in the design
of RTDB, and Mark Butler for his direction in the creation
of RTDB.
Processor Board
The Model 835/Series 935 processor board reuses much
of the technology developed for the Model 825/Series 925,
a practice frequently called "leverage" within HP. Eight
VLSI integrated circuits make up the core of the processor
board: the CPU (central processing unit), the SIU (system
interface unit), two CCUs (cache controller units), the TCU
(TLB controller unit), the FPC (floating-point controller),
and two commercially available floating-point chips. Of
these, the CPU, SIU, TCU, and two CCUs are functionally
identical to those used in the Model 825/Series 925 proces
sor but run 20% faster. These parts were designed in HP's
NMOS-III VLSI process.2'3 The FPC and the floating-point
chips, new for the Model 835/Series 935 processor, will be
discussed later.
In addition to faster VLSI, a number of performance en
hancements over the Model 825/Series 925 processor board
are found on the Model 835/Series 935 processor board.
These include:
An eight-times-larger cache (128K bytes by 2 sets, unified
instructions and data).
A two-times-larger translation lookaside buffer or TLB
(2K instruction entries and 2K data entries). Since HP
Precision Architecture defines page sizes to be 2K bytes,
this allows 8M bytes of main memory to be mapped
directly into the TLB.
Processor Board
Nonvolatile Memory
Stable Store
Control Panel Interface
Real-Time Clock
PDC ROM
To I/O Expander (8 Slots)
Cache Bus
CTB (9 Slots)
Memory
(8M Bytes)
Memory
(16M Bytes)
Graphics
Interface
HP-IB LAN
I O Interface Cards ,
Fig. 3. unit. diagram of the Model 835/Series 935 system processing unit.
Floating-Point Coprocessor
The Model 825/Series 935 floating-point coprocessor
provides hardware assistance for floating-point math oper
ations and is implemented by a floating-point controller
(FPC) and two floating-point integrated circuits. One of the
floating-point ICs, the ALU, performs the addition, subtrac
tion, compare, and convert operations, and the other, the
MPY, performs the multiply, divide, and optional square
root operations. All floating-point operations can be either
single-precision or double-precision and fully support the
IEEE 754 floating-point standard.
The FPC, as the name implies, is the central control
circuit for the floating-point coprocessor. It interprets the
floating-point instructions and manages the flow of oper
ands and results to and from the floating-point chips. The
FPC contains twelve 64-bit floating-point registers, a status
register, seven operation-exception registers, and a config
uration register.
The FPC gets its floating-point instructions and operands
over the cache bus. Instructions come from the CPU, but
operands are read into the 12 floating-point registers di
rectly from the cache. Double-precision operands require
three cache bus cycles to transfer the data. The first cycle
transfers the floating-point load instruction and the next
two transfer the operand. Single-precision operands re
quire only two cache bus cycles. When a floating-point
operation is begun by the CPU, the operands are loaded
into the operation-exception registers from the floating
point registers to be forwarded to the floating-point chips
over the 64-bit math bus. Although the FPC has seven
operation-exception registers, it only uses the first two.
(The remaining five are for architectural compliance.)
These registers act as a queue for the operations and also
Circuit Design
GND
ing was done using vapor phase reflow, additional testing was
done to compare vapor phase and infrared reflow for solder joint
reliability. This was done by subjecting the boards to a predeter
mined there of destructive random vibration.3 In these tests, there
was no difference between single-sided and double-sided boards,
there were no failures in product testing of the 16M-byte memory
board on production prototype and pilot run boards, and infrared
was statistically better than vapor phase reflow.
Summary
As a result of the dual-reflow process, component packing
density has been increased to about twice the single-sided sur
face mount density, with ICs as large as 44-pin PLCCs being
reliably placed on the bottom side. Process and product strife
testing has shown no difference in reliability from single-sided
surface mount technology. Since the surface mount process has
been changed very little from the single-sided process, the pro
cessing cost of a double-sided board is less than that of two
single-sided assemblies because some of the processes are
only done once (e.g., clean, depanel, test, etc.).
Acknowledgments
I would like to extend appreciation and recognize the following
individuals for their contributions to the design and implementa
tion of the SMT-2 process: Jim Baker, Mai Chow, Conrad Taysom,
and Keith Walden.
Andy Vogen
Project Manager
Surface Mount Development Center
References
1. D.W. Mass Double-Sided Surface Attachment: A Guide to What Component Mass
Molten Solder Will Support. Internal HP Paper, March 9, 1987.
2. M Rupert, "Design Characteristics of a Surface Mount Compatible Through-Hole
Connector," SMTA Expo, Las Vegas, Nevada. October 16-29, 1987.
3. C. Testing Report on the Results of the IR Retlow Acceptance Testing Using F-16
Double-Sided Boards. Internal HP Paper, October 14, 1988.
16M-Byte Memory
The design challenge for the 16M-byte memory board
shown in Fig. 4 was to double the capacity of the already
dense memory subsystem in a fixed volume with a minimal
increase in power consumption. That challenge has been
met by packaging 144 IM-bit DRAM chips, one 272-pin
PGA VLSI memory controller, one 100-pin connector, vari
ous control and buffering logic chips, and the necessary
bypass capacitors on a 6. 75-by-7. 25-inch printed circuit
board (roughly half the size of this page).
To allow interchangeability, the 16M-byte memory board
is the same size as the current 8M-byte memory board.1
Increasing the memory to 16M bytes requires an extra 72
DRAMs and their bypass capacitors on the bottom side of
the board. The bottom-side mounting of the DRAMs, which
are packaged in 0.300-inch SMT packages, required the
development of a new double-sided surface mount man
ufacturing process (SMT-2) and a new approach to printed
circuit board design and verification. For details, see "DoubleSided Surface Mount Process" on page 23.
The circuitry of the 8M-byte memory board released with
the Model 825/Series 925 was designed to allow future
expansion to 16M bytes with only minor modifications.
Slight modifications were made to allow either 8M or 16M
bytes to be loaded at the factory using the same board. The
8M-byte version simply omits the bottom-side DRAMs and
bypass capacitors. The NMOS-III VLSI memory controller
was designed to support 2M, 4M, 8M, or 16M bytes, includ
ing single-bit error correction, double-bit error detection,
and support for battery backup of the memory contents in
case of main power failure.
Buffer
Host
Data
Drive Unit
The first eight entries are reserved codewords that are used
to flag and control specific conditions. The next 256 entries
contain the byte values 0 through 255. The remaining loca
tions are linked-list entries that point to other dictionary
locations and eventually terminate by pointing at one of
the byte values 0 through 255. Using this linked-list data
structure, the possible byte combinations can be anywhere
from 2 bytes to 128 bytes long without requiring an exces
sively wide memory array to store them.
In the hardware implementation of the HP-DC scheme,
the dictionary is built and stored in a bank of random-access
memory (RAM) that is 23 bits wide. Each memory address
can contain a byte value in the lower 8 bits, a codeword
or pointer representing an entry in the next 12 bits, and
three condition flags in the upper 3 bits. The codewords
range in length from 9 bits to 12 bits and correspond to
dictionary entries that range from 0 to 4095. During the
dictionary building phase, the first 512 entries have 9-bit
codewords, the next 512 entries have 10-bit codewords,
the next 1024 entries have 11-bit codewords, and the final
2048 entries have 12-bit codewords. Once the dictionary
is full, no further entries are built, and all subsequent
codewords are 12 bits in length. The memory address for
a given dictionary entry is determined by a complex oper
ation performed on the entry value. Since the dictionary
can contain 4096 entries, it would appear that 4K bytes of
RAM is all that is needed to support a full dictionary.
However, in practice, more than 4K bytes of RAM is needed
because of dictionary "collisions" that occur during the
dictionary building phase. When a dictionary collision oc
curs, the two colliding values are recalculated to two new
locations and the original location is flagged as a collision
site.
An important property of the algorithm is the coupling
between compression and decompression. In the HP-DC
1C, these two operations are tied together both in the com
pression and decompression processes and in the packing
Input
Byte
Stream
Search
for
Longest
Match
Build
Dictionary
Entry
Output
Codeword
Stream
Match
Code (R) Code (I) Code(N) Code(T) Code (IN) Code (Tl) Code(N)
No Match
Input
Codeword
Stream
Look Up
Associated
Characters
Code(R) | Code (I) Code (N) Code (T) j Code (IN) \ Code (TI) j Code (N)
* * *
Build
Dictionary
Entry
Output
Byte
Stream
current_codeword := GETJNPUT_CODEWORD;
REPEAT
codeword := current_codeword;
REPEAT
byte := LOOKUP_DICTIONARY(codeword);
PLACE_BYTE_ON_OUTPUT_STACK(byte) ;
FIND_NEXT_ENTRY_IN_LIST(codeword,pointer_to_next_
entry);
codeword := pointer_to_next_entry;
UNTIL (codeword points to tail of list one of bytes 0-255);
BUILD_DICTIONARY(previous_codeword,byte);
REPEAT
output_byte := POP_ BYTE_FROM_OUTPUT_STACK;
OUTPUT_BYTE(output_byte) ;
UNTIL (stack is empty);
previous_codeword := current_codeword;
current_codeword := GET_INPUT_ CODEWORD;
UNTIL (no more input codewords to decompress);
Microprocessor Bus
Compression/Decompression
Converter
Acknowledgments
Data Description
MPE/MPE XL on HP 3000s
Series 68 (HP Desk)
Series 68 (Data Base)
Series 68 (Misc. Data)
Series 70 (Manufacturing)
Series 930 (Code)
HP-UX on HP 9000s
Series 800 (Commercial
HP-UX)
Series 500 (Code)
Series 500 (Data Base)
Series 500 (VLSI)
Series 300 (Archive)
DEC
DEC VAX (Code)
Volume Compression
(Mbytes) Ratio
311
3.93
4.31
4.30
4.31
3.44
226
2.06
363
329
2.38
4.07
2.52
2.30
423
2.31
467
2.47
5000
3.79
528
2924
1559
2924
336
785
HP 9000 Running
Pascal O.S.
Series 200 (Misc. Data)
Amdahl
Amdahl (HP Corporate
Data)
Record Record
# 5
# 6
Condition
Tape Capacity
(16K-Byte Input Records)
(M Bytes)
180 -r
Xo Data Compression or
Super-Blocking
Super-Blocking Only
4:1 Data Compression
Only
4:1 Data Compression and
Super-Blocking
Tape
Compaction
154
1.00:1
166
471
1.08:1
3.06:1
666
4.32:1
1 0
2 0
4 0
Complications
6 0
ever, this is not the case, since only the physical record
size is reduced in proportion to the compression ratio.
Thus the original 16K-byte records are indeed 4K bytes
long after compression, but the expected 616M-byte tape
capacity is only 471M bytes, which is 24% less. It is to
prevent this effective loss of capacity that super-blocking
is needed.
Using the example of 16K-byte records compressed to
4K-byte records, the effect of super-blocking can readily
be seen. The compressed 4K-byte records are super-blocked
and packed into 60K-byte records instead of being written
directly to the tape. This results in a tape capacity of 666M
bytes instead of 471M bytes. This is a capacity improve
ment of approximately 41.5%. By combining data compres
sion with super-blocking, the limitations that the half-inch
tape format imposes on data compression are overcome.
In addition to obtaining the full benefit of data compres
sion, super-blocking further improves the tape capacity.
The table below demonstrates how super-blocking affects
this example:
# 1
# 2
# 3
# 4
# 5
# 6
# 7
# 8
# 9
# 1 0
# 1 1
# 1 2
# 1 3
# 1 4
# 1 5
I B
# 1 6
# 1 7
# 1 8
# 1 9
# 2 0
# 2 1
# 2 2
# 2 3
# 2 4
# 2 5
Format Information'^^
Super-Blocked Records Size: 60K Bytes
MPE/MPE XL on HP 3000s
Series 68 (HP Desk) 528 3.93
Series 68 (Data Base) 2924 4.31
Series 68 (Misc. Data) 1559 4.30
Series 70
( M a n u f a c t u r i n g ) 2 9 2 4 4 . 3 1
S e r i e s 9 3 0 ( C o d e ) 3 1 1 3 . 4 4
4.35
4.83
5.04
4 . 8 3
3 . 9 7
HP-UX on HP 9000s
S e r i e s
8 0 0
2 2 6
2 . 0 6
2
(Commercial HP-UX)
S e r i e s 5 0 0 ( C o d e ) 3 6 3 2 . 3 8
Series 500 (Data Base) 336 4.07
S e r i e s 5 0 0 ( V L S I ) 7 8 5 2 . 5 2
Series 300 (Archive) 329 2.30
2 . 5 7
4.39
3 . 3 4
3.05
DEC
D E C
2 . 6 5
V A X
( C o d e )
4 2 3
2 . 3 1
. 7 3
2.8-1-
1.0
2
4
6
8
1 0
2 0
Average Host Data Record Size (K Bytes)
60
Information
Source
Laser
Modulation
Signal
Conditioning
Preamplifier
Digital or
Analog
Carrier
Optical Fiber
Photodiode
Receiver
(Demodulation)
Information
Recipient
Signal
Conditioning
I X I Postamplifier
Digital or
Analog
1 Carrier
Electrical mismatch
may limit sensitivity
at high speeds.
Laser sensitive
to reflections.
Diode bias
directly affects
bandwidth.
Fiber
may limit
bandwidth.
Fiber bulkheads,
connectors, and splices
reduce optical power.
Amplifier bandwidth
and flatness may
limit system speed.
Table I
Types of Lightwave Devices
Electrical
(RF)
Output
Electrical
(RF)
Input
Optical
(Modulated)
Input
Optical
(Modulated)
Output
Electrical-to-Electrical Electrical-to-Optical
Devices
Devices
i Laser Diodes and
i Amplifiers
LEDs
i Coaxial Cables and
i Optical Sources
Passive Components
i Optical Modulators
I Repeater Links
Optical-to-Electrical Optical-to-Optical
D e v i c e s D e v i c e s
RF
Out
Phase-Locked Loop
300-kHz-to3-GHz
Source
Output
Same as Input R
Same as Input R
Fig. hardware essentially 8702A Lightwave Component Analyzer block diagram. The hardware is essentially
the same as the HP 8753B RF Network Analyzer.
path.
Sweep-to-sweep averaging is another noise reduction
technique. This involves taking the complex exponential
average of several consecutive sweeps weighted by a userspecified averaging factor. Each new sweep is averaged
with the previous result until the number of sweeps equals
the averaging factor. Doubling the averaging factor reduces
the noise by 3 dB. This technique can only be used with
ratio measurements.
The raw data arrays store the results of all of the preced
ing data processing operations. All processing up to this
point is performed in real time by the fast digital signal
processor shown in Fig. 5. The remaining operations are
performed asynchronously by the main processor. These
arrays can be stored to an external disc drive and can be
accessed directly via the HP-IB (IEEE 488, IEC 625).
Vector error correction is performed next, if a measurment calibration has been performed and correction is
turned on. Error correction removes repeatable systematic
errors (stored in the error coefficient arrays) from the raw
arrays. This can vary from simple vector normalization to
full the (12-term) error correction. Correction for the
various types of lightwave measurements is described in
more detail below.
The results of error correction are stored in the data arrays
as complex number pairs. The data arrays can be stored to
disc and accessed via the HP-IB. If the data-to-memory
operation is performed, the data arrays are copied into
the memory arrays. The memory array is also externally
accessible.
The trace math operation selects either the data array,
the memory array, or both to continue flowing through the
data processing path. In addition, the complex ratio of the
two (data/memory) or the difference (data - memory) can
also be selected. If memory is displayed, the data from the
memory arrays goes through the same data processing flow
\f
Signals
Sampler/IF
Correction
Sweep/Sweep
Averaging
Raw Data
Arrays
Error
Correction
Error
Coefficient
Array
-> Markers
-> Limit Testing
Fig. flow diagram. 8702A Lightwave Component Analyzer data processing flow diagram.
tions, and limit testing are all derived from the format
arrays. The format arrays can be stored to an external disc
drive and can be accessed via the HP-IB.
The offset and scale operations prepare the formatted
data for display on the CRT. This is where the reference
line position, reference line value, and scale calculations
are performed as appropriate to the format and graticule
type.
The display memory stores the display image for presen
tation on the CRT. The information here includes grati
cules, annotation, and softkey labels in a form similar to
plotter commands. When hard-copy records are made, the
information sent to the plotter or printer is taken from
display memory.
The HP 8702A can be connected with an s-parameter
test set (HP 85046A) to make electrical reflection measure
ments, such as s-parameters s11 and s22 (return loss and
impedance). An HP 85047A S-Parameter Test Set can be
used to measure modulation transfer function to 6 GHz.
Firmware Features
PARAMETER
RESOLUTION
TRANSFORM SPAN
RANGE RESOLUTION
TRANSFORM MODE
START FREQUENCY
STOP FREQUENCY
FREQUENCY SPAN
NUMBER of POINTS
INDEX Of REFRACTION
PULSE WIDTH
SOURCE POWER
SWEEP TIME
IF BANDWIDTH
Channel 1
1 3 . B9 O 5 m
133.79 mm
40 ns
41 . OB7 mm
BANDPASS
300 kHz
3 GHz
2.9997 GHz
201
1.4B
651.55 ps
0 dBm
BOO ms
300O Hz
Lightwave
Receiver
Information
Source
Information
Receiver
Signal
Processing
f(t) = a(t)cos(o)t)
where a(t) is the RF modulation signal and cos(o)t) repre
sents the lightwave carrier signal at a given wavelength.
The device under test operates on the amplitude of both
the modulation envelope and the carrier signal identically
and delays both signals by identical amounts, yielding the
following relationship for the DUT output:
g(t) = |H|a(t + At)cos(w(t + At)),
where |H| is the magnitude of the transfer function of the
DUT, At = (f>/(a, and </> is the phase of H.
The impact of the DUT on the carrier can be determined
by measuring the modulation envelope. Basically, the mea
surement process consists of two steps: (1) calibration of
the system, and (2) measurement of the DUT. This measure
ment process is essentially a substitution method. The sys
tem is calibrated by measuring a known quantity and then
the DUT is substituted for the known device and measured .
Electrical-toOptical
Device
(2)
(1)
(3)
Optical-toElectrical
Device
Slope (r,)
= Responsivity
(AW)
APr
HP 8702A Lightwave
Component Analyzer
C H I
CH2
log
S T A R T
B/R
1 . 8 7 2
MAG
MAG
lln
For Calibration
6 5 9
50
M H z
mU/
S T O P
REF
OU
4 9 9 . 9 9 9
-.
B 5 9
M H z
350.91
mU
STOP 1 . B dBm
i. -9.2891 dB
STOP
light. The reflected light can couple back into the laser's
cavity, be reamplified, and change the laser's modulation
transfer characteristics. The fine-grain ripple that often re
sults is called reflection noise. Fig. 13 shows the measure
ment setup to characterize the change in the laser's modula
tion transfer function and bandwidth when different levels
of light are intentionally reflected back into the laser.
The directional coupler test port (point A) is where the
reflected light condition is developed. The modulation fre
quency response is referenced to a condition in which no
incident light at point A is reflected back toward the laser
under test, that is, an optical load is created at point A.
This reference condition is normalized to 0 dB. When the
reflection condition is changed, the resulting measurement
shows the deviation or change of the laser's modulation
response for that reflection condition (a laser reflection
sensitivity measurement). An example of such a measure
ment of a commercially available laser transmitter is shown
in Fig. 14. The worst response represents the condition
when approximately 95% of the light was reflected back
to the laser under test. The improved response was
achieved when a polarization controller was inserted be
tween the test port and the 95% optical reflector and the
polarization of the reflected light was adjusted to minimize
the response roll-off.
1 . 8 dBm
HP 8702A Lightwave
Component Analyzer
Photodiode Measurements
The loss, gain, and modulation bandwidth of any twoport optical device can be measured using the measurement
block diagram shown in Fig. 16. Examples of such devices
are optical connectors, attenuators, other passive optical
Polarization
Controller
OTDR
(HP8145A)
Yes
Measures loss
versus distance (dB/km) No Yes
(backscatter)
Measures splice loss and No Yes
breaks in fiber
Measures magnitudes and
p o s i t i o n s
o f
optical reflections
Y e s
Y e s
z o n e
N o n e
T e n s
o f
m e t e r s
( 1 )
o u t
u n w a n t e d
Y e s
N o
(1) Dead zone depends upon pulse width used in the measure
ment.
(2) Assumes that the index of refraction is known accurately and
does not limit the measurement accuracy.
(3) Theoretical limit. Assumes a 3-GHz frequency span. 6 cm
observed empirically in a nonoptimized experiment.
(4) Theoretical limit. Assumes a 6-GHz frequency span. 2.5 cm
observed empirically in a nonoptimized experiment.
1 dB/ REF O
HP 8702A Lightwave
Component Analyzer
For Calibration
CHI START
and optical components. The HP 8702A system is wellsuited to perform optical reflection and length measure
ments on a wide variety of components and subsystems.
Fig. 18 shows the block diagram for measuring optical
reflections and optical return loss of any optical device
under test. If a device has more than a single reflection,
for example reflections of varying magnitudes spaced out
at different distances in the device, the HP 8702A test sys
tem can measure the total reflection or each constituent
reflection and its respective location. This system can be
used to measure reflections of fiber optic components or
bulk optic components when the proper collimating optics
are added to the lightwave coupler test port in the test
system.
If there are two or more reflections in the device under
test, the individual reflections will have different phase
relationships with respect to the measurement reference
plane at a fixed modulation frequency that will sum to a
given modulation amplitude and phase. As the modulation
10 dB/ REF O dE
C o r
0 dB
O / O
10 dB
HP 8702A Lightwave
Component Analyzer
20 dB
30 dB
40 dB
50 dB (Ave = 16)
For Calibration
Optical-toElectrical
Device
60 dB
(Ave = 16)
Noise Floor
. 300 000 MHz
HP 8702A Lightwave
Component Analyzer
0.9 m
From
Optical
Coupler
Collimating
Lens
Rereflection
Path (Marker #4)
(Gold)
Metallized
Wafer
.5 dB/ REF 0 dB
CI
O
CH2 START 35 ns
S T O P
S T A R T
6 0
n s
Fig. 20. (top) A glass fiber with three internal mirrors produc
ing 2% reflections, (bottom) A measurement of the three re
flections and their locations. (Fiber internal mirrors courtesy
of Texas A&M University EE Department.)
C l
CHI
CH2
C H I
STOP 45 ns
CHI
B/R
log
MAG
10
OB/
REF
CHI START-5 ns
C H I
S T A R T
S T O P
. 5
n s
Polarization 20 x
Preserving Lens
2.5 T-
HP 8702A Lightwave
Component Analyzer
0.5 --
0.3
500
2500
3000
SELECT TYPE
OF MEASUREMENT
BANDWIDTH
BANDWIDTH
REFLECTION
BAIN
COMPRESS'S
CONFIGURE MEASUREMENT
AS SHOWN BELOW
MAKE NECESSARY
DC CONNECTIONS
REFLECTION
> REFLECTED
INCIDENT
REFLECTION versus FREQUENCY
GAIN
CONTINUE
CONTINUE
COMPRESSION
NORMAL
OPERATION
-ELECTRICAL
A photodiode receiver with 0.32 A/W or - 10 dB responsivity, -14 dB of optical input mismatch, and -14 dB of
electrical mismatch was measured by the system shown in
Fig. 24. The responsivity of the receiver can be read from
the CRT in dB for any given modulation frequency.
The uncertainties considered while computing the accu
racy of the measurement are as follows: optical match in
teraction of the lightwave source and receiver, optical
match interaction of the lightwave source and DUT, electri
cal match interaction of the lightwave receiver and the HP
8702A analyzer input, the same uncertainty for the DUT
and the HP 8702A analyzer input, reflection sensitivity of
the lightwave laser, dynamic accuracy, lightwave receiver
accuracy, lightwave receiver model uncertainty, and wave
length related uncertainty.
Fig. 25 shows the uncertainty (dB) of the receiver respon
sivity measurement (described above) over an RF modula
tion frequency range of 300 kHz to 3 GHz. The solid lines
represent the maximum and minimum values for the con
figuration shown in Fig. 24. The dashed line represents
PRIOR
MENU
OPTICAL
B / R
I t J B
M A G
1 0
( F R O
SELECT TYPE OF
DEVICE UNDER TEST
R E F
d B
- T R A N S M I S S I C N
M O D :
C o r
0 / 0
DEVICE
UNDER
TEST OUTPUT:
INPUT:
d B /
O O f A I N )
A v a
I B
E/0
E/E
O P T I C A L
E L E C T R I C A L
ELECTRICAL
- =
E /
O /
3 > E L E C T H I C A L
- ^ - O P T I C A L
ELECTRICAL
PRIOR
MENU
Fig. 29. Noise floor trace for a 3-GHz system for optical trans
mission measurements.
l j
10 OS/ HEF 0 OB
10 as/ HEF o as
log HAG
SNOI5E FL IOP. (FREO C jMAIN REI LECTION MO E
- 3 8
7 8 3
d E
Cor
0/0
Cor
a/a
AVQ
16
rflp
C H I
S T A R T
. 3 0 0
0 0 0
M H z
Fig. 30. Noise f loor trace fora 3-GHz system for optical reflec
tion measurements in the frequency domain.
10 dB/ REF 0 dB
IME DOMAIN REF LECTION MO
B/R
log
MAG
NOISE FLOOR 6
Cor
0/0
Cor
Avg
16
AVB
16
10 dB/ REF 0 OB
Z SYE TEM-R TFLEC" ION NODE
O/O
r/
STOP 20 na
START
3.
OOO
OOO
MHZ
3-GHz 6-GHz
System System
Electrical [1] or Electrooptical [2]
(Frequency Domain)
100 dB 80 dB
Optical [3]
Transmission (Frequency Domain) 47 dB 37 dB
Reflection (Frequency Domain) 40 dB 27 dB
Reflection (Time Domain) 52 dB 38 dB
1. Electrical-to-electrical device:
dB = 10log(P2/P1) = 20log(V2A?1)
where: Pj = RF power available at port 1,
P2 = RF power available at port 2,
Va = RF voltage at port 1,
V2 = RF voltage at port 2
(50 1 impedance system).
2. Electrical-to-optical device:
dB = 20log((rs)/(lW/A))
where: rs = slope responsivity of the electrical-tooptical device.
Optical-to-electrical device:
dB = 20log((rr)/(lA/W))
where: rr = slope responsivity of the optical-toelectrical device.
3. Optical device:
dB =
where: Pl = optical power at port 1,
P2 = optical power at port 2.
log MAG
FUOOI I 6 Eh
Acknowledgments
10 OB/ HEF 0 OB
z SYSTEM-?! :FLEC
Car
O/O
AVQ
16
CHI START O s
STOP 6 ns
References
1. R. Wong, M. Hart, G. Conrad, and D. Olney, The Lightwave
Component Analyzer: High-Frequency Measurements of Light
wave Systems and Components, Hewlett-Packard Publication No.
5956-4356.
2. T.S. Tan, R.L. Jungerman, and S.S. Elliott, "Calibration of Op
tical Receivers and Modulators Using an Optical Heterodyne
Technique," IEEE Transaclions on Microwave Theory and Tech
niques, Vol. MTT-2, May 25, 1988, pp. 1067-1070.
3. W. Op "A High-Precision Optical Connector for Op
tical Test and Instrumentation," Hewlett-Packard Journal, Vol. 38,
no. 2, February 1987, pp. 28-30.
The signal path through each source starts at the rearpanel RF connector and proceeds through a matching cir
cuit, an RF attenuator. The attenuator output is transformed
into a modulated light signal by a laser diode. The optical
laser output signal is transmitted through a short piece of
optical fiber to the front-panel connector (see Fig. 1).
Power for the source is supplied from the probe power
jacks on the front panel of the HP 8702A. Bias current
requirements of the internal components exceed the 400
mA available from this 15V supply, so each source includes
RF
Input
RF Attenuator
Laser Module
105--
104--
O ^ Light
Fiber Output
T
Probe
Power
102
100
5
5
0
2
5
Junction Temperature (C)
Laser Module
Photodiode
Laser
Diode
Output
Front-Face. F "O *ber
Back-Facet
Light
Light
Control
Circuit
V-
to 3 GHz.
The source microcircuit package is a straightforward
deep-well design. The laser package is retained in the mi
crocircuit package by two wedging clamps which force it
against x-axis and y-axis datum surfaces while keeping its
bottom surface pressed against the housing floor. This ap
proach was chosen to locate the laser precisely relative to
the sapphire microcircuit while ensuring adequate heat
sinking for the laser's internal thermoelectric heat pump.
The thin-film microstrip circuit provides the RF interface
between an SMA connector and the RF terminals of the
laser package. An epoxy-glass printed circuit board inter
connects the dc terminals of the laser with the filtered
feedthroughs of the microcircuit package (Fig. 7).
Receiver Design and Operation
The signal path through the receiver starts at the frontpanel optical connector (see Fig. 8). Once the modulated
optical signal is inside the receiver module, it travels
through a short input fiber to the optical launch, where it
is coupled to a pin photodiode chip. The output of the
photodiode is an alternating current at the same frequency
as the modulation. This signal is amplified by a transimpedance amplifier. The output of the amplifier is routed to the
back panel of the receiver by a short length of coaxial cable.
While simple in concept, the optical launch is difficult
70 kHz
Integrator
Laser Module
DC-to-DC
Converter
Temperature
Sensor
Current Flow:
Thermoelectric
Heat Pump
Laser Package
DC Terminals
RF Terminals
Printed
Circuit
Board
Thin-Film
Circuit
D a t u m
S u r f a c e ' '
C l a m p
l,hr.s
RF Modulation
Impedance
Matching
Light
Input
Fiber
Optical
Launch
Photodiode
Probe
Power
Transimpedance
Amplifier
f
Fig. 6. Input circuit of the lightwave source.
RF
Output
HP 8702A Lightwave
Component Analyzer
RF
Fiber
X-Y Positioner
Receiver Microcircuit
Fig. 10. Alignment of the optical launch.
Anti reflection
Coating
Top Ohmic
Bottom Contact
Tester
Typical playback
situation is
fully automated
Videoscope
Keystrokes.
Pointer
Movements
Test
Script
Keyboard
Host System
r rest Data
Signatures
Test Script
Test Data
File
Signature
File
Video Signature
Analyzer (VSA)
Power
SUT Backplane
Video Sync
Clock
To SUT Video Adapter
Video
Data in
Clock clear-
>
Signature
Out
X = Bit Position
Wait for go
Assert clear and busy
Wait for active
active
Deassert clear
Wait for hsync
hsync
Assert run until
not active and hsync
I Deassert busy
hsync = Horizontal Sync
Fig. 2. Hardware state machine.
States
NMI ISR = State 2
Start Counter
State 0
If (start = 0%) then
Counter ISR = State A
NMI ISR = State 1
Set Counter = stop
Else
Counter ISR = State B
NMI ISR = State 3
Set Counter = start
State B
NMI ISR = State 2
Send active to HSM
H (stop f 100%) Then
Set Counter = stop
Counter ISR = State A
Start Counter
State 2
Send not active to HSM
Disable NMI
Set done = TRUE
Count = 0 Interrupt
vsync (NMI) Interrupt
HSM = Hardware State Machine
ISR = Interrupt Service Routine
State 1
NMI ISR = State 2
Send active to HSM
If (stop js 100%) Then
Start Counter
Main Code:
Take Signature Procedure
NMI ISR = State 0
Reset Hardware State Machine
Enable NMI to Start Firmware
State Machine
Send go to Hardware State Machine
Fig. 4. Program flow for the main code in the video signature
analyzer.
Conclusion
Authors
June 1989
Michael J. Wright
Cynthia Givens
Le T. Hong
6 Real-Time Data Base :
Michael R. Light
Mike Light joined HP in
1980, shortly after receiv
ing his BS degree in com
puter science from the Uni
versity of Vermont. He con
tributed to the development
of the HP RTDB product as
an R&D engineer, and his
1 past responsibilities inelude the Image/1000,
Image/1 000-2, and Image/UX environments. Mike
was born in Panama City, Florida, and lives in San
Jose, California. "Games in any form" is how he de
scribes his leisure interests.
Feyzi Fatehi
I Working on the HP RealTime Data Base for over
three years, Feyzi Fatehi
designed and implemented
the indexing mechanisms
and contributed to all
phases of developing this
precision tool. He came to
HP in 1 986, after working as
a plant automation en
gineer at a Texas power plant. Feyzi's BSME
degree (1982) is from the University of Texas at
Austin, and his master's degree in computer sci
ence ( 1 985) is from Southwest Texas State Univer
sity He's currently studying toward an MBA degree
at Santa Clara University. He was born in Teheran,
Iran, lives in Sunnyvale, California, and serves as
a Junior Achievement advisor at the nearby Moun
tain View High School. His favorite pastimes in
clude tennis, hiking, and skiing.
John Keller
Ching-Chao Liu
A software development
engineer at HP's Industrial
Applications Center,
Ching-Chao Liu contri
buted his expertise to all
phases of the RTDB pro__ - ject. In previous assign^ ments, he was the technical
leader of the HP ALLBASE
OK^. DBCORE project, the pro
ject leader for the HP-UX MULTIPLAN tool, and a
designer of other software projects. He came to HP
in 1980. Ching-Chao coauthored two papers for
data base conferences and is a member of the As
sociation for Computing Machinery and of SIGMOD. His BS degree in nuclear engineering is from
the National Tsing Hua University in Taiwan (1 972),
and his MS degree in computer science is from
Oregon State University (1979). He was born in
Taiwan, is married, and has two children who
sparked his special interest in child education. He
lives in Sunnyvale, California. In his leisure time, he
likes swimming, playing bridge, and listening to
classical music.
18
Midrange Computers 1
Thomas O. Meyer
Tom Meyer was the project
manager for the HP 9000
/
Model 835 SPU hardware.
m .W SinceheioinedHPin 1977,
his design projects have in
cluded a memory board for
the HP 250 Computer, a
power supply for the HP
9000 Model 520 Computer,
the battery backup reg
ulator for the HP 9000 Model 825 Computer, and
project management for the HP 9000 Model 825
and HP 3000 Series 925 Computers. Tom joined
HP in 1977, soon after obtaining his BSEE degree
from the South Dakota School of Mines. He has
coauthored two previous articles for the HP Jour
nal. He was born in Rapid City, South Dakota, and
lives in Fort Collins, Colorado. His list of outside
interests includes sailing and sailboat racing,
scuba diving, skiing, hiking, and four-wheel-drive
vehicles.
Jeffrey G. Hargis
Designing the processor^EtiB|^ dependent hardware and
ll ^m conducting environmental
testing of the HP 9000
W* n Model 835 were Jeff Har
gis' first major projects after
joining HP's Systems Tech
nology Division in 1 987. He
has since moved on to the
design of components for
new SPUs. He attended Ohio State University,
where he obtained a BSEE degree in 1 987. Jeff was
born in Athens, Ohio, and is married He lives in Fort
Collins, Colorado. He enjoys playing the piano,
basketball, and backpacking.
26
Data Compression ,
Jeffery J. Kato
During development of the
HP 7980XC Tape Drive,
Jeff Kato's contributions fo
cused on the architecture
and design implementation
for the data compression
chip and firmware design
He has also designed read
_^^ _^ electonicsfortheHP7978A
..jB ^ Tape Drive and the PLL and
PLL 1C for the HP 7980A Tape Drive. He came to
HP in 1982, the same year he received his BSEE
degree from Montana State University. He is
named as a coinventor in three pending patents
describing data compression and blocking tech
niques. Jeff has coauthored a previous article for
the HP Journal. He is an active member of his
church and a United Way volunteer. He was born
in Havre, Montana, is married, and lives in Greeley,
Colorado. Among his spare-time activities, he likes
skiing, basketball, Softball, and camping.
Floyd E. Moore
Floyd Moore designed the
1 6M-byte memory circuitry
for the HP 9000 Model 835
and worked on the design
and testing of the HP 3000
Series 935 system. He is
presently working on the
design of an SPU for a
future HP Precision
IF Architecture system. He
came to HP in 1986, working on a project
associated with the tape-automated bonding
technique. Floyd was born in Richmond, California.
His bachelor's degree is from the California
Polytechnic State University at San Luis Obispo.
He is married and lives in Fort Collins, Colorado.
His favorite pastimes are photography and audio
engineering.
Russell C. Brockmann
Most of Russ Brockmann's
recent design activities
have concentrated on the
processor circuit for the H P
9000 Model 835 and HP
3000 Series 935 Comput
ers. He also designed the
battery backup unit used in
the HP 9000 Models 825
and 835 and HP 3000
Series 925 and 935 Computers. He completed de
sign of the Model 825/Series 925 processor circuit.
Currently, he is developing components for future
SPUs. He joined HP shortly after obtaining his BSEE
degree from Oregon State University in 1985. He
also attended Western Baptist College in Salem
(1977-1979) and Lane Community College in
Eugene (1981-1983), both in Oregon. Russ
teaches Sunday school and serves in a variety of
other church activities in Fort Collins, Colorado,
where he lives. He was born in Myrtle Point, Ore
gon, is married, and has three children. Fishing,
camping, playing a 12-string guitar, and bible
study are some of his favorite pastimes.
Mark J. Bianchi
Analog circuit design and
control systems are Mark's
principal professional in~F; terests. He was the R&D
engineer for the design,
layout, and testing of the
data compression chip for
the HP 7980XC On previous projects, he designed
the read channel elec
tronics for the HP 9144A and HP 9142A Tape
Drives. Mark received his BSEE degree from
Pennsylvania State University in 1 984, the year he
also joined HP's Greeley Division. Born in Vineland,
New Jersey, he lives in Fort Collins, Colorado. His
list of leisure activities includes weightlifting,
Softball, volleyball, basketball, boardsailing, skiing,
camping, and photography.
32
Super-Blocking "
Mark J. Bianchi
Author's biography appears elsewhere in this
section
Jeffery J. Kato
Author's biography appears elsewhere in this
section.
Paul Hernday
Paul Hernday is an R&D
project manager in HP's
Network Measurements
Division in Santa Rosa,
California. With HP since
1 969, he has been involved
with new-product develop
ments in sweepers, scalar
and vector network analyz
ers, and lightwave compo-
Geraldine A. Conrad
As a development engineer
J? on the HP 8702A Lightwave
Component Analyzer.
9 Gerry Conrad worked on
measurement accuracy
and system performance
analysis. She continues to
be involved in similar de
velopments, more specifi
cally in microwave circuit
design and optical system evaluation. In earlier
years of her career at HP, she worked first as a
product marketing engineer and later joined a
design team on the HP 8753A Network Analyzer.
Gerry originally joined HP as a summer student in
1980, then accepted a permanent position two
years later Her BSEE degree is from the University
of Florida (1982). She has authored a paper
describing an RF network analyzer verification
technique and coauthored a symposium paper
about high-frequency measurement of lightwave
systems. She is a member of the IEEE. Born in Trincomalee, Sri Lanka, Gerry is married and lives in
Santa Rosa, California. Her leisure interests include
travel, quilting, camping, hiking, cooking, and
reading.
Roger W. Wong
Lightwave and microwave
measurement technologies
are Roger Wong's special
interests, and as the R&D
program manager, he car
ried overall responsibility
for the development of the
HP 8702A Lightwave Com
ponent Analyzer. Past re
sponsibilities included sca
lar network analyzer detectors, directional bridges
and accessories, and the development of microcircuits and associated components for microwave
applications. Roger joined the Microwave Division
of HP in 1 968, after obtaining his MSEE degree from
Columbia University. His BSEE degree is from Ore
gon State University (1 966). He is a member of the
IEEE and the National Society for Professional En
gineers. He has authored or coauthored a number
of papers and articles on microwave transistor
modeling, microwave amplifier design, and high
speed lightwave measurements. Several patents
describing lightwave measurement techniques
Roger developed are pending. He was born in
Honolulu, Hawaii, is married, and has a five-yearold son. He lives in Santa Rosa, California. His
favorite pastimes include swimming, hiking, cook
ing, and baking bread.
52
Kenneth W. Shaughnessy
The HP 8753A and the HP
8754A Vector Network
Analyzers and a number of
lightwave instruments are
among the major projects
to which Ken Shaughnessy
has contributed design
ideas. On the HP 8702A
Lightwave Component
Analyzer System, he
; as a product designer. He joined the Santa
Rosa (California) Division of HP in 1 975 as a printed
circuit board designer, after previous positions as
a mechanical designer at Sperry Marine Systems
and Teledyne Avionics. Ken attended the Univer
sity of Virginia School of Engineering. He was born
in Chicago, Illinois, is married, and has five chil
dren. He lives in Kenwood, California. Woodwork
ing and automobile and bicycle repair are his favor
ite spare-time activities.
Kent W. Leyde
In development of the HP
8702A Lightwave Compo
nent Analyzer, Kent
Leyde's design work con
centrated on microcircuits
and optics for the lightwave
receivers. As a develop
ment engineer, he has
since started work on the
signal acquisition and pro
cessing elements of a new product. Kent's BSEE
degree (1 984) and MSEE degree (1 985) are from
Washington State University. While attending col
lege, he worked for local companies on such prod
uct developments as process controls and digital
protective relays for high-voltage ac transmission
systems. He joined HP in 1 985. He coauthored an
article describing an optical measurement system,
soon to be published in Optical Engineering. Born
in Seattle, Washington, he is married and has a
small daughter. He lives in Santa Rosa, California.
In his off-hours, he enjoys boardsailing and skiing.
Rollin F. Rawson
The HP 8753A and HP
8754A Network Analyzers
and the HP 8756A Scalar
Network Analyzer are
among the many product
developments to which
Fred Rawson has contrib
uted. His work on the HP
8702A Lightwave Compo
nent Analyzer has focused
on source leveling and the thermal loops, the re
ceiver power supplies, the RF attenuator and
source, and the RF interface He has worked for HP
since 1 960. Fred's BSEE degree is from California
State University at San Jose. Before enrolling at San
Jose, he served as a staff sergeant in the U.S. Air
Force. Born in Laguna Beach, California, he is mar
ried and has four children. He lives in Santa Rosa,
California. In his leisure time, heenjoys collecting,
refurbishing, and driving Studebaker automobiles;
he also collects stamps.
Robert D. Albin
Dale Albin was project
[manager for the lightwave
I sources and receivers disI cussed in this issue of the
[HP Journal- In his twelvejyear career at HP, he has
I been a production enIgineer at the Microwave
I Technology Division workling on device testing and
GaAs FET processing and a development en
gineer/project leader on millimeter source modules
at the Network Measurements Division. His BSEE
degree (1977) is from the University of Texas at
Arlington, and his MSEE degree is Irom Stanford
University. Two patents relating to (inline technol
ogy are based on his ideas. Dale has delivered
papers at HP symposia and has written a previous
HP Journal article about millimeter source mod
ules. He was born in Dallas, Texas, and lives in
Santa Rosa, California. His outside interests in
clude running, skiing, bow hunting, reading, and
aviation.
58 Videoscope '.
' cent
work in the Svstems
^H Architecture Laboratory of
Myron R. Turtle
Before working on the
hardware and firmware de
sign for the Videoscope
tool, Myron Turtle's respon
sibilities included develop
ment of the HP 45981 A Multimode Video Adapter and
the HP 2625 and HP 2628
Terminals. He joined the
Advanced Products Divi
sion of HP in 1 974 and is a member of both the As
sociation for Computing Machinery and the IEEE.
Myron's BSEE degree is from the University of
California at Berkeley. He served in the U.S. Navy
as an electronics technician. Born in San Francisco,
California, he is vice president of a homeowners as
sociation in Santa Clara, California, where he
lives. His hobbies are amateur radio and computer
programming.
Danny Low
Danny Low joined the
Cupertino Division of HP in
1972, shortly after obtain
ing a degree in computer
science from the University
I of California at Berkeley. He
developed the host soft^J ware for the Videoscope
fe4n tool and continues to sup
l-^ port it. In the past, his re
sponsibilities included software quality control for
the original MPE system. He also developed sys
tem software for the HP 300 and for the MPE-V com
puters. Danny was born in Canton, China, and lives
in Mountain View, California. His favorite off-hours
activities focus on computers, science fiction, and
photography.
79 _ Electromigration Model
Vladimir Naroditsky
As a professor of mathema
tics at California State Uni
versity at San Jose, Vladi
mir Naroditsky contributed
his expertise in the electromigration simulation pro
ject described in this issue
of the HP Journal. He emi
Wulf D. Rehder
"'
Paul J. Marcoux
Paul Marcoux is a project
[ manager for studies involv
ing failure analysis and faii[ ure physics for integrated
circuits. Inthis issue ofthe
HP Journal, he reports on
a new model for simulating
electromigration in thin
metal films. Aspects of in
tegrated circuit process
technology have been focal to most of his past pro
jects at HP. He has written about 20 articles about
chemistry and 1C processing for professional jour
nals, and he is a member of the American Vacuum
Society. A patent has been awarded for an 1C pro
cess he helped develop. Paul's BS degree is from
Villanova University (1 970), and his PhD degree in
chemistry is from Kansas State University (1975).
He did postdoctoral work in chemical kinetics at
Pennsylvania State University. Born in Pautucket,
Rhode Island, Paul is married and has two
daughters. He lives in Mountain View, California,
and his favorite pastime is photography.
Paul P. Merchant
As a project leader at HP
Laboratories, Paul
Merchant has had a variety
of R&D projects involving
electromigration, suicide
process development, and
multilevel metallization. He
handled modeling, testing,
and planning in the elecN^P5>r* ' s tromigration study dis
cussed in this issue. Processing and properties of
thin films are his specialty. He has published many
papers on solid-state physics and chemistry and
on microelectronics and is a member of both the
American Physical Society and the American Vac
uum Society. Paul's BS degree in physics is from
the University of Vermont (1 972), and his ScM de
gree (1 974) and his PhD degree in physics (1 978)
are both from Brown University. Two postdoctoral
positions, one in France and one at Brown Univer
sity, involved laser materials and photoelectrolysis.
He is married, has three sons, and lives in Menlo
Park, California. In his off-hours, he enjoys playing
the piano, astronomy, and bicycling.
answer.
In many cases, the data itself serves to determine the
architecture of the neural network required for a given
problem. Other cases require the problem to be mapped
onto structures that may not be obvious at first sight. By
looking at problems in terms of certain neural data struc
tures, we may find neural programming to be quite natural
and intuitive.
To develop an intuition for programming with neurons,
a conceptual model is needed. This model has three layers.
The innermost layer is the Hopfield neuron. Changing the
properties of the neuron has a global effect on the problem.
The second layer is composed of elemental data structures
suited to the properties of neurons. The third layer is the
method by which the gap between the data structure and
the problem statement is bridged. It can be explained and
observed but, like programming in conventional computer
languages, it is best practiced.
Hopfield Neurons
Forming the core of our conceptual model is the Hopfield
neuron (Figs. 2 and 3). Simply stated, it is a nonlinear
Start
O
(a)
(b)
(c)
Summer
Inhibitory
Inputs
Gain Nonlinearity
Gx
Output
E x c i ta t o r y
Inputs
-5
Fig. 3. Various neuron symbols the circle being the most
abstract. Often a circle will be shaded to indicate that a neuron
is active. The diameter of the circle can also be varied to
show the relative activity of the neuron.
Too much energy from the K input will allow two or more
neurons to predominate above the others, producing an
m-of-n-flop.
The above values are for n-flops that rely solely on lateral
inhibition to produce the 1-of-n final state. There is an
additional constraint that could be applied to ensure that
the summation of all the outputs will be close to some
value; 1 would be a good choice for the n-flop. Hopfield
called this constraint global inhibition. The global inhibi
tion constraint is added to the n-flop by first summing all
of the outputs of the n neurons. From this sum the desired
total value is subtracted. The final value is then sent to an
inhibitory input of each neuron in the n-flop. For example,
if all of the neurons in an n-flop were initialized to 0, then
a value of 1 would be applied to an inhibitory input of
each neuron. Applying - 1 to an inhibitory input is the
same as applying +1 to an excitatory input. The effect is
to drive the outputs up towards 1 so that the lateral inhi
bition factor can then take over to ensure a 1-of-n state.
The global inhibition mechanism seems to be somewhat
analogous to an automatic gain control. When in place, it
allows the n-flop to operate over a wider variation of param
eters (Fig. 8), thereby avoiding the m-of-n-flop problem.
It's easy to connect neurons into a 1-of-n structure and
then make the aggregate structure work reliably. We might
even say that this represents a natural form for neurons.
Neurons connected in this manner represent a more or
dered condition. Their stable equilibrium state represents
to Initial State
Final State
Gs
- - - - -
oooeooo
o o O O O
G 5 -
- - 00 -
-oooo
1 . 5
2 . 0
2 . 5
G 5
5
-
o
o
0.5
1.0
1.5
O
2.0
- o
O
2.5
0.5
K
the resolution of the constraint: "Pick only one of these
n." This 1-of-n condition can be thought of as a data struc
ture a means to represent the answer to an optimization
problem. For example, in the four-color map problem, a
syntactically correct answer is that each country is colored
only one of four colors. A qualitatively correct answer re
quires additionally that each country be a different color
from each of its neighbors.
NxN-Flops
- - o
1.0
1.5
2.0
2.5
K
other n 1 neurons in its column and similarly to the n 1
other neurons of its row. Thus, for this type of network
there are 2(n-l)n2 or 2(n3-n2) connections. For a 32 x 32flop there are 63,488 connections.
Programming with Neurons
^^^J
^^^^
^^^^
^^fa
^^^^
^^^^
.^^fa
^^^
ooooo
o o o o
0*000
o o o o
000*0
o o o o
oo o o o o o
o o o o o o o
o o o000*0
00 0 0 0 0 0
o o o o o o o
o o o00*00
o o o o
oo o o o o o
0 0 0
(a)
(b)
ooooooo
00000000
00000000
00000000
O
O
O
O
0
O
O
O
O
O
O
0
O
0
O
O
O
O
O
O
O
O
0
O
O
O
O
O
O
O
O
O
1-
O
Fig. 1 7. The traveling salesman problem link all of the cities
in the shortest possible distance.
o-J
I
0
Fig. 18. A given path is denoted by a list that indicates the
order of visits. The list CAEBD is interpreted as: starting at
C. first visit A, then E, B, and D, and then return to C. Every
path belongs to a set of 2n equivalent paths, where n is the
number of cities on the path.
c O O O O
D O O O O
E
o o
1A
B
C
D
oJ
i r
Q
Fig. 20. Distances between city B and every other city nor
malized to city pair AB, the most widely separated city pair
on the tour.
Section
Line
Inhibit 2s
Inhibit 1s
Reference
1. K. Appel and W. Haken, "The Solution of the Four-Color-Map
Problem," Scientific American, Vol. 237, October 1977, pp. 108121.
Bibliography
1. J.J. Hopfield and D.W. Tank, "'Neural' Computation of Deci
sions in Optimization Problems," Biological Cybernetics, Vol. 52,
1985, pp. 141-152.
2. J.J. Hopfield and D.W. Tank, "Computing with Neural Circuits:
A Model," Science, Vol. 233, no. 4764, August 8, 1986, pp. 625633.
3. D.W. Tank and J.J. Hopfield, "Collective Computation in
Neuronlike Circuits," Scientific American, Vol. 257, no. 6, De
cember 1987, pp. 104-114.
4. C. Peterson and J.R. Anderson, Neural Networks and NP-Complete Optimization Problems: A Performance Study on the Graph
Bisection Problem, MCC Technical Report No. EI-287-87,
December 14, 1987.
CORRECTION
In the April 1989 issue, Fig. 1 on page 66 should have an edge from node d to node
e. The correct figure is shown here.
Nodes
Edges
G:
Added
Edge
G':
(b)
Grain
Structure
Statistical
Initialization
Increase
Time
Model Overview
(kux
(1)
k g r a d ( u )
( 2 )
and
(3)
u(i,
- u(i.j).
rT
2p0(l + oT) = 0.
(4)
(5)
(6)
(7)
Fixed T = 350C
H = 1W/im-C
With Heating:
H = 0.75 MW/Mm-C
10
4.03.8-3.6
3
2
1
0
1
2
3
Expected Value for Normal Distribution (Standard Deviations)
(8)
(9)
References
1. H.B. Huntingtonand A.R. Grone, "Current-Induced Marker Mo
tion Vol. Gold Wires," Journal of Physical Chemistry Solids, Vol.
20, nos. 1-2, 1961, pp. 76-87.
2. J.R. Black, "Electromigration: A Brief Survey and Some Recent
Results," IEEE Transactions on Electron Devices, Vol. ED-16, 1969,
pp. 338-347.
3. M.J. Attardo, R. Rutledge, and R.C. Jack, "Statistical Metallur
gical Model for Electromigration Failure in Aluminum Thin-Film
Conductors," Journal of Applied Physics, Vol. 42, 1971, pp. 43434349.
4. K. Nikawa, "Monte Carlo Calculation Based on the Genera
Electromigration Failure Model," Proceedings of the 19th
h iSi
Internationa] Reliability Physics Symposium, 1981, pp. 175-181.
5. P. Kumar and R.S. Sorbello, "Linear Response Theory of the
Driving Forces for Electromigration," Thin Solid Films, Vol. 25,
1975, pp. 25-35.
6. R.S. Sorbello, "Theory of the Direct Force in Electromigration,"
Physical Review B, Vol. 31, no. 2, 1985, pp. 798-804.
7. A.H. Verbruggen, "Fundamental Questions in the Theory of
Electromigration." IBM Journal of Research and Development,
Vol. 32, no. 1, 1988, pp. 93-98.
8. L. Report, Heat Flow in Semiconductor Structures, Final Report,
San Jose State University, 1983.
9. D.S. Chhabra and N.G. Ainslie, Open-Circuit Failure in ThinFilm Conductors, IBM Technical Report 22.419, 1967.
10. L. Braun, "Electromigration Testing: A Current Problem," Mi
croelectronics and Reliability, Vol. 13, 1974, pp. 215-228.
11. J.M. Towner and P. van de Ven, "Aluminum Electromigration
under Pulsed DC Conditions," Proceedings of the 21st IEEE Inter
nationa/ Reliability Physics Symposium, 1983, pp. 36-39.
12. F.M. d'Heurle and P.S. Ho, "Electromigration in Thin Films,"
in J. Poate, K. Tu, and J. Mayer, eds., Interdijfusion and Reactions,
Wiley, 1978.
13. P. Merchant, "Electromigration: An Overview," Hewlett-Pack
ard Journal, Vol. 33, no. 8, August 1982, pp. 28-30.
14. P.B. Ghate, "Electromigration-Induced Failures in VLSI Inter
connects," Proceedings of the 20th IEEE International Reliability
Physics Symposium, 1982, pp. 292-299.
15. D.J. La Combe and E.L. Parks, "The Distribution of Electromi
gration Failures," Proceedings of the 24fh IEEE International Reli
ability Physics Symposium, 1986, pp. 1-6.
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